456 files changed, 282884 insertions, 5796 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index ee85e8aba636..c56320e78c0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -51,12 +51,15 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
 	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
 	amdgpu_dma_buf.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
-	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
-	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
-	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
+	amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \
+	amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \
+	amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o \
+	amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
 	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
 	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
-	amdgpu_fw_attestation.o amdgpu_securedisplay.o
+	amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o
+
+amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
 
 amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
 
@@ -71,7 +74,8 @@ amdgpu-y += \
 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
 	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
 	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
-	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o
+	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o \
+	beige_goby_reg_init.o yellow_carp_reg_init.o
 
 # add DF block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
index 65b1dca4b02e..148f6c3343ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
@@ -227,7 +227,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
 			break;
 		default:
 			break;
-		};
+		}
 	}
 
 	/* Reinit NBIF block */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 264176a01e16..c0316eaba547 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
 #include "amdgpu_gfxhub.h"
 #include "amdgpu_df.h"
 #include "amdgpu_smuio.h"
+#include "amdgpu_fdinfo.h"
 
 #define MAX_GPU_INSTANCE		16
 
@@ -129,6 +130,13 @@ struct amdgpu_mgpu_info
 	bool				pending_reset;
 };
 
+enum amdgpu_ss {
+	AMDGPU_SS_DRV_LOAD,
+	AMDGPU_SS_DEV_D0,
+	AMDGPU_SS_DEV_D3,
+	AMDGPU_SS_DRV_UNLOAD
+};
+
 struct amdgpu_watchdog_timer
 {
 	bool timeout_fatal_disable;
@@ -203,6 +211,7 @@ extern int amdgpu_discovery;
 extern int amdgpu_mes;
 extern int amdgpu_noretry;
 extern int amdgpu_force_asic_type;
+extern int amdgpu_smartshift_bias;
 #ifdef CONFIG_HSA_AMD
 extern int sched_policy;
 extern bool debug_evictions;
@@ -260,6 +269,10 @@ extern int amdgpu_num_kcq;
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
 
+/* smasrt shift bias level limits */
+#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
+#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
+
 struct amdgpu_device;
 struct amdgpu_ib;
 struct amdgpu_cs_parser;
@@ -267,7 +280,6 @@ struct amdgpu_job;
 struct amdgpu_irq_src;
 struct amdgpu_fpriv;
 struct amdgpu_bo_va_mapping;
-struct amdgpu_atif;
 struct kfd_vm_fault_info;
 struct amdgpu_hive_info;
 struct amdgpu_reset_context;
@@ -682,20 +694,6 @@ struct amdgpu_vram_scratch {
 };
 
 /*
- * ACPI
- */
-struct amdgpu_atcs_functions {
-	bool get_ext_state;
-	bool pcie_perf_req;
-	bool pcie_dev_rdy;
-	bool pcie_bus_width;
-};
-
-struct amdgpu_atcs {
-	struct amdgpu_atcs_functions functions;
-};
-
-/*
  * CGS
  */
 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
@@ -824,8 +822,6 @@ struct amdgpu_device {
 	struct notifier_block		acpi_nb;
 	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
 	struct debugfs_blob_wrapper     debugfs_vbios_blob;
-	struct amdgpu_atif		*atif;
-	struct amdgpu_atcs		atcs;
 	struct mutex			srbm_mutex;
 	/* GRBM index mutex. Protects concurrent access to GRBM index */
 	struct mutex                    grbm_idx_mutex;
@@ -1074,9 +1070,10 @@ struct amdgpu_device {
 
 	atomic_t			throttling_logging_enabled;
 	struct ratelimit_state		throttling_logging_rs;
-	uint32_t			ras_features;
+	uint32_t                        ras_hw_enabled;
+	uint32_t                        ras_enabled;
 
-	bool                            in_pci_err_recovery;
+	bool                            no_hw_access;
 	struct pci_saved_state          *pci_state;
 
 	struct amdgpu_reset_control     *reset_cntl;
@@ -1099,7 +1096,9 @@ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
 
 int amdgpu_device_init(struct amdgpu_device *adev,
 		       uint32_t flags);
-void amdgpu_device_fini(struct amdgpu_device *adev);
+void amdgpu_device_fini_hw(struct amdgpu_device *adev);
+void amdgpu_device_fini_sw(struct amdgpu_device *adev);
+
 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
 
 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
@@ -1142,6 +1141,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
  * Registers read & write functions.
  */
 #define AMDGPU_REGS_NO_KIQ    (1<<1)
+#define AMDGPU_REGS_RLC	(1<<2)
 
 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
@@ -1278,12 +1278,18 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
 bool amdgpu_device_supports_atpx(struct drm_device *dev);
 bool amdgpu_device_supports_px(struct drm_device *dev);
 bool amdgpu_device_supports_boco(struct drm_device *dev);
+bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
 bool amdgpu_device_supports_baco(struct drm_device *dev);
 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
 				      struct amdgpu_device *peer_adev);
 int amdgpu_device_baco_enter(struct drm_device *dev);
 int amdgpu_device_baco_exit(struct drm_device *dev);
 
+void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring);
+void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring);
+
 /* atpx handler */
 #if defined(CONFIG_VGA_SWITCHEROO)
 void amdgpu_register_atpx_handler(void);
@@ -1319,6 +1325,8 @@ void amdgpu_driver_lastclose_kms(struct drm_device *dev);
 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 				 struct drm_file *file_priv);
+void amdgpu_driver_release_kms(struct drm_device *dev);
+
 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
@@ -1350,21 +1358,38 @@ struct amdgpu_afmt_acr {
 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
 
 /* amdgpu_acpi.c */
+
+/* ATCS Device/Driver State */
+#define AMDGPU_ATCS_PSC_DEV_STATE_D0		0
+#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT	3
+#define AMDGPU_ATCS_PSC_DRV_STATE_OPR		0
+#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR	1
+
 #if defined(CONFIG_ACPI)
 int amdgpu_acpi_init(struct amdgpu_device *adev);
 void amdgpu_acpi_fini(struct amdgpu_device *adev);
 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
+bool amdgpu_acpi_is_power_shift_control_supported(void);
 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
 						u8 perf_req, bool advertise);
+int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
+				    u8 dev_state, bool drv_state);
+int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
 
-void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
-		struct amdgpu_dm_backlight_caps *caps);
+void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);
+void amdgpu_acpi_detect(void);
 #else
 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; }
+static inline void amdgpu_acpi_detect(void) { }
+static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
+static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
+						  u8 dev_state, bool drv_state) { return 0; }
+static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
+						 enum amdgpu_ss ss_state) { return 0; }
 #endif
 
 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 2e9b16fb3fcd..84a1b4bc9bb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -71,12 +71,31 @@ struct amdgpu_atif {
 	struct amdgpu_dm_backlight_caps backlight_caps;
 };
 
+struct amdgpu_atcs_functions {
+	bool get_ext_state;
+	bool pcie_perf_req;
+	bool pcie_dev_rdy;
+	bool pcie_bus_width;
+	bool power_shift_control;
+};
+
+struct amdgpu_atcs {
+	acpi_handle handle;
+
+	struct amdgpu_atcs_functions functions;
+};
+
+static struct amdgpu_acpi_priv {
+	struct amdgpu_atif atif;
+	struct amdgpu_atcs atcs;
+} amdgpu_acpi_priv;
+
 /* Call the ATIF method
  */
 /**
  * amdgpu_atif_call - call an ATIF method
  *
- * @handle: acpi handle
+ * @atif: atif structure
  * @function: the ATIF function to execute
  * @params: ATIF function params
  *
@@ -166,7 +185,6 @@ static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mas
 /**
  * amdgpu_atif_verify_interface - verify ATIF
  *
- * @handle: acpi handle
  * @atif: amdgpu atif struct
  *
  * Execute the ATIF_FUNCTION_VERIFY_INTERFACE ATIF function
@@ -208,40 +226,10 @@ out:
 	return err;
 }
 
-static acpi_handle amdgpu_atif_probe_handle(acpi_handle dhandle)
-{
-	acpi_handle handle = NULL;
-	char acpi_method_name[255] = { 0 };
-	struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name };
-	acpi_status status;
-
-	/* For PX/HG systems, ATIF and ATPX are in the iGPU's namespace, on dGPU only
-	 * systems, ATIF is in the dGPU's namespace.
-	 */
-	status = acpi_get_handle(dhandle, "ATIF", &handle);
-	if (ACPI_SUCCESS(status))
-		goto out;
-
-	if (amdgpu_has_atpx()) {
-		status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATIF",
-					 &handle);
-		if (ACPI_SUCCESS(status))
-			goto out;
-	}
-
-	DRM_DEBUG_DRIVER("No ATIF handle found\n");
-	return NULL;
-out:
-	acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
-	DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);
-	return handle;
-}
-
 /**
  * amdgpu_atif_get_notification_params - determine notify configuration
  *
- * @handle: acpi handle
- * @n: atif notification configuration struct
+ * @atif: acpi handle
  *
  * Execute the ATIF_FUNCTION_GET_SYSTEM_PARAMETERS ATIF function
  * to determine if a notifier is used and if so which one
@@ -304,7 +292,7 @@ out:
 /**
  * amdgpu_atif_query_backlight_caps - get min and max backlight input signal
  *
- * @handle: acpi handle
+ * @atif: acpi handle
  *
  * Execute the QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS ATIF function
  * to determine the acceptable range of backlight values
@@ -363,7 +351,7 @@ out:
 /**
  * amdgpu_atif_get_sbios_requests - get requested sbios event
  *
- * @handle: acpi handle
+ * @atif: acpi handle
  * @req: atif sbios request struct
  *
  * Execute the ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS ATIF function
@@ -416,7 +404,7 @@ out:
 static int amdgpu_atif_handler(struct amdgpu_device *adev,
 			       struct acpi_bus_event *event)
 {
-	struct amdgpu_atif *atif = adev->atif;
+	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;
 	int count;
 
 	DRM_DEBUG_DRIVER("event, device_class = %s, type = %#x\n",
@@ -426,8 +414,7 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
 		return NOTIFY_DONE;
 
 	/* Is this actually our event? */
-	if (!atif ||
-	    !atif->notification_cfg.enabled ||
+	if (!atif->notification_cfg.enabled ||
 	    event->type != atif->notification_cfg.command_code) {
 		/* These events will generate keypresses otherwise */
 		if (event->type == ACPI_VIDEO_NOTIFY_PROBE)
@@ -487,14 +474,15 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
 /**
  * amdgpu_atcs_call - call an ATCS method
  *
- * @handle: acpi handle
+ * @atcs: atcs structure
  * @function: the ATCS function to execute
  * @params: ATCS function params
  *
  * Executes the requested ATCS function (all asics).
  * Returns a pointer to the acpi output buffer.
  */
-static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function,
+static union acpi_object *amdgpu_atcs_call(struct amdgpu_atcs *atcs,
+					   int function,
 					   struct acpi_buffer *params)
 {
 	acpi_status status;
@@ -518,7 +506,7 @@ static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function,
 		atcs_arg_elements[1].integer.value = 0;
 	}
 
-	status = acpi_evaluate_object(handle, "ATCS", &atcs_arg, &buffer);
+	status = acpi_evaluate_object(atcs->handle, NULL, &atcs_arg, &buffer);
 
 	/* Fail only if calling the method fails and ATIF is supported */
 	if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
@@ -547,12 +535,12 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas
 	f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED;
 	f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED;
 	f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED;
+	f->power_shift_control = mask & ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED;
 }
 
 /**
  * amdgpu_atcs_verify_interface - verify ATCS
  *
- * @handle: acpi handle
  * @atcs: amdgpu atcs struct
  *
  * Execute the ATCS_FUNCTION_VERIFY_INTERFACE ATCS function
@@ -560,15 +548,14 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas
  * (all asics).
  * returns 0 on success, error on failure.
  */
-static int amdgpu_atcs_verify_interface(acpi_handle handle,
-					struct amdgpu_atcs *atcs)
+static int amdgpu_atcs_verify_interface(struct amdgpu_atcs *atcs)
 {
 	union acpi_object *info;
 	struct atcs_verify_interface output;
 	size_t size;
 	int err = 0;
 
-	info = amdgpu_atcs_call(handle, ATCS_FUNCTION_VERIFY_INTERFACE, NULL);
+	info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_VERIFY_INTERFACE, NULL);
 	if (!info)
 		return -EIO;
 
@@ -605,7 +592,7 @@ out:
  */
 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev)
 {
-	struct amdgpu_atcs *atcs = &adev->atcs;
+	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;
 
 	if (atcs->functions.pcie_perf_req && atcs->functions.pcie_dev_rdy)
 		return true;
@@ -614,6 +601,18 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade
 }
 
 /**
+ * amdgpu_acpi_is_power_shift_control_supported
+ *
+ * Check if the ATCS power shift control method
+ * is supported.
+ * returns true if supported, false if not.
+ */
+bool amdgpu_acpi_is_power_shift_control_supported(void)
+{
+	return amdgpu_acpi_priv.atcs.functions.power_shift_control;
+}
+
+/**
  * amdgpu_acpi_pcie_notify_device_ready
  *
  * @adev: amdgpu_device pointer
@@ -624,19 +623,13 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade
  */
 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev)
 {
-	acpi_handle handle;
 	union acpi_object *info;
-	struct amdgpu_atcs *atcs = &adev->atcs;
-
-	/* Get the device handle */
-	handle = ACPI_HANDLE(&adev->pdev->dev);
-	if (!handle)
-		return -EINVAL;
+	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;
 
 	if (!atcs->functions.pcie_dev_rdy)
 		return -EINVAL;
 
-	info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL);
+	info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL);
 	if (!info)
 		return -EIO;
 
@@ -659,9 +652,8 @@ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev)
 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
 					 u8 perf_req, bool advertise)
 {
-	acpi_handle handle;
 	union acpi_object *info;
-	struct amdgpu_atcs *atcs = &adev->atcs;
+	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;
 	struct atcs_pref_req_input atcs_input;
 	struct atcs_pref_req_output atcs_output;
 	struct acpi_buffer params;
@@ -671,11 +663,6 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
 	if (amdgpu_acpi_pcie_notify_device_ready(adev))
 		return -EINVAL;
 
-	/* Get the device handle */
-	handle = ACPI_HANDLE(&adev->pdev->dev);
-	if (!handle)
-		return -EINVAL;
-
 	if (!atcs->functions.pcie_perf_req)
 		return -EINVAL;
 
@@ -693,7 +680,7 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
 	params.pointer = &atcs_input;
 
 	while (retry--) {
-		info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, &params);
+		info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, &params);
 		if (!info)
 			return -EIO;
 
@@ -727,6 +714,96 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
 }
 
 /**
+ * amdgpu_acpi_power_shift_control
+ *
+ * @adev: amdgpu_device pointer
+ * @dev_state: device acpi state
+ * @drv_state: driver state
+ *
+ * Executes the POWER_SHIFT_CONTROL method to
+ * communicate current dGPU device state and
+ * driver state to APU/SBIOS.
+ * returns 0 on success, error on failure.
+ */
+int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
+				    u8 dev_state, bool drv_state)
+{
+	union acpi_object *info;
+	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;
+	struct atcs_pwr_shift_input atcs_input;
+	struct acpi_buffer params;
+
+	if (!amdgpu_acpi_is_power_shift_control_supported())
+		return -EINVAL;
+
+	atcs_input.size = sizeof(struct atcs_pwr_shift_input);
+	/* dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
+	atcs_input.dgpu_id = adev->pdev->devfn | (adev->pdev->bus->number << 8);
+	atcs_input.dev_acpi_state = dev_state;
+	atcs_input.drv_state = drv_state;
+
+	params.length = sizeof(struct atcs_pwr_shift_input);
+	params.pointer = &atcs_input;
+
+	info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_POWER_SHIFT_CONTROL, &params);
+	if (!info) {
+		DRM_ERROR("ATCS PSC update failed\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * amdgpu_acpi_smart_shift_update - update dGPU device state to SBIOS
+ *
+ * @dev: drm_device pointer
+ * @ss_state: current smart shift event
+ *
+ * returns 0 on success,
+ * otherwise return error number.
+ */
+int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state)
+{
+	struct amdgpu_device *adev = drm_to_adev(dev);
+	int r;
+
+	if (!amdgpu_device_supports_smart_shift(dev))
+		return 0;
+
+	switch (ss_state) {
+	/* SBIOS trigger “stop”, “enable” and “start” at D0, Driver Operational.
+	 * SBIOS trigger “stop” at D3, Driver Not Operational.
+	 * SBIOS trigger “stop” and “disable” at D0, Driver NOT operational.
+	 */
+	case AMDGPU_SS_DRV_LOAD:
+		r = amdgpu_acpi_power_shift_control(adev,
+						    AMDGPU_ATCS_PSC_DEV_STATE_D0,
+						    AMDGPU_ATCS_PSC_DRV_STATE_OPR);
+		break;
+	case AMDGPU_SS_DEV_D0:
+		r = amdgpu_acpi_power_shift_control(adev,
+						    AMDGPU_ATCS_PSC_DEV_STATE_D0,
+						    AMDGPU_ATCS_PSC_DRV_STATE_OPR);
+		break;
+	case AMDGPU_SS_DEV_D3:
+		r = amdgpu_acpi_power_shift_control(adev,
+						    AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT,
+						    AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR);
+		break;
+	case AMDGPU_SS_DRV_UNLOAD:
+		r = amdgpu_acpi_power_shift_control(adev,
+						    AMDGPU_ATCS_PSC_DEV_STATE_D0,
+						    AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return r;
+}
+
+/**
  * amdgpu_acpi_event - handle notify events
  *
  * @nb: notifier block
@@ -769,50 +846,15 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
  */
 int amdgpu_acpi_init(struct amdgpu_device *adev)
 {
-	acpi_handle handle, atif_handle;
-	struct amdgpu_atif *atif;
-	struct amdgpu_atcs *atcs = &adev->atcs;
-	int ret;
-
-	/* Get the device handle */
-	handle = ACPI_HANDLE(&adev->pdev->dev);
-
-	if (!adev->bios || !handle)
-		return 0;
-
-	/* Call the ATCS method */
-	ret = amdgpu_atcs_verify_interface(handle, atcs);
-	if (ret) {
-		DRM_DEBUG_DRIVER("Call to ATCS verify_interface failed: %d\n", ret);
-	}
-
-	/* Probe for ATIF, and initialize it if found */
-	atif_handle = amdgpu_atif_probe_handle(handle);
-	if (!atif_handle)
-		goto out;
-
-	atif = kzalloc(sizeof(*atif), GFP_KERNEL);
-	if (!atif) {
-		DRM_WARN("Not enough memory to initialize ATIF\n");
-		goto out;
-	}
-	atif->handle = atif_handle;
-
-	/* Call the ATIF method */
-	ret = amdgpu_atif_verify_interface(atif);
-	if (ret) {
-		DRM_DEBUG_DRIVER("Call to ATIF verify_interface failed: %d\n", ret);
-		kfree(atif);
-		goto out;
-	}
-	adev->atif = atif;
+	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;
 
 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	if (atif->notifications.brightness_change) {
 		if (amdgpu_device_has_dc_support(adev)) {
 #if defined(CONFIG_DRM_AMD_DC)
 			struct amdgpu_display_manager *dm = &adev->dm;
-			atif->bd = dm->backlight_dev;
+			if (dm->backlight_dev)
+				atif->bd = dm->backlight_dev;
 #endif
 		} else {
 			struct drm_encoder *tmp;
@@ -834,6 +876,129 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
 		}
 	}
 #endif
+	adev->acpi_nb.notifier_call = amdgpu_acpi_event;
+	register_acpi_notifier(&adev->acpi_nb);
+
+	return 0;
+}
+
+void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps)
+{
+	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;
+
+	caps->caps_valid = atif->backlight_caps.caps_valid;
+	caps->min_input_signal = atif->backlight_caps.min_input_signal;
+	caps->max_input_signal = atif->backlight_caps.max_input_signal;
+}
+
+/**
+ * amdgpu_acpi_fini - tear down driver acpi support
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Unregisters with the acpi notifier chain (all asics).
+ */
+void amdgpu_acpi_fini(struct amdgpu_device *adev)
+{
+	unregister_acpi_notifier(&adev->acpi_nb);
+}
+
+/**
+ * amdgpu_atif_pci_probe_handle - look up the ATIF handle
+ *
+ * @pdev: pci device
+ *
+ * Look up the ATIF handles (all asics).
+ * Returns true if the handle is found, false if not.
+ */
+static bool amdgpu_atif_pci_probe_handle(struct pci_dev *pdev)
+{
+	char acpi_method_name[255] = { 0 };
+	struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
+	acpi_handle dhandle, atif_handle;
+	acpi_status status;
+	int ret;
+
+	dhandle = ACPI_HANDLE(&pdev->dev);
+	if (!dhandle)
+		return false;
+
+	status = acpi_get_handle(dhandle, "ATIF", &atif_handle);
+	if (ACPI_FAILURE(status)) {
+		return false;
+	}
+	amdgpu_acpi_priv.atif.handle = atif_handle;
+	acpi_get_name(amdgpu_acpi_priv.atif.handle, ACPI_FULL_PATHNAME, &buffer);
+	DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);
+	ret = amdgpu_atif_verify_interface(&amdgpu_acpi_priv.atif);
+	if (ret) {
+		amdgpu_acpi_priv.atif.handle = 0;
+		return false;
+	}
+	return true;
+}
+
+/**
+ * amdgpu_atcs_pci_probe_handle - look up the ATCS handle
+ *
+ * @pdev: pci device
+ *
+ * Look up the ATCS handles (all asics).
+ * Returns true if the handle is found, false if not.
+ */
+static bool amdgpu_atcs_pci_probe_handle(struct pci_dev *pdev)
+{
+	char acpi_method_name[255] = { 0 };
+	struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name };
+	acpi_handle dhandle, atcs_handle;
+	acpi_status status;
+	int ret;
+
+	dhandle = ACPI_HANDLE(&pdev->dev);
+	if (!dhandle)
+		return false;
+
+	status = acpi_get_handle(dhandle, "ATCS", &atcs_handle);
+	if (ACPI_FAILURE(status)) {
+		return false;
+	}
+	amdgpu_acpi_priv.atcs.handle = atcs_handle;
+	acpi_get_name(amdgpu_acpi_priv.atcs.handle, ACPI_FULL_PATHNAME, &buffer);
+	DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);
+	ret = amdgpu_atcs_verify_interface(&amdgpu_acpi_priv.atcs);
+	if (ret) {
+		amdgpu_acpi_priv.atcs.handle = 0;
+		return false;
+	}
+	return true;
+}
+
+/*
+ * amdgpu_acpi_detect - detect ACPI ATIF/ATCS methods
+ *
+ * Check if we have the ATIF/ATCS methods and populate
+ * the structures in the driver.
+ */
+void amdgpu_acpi_detect(void)
+{
+	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;
+	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;
+	struct pci_dev *pdev = NULL;
+	int ret;
+
+	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
+		if (!atif->handle)
+			amdgpu_atif_pci_probe_handle(pdev);
+		if (!atcs->handle)
+			amdgpu_atcs_pci_probe_handle(pdev);
+	}
+
+	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
+		if (!atif->handle)
+			amdgpu_atif_pci_probe_handle(pdev);
+		if (!atcs->handle)
+			amdgpu_atcs_pci_probe_handle(pdev);
+	}
 
 	if (atif->functions.sbios_requests && !atif->functions.system_params) {
 		/* XXX check this workraround, if sbios request function is
@@ -863,42 +1028,13 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
 	} else {
 		atif->backlight_caps.caps_valid = false;
 	}
-
-out:
-	adev->acpi_nb.notifier_call = amdgpu_acpi_event;
-	register_acpi_notifier(&adev->acpi_nb);
-
-	return ret;
-}
-
-void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
-		struct amdgpu_dm_backlight_caps *caps)
-{
-	if (!adev->atif) {
-		caps->caps_valid = false;
-		return;
-	}
-	caps->caps_valid = adev->atif->backlight_caps.caps_valid;
-	caps->min_input_signal = adev->atif->backlight_caps.min_input_signal;
-	caps->max_input_signal = adev->atif->backlight_caps.max_input_signal;
-}
-
-/**
- * amdgpu_acpi_fini - tear down driver acpi support
- *
- * @adev: amdgpu_device pointer
- *
- * Unregisters with the acpi notifier chain (all asics).
- */
-void amdgpu_acpi_fini(struct amdgpu_device *adev)
-{
-	unregister_acpi_notifier(&adev->acpi_nb);
-	kfree(adev->atif);
 }
 
 /**
  * amdgpu_acpi_is_s0ix_supported
  *
+ * @adev: amdgpu_device_pointer
+ *
  * returns true if supported, false if not.
  */
 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 5f6696a3c778..f9c01bdc3d4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -170,7 +170,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 	}
 }
 
-void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
+void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
 {
 	if (adev->kfd.dev) {
 		kgd2kfd_device_exit(adev->kfd.dev);
@@ -670,10 +670,10 @@ int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
 	return 0;
 }
 
-int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid)
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid,
+				      enum TLB_FLUSH_TYPE flush_type)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-	const uint32_t flush_type = 0;
 	bool all_hub = false;
 
 	if (adev->family == AMDGPU_FAMILY_AI)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 5ffb07b02810..db16b3e83694 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -36,13 +36,26 @@
 
 extern uint64_t amdgpu_amdkfd_total_mem_size;
 
+enum TLB_FLUSH_TYPE {
+	TLB_FLUSH_LEGACY = 0,
+	TLB_FLUSH_LIGHTWEIGHT,
+	TLB_FLUSH_HEAVYWEIGHT
+};
+
 struct amdgpu_device;
 
-struct kfd_bo_va_list {
-	struct list_head bo_list;
-	struct amdgpu_bo_va *bo_va;
-	void *kgd_dev;
+enum kfd_mem_attachment_type {
+	KFD_MEM_ATT_SHARED,	/* Share kgd_mem->bo or another attachment's */
+	KFD_MEM_ATT_USERPTR,	/* SG bo to DMA map pages from a userptr bo */
+	KFD_MEM_ATT_DMABUF,	/* DMAbuf to DMA map TTM BOs */
+};
+
+struct kfd_mem_attachment {
+	struct list_head list;
+	enum kfd_mem_attachment_type type;
 	bool is_mapped;
+	struct amdgpu_bo_va *bo_va;
+	struct amdgpu_device *adev;
 	uint64_t va;
 	uint64_t pte_flags;
 };
@@ -50,7 +63,8 @@ struct kfd_bo_va_list {
 struct kgd_mem {
 	struct mutex lock;
 	struct amdgpu_bo *bo;
-	struct list_head bo_va_list;
+	struct dma_buf *dmabuf;
+	struct list_head attachments;
 	/* protected by amdkfd_process_info.lock */
 	struct ttm_validate_buffer validate_list;
 	struct ttm_validate_buffer resv_list;
@@ -75,6 +89,7 @@ struct amdgpu_amdkfd_fence {
 	struct mm_struct *mm;
 	spinlock_t lock;
 	char timeline_name[TASK_COMM_LEN];
+	struct svm_range_bo *svm_bo;
 };
 
 struct amdgpu_kfd_dev {
@@ -127,14 +142,15 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 			const void *ih_ring_entry);
 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
-void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
+void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 				uint32_t vmid, uint64_t gpu_addr,
 				uint32_t *ib_cmd, uint32_t ib_len);
 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid);
-int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid);
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid,
+				      enum TLB_FLUSH_TYPE flush_type);
 
 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
 
@@ -148,7 +164,8 @@ int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 					int queue_bit);
 
 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
-								struct mm_struct *mm);
+				struct mm_struct *mm,
+				struct svm_range_bo *svm_bo);
 #if IS_ENABLED(CONFIG_HSA_AMD)
 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
@@ -234,22 +251,27 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *s
 	})
 
 /* GPUVM API */
+#define drm_priv_to_vm(drm_priv)					\
+	(&((struct amdgpu_fpriv *)					\
+		((struct drm_file *)(drm_priv))->driver_priv)->vm)
+
 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
 					struct file *filp, u32 pasid,
-					void **vm, void **process_info,
+					void **process_info,
 					struct dma_fence **ef);
-void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);
-uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
+void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv);
+uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		struct kgd_dev *kgd, uint64_t va, uint64_t size,
-		void *vm, struct kgd_mem **mem,
+		void *drm_priv, struct kgd_mem **mem,
 		uint64_t *offset, uint32_t flags);
 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size);
+		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
+		uint64_t *size);
 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
+		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool *table_freed);
 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
+		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
 int amdgpu_amdkfd_gpuvm_sync_memory(
 		struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
@@ -260,7 +282,7 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
 					      struct kfd_vm_fault_info *info);
 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 				      struct dma_buf *dmabuf,
-				      uint64_t va, void *vm,
+				      uint64_t va, void *drm_priv,
 				      struct kgd_mem **mem, uint64_t *size,
 				      uint64_t *mmap_offset);
 int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
@@ -270,6 +292,7 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 				struct amdgpu_vm *vm);
 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
+void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
 #else
 static inline
 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 9ef9f3ddad48..6409d6b1b2df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -25,6 +25,7 @@
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
+#include "amdgpu_amdkfd_arcturus.h"
 #include "sdma0/sdma0_4_2_2_offset.h"
 #include "sdma0/sdma0_4_2_2_sh_mask.h"
 #include "sdma1/sdma1_4_2_2_offset.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 5af464933976..1d0dbff87d3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -28,6 +28,7 @@
 #include <linux/slab.h>
 #include <linux/sched/mm.h>
 #include "amdgpu_amdkfd.h"
+#include "kfd_svm.h"
 
 static const struct dma_fence_ops amdkfd_fence_ops;
 static atomic_t fence_seq = ATOMIC_INIT(0);
@@ -60,7 +61,8 @@ static atomic_t fence_seq = ATOMIC_INIT(0);
  */
 
 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
-						       struct mm_struct *mm)
+				struct mm_struct *mm,
+				struct svm_range_bo *svm_bo)
 {
 	struct amdgpu_amdkfd_fence *fence;
 
@@ -73,7 +75,7 @@ struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
 	fence->mm = mm;
 	get_task_comm(fence->timeline_name, current);
 	spin_lock_init(&fence->lock);
-
+	fence->svm_bo = svm_bo;
 	dma_fence_init(&fence->base, &amdkfd_fence_ops, &fence->lock,
 		   context, atomic_inc_return(&fence_seq));
 
@@ -111,6 +113,8 @@ static const char *amdkfd_fence_get_timeline_name(struct dma_fence *f)
  *  a KFD BO and schedules a job to move the BO.
  *  If fence is already signaled return true.
  *  If fence is not signaled schedule a evict KFD process work item.
+ *
+ *  @f: dma_fence
  */
 static bool amdkfd_fence_enable_signaling(struct dma_fence *f)
 {
@@ -122,16 +126,20 @@ static bool amdkfd_fence_enable_signaling(struct dma_fence *f)
 	if (dma_fence_is_signaled(f))
 		return true;
 
-	if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, f))
-		return true;
-
+	if (!fence->svm_bo) {
+		if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, f))
+			return true;
+	} else {
+		if (!svm_range_schedule_evict_svm_bo(fence))
+			return true;
+	}
 	return false;
 }
 
 /**
  * amdkfd_fence_release - callback that fence can be freed
  *
- * @fence: fence
+ * @f: dma_fence
  *
  * This function is called when the reference count becomes zero.
  * Drops the mm_struct reference and RCU schedules freeing up the fence.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 62aa1a6f64ed..491acdf92f73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 
 	lock_srbm(kgd, 0, 0, 0, vmid);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
+	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
 	/* APE1 no longer exists on GFX9 */
 
 	unlock_srbm(kgd);
@@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 
 	lock_srbm(kgd, mec, pipe, 0, 0);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
 		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 
@@ -239,13 +239,13 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 
 	for (reg = hqd_base;
 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
-		WREG32(reg, mqd_hqd[reg - hqd_base]);
+		WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
 
 
 	/* Activate doorbell logic before triggering WPTR poll. */
 	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
+	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 
 	if (wptr) {
 		/* Don't read wptr with get_user because the user
@@ -274,27 +274,27 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
 		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
 
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
 		       lower_32_bits(guessed_wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
 		       upper_32_bits(guessed_wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
 		       lower_32_bits((uint64_t)wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 		       upper_32_bits((uint64_t)wptr));
 		pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
 			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
 		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
 	}
 
 	/* Start the EOP fetcher */
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
+	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR,
 	       REG_SET_FIELD(m->cp_hqd_eop_rptr,
 			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
 
 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
+	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
 
 	release_queue(kgd);
 
@@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd,
 		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\
 			break;				\
 		(*dump)[i][0] = (addr) << 2;		\
-		(*dump)[i++][1] = RREG32(addr);		\
+		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\
 	} while (0)
 
 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 	uint32_t low, high;
 
 	acquire_queue(kgd, pipe_id, queue_id);
-	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 	if (act) {
 		low = lower_32_bits(queue_address >> 8);
 		high = upper_32_bits(queue_address >> 8);
 
-		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
-		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
+		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
+		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
 			retval = true;
 	}
 	release_queue(kgd);
@@ -621,11 +621,11 @@ loop:
 	preempt_enable();
 #endif
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
+	WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
 
 	end_jiffies = (utimeout * HZ / 1000) + jiffies;
 	while (true) {
-		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 			break;
 		if (time_after(jiffies, end_jiffies)) {
@@ -716,8 +716,8 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
 
 	mutex_lock(&adev->grbm_idx_mutex);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
+	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
+	WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
 
 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 		INSTANCE_BROADCAST_WRITES, 1);
@@ -726,7 +726,7 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 		SE_BROADCAST_WRITES, 1);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
+	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 	mutex_unlock(&adev->grbm_idx_mutex);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
index d39cff4a1fe3..1f5620cc3570 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
@@ -95,8 +95,8 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
 
 	lock_srbm(kgd, 0, 0, 0, vmid);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
+	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
 	/* APE1 no longer exists on GFX9 */
 
 	unlock_srbm(kgd);
@@ -129,7 +129,7 @@ static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)
 
 	lock_srbm(kgd, mec, pipe, 0, 0);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
 		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 
@@ -212,10 +212,10 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 
 		pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 			mec, pipe, queue_id);
-		value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
+		value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
 		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 			((mec << 5) | (pipe << 3) | queue_id | 0x80));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
+		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
 	}
 
 	/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
@@ -224,13 +224,13 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 
 	for (reg = hqd_base;
 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
-		WREG32(reg, mqd_hqd[reg - hqd_base]);
+		WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
 
 
 	/* Activate doorbell logic before triggering WPTR poll. */
 	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
+	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 
 	if (wptr) {
 		/* Don't read wptr with get_user because the user
@@ -259,17 +259,17 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
 		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
 
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
 		       lower_32_bits(guessed_wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
 		       upper_32_bits(guessed_wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
 		       lower_32_bits((uint64_t)wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 		       upper_32_bits((uint64_t)wptr));
 		pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
 			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
 		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
 	}
 
@@ -279,7 +279,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
 
 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
+	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
 
 	release_queue(kgd);
 
@@ -350,7 +350,7 @@ static int hqd_dump_v10_3(struct kgd_dev *kgd,
 		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\
 			break;				\
 		(*dump)[i][0] = (addr) << 2;		\
-		(*dump)[i++][1] = RREG32(addr);		\
+		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\
 	} while (0)
 
 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -482,13 +482,13 @@ static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address,
 	uint32_t low, high;
 
 	acquire_queue(kgd, pipe_id, queue_id);
-	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 	if (act) {
 		low = lower_32_bits(queue_address >> 8);
 		high = upper_32_bits(queue_address >> 8);
 
-		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
-		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
+		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
+		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
 			retval = true;
 	}
 	release_queue(kgd);
@@ -542,11 +542,11 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
 		break;
 	}
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
+	WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
 
 	end_jiffies = (utimeout * HZ / 1000) + jiffies;
 	while (true) {
-		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 			break;
 		if (time_after(jiffies, end_jiffies)) {
@@ -626,7 +626,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
 
 	mutex_lock(&adev->grbm_idx_mutex);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
+	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
 
 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
@@ -636,7 +636,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 		SE_BROADCAST_WRITES, 1);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
+	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 	mutex_unlock(&adev->grbm_idx_mutex);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index b43e68fc1378..ed3014fbb563 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -719,7 +719,7 @@ static void unlock_spi_csq_mutexes(struct amdgpu_device *adev)
 }
 
 /**
- * @get_wave_count: Read device registers to get number of waves in flight for
+ * get_wave_count: Read device registers to get number of waves in flight for
  * a particular queue. The method also returns the VMID associated with the
  * queue.
  *
@@ -755,19 +755,19 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx,
 }
 
 /**
- * @kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each
+ * kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each
  * shader engine and aggregates the number of waves that are in flight for the
  * process whose pasid is provided as a parameter. The process could have ZERO
  * or more queues running and submitting waves to compute units.
  *
  * @kgd: Handle of device from which to get number of waves in flight
  * @pasid: Identifies the process for which this query call is invoked
- * @wave_cnt: Output parameter updated with number of waves in flight that
+ * @pasid_wave_cnt: Output parameter updated with number of waves in flight that
  * belong to process with given pasid
  * @max_waves_per_cu: Output parameter updated with maximum number of waves
  * possible per Compute Unit
  *
- * @note: It's possible that the device has too many queues (oversubscription)
+ * Note: It's possible that the device has too many queues (oversubscription)
  * in which case a VMID could be remapped to a different PASID. This could lead
  * to an iaccurate wave count. Following is a high-level sequence:
  *    Time T1: vmid = getVmid(); vmid is associated with Pasid P1
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 7d4118c8128a..3b8e1ee8c475 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -33,9 +33,6 @@
 #include <uapi/linux/kfd_ioctl.h>
 #include "amdgpu_xgmi.h"
 
-/* BO flag to indicate a KFD userptr BO */
-#define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
-
 /* Userptr restore delay, just long enough to allow consecutive VM
  * changes to accumulate
  */
@@ -50,12 +47,6 @@ static struct {
 	spinlock_t mem_limit_lock;
 } kfd_mem_limit;
 
-/* Struct used for amdgpu_amdkfd_bo_validate */
-struct amdgpu_vm_parser {
-	uint32_t        domain;
-	bool            wait;
-};
-
 static const char * const domain_bit_to_string[] = {
 		"CPU",
 		"GTT",
@@ -75,16 +66,16 @@ static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 	return (struct amdgpu_device *)kgd;
 }
 
-static bool check_if_add_bo_to_vm(struct amdgpu_vm *avm,
+static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
 		struct kgd_mem *mem)
 {
-	struct kfd_bo_va_list *entry;
+	struct kfd_mem_attachment *entry;
 
-	list_for_each_entry(entry, &mem->bo_va_list, bo_list)
+	list_for_each_entry(entry, &mem->attachments, list)
 		if (entry->bo_va->base.vm == avm)
-			return false;
+			return true;
 
-	return true;
+	return false;
 }
 
 /* Set memory usage limits. Current, limits are
@@ -108,6 +99,11 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
 		(kfd_mem_limit.max_ttm_mem_limit >> 20));
 }
 
+void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
+{
+	kfd_mem_limit.system_mem_used += size;
+}
+
 /* Estimate page table size needed to represent a given memory size
  *
  * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
@@ -217,7 +213,7 @@ void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
 	u32 domain = bo->preferred_domains;
 	bool sg = (bo->preferred_domains == AMDGPU_GEM_DOMAIN_CPU);
 
-	if (bo->flags & AMDGPU_AMDKFD_USERPTR_BO) {
+	if (bo->flags & AMDGPU_AMDKFD_CREATE_USERPTR_BO) {
 		domain = AMDGPU_GEM_DOMAIN_CPU;
 		sg = false;
 	}
@@ -245,7 +241,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
 	if (!ef)
 		return -EINVAL;
 
-	old = dma_resv_get_list(resv);
+	old = dma_resv_shared_list(resv);
 	if (!old)
 		return 0;
 
@@ -276,7 +272,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
 	write_seqcount_end(&resv->seq);
 
 	/* Drop the references to the removed fences or move them to ef_list */
-	for (i = j, k = 0; i < old->shared_count; ++i) {
+	for (i = j; i < old->shared_count; ++i) {
 		struct dma_fence *f;
 
 		f = rcu_dereference_protected(new->shared[i],
@@ -346,11 +342,9 @@ validate_fail:
 	return ret;
 }
 
-static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo)
+static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
 {
-	struct amdgpu_vm_parser *p = param;
-
-	return amdgpu_amdkfd_bo_validate(bo, p->domain, p->wait);
+	return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
 }
 
 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
@@ -362,28 +356,23 @@ static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo)
  */
 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 {
-	struct amdgpu_bo *pd = vm->root.base.bo;
+	struct amdgpu_bo *pd = vm->root.bo;
 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
-	struct amdgpu_vm_parser param;
 	int ret;
 
-	param.domain = AMDGPU_GEM_DOMAIN_VRAM;
-	param.wait = false;
-
-	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,
-					&param);
+	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
 	if (ret) {
 		pr_err("failed to validate PT BOs\n");
 		return ret;
 	}
 
-	ret = amdgpu_amdkfd_validate(&param, pd);
+	ret = amdgpu_amdkfd_validate_vm_bo(NULL, pd);
 	if (ret) {
 		pr_err("failed to validate PD\n");
 		return ret;
 	}
 
-	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
+	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 
 	if (vm->use_cpu_for_update) {
 		ret = amdgpu_bo_kmap(pd, NULL);
@@ -398,7 +387,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 
 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
 {
-	struct amdgpu_bo *pd = vm->root.base.bo;
+	struct amdgpu_bo *pd = vm->root.bo;
 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 	int ret;
 
@@ -431,7 +420,8 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
 				mapping_flags |= coherent ?
 					AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
 			else
-				mapping_flags |= AMDGPU_VM_MTYPE_UC;
+				mapping_flags |= coherent ?
+					AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
 		} else {
 			mapping_flags |= coherent ?
 				AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
@@ -450,7 +440,8 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
 				if (adev->gmc.xgmi.connected_to_cpu)
 					snoop = true;
 			} else {
-				mapping_flags |= AMDGPU_VM_MTYPE_UC;
+				mapping_flags |= coherent ?
+					AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
 				if (amdgpu_xgmi_same_hive(adev, bo_adev))
 					snoop = true;
 			}
@@ -471,87 +462,320 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
 	return pte_flags;
 }
 
-/* add_bo_to_vm - Add a BO to a VM
+static int
+kfd_mem_dmamap_userptr(struct kgd_mem *mem,
+		       struct kfd_mem_attachment *attachment)
+{
+	enum dma_data_direction direction =
+		mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
+	struct ttm_operation_ctx ctx = {.interruptible = true};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+	struct amdgpu_device *adev = attachment->adev;
+	struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
+	struct ttm_tt *ttm = bo->tbo.ttm;
+	int ret;
+
+	ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
+	if (unlikely(!ttm->sg))
+		return -ENOMEM;
+
+	if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
+		return -EINVAL;
+
+	/* Same sequence as in amdgpu_ttm_tt_pin_userptr */
+	ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
+					ttm->num_pages, 0,
+					(u64)ttm->num_pages << PAGE_SHIFT,
+					GFP_KERNEL);
+	if (unlikely(ret))
+		goto free_sg;
+
+	ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
+	if (unlikely(ret))
+		goto release_sg;
+
+	drm_prime_sg_to_dma_addr_array(ttm->sg, ttm->dma_address,
+				       ttm->num_pages);
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
+	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+	if (ret)
+		goto unmap_sg;
+
+	return 0;
+
+unmap_sg:
+	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
+release_sg:
+	pr_err("DMA map userptr failed: %d\n", ret);
+	sg_free_table(ttm->sg);
+free_sg:
+	kfree(ttm->sg);
+	ttm->sg = NULL;
+	return ret;
+}
+
+static int
+kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
+{
+	struct ttm_operation_ctx ctx = {.interruptible = true};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
+	return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+}
+
+static int
+kfd_mem_dmamap_attachment(struct kgd_mem *mem,
+			  struct kfd_mem_attachment *attachment)
+{
+	switch (attachment->type) {
+	case KFD_MEM_ATT_SHARED:
+		return 0;
+	case KFD_MEM_ATT_USERPTR:
+		return kfd_mem_dmamap_userptr(mem, attachment);
+	case KFD_MEM_ATT_DMABUF:
+		return kfd_mem_dmamap_dmabuf(attachment);
+	default:
+		WARN_ON_ONCE(1);
+	}
+	return -EINVAL;
+}
+
+static void
+kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
+			 struct kfd_mem_attachment *attachment)
+{
+	enum dma_data_direction direction =
+		mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
+	struct ttm_operation_ctx ctx = {.interruptible = false};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+	struct amdgpu_device *adev = attachment->adev;
+	struct ttm_tt *ttm = bo->tbo.ttm;
+
+	if (unlikely(!ttm->sg))
+		return;
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
+	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+
+	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
+	sg_free_table(ttm->sg);
+	ttm->sg = NULL;
+}
+
+static void
+kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
+{
+	struct ttm_operation_ctx ctx = {.interruptible = true};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
+	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+}
+
+static void
+kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
+			    struct kfd_mem_attachment *attachment)
+{
+	switch (attachment->type) {
+	case KFD_MEM_ATT_SHARED:
+		break;
+	case KFD_MEM_ATT_USERPTR:
+		kfd_mem_dmaunmap_userptr(mem, attachment);
+		break;
+	case KFD_MEM_ATT_DMABUF:
+		kfd_mem_dmaunmap_dmabuf(attachment);
+		break;
+	default:
+		WARN_ON_ONCE(1);
+	}
+}
+
+static int
+kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem,
+		       struct amdgpu_bo **bo)
+{
+	unsigned long bo_size = mem->bo->tbo.base.size;
+	struct drm_gem_object *gobj;
+	int ret;
+
+	ret = amdgpu_bo_reserve(mem->bo, false);
+	if (ret)
+		return ret;
+
+	ret = amdgpu_gem_object_create(adev, bo_size, 1,
+				       AMDGPU_GEM_DOMAIN_CPU,
+				       AMDGPU_GEM_CREATE_PREEMPTIBLE,
+				       ttm_bo_type_sg, mem->bo->tbo.base.resv,
+				       &gobj);
+	amdgpu_bo_unreserve(mem->bo);
+	if (ret)
+		return ret;
+
+	*bo = gem_to_amdgpu_bo(gobj);
+	(*bo)->parent = amdgpu_bo_ref(mem->bo);
+
+	return 0;
+}
+
+static int
+kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
+		      struct amdgpu_bo **bo)
+{
+	struct drm_gem_object *gobj;
+	int ret;
+
+	if (!mem->dmabuf) {
+		mem->dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base,
+			mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+				DRM_RDWR : 0);
+		if (IS_ERR(mem->dmabuf)) {
+			ret = PTR_ERR(mem->dmabuf);
+			mem->dmabuf = NULL;
+			return ret;
+		}
+	}
+
+	gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
+	if (IS_ERR(gobj))
+		return PTR_ERR(gobj);
+
+	/* Import takes an extra reference on the dmabuf. Drop it now to
+	 * avoid leaking it. We only need the one reference in
+	 * kgd_mem->dmabuf.
+	 */
+	dma_buf_put(mem->dmabuf);
+
+	*bo = gem_to_amdgpu_bo(gobj);
+	(*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
+	(*bo)->parent = amdgpu_bo_ref(mem->bo);
+
+	return 0;
+}
+
+/* kfd_mem_attach - Add a BO to a VM
  *
  * Everything that needs to bo done only once when a BO is first added
  * to a VM. It can later be mapped and unmapped many times without
  * repeating these steps.
  *
+ * 0. Create BO for DMA mapping, if needed
  * 1. Allocate and initialize BO VA entry data structure
  * 2. Add BO to the VM
  * 3. Determine ASIC-specific PTE flags
  * 4. Alloc page tables and directories if needed
  * 4a.  Validate new page tables and directories
  */
-static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem,
-		struct amdgpu_vm *vm, bool is_aql,
-		struct kfd_bo_va_list **p_bo_va_entry)
+static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
+		struct amdgpu_vm *vm, bool is_aql)
 {
-	int ret;
-	struct kfd_bo_va_list *bo_va_entry;
-	struct amdgpu_bo *bo = mem->bo;
+	struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
+	unsigned long bo_size = mem->bo->tbo.base.size;
 	uint64_t va = mem->va;
-	struct list_head *list_bo_va = &mem->bo_va_list;
-	unsigned long bo_size = bo->tbo.base.size;
+	struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
+	struct amdgpu_bo *bo[2] = {NULL, NULL};
+	int i, ret;
 
 	if (!va) {
 		pr_err("Invalid VA when adding BO to VM\n");
 		return -EINVAL;
 	}
 
-	if (is_aql)
-		va += bo_size;
-
-	bo_va_entry = kzalloc(sizeof(*bo_va_entry), GFP_KERNEL);
-	if (!bo_va_entry)
-		return -ENOMEM;
+	for (i = 0; i <= is_aql; i++) {
+		attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
+		if (unlikely(!attachment[i])) {
+			ret = -ENOMEM;
+			goto unwind;
+		}
 
-	pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
-			va + bo_size, vm);
+		pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
+			 va + bo_size, vm);
 
-	/* Add BO to VM internal data structures*/
-	bo_va_entry->bo_va = amdgpu_vm_bo_add(adev, vm, bo);
-	if (!bo_va_entry->bo_va) {
-		ret = -EINVAL;
-		pr_err("Failed to add BO object to VM. ret == %d\n",
-				ret);
-		goto err_vmadd;
-	}
+		if (adev == bo_adev || (mem->domain == AMDGPU_GEM_DOMAIN_VRAM &&
+					amdgpu_xgmi_same_hive(adev, bo_adev))) {
+			/* Mappings on the local GPU and VRAM mappings in the
+			 * local hive share the original BO
+			 */
+			attachment[i]->type = KFD_MEM_ATT_SHARED;
+			bo[i] = mem->bo;
+			drm_gem_object_get(&bo[i]->tbo.base);
+		} else if (i > 0) {
+			/* Multiple mappings on the same GPU share the BO */
+			attachment[i]->type = KFD_MEM_ATT_SHARED;
+			bo[i] = bo[0];
+			drm_gem_object_get(&bo[i]->tbo.base);
+		} else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
+			/* Create an SG BO to DMA-map userptrs on other GPUs */
+			attachment[i]->type = KFD_MEM_ATT_USERPTR;
+			ret = kfd_mem_attach_userptr(adev, mem, &bo[i]);
+			if (ret)
+				goto unwind;
+		} else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT &&
+			   mem->bo->tbo.type != ttm_bo_type_sg) {
+			/* GTT BOs use DMA-mapping ability of dynamic-attach
+			 * DMA bufs. TODO: The same should work for VRAM on
+			 * large-BAR GPUs.
+			 */
+			attachment[i]->type = KFD_MEM_ATT_DMABUF;
+			ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
+			if (ret)
+				goto unwind;
+		} else {
+			/* FIXME: Need to DMA-map other BO types:
+			 * large-BAR VRAM, doorbells, MMIO remap
+			 */
+			attachment[i]->type = KFD_MEM_ATT_SHARED;
+			bo[i] = mem->bo;
+			drm_gem_object_get(&bo[i]->tbo.base);
+		}
 
-	bo_va_entry->va = va;
-	bo_va_entry->pte_flags = get_pte_flags(adev, mem);
-	bo_va_entry->kgd_dev = (void *)adev;
-	list_add(&bo_va_entry->bo_list, list_bo_va);
+		/* Add BO to VM internal data structures */
+		attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
+		if (unlikely(!attachment[i]->bo_va)) {
+			ret = -ENOMEM;
+			pr_err("Failed to add BO object to VM. ret == %d\n",
+			       ret);
+			goto unwind;
+		}
 
-	if (p_bo_va_entry)
-		*p_bo_va_entry = bo_va_entry;
+		attachment[i]->va = va;
+		attachment[i]->pte_flags = get_pte_flags(adev, mem);
+		attachment[i]->adev = adev;
+		list_add(&attachment[i]->list, &mem->attachments);
 
-	/* Allocate validate page tables if needed */
-	ret = vm_validate_pt_pd_bos(vm);
-	if (ret) {
-		pr_err("validate_pt_pd_bos() failed\n");
-		goto err_alloc_pts;
+		va += bo_size;
 	}
 
 	return 0;
 
-err_alloc_pts:
-	amdgpu_vm_bo_rmv(adev, bo_va_entry->bo_va);
-	list_del(&bo_va_entry->bo_list);
-err_vmadd:
-	kfree(bo_va_entry);
+unwind:
+	for (; i >= 0; i--) {
+		if (!attachment[i])
+			continue;
+		if (attachment[i]->bo_va) {
+			amdgpu_vm_bo_rmv(adev, attachment[i]->bo_va);
+			list_del(&attachment[i]->list);
+		}
+		if (bo[i])
+			drm_gem_object_put(&bo[i]->tbo.base);
+		kfree(attachment[i]);
+	}
 	return ret;
 }
 
-static void remove_bo_from_vm(struct amdgpu_device *adev,
-		struct kfd_bo_va_list *entry, unsigned long size)
+static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
 {
-	pr_debug("\t remove VA 0x%llx - 0x%llx in entry %p\n",
-			entry->va,
-			entry->va + size, entry);
-	amdgpu_vm_bo_rmv(adev, entry->bo_va);
-	list_del(&entry->bo_list);
-	kfree(entry);
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+
+	pr_debug("\t remove VA 0x%llx in entry %p\n",
+			attachment->va, attachment);
+	amdgpu_vm_bo_rmv(attachment->adev, attachment->bo_va);
+	drm_gem_object_put(&bo->tbo.base);
+	list_del(&attachment->list);
+	kfree(attachment);
 }
 
 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
@@ -726,7 +950,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
 				struct bo_vm_reservation_context *ctx)
 {
 	struct amdgpu_bo *bo = mem->bo;
-	struct kfd_bo_va_list *entry;
+	struct kfd_mem_attachment *entry;
 	unsigned int i;
 	int ret;
 
@@ -738,7 +962,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
 	INIT_LIST_HEAD(&ctx->list);
 	INIT_LIST_HEAD(&ctx->duplicates);
 
-	list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
+	list_for_each_entry(entry, &mem->attachments, list) {
 		if ((vm && vm != entry->bo_va->base.vm) ||
 			(entry->is_mapped != map_type
 			&& map_type != BO_VM_ALL))
@@ -760,7 +984,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
 	list_add(&ctx->kfd_bo.tv.head, &ctx->list);
 
 	i = 0;
-	list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
+	list_for_each_entry(entry, &mem->attachments, list) {
 		if ((vm && vm != entry->bo_va->base.vm) ||
 			(entry->is_mapped != map_type
 			&& map_type != BO_VM_ALL))
@@ -814,11 +1038,12 @@ static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
 	return ret;
 }
 
-static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
-				struct kfd_bo_va_list *entry,
+static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
+				struct kfd_mem_attachment *entry,
 				struct amdgpu_sync *sync)
 {
 	struct amdgpu_bo_va *bo_va = entry->bo_va;
+	struct amdgpu_device *adev = entry->adev;
 	struct amdgpu_vm *vm = bo_va->base.vm;
 
 	amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
@@ -827,18 +1052,24 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
 
 	amdgpu_sync_fence(sync, bo_va->last_pt_update);
 
-	return 0;
+	kfd_mem_dmaunmap_attachment(mem, entry);
 }
 
-static int update_gpuvm_pte(struct amdgpu_device *adev,
-		struct kfd_bo_va_list *entry,
-		struct amdgpu_sync *sync)
+static int update_gpuvm_pte(struct kgd_mem *mem,
+			    struct kfd_mem_attachment *entry,
+			    struct amdgpu_sync *sync,
+			    bool *table_freed)
 {
-	int ret;
 	struct amdgpu_bo_va *bo_va = entry->bo_va;
+	struct amdgpu_device *adev = entry->adev;
+	int ret;
+
+	ret = kfd_mem_dmamap_attachment(mem, entry);
+	if (ret)
+		return ret;
 
 	/* Update the page tables  */
-	ret = amdgpu_vm_bo_update(adev, bo_va, false);
+	ret = amdgpu_vm_bo_update(adev, bo_va, false, table_freed);
 	if (ret) {
 		pr_err("amdgpu_vm_bo_update failed\n");
 		return ret;
@@ -847,14 +1078,16 @@ static int update_gpuvm_pte(struct amdgpu_device *adev,
 	return amdgpu_sync_fence(sync, bo_va->last_pt_update);
 }
 
-static int map_bo_to_gpuvm(struct amdgpu_device *adev,
-		struct kfd_bo_va_list *entry, struct amdgpu_sync *sync,
-		bool no_update_pte)
+static int map_bo_to_gpuvm(struct kgd_mem *mem,
+			   struct kfd_mem_attachment *entry,
+			   struct amdgpu_sync *sync,
+			   bool no_update_pte,
+			   bool *table_freed)
 {
 	int ret;
 
 	/* Set virtual address for the allocation */
-	ret = amdgpu_vm_bo_map(adev, entry->bo_va, entry->va, 0,
+	ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
 			       amdgpu_bo_size(entry->bo_va->base.bo),
 			       entry->pte_flags);
 	if (ret) {
@@ -866,7 +1099,7 @@ static int map_bo_to_gpuvm(struct amdgpu_device *adev,
 	if (no_update_pte)
 		return 0;
 
-	ret = update_gpuvm_pte(adev, entry, sync);
+	ret = update_gpuvm_pte(mem, entry, sync, table_freed);
 	if (ret) {
 		pr_err("update_gpuvm_pte() failed\n");
 		goto update_gpuvm_pte_failed;
@@ -875,7 +1108,7 @@ static int map_bo_to_gpuvm(struct amdgpu_device *adev,
 	return 0;
 
 update_gpuvm_pte_failed:
-	unmap_bo_from_gpuvm(adev, entry, sync);
+	unmap_bo_from_gpuvm(mem, entry, sync);
 	return ret;
 }
 
@@ -920,7 +1153,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
 
 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
 			    vm_list_node) {
-		struct amdgpu_bo *pd = peer_vm->root.base.bo;
+		struct amdgpu_bo *pd = peer_vm->root.bo;
 
 		ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
 				       AMDGPU_SYNC_NE_OWNER,
@@ -967,7 +1200,8 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
 
 		info->eviction_fence =
 			amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
-						   current->mm);
+						   current->mm,
+						   NULL);
 		if (!info->eviction_fence) {
 			pr_err("Failed to create eviction fence\n");
 			ret = -ENOMEM;
@@ -986,7 +1220,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
 	vm->process_info = *process_info;
 
 	/* Validate page directory and attach eviction fence */
-	ret = amdgpu_bo_reserve(vm->root.base.bo, true);
+	ret = amdgpu_bo_reserve(vm->root.bo, true);
 	if (ret)
 		goto reserve_pd_fail;
 	ret = vm_validate_pt_pd_bos(vm);
@@ -994,16 +1228,16 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
 		pr_err("validate_pt_pd_bos() failed\n");
 		goto validate_pd_fail;
 	}
-	ret = amdgpu_bo_sync_wait(vm->root.base.bo,
+	ret = amdgpu_bo_sync_wait(vm->root.bo,
 				  AMDGPU_FENCE_OWNER_KFD, false);
 	if (ret)
 		goto wait_pd_fail;
-	ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);
+	ret = dma_resv_reserve_shared(vm->root.bo->tbo.base.resv, 1);
 	if (ret)
 		goto reserve_shared_fail;
-	amdgpu_bo_fence(vm->root.base.bo,
+	amdgpu_bo_fence(vm->root.bo,
 			&vm->process_info->eviction_fence->base, true);
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 
 	/* Update process info */
 	mutex_lock(&vm->process_info->lock);
@@ -1017,7 +1251,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
 reserve_shared_fail:
 wait_pd_fail:
 validate_pd_fail:
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 reserve_pd_fail:
 	vm->process_info = NULL;
 	if (info) {
@@ -1036,15 +1270,19 @@ create_evict_fence_fail:
 
 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
 					   struct file *filp, u32 pasid,
-					   void **vm, void **process_info,
+					   void **process_info,
 					   struct dma_fence **ef)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	struct drm_file *drm_priv = filp->private_data;
-	struct amdgpu_fpriv *drv_priv = drm_priv->driver_priv;
-	struct amdgpu_vm *avm = &drv_priv->vm;
+	struct amdgpu_fpriv *drv_priv;
+	struct amdgpu_vm *avm;
 	int ret;
 
+	ret = amdgpu_file_to_fpriv(filp, &drv_priv);
+	if (ret)
+		return ret;
+	avm = &drv_priv->vm;
+
 	/* Already a compute VM? */
 	if (avm->process_info)
 		return -EINVAL;
@@ -1059,7 +1297,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
 	if (ret)
 		return ret;
 
-	*vm = (void *)avm;
+	amdgpu_vm_set_task_info(avm);
 
 	return 0;
 }
@@ -1068,7 +1306,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 				    struct amdgpu_vm *vm)
 {
 	struct amdkfd_process_info *process_info = vm->process_info;
-	struct amdgpu_bo *pd = vm->root.base.bo;
+	struct amdgpu_bo *pd = vm->root.bo;
 
 	if (!process_info)
 		return;
@@ -1100,15 +1338,17 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 	}
 }
 
-void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
+void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
+	struct amdgpu_vm *avm;
 
-	if (WARN_ON(!kgd || !vm))
+	if (WARN_ON(!kgd || !drm_priv))
 		return;
 
-	pr_debug("Releasing process vm %p\n", vm);
+	avm = drm_priv_to_vm(drm_priv);
+
+	pr_debug("Releasing process vm %p\n", avm);
 
 	/* The original pasid of amdgpu vm has already been
 	 * released during making a amdgpu vm to a compute vm
@@ -1119,10 +1359,10 @@ void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
 	amdgpu_vm_release_compute(adev, avm);
 }
 
-uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm)
+uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
 {
-	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
-	struct amdgpu_bo *pd = avm->root.base.bo;
+	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
+	struct amdgpu_bo *pd = avm->root.bo;
 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 
 	if (adev->asic_type < CHIP_VEGA10)
@@ -1132,11 +1372,11 @@ uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm)
 
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		struct kgd_dev *kgd, uint64_t va, uint64_t size,
-		void *vm, struct kgd_mem **mem,
+		void *drm_priv, struct kgd_mem **mem,
 		uint64_t *offset, uint32_t flags)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
+	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
 	enum ttm_bo_type bo_type = ttm_bo_type_device;
 	struct sg_table *sg = NULL;
 	uint64_t user_addr = 0;
@@ -1161,7 +1401,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 	} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
 		domain = AMDGPU_GEM_DOMAIN_GTT;
 		alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
-		alloc_flags = 0;
+		alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
 		if (!offset || !*offset)
 			return -EINVAL;
 		user_addr = untagged_addr(*offset);
@@ -1185,7 +1425,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		ret = -ENOMEM;
 		goto err;
 	}
-	INIT_LIST_HEAD(&(*mem)->bo_va_list);
+	INIT_LIST_HEAD(&(*mem)->attachments);
 	mutex_init(&(*mem)->lock);
 	(*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
 
@@ -1216,6 +1456,11 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 			 domain_string(alloc_domain), ret);
 		goto err_bo_create;
 	}
+	ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
+	if (ret) {
+		pr_debug("Failed to allow vma node access. ret %d\n", ret);
+		goto err_node_allow;
+	}
 	bo = gem_to_amdgpu_bo(gobj);
 	if (bo_type == ttm_bo_type_sg) {
 		bo->tbo.sg = sg;
@@ -1224,7 +1469,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 	bo->kfd_bo = *mem;
 	(*mem)->bo = bo;
 	if (user_addr)
-		bo->flags |= AMDGPU_AMDKFD_USERPTR_BO;
+		bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
 
 	(*mem)->va = va;
 	(*mem)->domain = domain;
@@ -1245,6 +1490,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 
 allocate_init_user_pages_failed:
 	remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
+	drm_vma_node_revoke(&gobj->vma_node, drm_priv);
+err_node_allow:
 	amdgpu_bo_unref(&bo);
 	/* Don't unreserve system mem limit twice */
 	goto err_reserve_limit;
@@ -1262,11 +1509,12 @@ err:
 }
 
 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size)
+		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
+		uint64_t *size)
 {
 	struct amdkfd_process_info *process_info = mem->process_info;
 	unsigned long bo_size = mem->bo->tbo.base.size;
-	struct kfd_bo_va_list *entry, *tmp;
+	struct kfd_mem_attachment *entry, *tmp;
 	struct bo_vm_reservation_context ctx;
 	struct ttm_validate_buffer *bo_list_entry;
 	unsigned int mapped_to_gpu_memory;
@@ -1309,13 +1557,12 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 	pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
 		mem->va + bo_size * (1 + mem->aql_queue));
 
-	/* Remove from VM internal data structures */
-	list_for_each_entry_safe(entry, tmp, &mem->bo_va_list, bo_list)
-		remove_bo_from_vm((struct amdgpu_device *)entry->kgd_dev,
-				entry, bo_size);
-
 	ret = unreserve_bo_and_vms(&ctx, false, false);
 
+	/* Remove from VM internal data structures */
+	list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
+		kfd_mem_detach(entry);
+
 	/* Free the sync object */
 	amdgpu_sync_free(&mem->sync);
 
@@ -1339,6 +1586,9 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 	}
 
 	/* Free the BO*/
+	drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
+	if (mem->dmabuf)
+		dma_buf_put(mem->dmabuf);
 	drm_gem_object_put(&mem->bo->tbo.base);
 	mutex_destroy(&mem->lock);
 	kfree(mem);
@@ -1347,17 +1597,16 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 }
 
 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, void *vm)
+		struct kgd_dev *kgd, struct kgd_mem *mem,
+		void *drm_priv, bool *table_freed)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
+	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
 	int ret;
 	struct amdgpu_bo *bo;
 	uint32_t domain;
-	struct kfd_bo_va_list *entry;
+	struct kfd_mem_attachment *entry;
 	struct bo_vm_reservation_context ctx;
-	struct kfd_bo_va_list *bo_va_entry = NULL;
-	struct kfd_bo_va_list *bo_va_entry_aql = NULL;
 	unsigned long bo_size;
 	bool is_invalid_userptr = false;
 
@@ -1391,9 +1640,15 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
 	pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
 			mem->va,
 			mem->va + bo_size * (1 + mem->aql_queue),
-			vm, domain_string(domain));
+			avm, domain_string(domain));
 
-	ret = reserve_bo_and_vm(mem, vm, &ctx);
+	if (!kfd_mem_is_attached(avm, mem)) {
+		ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
+		if (ret)
+			goto out;
+	}
+
+	ret = reserve_bo_and_vm(mem, avm, &ctx);
 	if (unlikely(ret))
 		goto out;
 
@@ -1403,25 +1658,12 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
 	 * the next restore worker
 	 */
 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
-	    bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
+	    bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
 		is_invalid_userptr = true;
 
-	if (check_if_add_bo_to_vm(avm, mem)) {
-		ret = add_bo_to_vm(adev, mem, avm, false,
-				&bo_va_entry);
-		if (ret)
-			goto add_bo_to_vm_failed;
-		if (mem->aql_queue) {
-			ret = add_bo_to_vm(adev, mem, avm,
-					true, &bo_va_entry_aql);
-			if (ret)
-				goto add_bo_to_vm_failed_aql;
-		}
-	} else {
-		ret = vm_validate_pt_pd_bos(avm);
-		if (unlikely(ret))
-			goto add_bo_to_vm_failed;
-	}
+	ret = vm_validate_pt_pd_bos(avm);
+	if (unlikely(ret))
+		goto out_unreserve;
 
 	if (mem->mapped_to_gpu_memory == 0 &&
 	    !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
@@ -1432,34 +1674,34 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
 		ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
 		if (ret) {
 			pr_debug("Validate failed\n");
-			goto map_bo_to_gpuvm_failed;
+			goto out_unreserve;
 		}
 	}
 
-	list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
-		if (entry->bo_va->base.vm == vm && !entry->is_mapped) {
-			pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
-					entry->va, entry->va + bo_size,
-					entry);
+	list_for_each_entry(entry, &mem->attachments, list) {
+		if (entry->bo_va->base.vm != avm || entry->is_mapped)
+			continue;
 
-			ret = map_bo_to_gpuvm(adev, entry, ctx.sync,
-					      is_invalid_userptr);
-			if (ret) {
-				pr_err("Failed to map bo to gpuvm\n");
-				goto map_bo_to_gpuvm_failed;
-			}
+		pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
+			 entry->va, entry->va + bo_size, entry);
 
-			ret = vm_update_pds(vm, ctx.sync);
-			if (ret) {
-				pr_err("Failed to update page directories\n");
-				goto map_bo_to_gpuvm_failed;
-			}
+		ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
+				      is_invalid_userptr, table_freed);
+		if (ret) {
+			pr_err("Failed to map bo to gpuvm\n");
+			goto out_unreserve;
+		}
 
-			entry->is_mapped = true;
-			mem->mapped_to_gpu_memory++;
-			pr_debug("\t INC mapping count %d\n",
-					mem->mapped_to_gpu_memory);
+		ret = vm_update_pds(avm, ctx.sync);
+		if (ret) {
+			pr_err("Failed to update page directories\n");
+			goto out_unreserve;
 		}
+
+		entry->is_mapped = true;
+		mem->mapped_to_gpu_memory++;
+		pr_debug("\t INC mapping count %d\n",
+			 mem->mapped_to_gpu_memory);
 	}
 
 	if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
@@ -1470,13 +1712,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
 
 	goto out;
 
-map_bo_to_gpuvm_failed:
-	if (bo_va_entry_aql)
-		remove_bo_from_vm(adev, bo_va_entry_aql, bo_size);
-add_bo_to_vm_failed_aql:
-	if (bo_va_entry)
-		remove_bo_from_vm(adev, bo_va_entry, bo_size);
-add_bo_to_vm_failed:
+out_unreserve:
 	unreserve_bo_and_vms(&ctx, false, false);
 out:
 	mutex_unlock(&mem->process_info->lock);
@@ -1485,19 +1721,18 @@ out:
 }
 
 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, void *vm)
+		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
 {
-	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	struct amdkfd_process_info *process_info =
-		((struct amdgpu_vm *)vm)->process_info;
+	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
+	struct amdkfd_process_info *process_info = avm->process_info;
 	unsigned long bo_size = mem->bo->tbo.base.size;
-	struct kfd_bo_va_list *entry;
+	struct kfd_mem_attachment *entry;
 	struct bo_vm_reservation_context ctx;
 	int ret;
 
 	mutex_lock(&mem->lock);
 
-	ret = reserve_bo_and_cond_vms(mem, vm, BO_VM_MAPPED, &ctx);
+	ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
 	if (unlikely(ret))
 		goto out;
 	/* If no VMs were reserved, it means the BO wasn't actually mapped */
@@ -1506,35 +1741,28 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
 		goto unreserve_out;
 	}
 
-	ret = vm_validate_pt_pd_bos((struct amdgpu_vm *)vm);
+	ret = vm_validate_pt_pd_bos(avm);
 	if (unlikely(ret))
 		goto unreserve_out;
 
 	pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
 		mem->va,
 		mem->va + bo_size * (1 + mem->aql_queue),
-		vm);
-
-	list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
-		if (entry->bo_va->base.vm == vm && entry->is_mapped) {
-			pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
-					entry->va,
-					entry->va + bo_size,
-					entry);
-
-			ret = unmap_bo_from_gpuvm(adev, entry, ctx.sync);
-			if (ret == 0) {
-				entry->is_mapped = false;
-			} else {
-				pr_err("failed to unmap VA 0x%llx\n",
-						mem->va);
-				goto unreserve_out;
-			}
+		avm);
 
-			mem->mapped_to_gpu_memory--;
-			pr_debug("\t DEC mapping count %d\n",
-					mem->mapped_to_gpu_memory);
-		}
+	list_for_each_entry(entry, &mem->attachments, list) {
+		if (entry->bo_va->base.vm != avm || !entry->is_mapped)
+			continue;
+
+		pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
+			 entry->va, entry->va + bo_size, entry);
+
+		unmap_bo_from_gpuvm(mem, entry, ctx.sync);
+		entry->is_mapped = false;
+
+		mem->mapped_to_gpu_memory--;
+		pr_debug("\t DEC mapping count %d\n",
+			 mem->mapped_to_gpu_memory);
 	}
 
 	/* If BO is unmapped from all VMs, unfence it. It can be evicted if
@@ -1642,14 +1870,15 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
 
 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 				      struct dma_buf *dma_buf,
-				      uint64_t va, void *vm,
+				      uint64_t va, void *drm_priv,
 				      struct kgd_mem **mem, uint64_t *size,
 				      uint64_t *mmap_offset)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
 	struct drm_gem_object *obj;
 	struct amdgpu_bo *bo;
-	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
+	int ret;
 
 	if (dma_buf->ops != &amdgpu_dmabuf_ops)
 		/* Can't handle non-graphics buffers */
@@ -1670,13 +1899,19 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 	if (!*mem)
 		return -ENOMEM;
 
+	ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
+	if (ret) {
+		kfree(mem);
+		return ret;
+	}
+
 	if (size)
 		*size = amdgpu_bo_size(bo);
 
 	if (mmap_offset)
 		*mmap_offset = amdgpu_bo_mmap_offset(bo);
 
-	INIT_LIST_HEAD(&(*mem)->bo_va_list);
+	INIT_LIST_HEAD(&(*mem)->attachments);
 	mutex_init(&(*mem)->lock);
 
 	(*mem)->alloc_flags =
@@ -1873,7 +2108,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
 	list_for_each_entry_safe(mem, tmp_mem,
 				 &process_info->userptr_inval_list,
 				 validate_list.head) {
-		struct kfd_bo_va_list *bo_va_entry;
+		struct kfd_mem_attachment *attachment;
 
 		bo = mem->bo;
 
@@ -1896,13 +2131,12 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
 		 * VM faults if the GPU tries to access the invalid
 		 * memory.
 		 */
-		list_for_each_entry(bo_va_entry, &mem->bo_va_list, bo_list) {
-			if (!bo_va_entry->is_mapped)
+		list_for_each_entry(attachment, &mem->attachments, list) {
+			if (!attachment->is_mapped)
 				continue;
 
-			ret = update_gpuvm_pte((struct amdgpu_device *)
-					       bo_va_entry->kgd_dev,
-					       bo_va_entry, &sync);
+			kfd_mem_dmaunmap_attachment(mem, attachment);
+			ret = update_gpuvm_pte(mem, attachment, &sync, NULL);
 			if (ret) {
 				pr_err("%s: update PTE failed\n", __func__);
 				/* make sure this gets validated again */
@@ -2083,7 +2317,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
 
 		struct amdgpu_bo *bo = mem->bo;
 		uint32_t domain = mem->domain;
-		struct kfd_bo_va_list *bo_va_entry;
+		struct kfd_mem_attachment *attachment;
 
 		total_size += amdgpu_bo_size(bo);
 
@@ -2103,12 +2337,12 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
 			pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
 			goto validate_map_fail;
 		}
-		list_for_each_entry(bo_va_entry, &mem->bo_va_list,
-				    bo_list) {
-			ret = update_gpuvm_pte((struct amdgpu_device *)
-					      bo_va_entry->kgd_dev,
-					      bo_va_entry,
-					      &sync_obj);
+		list_for_each_entry(attachment, &mem->attachments, list) {
+			if (!attachment->is_mapped)
+				continue;
+
+			kfd_mem_dmaunmap_attachment(mem, attachment);
+			ret = update_gpuvm_pte(mem, attachment, &sync_obj, NULL);
 			if (ret) {
 				pr_debug("Memory eviction: update PTE failed. Try again\n");
 				goto validate_map_fail;
@@ -2135,7 +2369,8 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
 	 */
 	new_fence = amdgpu_amdkfd_fence_create(
 				process_info->eviction_fence->base.context,
-				process_info->eviction_fence->mm);
+				process_info->eviction_fence->mm,
+				NULL);
 	if (!new_fence) {
 		pr_err("Failed to create eviction fence\n");
 		ret = -ENOMEM;
@@ -2154,7 +2389,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
 	/* Attach eviction fence to PD / PT BOs */
 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
 			    vm_list_node) {
-		struct amdgpu_bo *bo = peer_vm->root.base.bo;
+		struct amdgpu_bo *bo = peer_vm->root.bo;
 
 		amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
 	}
@@ -2182,7 +2417,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem
 		return -ENOMEM;
 
 	mutex_init(&(*mem)->lock);
-	INIT_LIST_HEAD(&(*mem)->bo_va_list);
+	INIT_LIST_HEAD(&(*mem)->attachments);
 	(*mem)->bo = amdgpu_bo_ref(gws_bo);
 	(*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
 	(*mem)->process_info = process_info;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 494b2e1717d5..96b7bb13a2dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1768,6 +1768,15 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
 		   NULL);
 
+static struct attribute *amdgpu_vbios_version_attrs[] = {
+	&dev_attr_vbios_version.attr,
+	NULL
+};
+
+const struct attribute_group amdgpu_vbios_version_attr_group = {
+	.attrs = amdgpu_vbios_version_attrs
+};
+
 /**
  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
  *
@@ -1787,7 +1796,6 @@ void amdgpu_atombios_fini(struct amdgpu_device *adev)
 	adev->mode_info.atom_context = NULL;
 	kfree(adev->mode_info.atom_card_info);
 	adev->mode_info.atom_card_info = NULL;
-	device_remove_file(adev->dev, &dev_attr_vbios_version);
 }
 
 /**
@@ -1804,7 +1812,6 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
 {
 	struct card_info *atom_card_info =
 	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
-	int ret;
 
 	if (!atom_card_info)
 		return -ENOMEM;
@@ -1828,17 +1835,14 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
 	if (adev->is_atom_fw) {
 		amdgpu_atomfirmware_scratch_regs_init(adev);
 		amdgpu_atomfirmware_allocate_fb_scratch(adev);
+		/* cached firmware_flags for further usage */
+		adev->mode_info.firmware_flags =
+			amdgpu_atomfirmware_query_firmware_capability(adev);
 	} else {
 		amdgpu_atombios_scratch_regs_init(adev);
 		amdgpu_atombios_allocate_fb_scratch(adev);
 	}
 
-	ret = device_create_file(adev->dev, &dev_attr_vbios_version);
-	if (ret) {
-		DRM_ERROR("Failed to create device file for VBIOS version\n");
-		return ret;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 60716b35444b..3b5d13189073 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -29,23 +29,59 @@
 #include "atombios.h"
 #include "soc15_hw_ip.h"
 
-bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
+union firmware_info {
+	struct atom_firmware_info_v3_1 v31;
+	struct atom_firmware_info_v3_2 v32;
+	struct atom_firmware_info_v3_3 v33;
+	struct atom_firmware_info_v3_4 v34;
+};
+
+/*
+ * Helper function to query firmware capability
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Return firmware_capability in firmwareinfo table on success or 0 if not
+ */
+uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
 {
-	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
-						firmwareinfo);
-	uint16_t data_offset;
+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+	int index;
+	u16 data_offset, size;
+	union firmware_info *firmware_info;
+	u8 frev, crev;
+	u32 fw_cap = 0;
 
-	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
-					  NULL, NULL, &data_offset)) {
-		struct atom_firmware_info_v3_1 *firmware_info =
-			(struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
-							   data_offset);
+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+			firmwareinfo);
 
-		if (le32_to_cpu(firmware_info->firmware_capability) &
-		    ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
-			return true;
+	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
+				index, &size, &frev, &crev, &data_offset)) {
+		/* support firmware_info 3.1 + */
+		if ((frev == 3 && crev >=1) || (frev > 3)) {
+			firmware_info = (union firmware_info *)
+				(mode_info->atom_context->bios + data_offset);
+			fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
+		}
 	}
-	return false;
+
+	return fw_cap;
+}
+
+/*
+ * Helper function to query gpu virtualizaiton capability
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Return true if gpu virtualization is supported or false if not
+ */
+bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
+{
+	u32 fw_cap;
+
+	fw_cap = adev->mode_info.firmware_flags;
+
+	return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
 }
 
 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
@@ -400,41 +436,36 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 	return ecc_default_enabled;
 }
 
-union firmware_info {
-	struct atom_firmware_info_v3_1 v31;
-	struct atom_firmware_info_v3_2 v32;
-	struct atom_firmware_info_v3_3 v33;
-	struct atom_firmware_info_v3_4 v34;
-};
-
 /*
+ * Helper function to query sram ecc capablity
+ *
+ * @adev: amdgpu_device pointer
+ *
  * Return true if vbios supports sram ecc or false if not
  */
 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 {
-	struct amdgpu_mode_info *mode_info = &adev->mode_info;
-	int index;
-	u16 data_offset, size;
-	union firmware_info *firmware_info;
-	u8 frev, crev;
-	bool sram_ecc_supported = false;
+	u32 fw_cap;
 
-	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
-			firmwareinfo);
+	fw_cap = adev->mode_info.firmware_flags;
 
-	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
-				index, &size, &frev, &crev, &data_offset)) {
-		/* support firmware_info 3.1 + */
-		if ((frev == 3 && crev >=1) || (frev > 3)) {
-			firmware_info = (union firmware_info *)
-				(mode_info->atom_context->bios + data_offset);
-			sram_ecc_supported =
-				(le32_to_cpu(firmware_info->v31.firmware_capability) &
-				 ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
-		}
-	}
+	return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
+}
 
-	return sram_ecc_supported;
+/*
+ * Helper function to query dynamic boot config capability
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Return true if vbios supports dynamic boot config or false if not
+ */
+bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
+{
+	u32 fw_cap;
+
+	fw_cap = adev->mode_info.firmware_flags;
+
+	return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
 }
 
 union smu_info {
@@ -466,10 +497,6 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 		adev->pm.current_sclk = adev->clock.default_sclk;
 		adev->pm.current_mclk = adev->clock.default_mclk;
 
-		/* not technically a clock, but... */
-		adev->mode_info.firmware_flags =
-			le32_to_cpu(firmware_info->v31.firmware_capability);
-
 		ret = 0;
 	}
 
@@ -519,6 +546,21 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 		ret = 0;
 	}
 
+	/* if asic is Navi+, the rlc reference clock is used for system clock
+	 * from vbios gfx_info table */
+	if (adev->asic_type >= CHIP_NAVI10) {
+		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+						   gfx_info);
+		if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
+					  &frev, &crev, &data_offset)) {
+			struct atom_gfx_info_v2_2 *gfx_info = (struct atom_gfx_info_v2_2*)
+				(mode_info->atom_context->bios + data_offset);
+			if ((frev == 2) && (crev >= 2))
+				spll->reference_freq = le32_to_cpu(gfx_info->rlc_gpu_timer_refclk);
+			ret = 0;
+		}
+	}
+
 	return ret;
 }
 
@@ -584,67 +626,19 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 }
 
 /*
- * Check if VBIOS supports GDDR6 training data save/restore
+ * Helper function to query two stage mem training capability
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Return true if two stage mem training is supported or false if not
  */
-static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
+bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
 {
-	uint16_t data_offset;
-	int index;
-
-	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
-					    firmwareinfo);
-	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
-					  NULL, NULL, &data_offset)) {
-		struct atom_firmware_info_v3_1 *firmware_info =
-			(struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
-							   data_offset);
-
-		DRM_DEBUG("atom firmware capability:0x%08x.\n",
-			  le32_to_cpu(firmware_info->firmware_capability));
+	u32 fw_cap;
 
-		if (le32_to_cpu(firmware_info->firmware_capability) &
-		    ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
-			return true;
-	}
+	fw_cap = adev->mode_info.firmware_flags;
 
-	return false;
-}
-
-int amdgpu_mem_train_support(struct amdgpu_device *adev)
-{
-	int ret;
-	uint32_t major, minor, revision, hw_v;
-
-	if (gddr6_mem_train_vbios_support(adev)) {
-		amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
-		hw_v = HW_REV(major, minor, revision);
-		/*
-		 * treat 0 revision as a special case since register for MP0 and MMHUB is missing
-		 * for some Navi10 A0, preventing driver from discovering the hwip information since
-		 * none of the functions will be initialized, it should not cause any problems
-		 */
-		switch (hw_v) {
-		case HW_REV(11, 0, 0):
-		case HW_REV(11, 0, 5):
-		case HW_REV(11, 0, 7):
-		case HW_REV(11, 0, 11):
-		case HW_REV(11, 0, 12):
-			ret = 1;
-			break;
-		default:
-			DRM_ERROR("memory training vbios supports but psp hw(%08x)"
-				  " doesn't support!\n", hw_v);
-			ret = -1;
-			break;
-		}
-	} else {
-		ret = 0;
-		hw_v = -1;
-	}
-
-
-	DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
-	return ret;
+	return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
 }
 
 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index 9f0d4356e8df..1bbbb195015d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -26,7 +26,8 @@
 
 #define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
 
-bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev);
+uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev);
+bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev);
 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
@@ -35,7 +36,8 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev);
+bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev);
+bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev);
-int amdgpu_mem_train_support(struct amdgpu_device *adev);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b5c766998045..76fe5b71e35d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -396,10 +396,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 	spin_unlock(&adev->mm_stats.lock);
 }
 
-static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
-				 struct amdgpu_bo *bo)
+static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+	struct amdgpu_cs_parser *p = param;
 	struct ttm_operation_ctx ctx = {
 		.interruptible = true,
 		.no_wait_gpu = false,
@@ -451,21 +451,6 @@ retry:
 	return r;
 }
 
-static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
-{
-	struct amdgpu_cs_parser *p = param;
-	int r;
-
-	r = amdgpu_cs_bo_validate(p, bo);
-	if (r)
-		return r;
-
-	if (bo->shadow)
-		r = amdgpu_cs_bo_validate(p, bo->shadow);
-
-	return r;
-}
-
 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 			    struct list_head *validated)
 {
@@ -493,7 +478,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 						     lobj->user_pages);
 		}
 
-		r = amdgpu_cs_validate(p, bo);
+		r = amdgpu_cs_bo_validate(p, bo);
 		if (r)
 			return r;
 
@@ -593,7 +578,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 	p->bytes_moved_vis = 0;
 
 	r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
-				      amdgpu_cs_validate, p);
+				      amdgpu_cs_bo_validate, p);
 	if (r) {
 		DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 		goto error_validate;
@@ -672,12 +657,12 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 }
 
 /**
- * cs_parser_fini() - clean parser states
+ * amdgpu_cs_parser_fini() - clean parser states
  * @parser:	parser structure holding parsing context.
  * @error:	error number
  * @backoff:	indicator to backoff the reservation
  *
- * If error is set than unvalidate buffer, otherwise just free memory
+ * If error is set then unvalidate buffer, otherwise just free memory
  * used by parsing context.
  **/
 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
@@ -796,7 +781,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 	if (r)
 		return r;
 
-	r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
+	r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
 	if (r)
 		return r;
 
@@ -807,7 +792,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 	if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 		bo_va = fpriv->csa_va;
 		BUG_ON(!bo_va);
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			return r;
 
@@ -826,7 +811,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 		if (bo_va == NULL)
 			continue;
 
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			return r;
 
@@ -847,7 +832,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 	if (r)
 		return r;
 
-	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
+	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 
 	if (amdgpu_vm_debug) {
 		/* Invalidate all BOs to test for userspace bugs */
@@ -1488,7 +1473,7 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
 }
 
 /**
- * amdgpu_cs_wait_all_fence - wait on all fences to signal
+ * amdgpu_cs_wait_all_fences - wait on all fences to signal
  *
  * @adev: amdgpu device
  * @filp: file private
@@ -1639,7 +1624,7 @@ err_free_fences:
 }
 
 /**
- * amdgpu_cs_find_bo_va - find bo_va for VM address
+ * amdgpu_cs_find_mapping - find bo_va for VM address
  *
  * @parser: command submission parser context
  * @addr: VM address
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 6819fe5612d9..e7a010b7ca1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
 	return 0;
 }
 
+#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
+
 static int amdgpu_ctx_query2(struct amdgpu_device *adev,
-	struct amdgpu_fpriv *fpriv, uint32_t id,
-	union drm_amdgpu_ctx_out *out)
+			     struct amdgpu_fpriv *fpriv, uint32_t id,
+			     union drm_amdgpu_ctx_out *out)
 {
+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct amdgpu_ctx *ctx;
 	struct amdgpu_ctx_mgr *mgr;
 
@@ -361,6 +364,30 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
 	if (atomic_read(&ctx->guilty))
 		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
 
+	if (adev->ras_enabled && con) {
+		/* Return the cached values in O(1),
+		 * and schedule delayed work to cache
+		 * new vaues.
+		 */
+		int ce_count, ue_count;
+
+		ce_count = atomic_read(&con->ras_ce_count);
+		ue_count = atomic_read(&con->ras_ue_count);
+
+		if (ce_count != ctx->ras_counter_ce) {
+			ctx->ras_counter_ce = ce_count;
+			out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
+		}
+
+		if (ue_count != ctx->ras_counter_ue) {
+			ctx->ras_counter_ue = ue_count;
+			out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
+		}
+
+		schedule_delayed_work(&con->ras_counte_delay_work,
+				      msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
+	}
+
 	mutex_unlock(&mgr->lock);
 	return 0;
 }
@@ -635,3 +662,81 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
 	idr_destroy(&mgr->ctx_handles);
 	mutex_destroy(&mgr->lock);
 }
+
+static void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx,
+		struct amdgpu_ctx_entity *centity, ktime_t *total, ktime_t *max)
+{
+	ktime_t now, t1;
+	uint32_t i;
+
+	*total = *max = 0;
+
+	now = ktime_get();
+	for (i = 0; i < amdgpu_sched_jobs; i++) {
+		struct dma_fence *fence;
+		struct drm_sched_fence *s_fence;
+
+		spin_lock(&ctx->ring_lock);
+		fence = dma_fence_get(centity->fences[i]);
+		spin_unlock(&ctx->ring_lock);
+		if (!fence)
+			continue;
+		s_fence = to_drm_sched_fence(fence);
+		if (!dma_fence_is_signaled(&s_fence->scheduled)) {
+			dma_fence_put(fence);
+			continue;
+		}
+		t1 = s_fence->scheduled.timestamp;
+		if (!ktime_before(t1, now)) {
+			dma_fence_put(fence);
+			continue;
+		}
+		if (dma_fence_is_signaled(&s_fence->finished) &&
+			s_fence->finished.timestamp < now)
+			*total += ktime_sub(s_fence->finished.timestamp, t1);
+		else
+			*total += ktime_sub(now, t1);
+		t1 = ktime_sub(now, t1);
+		dma_fence_put(fence);
+		*max = max(t1, *max);
+	}
+}
+
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+		uint32_t idx, uint64_t *elapsed)
+{
+	struct idr *idp;
+	struct amdgpu_ctx *ctx;
+	uint32_t id;
+	struct amdgpu_ctx_entity *centity;
+	ktime_t total = 0, max = 0;
+
+	if (idx >= AMDGPU_MAX_ENTITY_NUM)
+		return 0;
+	idp = &mgr->ctx_handles;
+	mutex_lock(&mgr->lock);
+	idr_for_each_entry(idp, ctx, id) {
+		ktime_t ttotal, tmax;
+
+		if (!ctx->entities[hwip][idx])
+			continue;
+
+		centity = ctx->entities[hwip][idx];
+		amdgpu_ctx_fence_time(ctx, centity, &ttotal, &tmax);
+
+		/* Harmonic mean approximation diverges for very small
+		 * values. If ratio < 0.01% ignore
+		 */
+		if (AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(tmax, ttotal))
+			continue;
+
+		total = ktime_add(total, ttotal);
+		max = ktime_after(tmax, max) ? tmax : max;
+	}
+
+	mutex_unlock(&mgr->lock);
+	if (elapsed)
+		*elapsed = max;
+
+	return total;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index f54e10314661..14db16bc3322 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -30,6 +30,7 @@ struct drm_file;
 struct amdgpu_fpriv;
 
 #define AMDGPU_MAX_ENTITY_NUM 4
+#define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total))
 
 struct amdgpu_ctx_entity {
 	uint64_t		sequence;
@@ -87,5 +88,6 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
-
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+		uint32_t idx, uint64_t *elapsed);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index bcaf271b39bf..536005bff24a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -990,7 +990,7 @@ err:
 }
 
 /**
- * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
+ * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
  *
  * @f: open file handle
  * @buf: User buffer to write data from
@@ -1041,7 +1041,7 @@ static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *bu
 
 
 /**
- * amdgpu_debugfs_regs_gfxoff_status - read gfxoff status
+ * amdgpu_debugfs_gfxoff_read - read gfxoff status
  *
  * @f: open file handle
  * @buf: User buffer to store read data in
@@ -1304,11 +1304,11 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
 
 		seq_printf(m, "pid:%d\tProcess:%s ----------\n",
 				vm->task_info.pid, vm->task_info.process_name);
-		r = amdgpu_bo_reserve(vm->root.base.bo, true);
+		r = amdgpu_bo_reserve(vm->root.bo, true);
 		if (r)
 			break;
 		amdgpu_debugfs_vm_bo_info(vm, m);
-		amdgpu_bo_unreserve(vm->root.base.bo);
+		amdgpu_bo_unreserve(vm->root.bo);
 	}
 
 	mutex_unlock(&dev->filelist_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 57ec108b5972..130a9adf09ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -71,6 +71,8 @@
 #include <drm/task_barrier.h>
 #include <linux/pm_runtime.h>
 
+#include <drm/drm_drv.h>
+
 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
@@ -82,6 +84,7 @@ MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS		2000
 
@@ -119,6 +122,8 @@ const char *amdgpu_asic_name[] = {
 	"NAVY_FLOUNDER",
 	"VANGOGH",
 	"DIMGREY_CAVEFISH",
+	"BEIGE_GOBY",
+	"YELLOW_CARP",
 	"LAST",
 };
 
@@ -262,6 +267,21 @@ bool amdgpu_device_supports_baco(struct drm_device *dev)
 	return amdgpu_asic_supports_baco(adev);
 }
 
+/**
+ * amdgpu_device_supports_smart_shift - Is the device dGPU with
+ * smart shift support
+ *
+ * @dev: drm_device pointer
+ *
+ * Returns true if the device is a dGPU with Smart Shift support,
+ * otherwise returns false.
+ */
+bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
+{
+	return (amdgpu_device_supports_boco(dev) &&
+		amdgpu_acpi_is_power_shift_control_supported());
+}
+
 /*
  * VRAM access helper functions
  */
@@ -281,7 +301,10 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 	unsigned long flags;
 	uint32_t hi = ~0;
 	uint64_t last;
+	int idx;
 
+	if (!drm_dev_enter(&adev->ddev, &idx))
+		return;
 
 #ifdef CONFIG_64BIT
 	last = min(pos + size, adev->gmc.visible_vram_size);
@@ -292,15 +315,15 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 		if (write) {
 			memcpy_toio(addr, buf, count);
 			mb();
-			amdgpu_asic_flush_hdp(adev, NULL);
+			amdgpu_device_flush_hdp(adev, NULL);
 		} else {
-			amdgpu_asic_invalidate_hdp(adev, NULL);
+			amdgpu_device_invalidate_hdp(adev, NULL);
 			mb();
 			memcpy_fromio(buf, addr, count);
 		}
 
 		if (count == size)
-			return;
+			goto exit;
 
 		pos += count;
 		buf += count / 4;
@@ -323,6 +346,11 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 			*buf++ = RREG32_NO_KIQ(mmMM_DATA);
 	}
 	spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+
+#ifdef CONFIG_64BIT
+exit:
+#endif
+	drm_dev_exit(idx);
 }
 
 /*
@@ -332,7 +360,7 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 /* Check if hw access should be skipped because of hotplug or device error */
 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
 {
-	if (adev->in_pci_err_recovery)
+	if (adev->no_hw_access)
 		return true;
 
 #ifdef CONFIG_LOCKDEP
@@ -490,7 +518,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
 	    adev->gfx.rlc.funcs &&
 	    adev->gfx.rlc.funcs->is_rlcg_access_range) {
 		if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
-			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
+			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 0);
 	} else {
 		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 	}
@@ -1820,6 +1848,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 	default:
 		return 0;
 	case CHIP_VEGA10:
@@ -1857,6 +1886,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 		chip_name = "vangogh";
 		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
 	}
 
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -2033,9 +2065,13 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
 	case  CHIP_SIENNA_CICHLID:
 	case  CHIP_NAVY_FLOUNDER:
 	case  CHIP_DIMGREY_CAVEFISH:
+	case  CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		if (adev->asic_type == CHIP_VANGOGH)
 			adev->family = AMDGPU_FAMILY_VGH;
+		else if (adev->asic_type == CHIP_YELLOW_CARP)
+			adev->family = AMDGPU_FAMILY_YC;
 		else
 			adev->family = AMDGPU_FAMILY_NV;
 
@@ -2571,34 +2607,26 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
 	return 0;
 }
 
-/**
- * amdgpu_device_ip_fini - run fini for hardware IPs
- *
- * @adev: amdgpu_device pointer
- *
- * Main teardown pass for hardware IPs.  The list of all the hardware
- * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
- * are run.  hw_fini tears down the hardware associated with each IP
- * and sw_fini tears down any software state associated with each IP.
- * Returns 0 on success, negative error code on failure.
- */
-static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
+static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
 {
 	int i, r;
 
-	if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
-		amdgpu_virt_release_ras_err_handler_data(adev);
+	for (i = 0; i < adev->num_ip_blocks; i++) {
+		if (!adev->ip_blocks[i].version->funcs->early_fini)
+			continue;
 
-	amdgpu_ras_pre_fini(adev);
+		r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
+		if (r) {
+			DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
+				  adev->ip_blocks[i].version->funcs->name, r);
+		}
+	}
 
-	if (adev->gmc.xgmi.num_physical_nodes > 1)
-		amdgpu_xgmi_remove_device(adev);
+	amdgpu_amdkfd_suspend(adev, false);
 
 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
 
-	amdgpu_amdkfd_device_fini(adev);
-
 	/* need to disable SMC first */
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.hw)
@@ -2629,6 +2657,33 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
 		adev->ip_blocks[i].status.hw = false;
 	}
 
+	return 0;
+}
+
+/**
+ * amdgpu_device_ip_fini - run fini for hardware IPs
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Main teardown pass for hardware IPs.  The list of all the hardware
+ * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
+ * are run.  hw_fini tears down the hardware associated with each IP
+ * and sw_fini tears down any software state associated with each IP.
+ * Returns 0 on success, negative error code on failure.
+ */
+static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
+{
+	int i, r;
+
+	if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
+		amdgpu_virt_release_ras_err_handler_data(adev);
+
+	amdgpu_ras_pre_fini(adev);
+
+	if (adev->gmc.xgmi.num_physical_nodes > 1)
+		amdgpu_xgmi_remove_device(adev);
+
+	amdgpu_amdkfd_device_fini_sw(adev);
 
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
 		if (!adev->ip_blocks[i].status.sw)
@@ -2856,7 +2911,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
 		AMD_IP_BLOCK_TYPE_IH,
 	};
 
-	for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
+	for (i = 0; i < adev->num_ip_blocks; i++) {
 		int j;
 		struct amdgpu_ip_block *block;
 
@@ -3034,7 +3089,7 @@ static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
 {
 	if (amdgpu_sriov_vf(adev)) {
 		if (adev->is_atom_fw) {
-			if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
+			if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
 				adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
 		} else {
 			if (amdgpu_atombios_has_gpu_virtualization_table(adev))
@@ -3097,7 +3152,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 #endif
 		return amdgpu_dc != 0;
 #endif
@@ -3181,8 +3238,8 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
 	int ret = 0;
 
 	/*
-	 * By default timeout for non compute jobs is 10000.
-	 * And there is no timeout enforced on compute jobs.
+	 * By default timeout for non compute jobs is 10000
+	 * and 60000 for compute jobs.
 	 * In SR-IOV or passthrough mode, timeout for compute
 	 * jobs are 60000 by default.
 	 */
@@ -3191,10 +3248,8 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
 	if (amdgpu_sriov_vf(adev))
 		adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
 					msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
-	else if (amdgpu_passthrough(adev))
-		adev->compute_timeout =  msecs_to_jiffies(60000);
 	else
-		adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
+		adev->compute_timeout =  msecs_to_jiffies(60000);
 
 	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
 		while ((timeout_setting = strsep(&input, ",")) &&
@@ -3251,7 +3306,6 @@ static const struct attribute *amdgpu_dev_attributes[] = {
 	NULL
 };
 
-
 /**
  * amdgpu_device_init - initialize the driver
  *
@@ -3653,6 +3707,27 @@ failed_unmap:
 	return r;
 }
 
+static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
+{
+	/* Clear all CPU mappings pointing to this device */
+	unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
+
+	/* Unmap all mapped bars - Doorbell, registers and VRAM */
+	amdgpu_device_doorbell_fini(adev);
+
+	iounmap(adev->rmmio);
+	adev->rmmio = NULL;
+	if (adev->mman.aper_base_kaddr)
+		iounmap(adev->mman.aper_base_kaddr);
+	adev->mman.aper_base_kaddr = NULL;
+
+	/* Memory manager related */
+	if (!adev->gmc.xgmi.connected_to_cpu) {
+		arch_phys_wc_del(adev->gmc.vram_mtrr);
+		arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+	}
+}
+
 /**
  * amdgpu_device_fini - tear down the driver
  *
@@ -3661,15 +3736,13 @@ failed_unmap:
  * Tear down the driver info (all asics).
  * Called at driver shutdown.
  */
-void amdgpu_device_fini(struct amdgpu_device *adev)
+void amdgpu_device_fini_hw(struct amdgpu_device *adev)
 {
 	dev_info(adev->dev, "amdgpu: finishing device.\n");
 	flush_delayed_work(&adev->delayed_init_work);
 	ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
 	adev->shutdown = true;
 
-	kfree(adev->pci_state);
-
 	/* make sure IB test finished before entering exclusive mode
 	 * to avoid preemption on IB test
 	 * */
@@ -3686,11 +3759,29 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 		else
 			drm_atomic_helper_shutdown(adev_to_drm(adev));
 	}
-	amdgpu_fence_driver_fini(adev);
+	amdgpu_fence_driver_fini_hw(adev);
+
 	if (adev->pm_sysfs_en)
 		amdgpu_pm_sysfs_fini(adev);
+	if (adev->ucode_sysfs_en)
+		amdgpu_ucode_sysfs_fini(adev);
+	sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
+
 	amdgpu_fbdev_fini(adev);
+
+	amdgpu_irq_fini_hw(adev);
+
+	amdgpu_device_ip_fini_early(adev);
+
+	amdgpu_gart_dummy_page_fini(adev);
+
+	amdgpu_device_unmap_mmio(adev);
+}
+
+void amdgpu_device_fini_sw(struct amdgpu_device *adev)
+{
 	amdgpu_device_ip_fini(adev);
+	amdgpu_fence_driver_fini_sw(adev);
 	release_firmware(adev->firmware.gpu_info_fw);
 	adev->firmware.gpu_info_fw = NULL;
 	adev->accel_working = false;
@@ -3712,18 +3803,14 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 	}
 	if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
 		vga_client_register(adev->pdev, NULL, NULL, NULL);
-	iounmap(adev->rmmio);
-	adev->rmmio = NULL;
-	amdgpu_device_doorbell_fini(adev);
-
-	if (adev->ucode_sysfs_en)
-		amdgpu_ucode_sysfs_fini(adev);
 
-	sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
 	if (IS_ENABLED(CONFIG_PERF_EVENTS))
 		amdgpu_pmu_fini(adev);
 	if (adev->mman.discovery_bin)
 		amdgpu_discovery_fini(adev);
+
+	kfree(adev->pci_state);
+
 }
 
 
@@ -3743,12 +3830,15 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 {
 	struct amdgpu_device *adev = drm_to_adev(dev);
-	int r;
 
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 
 	adev->in_suspend = true;
+
+	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
+		DRM_WARN("smart shift update failed\n");
+
 	drm_kms_helper_poll_disable(dev);
 
 	if (fbcon)
@@ -3758,7 +3848,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
 	amdgpu_ras_suspend(adev);
 
-	r = amdgpu_device_ip_suspend_phase1(adev);
+	amdgpu_device_ip_suspend_phase1(adev);
 
 	if (!adev->in_s0ix)
 		amdgpu_amdkfd_suspend(adev, adev->in_runpm);
@@ -3768,7 +3858,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
 	amdgpu_fence_driver_suspend(adev);
 
-	r = amdgpu_device_ip_suspend_phase2(adev);
+	amdgpu_device_ip_suspend_phase2(adev);
 	/* evict remaining vram memory
 	 * This second call to evict vram is to evict the gart page table
 	 * using the CPU.
@@ -3858,6 +3948,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
 #endif
 	adev->in_suspend = false;
 
+	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
+		DRM_WARN("smart shift update failed\n");
+
 	return 0;
 }
 
@@ -4031,6 +4124,7 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
 {
 	struct dma_fence *fence = NULL, *next = NULL;
 	struct amdgpu_bo *shadow;
+	struct amdgpu_bo_vm *vmbo;
 	long r = 1, tmo;
 
 	if (amdgpu_sriov_runtime(adev))
@@ -4040,12 +4134,12 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
 
 	dev_info(adev->dev, "recover vram bo from shadow start\n");
 	mutex_lock(&adev->shadow_list_lock);
-	list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
-
+	list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
+		shadow = &vmbo->bo;
 		/* No need to recover an evicted BO */
-		if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
-		    shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
-		    shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
+		if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
+		    shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
+		    shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
 			continue;
 
 		r = amdgpu_bo_restore_shadow(shadow, &next);
@@ -4634,7 +4728,7 @@ static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
 	return 0;
 }
 
-void amdgpu_device_recheck_guilty_jobs(
+static void amdgpu_device_recheck_guilty_jobs(
 	struct amdgpu_device *adev, struct list_head *device_list_handle,
 	struct amdgpu_reset_context *reset_context)
 {
@@ -4937,6 +5031,8 @@ skip_hw_reset:
 			amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
 		} else {
 			dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
+			if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
+				DRM_WARN("smart shift update failed\n");
 		}
 	}
 
@@ -5125,7 +5221,8 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
 	if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
 		return -ENOTSUPP;
 
-	if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
+	if (ras && adev->ras_enabled &&
+	    adev->nbio.funcs->enable_doorbell_interrupt)
 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 
 	return amdgpu_dpm_baco_enter(adev);
@@ -5144,7 +5241,8 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
 	if (ret)
 		return ret;
 
-	if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
+	if (ras && adev->ras_enabled &&
+	    adev->nbio.funcs->enable_doorbell_interrupt)
 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 
 	return 0;
@@ -5290,9 +5388,9 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
 	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
 	set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
 
-	adev->in_pci_err_recovery = true;
+	adev->no_hw_access = true;
 	r = amdgpu_device_pre_asic_reset(adev, &reset_context);
-	adev->in_pci_err_recovery = false;
+	adev->no_hw_access = false;
 	if (r)
 		goto out;
 
@@ -5387,4 +5485,31 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
 	return true;
 }
 
+void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring)
+{
+#ifdef CONFIG_X86_64
+	if (adev->flags & AMD_IS_APU)
+		return;
+#endif
+	if (adev->gmc.xgmi.connected_to_cpu)
+		return;
 
+	if (ring && ring->funcs->emit_hdp_flush)
+		amdgpu_ring_emit_hdp_flush(ring);
+	else
+		amdgpu_asic_flush_hdp(adev, ring);
+}
+
+void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring)
+{
+#ifdef CONFIG_X86_64
+	if (adev->flags & AMD_IS_APU)
+		return;
+#endif
+	if (adev->gmc.xgmi.connected_to_cpu)
+		return;
+
+	amdgpu_asic_invalidate_hdp(adev, ring);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index e1b6f5891759..43e7b61d1c5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -325,7 +325,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 	return 0;
 }
 
-int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
 				    int *major, int *minor, int *revision)
 {
 	struct binary_header *bhdr;
@@ -357,7 +357,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
 		for (j = 0; j < num_ips; j++) {
 			ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 
-			if (le16_to_cpu(ip->hw_id) == hw_id) {
+			if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
 				if (major)
 					*major = ip->major;
 				if (minor)
@@ -373,6 +373,14 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
 	return -EINVAL;
 }
 
+
+int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
+				     int *major, int *minor, int *revision)
+{
+	return amdgpu_discovery_get_ip_version(adev, VCN_HWID,
+					       vcn_instance, major, minor, revision);
+}
+
 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 {
 	struct binary_header *bhdr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
index 1b1ae21b1037..48e6b88cfdfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
@@ -30,8 +30,11 @@
 void amdgpu_discovery_fini(struct amdgpu_device *adev);
 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
-int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
                                     int *major, int *minor, int *revision);
+
+int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
+				     int *major, int *minor, int *revision);
 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
 
 #endif /* __AMDGPU_DISCOVERY__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 2a4cd7d377bf..8e5a7ac8c36f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -203,9 +203,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 		goto unpin;
 	}
 
-	r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,
-					      &work->shared_count,
-					      &work->shared);
+	r = dma_resv_get_fences(new_abo->tbo.base.resv, &work->excl,
+				&work->shared_count, &work->shared);
 	if (unlikely(r != 0)) {
 		DRM_ERROR("failed to get fences for buffer\n");
 		goto unpin;
@@ -1075,12 +1074,9 @@ int amdgpu_display_gem_fb_verify_and_init(
 	/* Verify that the modifier is supported. */
 	if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
 				      mode_cmd->modifier[0])) {
-		struct drm_format_name_buf format_name;
 		drm_dbg_kms(dev,
-			    "unsupported pixel format %s / modifier 0x%llx\n",
-			    drm_get_format_name(mode_cmd->pixel_format,
-						&format_name),
-			    mode_cmd->modifier[0]);
+			    "unsupported pixel format %p4cc / modifier 0x%llx\n",
+			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);
 
 		ret = -EINVAL;
 		goto err;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index 37ec59365080..a9475b207510 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -42,52 +42,6 @@
 #include <linux/pci-p2pdma.h>
 #include <linux/pm_runtime.h>
 
-/**
- * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
- * @obj: GEM BO
- * @vma: Virtual memory area
- *
- * Sets up a userspace mapping of the BO's memory in the given
- * virtual memory area.
- *
- * Returns:
- * 0 on success or a negative error code on failure.
- */
-int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
-			  struct vm_area_struct *vma)
-{
-	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-	unsigned asize = amdgpu_bo_size(bo);
-	int ret;
-
-	if (!vma->vm_file)
-		return -ENODEV;
-
-	if (adev == NULL)
-		return -ENODEV;
-
-	/* Check for valid size. */
-	if (asize < vma->vm_end - vma->vm_start)
-		return -EINVAL;
-
-	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
-	    (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
-		return -EPERM;
-	}
-	vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
-
-	/* prime mmap does not need to check access, so allow here */
-	ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
-	if (ret)
-		return ret;
-
-	ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
-	drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
-
-	return ret;
-}
-
 static int
 __dma_resv_make_exclusive(struct dma_resv *obj)
 {
@@ -95,10 +49,10 @@ __dma_resv_make_exclusive(struct dma_resv *obj)
 	unsigned int count;
 	int r;
 
-	if (!dma_resv_get_list(obj)) /* no shared fences to convert */
+	if (!dma_resv_shared_list(obj)) /* no shared fences to convert */
 		return 0;
 
-	r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences);
+	r = dma_resv_get_fences(obj, NULL, &count, &fences);
 	if (r)
 		return r;
 
@@ -284,12 +238,12 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
 		if (r)
 			return ERR_PTR(r);
 
-	} else if (!(amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type) &
+	} else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) &
 		     AMDGPU_GEM_DOMAIN_GTT)) {
 		return ERR_PTR(-EBUSY);
 	}
 
-	switch (bo->tbo.mem.mem_type) {
+	switch (bo->tbo.resource->mem_type) {
 	case TTM_PL_TT:
 		sgt = drm_prime_pages_to_sg(obj->dev,
 					    bo->tbo.ttm->pages,
@@ -303,8 +257,9 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
 		break;
 
 	case TTM_PL_VRAM:
-		r = amdgpu_vram_mgr_alloc_sgt(adev, &bo->tbo.mem, 0,
-				bo->tbo.base.size, attach->dev, dir, &sgt);
+		r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
+					      bo->tbo.base.size, attach->dev,
+					      dir, &sgt);
 		if (r)
 			return ERR_PTR(r);
 		break;
@@ -494,7 +449,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
 	struct amdgpu_vm_bo_base *bo_base;
 	int r;
 
-	if (bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
+	if (bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
 		return;
 
 	r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
@@ -505,7 +460,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
 
 	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
 		struct amdgpu_vm *vm = bo_base->vm;
-		struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+		struct dma_resv *resv = vm->root.bo->tbo.base.resv;
 
 		if (ticket) {
 			/* When we get an error here it means that somebody
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
index 39b5b9616fd8..3e93b9b407a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
@@ -31,8 +31,6 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
 					    struct dma_buf *dma_buf);
 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
 				      struct amdgpu_bo *bo);
-int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
-			  struct vm_area_struct *vma);
 
 extern const struct dma_buf_ops amdgpu_dmabuf_ops;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f93883db2b46..6f30c525caac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -23,6 +23,7 @@
  */
 
 #include <drm/amdgpu_drm.h>
+#include <drm/drm_aperture.h>
 #include <drm/drm_drv.h>
 #include <drm/drm_gem.h>
 #include <drm/drm_vblank.h>
@@ -42,7 +43,7 @@
 #include "amdgpu_irq.h"
 #include "amdgpu_dma_buf.h"
 #include "amdgpu_sched.h"
-
+#include "amdgpu_fdinfo.h"
 #include "amdgpu_amdkfd.h"
 
 #include "amdgpu_ras.h"
@@ -94,9 +95,10 @@
  * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
  * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
  * - 3.41.0 - Add video codec query
+ * - 3.42.0 - Add 16bpc fixed point display support
  */
 #define KMS_DRIVER_MAJOR	3
-#define KMS_DRIVER_MINOR	41
+#define KMS_DRIVER_MINOR	42
 #define KMS_DRIVER_PATCHLEVEL	0
 
 int amdgpu_vram_limit;
@@ -171,6 +173,7 @@ int amdgpu_tmz = -1; /* auto */
 uint amdgpu_freesync_vid_mode;
 int amdgpu_reset_method = -1; /* auto */
 int amdgpu_num_kcq = -1;
+int amdgpu_smartshift_bias;
 
 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
 
@@ -287,9 +290,9 @@ module_param_named(msi, amdgpu_msi, int, 0444);
  *   for SDMA and Video.
  *
  * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
- * jobs is 10000. And there is no timeout enforced on compute jobs.
+ * jobs is 10000. The timeout for compute is 60000.
  */
-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
+MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
 		"for passthrough or sriov, 10000 for all jobs."
 		" 0: keep default value. negative: infinity timeout), "
 		"format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
@@ -640,7 +643,8 @@ module_param_named(mes, amdgpu_mes, int, 0444);
 
 /**
  * DOC: noretry (int)
- * Disable retry faults in the GPU memory controller.
+ * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
+ * do not support per-process XNACK this also disables retry page faults.
  * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
  */
 MODULE_PARM_DESC(noretry,
@@ -833,8 +837,23 @@ module_param_named(tmz, amdgpu_tmz, int, 0444);
 
 /**
  * DOC: freesync_video (uint)
- * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience
- * when setting a freesync supported mode for which full modeset is not needed.
+ * Enable the optimization to adjust front porch timing to achieve seamless
+ * mode change experience when setting a freesync supported mode for which full
+ * modeset is not needed.
+ *
+ * The Display Core will add a set of modes derived from the base FreeSync
+ * video mode into the corresponding connector's mode list based on commonly
+ * used refresh rates and VRR range of the connected display, when users enable
+ * this feature. From the userspace perspective, they can see a seamless mode
+ * change experience when the change between different refresh rates under the
+ * same resolution. Additionally, userspace applications such as Video playback
+ * can read this modeset list and change the refresh rate based on the video
+ * frame rate. Finally, the userspace can also derive an appropriate mode for a
+ * particular refresh rate based on the FreeSync Mode and add it to the
+ * connector's mode list.
+ *
+ * Note: This is an experimental feature.
+ *
  * The default value: 0 (off).
  */
 MODULE_PARM_DESC(
@@ -1185,6 +1204,7 @@ static const struct pci_device_id pciidlist[] = {
 	{0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
 	{0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
 	{0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
+	{0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
 
 	{0, 0, 0}
 };
@@ -1258,7 +1278,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
 #endif
 
 	/* Get rid of things like offb */
-	ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb");
+	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb");
 	if (ret)
 		return ret;
 
@@ -1310,14 +1330,16 @@ amdgpu_pci_remove(struct pci_dev *pdev)
 {
 	struct drm_device *dev = pci_get_drvdata(pdev);
 
-#ifdef MODULE
-	if (THIS_MODULE->state != MODULE_STATE_GOING)
-#endif
-		DRM_ERROR("Hotplug removal is not supported\n");
 	drm_dev_unplug(dev);
 	amdgpu_driver_unload_kms(dev);
+
+	/*
+	 * Flush any in flight DMA operations from device.
+	 * Clear the Bus Master Enable bit and then wait on the PCIe Device
+	 * StatusTransactions Pending bit.
+	 */
 	pci_disable_device(pdev);
-	pci_set_drvdata(pdev, NULL);
+	pci_wait_for_pending_transaction(pdev);
 }
 
 static void
@@ -1552,6 +1574,10 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
 	if (!adev->runpm)
 		return -EINVAL;
 
+	/* Avoids registers access if device is physically gone */
+	if (!pci_device_is_present(adev->pdev))
+		adev->no_hw_access = true;
+
 	if (amdgpu_device_supports_px(drm_dev)) {
 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
@@ -1597,17 +1623,15 @@ static int amdgpu_pmops_runtime_idle(struct device *dev)
 	if (amdgpu_device_has_dc_support(adev)) {
 		struct drm_crtc *crtc;
 
-		drm_modeset_lock_all(drm_dev);
-
 		drm_for_each_crtc(crtc, drm_dev) {
-			if (crtc->state->active) {
+			drm_modeset_lock(&crtc->mutex, NULL);
+			if (crtc->state->active)
 				ret = -EBUSY;
+			drm_modeset_unlock(&crtc->mutex);
+			if (ret < 0)
 				break;
-			}
 		}
 
-		drm_modeset_unlock_all(drm_dev);
-
 	} else {
 		struct drm_connector *list_connector;
 		struct drm_connector_list_iter iter;
@@ -1688,12 +1712,15 @@ static const struct file_operations amdgpu_driver_kms_fops = {
 	.flush = amdgpu_flush,
 	.release = drm_release,
 	.unlocked_ioctl = amdgpu_drm_ioctl,
-	.mmap = amdgpu_mmap,
+	.mmap = drm_gem_mmap,
 	.poll = drm_poll,
 	.read = drm_read,
 #ifdef CONFIG_COMPAT
 	.compat_ioctl = amdgpu_kms_compat_ioctl,
 #endif
+#ifdef CONFIG_PROC_FS
+	.show_fdinfo = amdgpu_show_fdinfo
+#endif
 };
 
 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
@@ -1747,11 +1774,12 @@ static const struct drm_driver amdgpu_kms_driver = {
 	.dumb_create = amdgpu_mode_dumb_create,
 	.dumb_map_offset = amdgpu_mode_dumb_mmap,
 	.fops = &amdgpu_driver_kms_fops,
+	.release = &amdgpu_driver_release_kms,
 
 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 	.gem_prime_import = amdgpu_gem_prime_import,
-	.gem_prime_mmap = amdgpu_gem_prime_mmap,
+	.gem_prime_mmap = drm_gem_prime_mmap,
 
 	.name = DRIVER_NAME,
 	.desc = DRIVER_DESC,
@@ -1768,6 +1796,18 @@ static struct pci_error_handlers amdgpu_pci_err_handler = {
 	.resume		= amdgpu_pci_resume,
 };
 
+extern const struct attribute_group amdgpu_vram_mgr_attr_group;
+extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
+extern const struct attribute_group amdgpu_vbios_version_attr_group;
+
+static const struct attribute_group *amdgpu_sysfs_groups[] = {
+	&amdgpu_vram_mgr_attr_group,
+	&amdgpu_gtt_mgr_attr_group,
+	&amdgpu_vbios_version_attr_group,
+	NULL,
+};
+
+
 static struct pci_driver amdgpu_kms_pci_driver = {
 	.name = DRIVER_NAME,
 	.id_table = pciidlist,
@@ -1776,6 +1816,7 @@ static struct pci_driver amdgpu_kms_pci_driver = {
 	.shutdown = amdgpu_pci_shutdown,
 	.driver.pm = &amdgpu_pm_ops,
 	.err_handler = &amdgpu_pci_err_handler,
+	.dev_groups = amdgpu_sysfs_groups,
 };
 
 static int __init amdgpu_init(void)
@@ -1797,6 +1838,7 @@ static int __init amdgpu_init(void)
 
 	DRM_INFO("amdgpu kernel modesetting enabled.\n");
 	amdgpu_register_atpx_handler();
+	amdgpu_acpi_detect();
 
 	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
 	amdgpu_amdkfd_init();
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
new file mode 100644
index 000000000000..d94c5419ec25
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: MIT
+/* Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: David Nieto
+ *          Roy Sun
+ */
+
+#include <linux/debugfs.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/reboot.h>
+#include <linux/syscalls.h>
+
+#include <drm/amdgpu_drm.h>
+#include <drm/drm_debugfs.h>
+
+#include "amdgpu.h"
+#include "amdgpu_vm.h"
+#include "amdgpu_gem.h"
+#include "amdgpu_ctx.h"
+#include "amdgpu_fdinfo.h"
+
+
+static const char *amdgpu_ip_name[AMDGPU_HW_IP_NUM] = {
+	[AMDGPU_HW_IP_GFX]	=	"gfx",
+	[AMDGPU_HW_IP_COMPUTE]	=	"compute",
+	[AMDGPU_HW_IP_DMA]	=	"dma",
+	[AMDGPU_HW_IP_UVD]	=	"dec",
+	[AMDGPU_HW_IP_VCE]	=	"enc",
+	[AMDGPU_HW_IP_UVD_ENC]	=	"enc_1",
+	[AMDGPU_HW_IP_VCN_DEC]	=	"dec",
+	[AMDGPU_HW_IP_VCN_ENC]	=	"enc",
+	[AMDGPU_HW_IP_VCN_JPEG]	=	"jpeg",
+};
+
+void amdgpu_show_fdinfo(struct seq_file *m, struct file *f)
+{
+	struct amdgpu_fpriv *fpriv;
+	uint32_t bus, dev, fn, i, domain;
+	uint64_t vram_mem = 0, gtt_mem = 0, cpu_mem = 0;
+	struct drm_file *file = f->private_data;
+	struct amdgpu_device *adev = drm_to_adev(file->minor->dev);
+	int ret;
+
+	ret = amdgpu_file_to_fpriv(f, &fpriv);
+	if (ret)
+		return;
+	bus = adev->pdev->bus->number;
+	domain = pci_domain_nr(adev->pdev->bus);
+	dev = PCI_SLOT(adev->pdev->devfn);
+	fn = PCI_FUNC(adev->pdev->devfn);
+
+	ret = amdgpu_bo_reserve(fpriv->vm.root.bo, false);
+	if (ret) {
+		DRM_ERROR("Fail to reserve bo\n");
+		return;
+	}
+	amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, &gtt_mem, &cpu_mem);
+	amdgpu_bo_unreserve(fpriv->vm.root.bo);
+	seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus,
+			dev, fn, fpriv->vm.pasid);
+	seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL);
+	seq_printf(m, "gtt mem:\t%llu kB\n", gtt_mem/1024UL);
+	seq_printf(m, "cpu mem:\t%llu kB\n", cpu_mem/1024UL);
+	for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
+		uint32_t count = amdgpu_ctx_num_entities[i];
+		int idx = 0;
+		uint64_t total = 0, min = 0;
+		uint32_t perc, frac;
+
+		for (idx = 0; idx < count; idx++) {
+			total = amdgpu_ctx_mgr_fence_usage(&fpriv->ctx_mgr,
+				i, idx, &min);
+			if ((total == 0) || (min == 0))
+				continue;
+
+			perc = div64_u64(10000 * total, min);
+			frac = perc % 100;
+
+			seq_printf(m, "%s%d:\t%d.%d%%\n",
+					amdgpu_ip_name[i],
+					idx, perc/100, frac);
+		}
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
new file mode 100644
index 000000000000..41a4c7056729
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: David Nieto
+ *          Roy Sun
+ */
+#ifndef __AMDGPU_SMI_H__
+#define __AMDGPU_SMI_H__
+
+#include <linux/idr.h>
+#include <linux/kfifo.h>
+#include <linux/rbtree.h>
+#include <drm/gpu_scheduler.h>
+#include <drm/drm_file.h>
+#include <drm/ttm/ttm_bo_driver.h>
+#include <linux/sched/mm.h>
+
+#include "amdgpu_sync.h"
+#include "amdgpu_ring.h"
+#include "amdgpu_ids.h"
+
+uint32_t amdgpu_get_ip_count(struct amdgpu_device *adev, int id);
+void amdgpu_show_fdinfo(struct seq_file *m, struct file *f);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 47ea46859618..72d9b92b1754 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -36,6 +36,7 @@
 #include <linux/firmware.h>
 #include <linux/pm_runtime.h>
 
+#include <drm/drm_drv.h>
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
 
@@ -434,6 +435,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
  *
  * @ring: ring to init the fence driver on
  * @num_hw_submission: number of entries on the hardware queue
+ * @sched_score: optional score atomic shared with other schedulers
  *
  * Init the fence driver for the requested ring (all asics).
  * Helper function for amdgpu_fence_driver_init().
@@ -523,10 +525,9 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev)
  *
  * Tear down the fence driver for all possible rings (all asics).
  */
-void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
+void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev)
 {
-	unsigned i, j;
-	int r;
+	int i, r;
 
 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 		struct amdgpu_ring *ring = adev->rings[i];
@@ -535,16 +536,33 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 			continue;
 		if (!ring->no_scheduler)
 			drm_sched_fini(&ring->sched);
-		r = amdgpu_fence_wait_empty(ring);
-		if (r) {
-			/* no need to trigger GPU reset as we are unloading */
+		/* You can't wait for HW to signal if it's gone */
+		if (!drm_dev_is_unplugged(&adev->ddev))
+			r = amdgpu_fence_wait_empty(ring);
+		else
+			r = -ENODEV;
+		/* no need to trigger GPU reset as we are unloading */
+		if (r)
 			amdgpu_fence_driver_force_completion(ring);
-		}
+
 		if (ring->fence_drv.irq_src)
 			amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 				       ring->fence_drv.irq_type);
 
 		del_timer_sync(&ring->fence_drv.fallback_timer);
+	}
+}
+
+void amdgpu_fence_driver_fini_sw(struct amdgpu_device *adev)
+{
+	unsigned int i, j;
+
+	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+		struct amdgpu_ring *ring = adev->rings[i];
+
+		if (!ring || !ring->fence_drv.initialized)
+			continue;
+
 		for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 			dma_fence_put(ring->fence_drv.fences[j]);
 		kfree(ring->fence_drv.fences);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
index 8d1ad294cb02..2ca3c329de6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
@@ -121,6 +121,9 @@ static const struct file_operations amdgpu_fw_attestation_debugfs_ops = {
 
 static int amdgpu_is_fw_attestation_supported(struct amdgpu_device *adev)
 {
+	if (adev->flags & AMD_IS_APU)
+		return 0;
+
 	if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 		return 1;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index c5a9a4fb10d2..b36405170ff3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -60,7 +60,7 @@
  */
 
 /**
- * amdgpu_dummy_page_init - init dummy page used by the driver
+ * amdgpu_gart_dummy_page_init - init dummy page used by the driver
  *
  * @adev: amdgpu_device pointer
  *
@@ -86,13 +86,13 @@ static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_dummy_page_fini - free dummy page used by the driver
+ * amdgpu_gart_dummy_page_fini - free dummy page used by the driver
  *
  * @adev: amdgpu_device pointer
  *
  * Frees the dummy page used by the driver (all asics).
  */
-static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
+void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
 {
 	if (!adev->dummy_page_addr)
 		return;
@@ -250,7 +250,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
 		}
 	}
 	mb();
-	amdgpu_asic_flush_hdp(adev, NULL);
+	amdgpu_device_flush_hdp(adev, NULL);
 	for (i = 0; i < adev->num_vmhubs; i++)
 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
 
@@ -300,7 +300,6 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
  * @adev: amdgpu_device pointer
  * @offset: offset into the GPU's gart aperture
  * @pages: number of pages to bind
- * @pagelist: pages to bind
  * @dma_addr: DMA addresses of pages
  * @flags: page table entry flags
  *
@@ -309,11 +308,9 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
  * Returns 0 for success, -EINVAL for failure.
  */
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
-		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
+		     int pages, dma_addr_t *dma_addr,
 		     uint64_t flags)
 {
-	int r, i;
-
 	if (!adev->gart.ready) {
 		WARN(1, "trying to bind memory to uninitialized GART !\n");
 		return -EINVAL;
@@ -322,16 +319,26 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
 	if (!adev->gart.ptr)
 		return 0;
 
-	r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
-		    adev->gart.ptr);
-	if (r)
-		return r;
+	return amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
+			       adev->gart.ptr);
+}
+
+/**
+ * amdgpu_gart_invalidate_tlb - invalidate gart TLB
+ *
+ * @adev: amdgpu device driver pointer
+ *
+ * Invalidate gart TLB which can be use as a way to flush gart changes
+ *
+ */
+void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
+{
+	int i;
 
 	mb();
-	amdgpu_asic_flush_hdp(adev, NULL);
+	amdgpu_device_flush_hdp(adev, NULL);
 	for (i = 0; i < adev->num_vmhubs; i++)
 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
-	return 0;
 }
 
 /**
@@ -365,15 +372,3 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
 
 	return 0;
 }
-
-/**
- * amdgpu_gart_fini - tear down the driver info for managing the gart
- *
- * @adev: amdgpu_device pointer
- *
- * Tear down the gart driver info and free the dummy page (all asics).
- */
-void amdgpu_gart_fini(struct amdgpu_device *adev)
-{
-	amdgpu_gart_dummy_page_fini(adev);
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index a25fe97b0196..78895413cf9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -57,14 +57,13 @@ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
 int amdgpu_gart_init(struct amdgpu_device *adev);
-void amdgpu_gart_fini(struct amdgpu_device *adev);
+void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);
 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
 		       int pages);
 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
 		    int pages, dma_addr_t *dma_addr, uint64_t flags,
 		    void *dst);
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
-		     int pages, struct page **pagelist,
-		     dma_addr_t *dma_addr, uint64_t flags);
-
+		     int pages, dma_addr_t *dma_addr, uint64_t flags);
+void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 311bcdc59eda..b3404c43a911 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -32,6 +32,7 @@
 #include <linux/dma-buf.h>
 
 #include <drm/amdgpu_drm.h>
+#include <drm/drm_drv.h>
 #include <drm/drm_gem_ttm_helper.h>
 
 #include "amdgpu.h"
@@ -41,6 +42,46 @@
 
 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
 
+static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
+{
+	struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
+	struct drm_device *ddev = bo->base.dev;
+	vm_fault_t ret;
+	int idx;
+
+	ret = ttm_bo_vm_reserve(bo, vmf);
+	if (ret)
+		return ret;
+
+	if (drm_dev_enter(ddev, &idx)) {
+		ret = amdgpu_bo_fault_reserve_notify(bo);
+		if (ret) {
+			drm_dev_exit(idx);
+			goto unlock;
+		}
+
+		 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
+						TTM_BO_VM_NUM_PREFAULT, 1);
+
+		 drm_dev_exit(idx);
+	} else {
+		ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
+	}
+	if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
+		return ret;
+
+unlock:
+	dma_resv_unlock(bo->base.resv);
+	return ret;
+}
+
+static const struct vm_operations_struct amdgpu_gem_vm_ops = {
+	.fault = amdgpu_gem_fault,
+	.open = ttm_bo_vm_open,
+	.close = ttm_bo_vm_close,
+	.access = ttm_bo_vm_access
+};
+
 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
 {
 	struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
@@ -129,7 +170,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,
 		return -EPERM;
 
 	if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
-	    abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
+	    abo->tbo.base.resv != vm->root.bo->tbo.base.resv)
 		return -EPERM;
 
 	r = amdgpu_bo_reserve(abo, false);
@@ -185,7 +226,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj,
 	if (!amdgpu_vm_ready(vm))
 		goto out_unlock;
 
-	fence = dma_resv_get_excl(bo->tbo.base.resv);
+	fence = dma_resv_excl_fence(bo->tbo.base.resv);
 	if (fence) {
 		amdgpu_bo_fence(bo, fence, true);
 		fence = NULL;
@@ -205,6 +246,18 @@ out_unlock:
 	ttm_eu_backoff_reservation(&ticket, &list);
 }
 
+static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
+{
+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
+
+	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
+		return -EPERM;
+	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
+		return -EPERM;
+
+	return drm_gem_ttm_mmap(obj, vma);
+}
+
 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
 	.free = amdgpu_gem_object_free,
 	.open = amdgpu_gem_object_open,
@@ -212,6 +265,8 @@ static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
 	.export = amdgpu_gem_prime_export,
 	.vmap = drm_gem_ttm_vmap,
 	.vunmap = drm_gem_ttm_vunmap,
+	.mmap = amdgpu_gem_object_mmap,
+	.vm_ops = &amdgpu_gem_vm_ops,
 };
 
 /*
@@ -265,11 +320,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 	}
 
 	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
-		r = amdgpu_bo_reserve(vm->root.base.bo, false);
+		r = amdgpu_bo_reserve(vm->root.bo, false);
 		if (r)
 			return r;
 
-		resv = vm->root.base.bo->tbo.base.resv;
+		resv = vm->root.bo->tbo.base.resv;
 	}
 
 	initial_domain = (u32)(0xffffffff & args->in.domains);
@@ -298,9 +353,9 @@ retry:
 		if (!r) {
 			struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 
-			abo->parent = amdgpu_bo_ref(vm->root.base.bo);
+			abo->parent = amdgpu_bo_ref(vm->root.bo);
 		}
-		amdgpu_bo_unreserve(vm->root.base.bo);
+		amdgpu_bo_unreserve(vm->root.bo);
 	}
 	if (r)
 		return r;
@@ -471,8 +526,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 		return -ENOENT;
 	}
 	robj = gem_to_amdgpu_bo(gobj);
-	ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true,
-						  timeout);
+	ret = dma_resv_wait_timeout(robj->tbo.base.resv, true, true, timeout);
 
 	/* ret == 0 means not signaled,
 	 * ret > 0 means signaled
@@ -558,7 +612,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 
 	if (operation == AMDGPU_VA_OP_MAP ||
 	    operation == AMDGPU_VA_OP_REPLACE) {
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			goto error;
 	}
@@ -766,7 +820,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 		void __user *out = u64_to_user_ptr(args->value);
 
 		info.bo_size = robj->tbo.base.size;
-		info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
+		info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
 		info.domains = robj->preferred_domains;
 		info.domain_flags = robj->flags;
 		amdgpu_bo_unreserve(robj);
@@ -787,7 +841,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 		}
 		for (base = robj->vm_bo; base; base = base->next)
 			if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
-				amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) {
+				amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
 				r = -EINVAL;
 				amdgpu_bo_unreserve(robj);
 				goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 95d4f43a03df..a0be0772c8b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -607,7 +607,6 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
 	struct ras_ih_if ih_info = {
 		.cb = amdgpu_gfx_process_ras_data_cb,
 	};
-	struct ras_query_if info = { 0 };
 
 	if (!adev->gfx.ras_if) {
 		adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
@@ -625,12 +624,8 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
 		goto free;
 
 	if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
-		if (adev->gmc.xgmi.connected_to_cpu) {
-			info.head = *adev->gfx.ras_if;
-			amdgpu_ras_query_error_status(adev, &info);
-		} else {
+		if (!amdgpu_persistent_edc_harvesting_supported(adev))
 			amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
-		}
 
 		r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 		if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
index 66ebc2e3b2ad..beabab515836 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
@@ -34,6 +34,7 @@ struct amdgpu_gfxhub_funcs {
 	void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value);
 	void (*init)(struct amdgpu_device *adev);
 	int (*get_xgmi_info)(struct amdgpu_device *adev);
+	void (*utcl2_harvest)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_gfxhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index c39ed9eb0987..0174f7817ce2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -31,6 +31,8 @@
 #include "amdgpu_ras.h"
 #include "amdgpu_xgmi.h"
 
+#include <drm/drm_drv.h>
+
 /**
  * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
  *
@@ -99,7 +101,7 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 
-	switch (bo->tbo.mem.mem_type) {
+	switch (bo->tbo.resource->mem_type) {
 	case TTM_PL_TT:
 		*addr = bo->tbo.ttm->dma_address[0];
 		break;
@@ -110,7 +112,7 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
 		*addr = 0;
 		break;
 	}
-	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
+	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);
 	amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
 }
 
@@ -151,6 +153,10 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 {
 	void __iomem *ptr = (void *)cpu_pt_addr;
 	uint64_t value;
+	int idx;
+
+	if (!drm_dev_enter(&adev->ddev, &idx))
+		return 0;
 
 	/*
 	 * The following is for PTE only. GART does not have PDEs.
@@ -158,6 +164,9 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 	value = addr & 0x0000FFFFFFFFF000ULL;
 	value |= flags;
 	writeq(value, ptr + (gpu_page_idx * 8));
+
+	drm_dev_exit(idx);
+
 	return 0;
 }
 
@@ -333,6 +342,17 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
 }
 
 /**
+ * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid
+ *
+ * @addr: 48 bit physical address, page aligned (36 significant bits)
+ * @pasid: 16 bit process address space identifier
+ */
+static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)
+{
+	return addr << 4 | pasid;
+}
+
+/**
  * amdgpu_gmc_filter_faults - filter VM faults
  *
  * @adev: amdgpu device structure
@@ -348,8 +368,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
 			      uint16_t pasid, uint64_t timestamp)
 {
 	struct amdgpu_gmc *gmc = &adev->gmc;
-
-	uint64_t stamp, key = addr << 4 | pasid;
+	uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);
 	struct amdgpu_gmc_fault *fault;
 	uint32_t hash;
 
@@ -365,7 +384,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
 	while (fault->timestamp >= stamp) {
 		uint64_t tmp;
 
-		if (fault->key == key)
+		if (atomic64_read(&fault->key) == key)
 			return true;
 
 		tmp = fault->timestamp;
@@ -378,7 +397,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
 
 	/* Add the fault to the ring */
 	fault = &gmc->fault_ring[gmc->last_fault];
-	fault->key = key;
+	atomic64_set(&fault->key, key);
 	fault->timestamp = timestamp;
 
 	/* And update the hash */
@@ -387,6 +406,36 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
 	return false;
 }
 
+/**
+ * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
+ *
+ * @adev: amdgpu device structure
+ * @addr: address of the VM fault
+ * @pasid: PASID of the process causing the fault
+ *
+ * Remove the address from fault filter, then future vm fault on this address
+ * will pass to retry fault handler to recover.
+ */
+void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
+				     uint16_t pasid)
+{
+	struct amdgpu_gmc *gmc = &adev->gmc;
+	uint64_t key = amdgpu_gmc_fault_key(addr, pasid);
+	struct amdgpu_gmc_fault *fault;
+	uint32_t hash;
+	uint64_t tmp;
+
+	hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
+	fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
+	do {
+		if (atomic64_cmpxchg(&fault->key, key, 0) == key)
+			break;
+
+		tmp = fault->timestamp;
+		fault = &gmc->fault_ring[fault->next];
+	} while (fault->timestamp < tmp);
+}
+
 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
 {
 	int r;
@@ -415,6 +464,13 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
 			return r;
 	}
 
+	if (adev->hdp.ras_funcs &&
+	    adev->hdp.ras_funcs->ras_late_init) {
+		r = adev->hdp.ras_funcs->ras_late_init(adev);
+		if (r)
+			return r;
+	}
+
 	return 0;
 }
 
@@ -426,11 +482,15 @@ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
 
 	if (adev->mmhub.ras_funcs &&
 	    adev->mmhub.ras_funcs->ras_fini)
-		amdgpu_mmhub_ras_fini(adev);
+		adev->mmhub.ras_funcs->ras_fini(adev);
 
 	if (adev->gmc.xgmi.ras_funcs &&
 	    adev->gmc.xgmi.ras_funcs->ras_fini)
 		adev->gmc.xgmi.ras_funcs->ras_fini(adev);
+
+	if (adev->hdp.ras_funcs &&
+	    adev->hdp.ras_funcs->ras_fini)
+		adev->hdp.ras_funcs->ras_fini(adev);
 }
 
 	/*
@@ -477,7 +537,7 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_tmz_set -- check and set if a device supports TMZ
+ * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ
  * @adev: amdgpu_device pointer
  *
  * Check and set if an the device @adev supports Trusted Memory
@@ -523,7 +583,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_noretry_set -- set per asic noretry defaults
+ * amdgpu_gmc_noretry_set -- set per asic noretry defaults
  * @adev: amdgpu_device pointer
  *
  * Set a per asic default for the no-retry parameter.
@@ -578,13 +638,18 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
 	for (i = 0; i < 16; i++) {
 		reg = hub->vm_context0_cntl + hub->ctx_distance * i;
 
-		tmp = RREG32(reg);
+		tmp = (hub_type == AMDGPU_GFXHUB_0) ?
+			RREG32_SOC15_IP(GC, reg) :
+			RREG32_SOC15_IP(MMHUB, reg);
+
 		if (enable)
 			tmp |= hub->vm_cntx_cntl_vm_fault;
 		else
 			tmp &= ~hub->vm_cntx_cntl_vm_fault;
 
-		WREG32(reg, tmp);
+		(hub_type == AMDGPU_GFXHUB_0) ?
+			WREG32_SOC15_IP(GC, reg, tmp) :
+			WREG32_SOC15_IP(MMHUB, reg, tmp);
 	}
 }
 
@@ -720,3 +785,22 @@ uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo
 {
 	return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
 }
+
+void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev)
+{
+	/* Some ASICs need to reserve a region of video memory to avoid access
+	 * from driver */
+	adev->mman.stolen_reserved_offset = 0;
+	adev->mman.stolen_reserved_size = 0;
+
+	switch (adev->asic_type) {
+	case CHIP_YELLOW_CARP:
+		if (amdgpu_discovery == 0) {
+			adev->mman.stolen_reserved_offset = 0x1ffb0000;
+			adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
+		}
+		break;
+	default:
+		break;
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 9d11c02a3938..e55201134a01 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -66,9 +66,9 @@ struct firmware;
  * GMC page fault information
  */
 struct amdgpu_gmc_fault {
-	uint64_t	timestamp;
+	uint64_t	timestamp:48;
 	uint64_t	next:AMDGPU_GMC_FAULT_RING_ORDER;
-	uint64_t	key:52;
+	atomic64_t	key;
 };
 
 /*
@@ -318,6 +318,8 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
 			     struct amdgpu_gmc *mc);
 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
 			      uint16_t pasid, uint64_t timestamp);
+void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
+				     uint16_t pasid);
 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
@@ -330,6 +332,7 @@ amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
 			      bool enable);
 
 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
+void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev);
 
 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 540c01052b21..ec96e0b26b11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -22,17 +22,26 @@
  * Authors: Christian König
  */
 
+#include <drm/ttm/ttm_range_manager.h>
+
 #include "amdgpu.h"
 
-static inline struct amdgpu_gtt_mgr *to_gtt_mgr(struct ttm_resource_manager *man)
+struct amdgpu_gtt_node {
+	struct ttm_buffer_object *tbo;
+	struct ttm_range_mgr_node base;
+};
+
+static inline struct amdgpu_gtt_mgr *
+to_gtt_mgr(struct ttm_resource_manager *man)
 {
 	return container_of(man, struct amdgpu_gtt_mgr, manager);
 }
 
-struct amdgpu_gtt_node {
-	struct drm_mm_node node;
-	struct ttm_buffer_object *tbo;
-};
+static inline struct amdgpu_gtt_node *
+to_amdgpu_gtt_node(struct ttm_resource *res)
+{
+	return container_of(res, struct amdgpu_gtt_node, base.base);
+}
 
 /**
  * DOC: mem_info_gtt_total
@@ -43,12 +52,14 @@ struct amdgpu_gtt_node {
  * the GTT block, in bytes
  */
 static ssize_t amdgpu_mem_info_gtt_total_show(struct device *dev,
-		struct device_attribute *attr, char *buf)
+					      struct device_attribute *attr,
+					      char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = drm_to_adev(ddev);
-	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
+	struct ttm_resource_manager *man;
 
+	man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 	return sysfs_emit(buf, "%llu\n", man->size * PAGE_SIZE);
 }
 
@@ -61,12 +72,14 @@ static ssize_t amdgpu_mem_info_gtt_total_show(struct device *dev,
  * size of the GTT block, in bytes
  */
 static ssize_t amdgpu_mem_info_gtt_used_show(struct device *dev,
-		struct device_attribute *attr, char *buf)
+					     struct device_attribute *attr,
+					     char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = drm_to_adev(ddev);
-	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
+	struct ttm_resource_manager *man;
 
+	man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 	return sysfs_emit(buf, "%llu\n", amdgpu_gtt_mgr_usage(man));
 }
 
@@ -75,90 +88,28 @@ static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO,
 static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO,
 	           amdgpu_mem_info_gtt_used_show, NULL);
 
-static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func;
-/**
- * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
- *
- * @adev: amdgpu_device pointer
- * @gtt_size: maximum size of GTT
- *
- * Allocate and initialize the GTT manager.
- */
-int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
-{
-	struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr;
-	struct ttm_resource_manager *man = &mgr->manager;
-	uint64_t start, size;
-	int ret;
-
-	man->use_tt = true;
-	man->func = &amdgpu_gtt_mgr_func;
-
-	ttm_resource_manager_init(man, gtt_size >> PAGE_SHIFT);
-
-	start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
-	size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
-	drm_mm_init(&mgr->mm, start, size);
-	spin_lock_init(&mgr->lock);
-	atomic64_set(&mgr->available, gtt_size >> PAGE_SHIFT);
-
-	ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_total);
-	if (ret) {
-		DRM_ERROR("Failed to create device file mem_info_gtt_total\n");
-		return ret;
-	}
-	ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_used);
-	if (ret) {
-		DRM_ERROR("Failed to create device file mem_info_gtt_used\n");
-		return ret;
-	}
-
-	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager);
-	ttm_resource_manager_set_used(man, true);
-	return 0;
-}
-
-/**
- * amdgpu_gtt_mgr_fini - free and destroy GTT manager
- *
- * @adev: amdgpu_device pointer
- *
- * Destroy and free the GTT manager, returns -EBUSY if ranges are still
- * allocated inside it.
- */
-void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev)
-{
-	struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr;
-	struct ttm_resource_manager *man = &mgr->manager;
-	int ret;
-
-	ttm_resource_manager_set_used(man, false);
-
-	ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
-	if (ret)
-		return;
-
-	spin_lock(&mgr->lock);
-	drm_mm_takedown(&mgr->mm);
-	spin_unlock(&mgr->lock);
-
-	device_remove_file(adev->dev, &dev_attr_mem_info_gtt_total);
-	device_remove_file(adev->dev, &dev_attr_mem_info_gtt_used);
+static struct attribute *amdgpu_gtt_mgr_attributes[] = {
+	&dev_attr_mem_info_gtt_total.attr,
+	&dev_attr_mem_info_gtt_used.attr,
+	NULL
+};
 
-	ttm_resource_manager_cleanup(man);
-	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL);
-}
+const struct attribute_group amdgpu_gtt_mgr_attr_group = {
+	.attrs = amdgpu_gtt_mgr_attributes
+};
 
 /**
  * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space
  *
- * @mem: the mem object to check
+ * @res: the mem object to check
  *
  * Check if a mem object has already address space allocated.
  */
-bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem)
+bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *res)
 {
-	return mem->mm_node != NULL;
+	struct amdgpu_gtt_node *node = to_amdgpu_gtt_node(res);
+
+	return drm_mm_node_allocated(&node->base.mm_nodes[0]);
 }
 
 /**
@@ -174,54 +125,57 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem)
 static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
 			      struct ttm_buffer_object *tbo,
 			      const struct ttm_place *place,
-			      struct ttm_resource *mem)
+			      struct ttm_resource **res)
 {
 	struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
+	uint32_t num_pages = PFN_UP(tbo->base.size);
 	struct amdgpu_gtt_node *node;
 	int r;
 
 	spin_lock(&mgr->lock);
-	if ((&tbo->mem == mem || tbo->mem.mem_type != TTM_PL_TT) &&
-	    atomic64_read(&mgr->available) < mem->num_pages) {
+	if (tbo->resource && tbo->resource->mem_type != TTM_PL_TT &&
+	    atomic64_read(&mgr->available) < num_pages) {
 		spin_unlock(&mgr->lock);
 		return -ENOSPC;
 	}
-	atomic64_sub(mem->num_pages, &mgr->available);
+	atomic64_sub(num_pages, &mgr->available);
 	spin_unlock(&mgr->lock);
 
-	if (!place->lpfn) {
-		mem->mm_node = NULL;
-		mem->start = AMDGPU_BO_INVALID_OFFSET;
-		return 0;
-	}
-
-	node = kzalloc(sizeof(*node), GFP_KERNEL);
+	node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL);
 	if (!node) {
 		r = -ENOMEM;
 		goto err_out;
 	}
 
 	node->tbo = tbo;
+	ttm_resource_init(tbo, place, &node->base.base);
 
-	spin_lock(&mgr->lock);
-	r = drm_mm_insert_node_in_range(&mgr->mm, &node->node, mem->num_pages,
-					mem->page_alignment, 0, place->fpfn,
-					place->lpfn, DRM_MM_INSERT_BEST);
-	spin_unlock(&mgr->lock);
-
-	if (unlikely(r))
-		goto err_free;
-
-	mem->mm_node = node;
-	mem->start = node->node.start;
+	if (place->lpfn) {
+		spin_lock(&mgr->lock);
+		r = drm_mm_insert_node_in_range(&mgr->mm,
+						&node->base.mm_nodes[0],
+						num_pages, tbo->page_alignment,
+						0, place->fpfn, place->lpfn,
+						DRM_MM_INSERT_BEST);
+		spin_unlock(&mgr->lock);
+		if (unlikely(r))
+			goto err_free;
+
+		node->base.base.start = node->base.mm_nodes[0].start;
+	} else {
+		node->base.mm_nodes[0].start = 0;
+		node->base.mm_nodes[0].size = node->base.base.num_pages;
+		node->base.base.start = AMDGPU_BO_INVALID_OFFSET;
+	}
 
+	*res = &node->base.base;
 	return 0;
 
 err_free:
 	kfree(node);
 
 err_out:
-	atomic64_add(mem->num_pages, &mgr->available);
+	atomic64_add(num_pages, &mgr->available);
 
 	return r;
 }
@@ -235,19 +189,18 @@ err_out:
  * Free the allocated GTT again.
  */
 static void amdgpu_gtt_mgr_del(struct ttm_resource_manager *man,
-			       struct ttm_resource *mem)
+			       struct ttm_resource *res)
 {
+	struct amdgpu_gtt_node *node = to_amdgpu_gtt_node(res);
 	struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
-	struct amdgpu_gtt_node *node = mem->mm_node;
 
-	if (node) {
-		spin_lock(&mgr->lock);
-		drm_mm_remove_node(&node->node);
-		spin_unlock(&mgr->lock);
-		kfree(node);
-	}
+	spin_lock(&mgr->lock);
+	if (drm_mm_node_allocated(&node->base.mm_nodes[0]))
+		drm_mm_remove_node(&node->base.mm_nodes[0]);
+	spin_unlock(&mgr->lock);
+	atomic64_add(res->num_pages, &mgr->available);
 
-	atomic64_add(mem->num_pages, &mgr->available);
+	kfree(node);
 }
 
 /**
@@ -265,22 +218,33 @@ uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man)
 	return (result > 0 ? result : 0) * PAGE_SIZE;
 }
 
+/**
+ * amdgpu_gtt_mgr_recover - re-init gart
+ *
+ * @man: TTM memory type manager
+ *
+ * Re-init the gart for each known BO in the GTT.
+ */
 int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man)
 {
 	struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
+	struct amdgpu_device *adev;
 	struct amdgpu_gtt_node *node;
 	struct drm_mm_node *mm_node;
 	int r = 0;
 
+	adev = container_of(mgr, typeof(*adev), mman.gtt_mgr);
 	spin_lock(&mgr->lock);
 	drm_mm_for_each_node(mm_node, &mgr->mm) {
-		node = container_of(mm_node, struct amdgpu_gtt_node, node);
+		node = container_of(mm_node, typeof(*node), base.mm_nodes[0]);
 		r = amdgpu_ttm_recover_gart(node->tbo);
 		if (r)
 			break;
 	}
 	spin_unlock(&mgr->lock);
 
+	amdgpu_gart_invalidate_tlb(adev);
+
 	return r;
 }
 
@@ -311,3 +275,61 @@ static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = {
 	.free = amdgpu_gtt_mgr_del,
 	.debug = amdgpu_gtt_mgr_debug
 };
+
+/**
+ * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
+ *
+ * @adev: amdgpu_device pointer
+ * @gtt_size: maximum size of GTT
+ *
+ * Allocate and initialize the GTT manager.
+ */
+int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
+{
+	struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr;
+	struct ttm_resource_manager *man = &mgr->manager;
+	uint64_t start, size;
+
+	man->use_tt = true;
+	man->func = &amdgpu_gtt_mgr_func;
+
+	ttm_resource_manager_init(man, gtt_size >> PAGE_SHIFT);
+
+	start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
+	size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
+	drm_mm_init(&mgr->mm, start, size);
+	spin_lock_init(&mgr->lock);
+	atomic64_set(&mgr->available, gtt_size >> PAGE_SHIFT);
+
+	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager);
+	ttm_resource_manager_set_used(man, true);
+	return 0;
+}
+
+/**
+ * amdgpu_gtt_mgr_fini - free and destroy GTT manager
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Destroy and free the GTT manager, returns -EBUSY if ranges are still
+ * allocated inside it.
+ */
+void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev)
+{
+	struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr;
+	struct ttm_resource_manager *man = &mgr->manager;
+	int ret;
+
+	ttm_resource_manager_set_used(man, false);
+
+	ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
+	if (ret)
+		return;
+
+	spin_lock(&mgr->lock);
+	drm_mm_takedown(&mgr->mm);
+	spin_unlock(&mgr->lock);
+
+	ttm_resource_manager_cleanup(man);
+	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
new file mode 100644
index 000000000000..1d50d534d77c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "amdgpu_ras.h"
+
+int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev)
+{
+	int r;
+	struct ras_ih_if ih_info = {
+		.cb = NULL,
+	};
+	struct ras_fs_if fs_info = {
+		.sysfs_name = "hdp_err_count",
+	};
+
+	if (!adev->hdp.ras_if) {
+		adev->hdp.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+		if (!adev->hdp.ras_if)
+			return -ENOMEM;
+		adev->hdp.ras_if->block = AMDGPU_RAS_BLOCK__HDP;
+		adev->hdp.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+		adev->hdp.ras_if->sub_block_index = 0;
+		strcpy(adev->hdp.ras_if->name, "hdp");
+	}
+	ih_info.head = fs_info.head = *adev->hdp.ras_if;
+	r = amdgpu_ras_late_init(adev, adev->hdp.ras_if,
+				 &fs_info, &ih_info);
+	if (r || !amdgpu_ras_is_supported(adev, adev->hdp.ras_if->block)) {
+		kfree(adev->hdp.ras_if);
+		adev->hdp.ras_if = NULL;
+	}
+
+	return r;
+}
+
+void amdgpu_hdp_ras_fini(struct amdgpu_device *adev)
+{
+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP) &&
+	    adev->hdp.ras_if) {
+		struct ras_common_if *ras_if = adev->hdp.ras_if;
+		struct ras_ih_if ih_info = {
+			.cb = NULL,
+		};
+
+		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
+		kfree(ras_if);
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
index 43caf9f8cc11..7ec99d591584 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
@@ -23,18 +23,29 @@
 #ifndef __AMDGPU_HDP_H__
 #define __AMDGPU_HDP_H__
 
+struct amdgpu_hdp_ras_funcs {
+	int (*ras_late_init)(struct amdgpu_device *adev);
+	void (*ras_fini)(struct amdgpu_device *adev);
+	void (*query_ras_error_count)(struct amdgpu_device *adev,
+				      void *ras_error_status);
+	void (*reset_ras_error_count)(struct amdgpu_device *adev);
+};
+
 struct amdgpu_hdp_funcs {
 	void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 	void (*invalidate_hdp)(struct amdgpu_device *adev,
 			       struct amdgpu_ring *ring);
-	void (*reset_ras_error_count)(struct amdgpu_device *adev);
 	void (*update_clock_gating)(struct amdgpu_device *adev, bool enable);
 	void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags);
 	void (*init_registers)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_hdp {
+	struct ras_common_if			*ras_if;
 	const struct amdgpu_hdp_funcs		*funcs;
+	const struct amdgpu_hdp_ras_funcs	*ras_funcs;
 };
 
+int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev);
+void amdgpu_hdp_ras_fini(struct amdgpu_device *adev);
 #endif /* __AMDGPU_HDP_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c1..ec65ab0ddf89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -130,7 +130,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	struct amdgpu_device *adev = ring->adev;
 	struct amdgpu_ib *ib = &ibs[0];
 	struct dma_fence *tmp = NULL;
-	bool skip_preamble, need_ctx_switch;
+	bool need_ctx_switch;
 	unsigned patch_offset = ~0;
 	struct amdgpu_vm *vm;
 	uint64_t fence_ctx;
@@ -214,20 +214,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if (job && ring->funcs->init_cond_exec)
 		patch_offset = amdgpu_ring_init_cond_exec(ring);
 
-#ifdef CONFIG_X86_64
-	if (!(adev->flags & AMD_IS_APU))
-#endif
-	{
-		if (ring->funcs->emit_hdp_flush)
-			amdgpu_ring_emit_hdp_flush(ring);
-		else
-			amdgpu_asic_flush_hdp(adev, ring);
-	}
+	amdgpu_device_flush_hdp(adev, ring);
 
 	if (need_ctx_switch)
 		status |= AMDGPU_HAVE_CTX_SWITCH;
 
-	skip_preamble = ring->current_ctx == fence_ctx;
 	if (job && ring->funcs->emit_cntxcntl) {
 		status |= job->preamble_status;
 		status |= job->preemption_status;
@@ -245,14 +236,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	for (i = 0; i < num_ibs; ++i) {
 		ib = &ibs[i];
 
-		/* drop preamble IBs if we don't have a context switch */
-		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-		    skip_preamble &&
-		    !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
-		    !amdgpu_mcbp &&
-		    !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
-			continue;
-
 		if (job && ring->funcs->emit_frame_cntl) {
 			if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
 				amdgpu_ring_emit_frame_cntl(ring, false, secure);
@@ -268,10 +251,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if (job && ring->funcs->emit_frame_cntl)
 		amdgpu_ring_emit_frame_cntl(ring, false, secure);
 
-#ifdef CONFIG_X86_64
-	if (!(adev->flags & AMD_IS_APU))
-#endif
-		amdgpu_asic_invalidate_hdp(adev, ring);
+	amdgpu_device_invalidate_hdp(adev, ring);
 
 	if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
 		fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
@@ -328,7 +308,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
 
 	for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
 		if (i == AMDGPU_IB_POOL_DIRECT)
-			size = PAGE_SIZE * 2;
+			size = PAGE_SIZE * 6;
 		else
 			size = AMDGPU_IB_POOL_SIZE;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index b4971e90b98c..b7fb72bff2c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -112,7 +112,7 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,
 	unsigned count;
 	int r;
 
-	r = dma_resv_get_fences_rcu(resv, NULL, &count, &fences);
+	r = dma_resv_get_fences(resv, NULL, &count, &fences);
 	if (r)
 		goto fallback;
 
@@ -156,8 +156,7 @@ fallback:
 	/* Not enough memory for the delayed delete, as last resort
 	 * block for all the fences to complete.
 	 */
-	dma_resv_wait_timeout_rcu(resv, true, false,
-					    MAX_SCHEDULE_TIMEOUT);
+	dma_resv_wait_timeout(resv, true, false, MAX_SCHEDULE_TIMEOUT);
 	amdgpu_pasid_free(pasid);
 }
 
@@ -183,7 +182,7 @@ bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
 }
 
 /**
- * amdgpu_vm_grab_idle - grab idle VMID
+ * amdgpu_vmid_grab_idle - grab idle VMID
  *
  * @vm: vm to allocate id for
  * @ring: ring we want to submit job to
@@ -256,7 +255,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
 }
 
 /**
- * amdgpu_vm_grab_reserved - try to assign reserved VMID
+ * amdgpu_vmid_grab_reserved - try to assign reserved VMID
  *
  * @vm: vm to allocate id for
  * @ring: ring we want to submit job to
@@ -325,7 +324,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
 }
 
 /**
- * amdgpu_vm_grab_used - try to reuse a VMID
+ * amdgpu_vmid_grab_used - try to reuse a VMID
  *
  * @vm: vm to allocate id for
  * @ring: ring we want to submit job to
@@ -397,7 +396,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
 }
 
 /**
- * amdgpu_vm_grab_id - allocate the next free VMID
+ * amdgpu_vmid_grab - allocate the next free VMID
  *
  * @vm: vm to allocate id for
  * @ring: ring we want to submit job to
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index faaa6aa2faaf..f3d62e196901 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -115,9 +115,11 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
  */
 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
 {
+
+	if (!ih->ring)
+		return;
+
 	if (ih->use_bus_addr) {
-		if (!ih->ring)
-			return;
 
 		/* add 8 bytes for the rptr/wptr shadows and
 		 * add them to the end of the ring allocation.
@@ -175,7 +177,9 @@ static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev,
 		cur_rptr += ih->ptr_mask + 1;
 	*prev_rptr = cur_rptr;
 
-	return cur_rptr >= checkpoint_wptr;
+	/* check ring is empty to workaround missing wptr overflow flag */
+	return cur_rptr >= checkpoint_wptr ||
+	       (cur_rptr & ih->ptr_mask) == amdgpu_ih_get_wptr(adev, ih);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 90f50561b43a..32ce0e679dc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -49,6 +49,7 @@
 #include <drm/drm_irq.h>
 #include <drm/drm_vblank.h>
 #include <drm/amdgpu_drm.h>
+#include <drm/drm_drv.h>
 #include "amdgpu.h"
 #include "amdgpu_ih.h"
 #include "atom.h"
@@ -348,6 +349,25 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 	return 0;
 }
 
+
+void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
+{
+	if (adev->irq.installed) {
+		drm_irq_uninstall(&adev->ddev);
+		adev->irq.installed = false;
+		if (adev->irq.msi_enabled)
+			pci_free_irq_vectors(adev->pdev);
+
+		if (!amdgpu_device_has_dc_support(adev))
+			flush_work(&adev->hotplug_work);
+	}
+
+	amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
+	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
+	amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
+}
+
 /**
  * amdgpu_irq_fini - shut down interrupt handling
  *
@@ -357,19 +377,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
  * functionality, shuts down vblank, hotplug and reset interrupt handling,
  * turns off interrupts from all sources (all ASICs).
  */
-void amdgpu_irq_fini(struct amdgpu_device *adev)
+void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
 {
 	unsigned i, j;
 
-	if (adev->irq.installed) {
-		drm_irq_uninstall(adev_to_drm(adev));
-		adev->irq.installed = false;
-		if (adev->irq.msi_enabled)
-			pci_free_irq_vectors(adev->pdev);
-		if (!amdgpu_device_has_dc_support(adev))
-			flush_work(&adev->hotplug_work);
-	}
-
 	for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
 		if (!adev->irq.client[i].sources)
 			continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index cf6116648322..78ad4784cc74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -103,7 +103,8 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev);
 irqreturn_t amdgpu_irq_handler(int irq, void *arg);
 
 int amdgpu_irq_init(struct amdgpu_device *adev);
-void amdgpu_irq_fini(struct amdgpu_device *adev);
+void amdgpu_irq_fini_sw(struct amdgpu_device *adev);
+void amdgpu_irq_fini_hw(struct amdgpu_device *adev);
 int amdgpu_irq_add_id(struct amdgpu_device *adev,
 		      unsigned client_id, unsigned src_id,
 		      struct amdgpu_irq_src *source);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 759b34799221..d33e6d97cc89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -25,6 +25,8 @@
 #include <linux/wait.h>
 #include <linux/sched.h>
 
+#include <drm/drm_drv.h>
+
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
 
@@ -34,6 +36,15 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
 	struct amdgpu_job *job = to_amdgpu_job(s_job);
 	struct amdgpu_task_info ti;
 	struct amdgpu_device *adev = ring->adev;
+	int idx;
+
+	if (!drm_dev_enter(&adev->ddev, &idx)) {
+		DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
+			 __func__, s_job->sched->name);
+
+		/* Effectively the job is aborted as the device is gone */
+		return DRM_GPU_SCHED_STAT_ENODEV;
+	}
 
 	memset(&ti, 0, sizeof(struct amdgpu_task_info));
 
@@ -41,7 +52,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
 	    amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
 		DRM_ERROR("ring %s timeout, but soft recovered\n",
 			  s_job->sched->name);
-		return DRM_GPU_SCHED_STAT_NOMINAL;
+		goto exit;
 	}
 
 	amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
@@ -53,13 +64,15 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
 
 	if (amdgpu_device_should_recover_gpu(ring->adev)) {
 		amdgpu_device_gpu_recover(ring->adev, job);
-		return DRM_GPU_SCHED_STAT_NOMINAL;
 	} else {
 		drm_sched_suspend_timeout(&ring->sched);
 		if (amdgpu_sriov_vf(adev))
 			adev->virt.tdr_debug = true;
-		return DRM_GPU_SCHED_STAT_NOMINAL;
 	}
+
+exit:
+	drm_dev_exit(idx);
+	return DRM_GPU_SCHED_STAT_NOMINAL;
 }
 
 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 39ee88d29cca..96ef3f1051d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -28,6 +28,7 @@
 
 #include "amdgpu.h"
 #include <drm/amdgpu_drm.h>
+#include <drm/drm_drv.h>
 #include "amdgpu_uvd.h"
 #include "amdgpu_vce.h"
 #include "atom.h"
@@ -91,8 +92,11 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)
 		pm_runtime_forbid(dev->dev);
 	}
 
+	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
+		DRM_WARN("smart shift update failed\n");
+
 	amdgpu_acpi_fini(adev);
-	amdgpu_device_fini(adev);
+	amdgpu_device_fini_hw(adev);
 }
 
 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
@@ -120,6 +124,22 @@ void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 	mutex_unlock(&mgpu_info.mutex);
 }
 
+static void amdgpu_get_audio_func(struct amdgpu_device *adev)
+{
+	struct pci_dev *p = NULL;
+
+	p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
+			adev->pdev->bus->number, 1);
+	if (p) {
+		pm_runtime_get_sync(&p->dev);
+
+		pm_runtime_mark_last_busy(&p->dev);
+		pm_runtime_put_autosuspend(&p->dev);
+
+		pci_dev_put(p);
+	}
+}
+
 /**
  * amdgpu_driver_load_kms - Main load function for KMS.
  *
@@ -209,11 +229,40 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 						DPM_FLAG_MAY_SKIP_RESUME);
 		pm_runtime_use_autosuspend(dev->dev);
 		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
+
 		pm_runtime_allow(dev->dev);
+
 		pm_runtime_mark_last_busy(dev->dev);
 		pm_runtime_put_autosuspend(dev->dev);
+
+		/*
+		 * For runpm implemented via BACO, PMFW will handle the
+		 * timing for BACO in and out:
+		 *   - put ASIC into BACO state only when both video and
+		 *     audio functions are in D3 state.
+		 *   - pull ASIC out of BACO state when either video or
+		 *     audio function is in D0 state.
+		 * Also, at startup, PMFW assumes both functions are in
+		 * D0 state.
+		 *
+		 * So if snd driver was loaded prior to amdgpu driver
+		 * and audio function was put into D3 state, there will
+		 * be no PMFW-aware D-state transition(D0->D3) on runpm
+		 * suspend. Thus the BACO will be not correctly kicked in.
+		 *
+		 * Via amdgpu_get_audio_func(), the audio dev is put
+		 * into D0 state. Then there will be a PMFW-aware D-state
+		 * transition(D0->D3) on runpm suspend.
+		 */
+		if (amdgpu_device_supports_baco(dev) &&
+		    !(adev->flags & AMD_IS_APU) &&
+		    (adev->asic_type >= CHIP_NAVI10))
+			amdgpu_get_audio_func(adev);
 	}
 
+	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
+		DRM_WARN("smart shift update failed\n");
+
 out:
 	if (r) {
 		/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
@@ -861,6 +910,21 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 					    min((size_t)size, (size_t)(bios_size - bios_offset)))
 					? -EFAULT : 0;
 		}
+		case AMDGPU_INFO_VBIOS_INFO: {
+			struct drm_amdgpu_info_vbios vbios_info = {};
+			struct atom_context *atom_context;
+
+			atom_context = adev->mode_info.atom_context;
+			memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
+			memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
+			vbios_info.version = atom_context->version;
+			memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
+						sizeof(atom_context->vbios_ver_str));
+			memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
+
+			return copy_to_user(out, &vbios_info,
+						min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
+		}
 		default:
 			DRM_DEBUG_KMS("Invalid request %d\n",
 					info->vbios_info.type);
@@ -986,7 +1050,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 
 		if (!ras)
 			return -EINVAL;
-		ras_mask = (uint64_t)ras->supported << 32 | ras->features;
+		ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
 
 		return copy_to_user(out, &ras_mask,
 				min_t(u64, size, sizeof(ras_mask))) ?
@@ -1114,7 +1178,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 		dev_warn(adev->dev, "No more PASIDs available!");
 		pasid = 0;
 	}
-	r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
+
+	r = amdgpu_vm_init(adev, &fpriv->vm, pasid);
 	if (r)
 		goto error_pasid;
 
@@ -1197,7 +1262,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
 	}
 
 	pasid = fpriv->vm.pasid;
-	pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
+	pd = amdgpu_bo_ref(fpriv->vm.root.bo);
 
 	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 	amdgpu_vm_fini(adev, &fpriv->vm);
@@ -1219,6 +1284,15 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
 	pm_runtime_put_autosuspend(dev->dev);
 }
 
+
+void amdgpu_driver_release_kms(struct drm_device *dev)
+{
+	struct amdgpu_device *adev = drm_to_adev(dev);
+
+	amdgpu_device_fini_sw(adev);
+	pci_set_drvdata(adev->pdev, NULL);
+}
+
 /*
  * VBlank related functions.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
index 11aa29933c1f..b27fcbccce2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
@@ -28,6 +28,7 @@ struct amdgpu_mmhub_ras_funcs {
 				      void *ras_error_status);
 	void (*query_ras_error_status)(struct amdgpu_device *adev);
 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
+	void (*reset_ras_error_status)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_mmhub_funcs {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 828b5167ff12..d6c54c7f7679 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -75,8 +75,8 @@ static bool amdgpu_mn_invalidate_gfx(struct mmu_interval_notifier *mni,
 
 	mmu_interval_set_seq(mni, cur_seq);
 
-	r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, true, false,
-				      MAX_SCHEDULE_TIMEOUT);
+	r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false,
+				  MAX_SCHEDULE_TIMEOUT);
 	mutex_unlock(&adev->notifier_lock);
 	if (r <= 0)
 		DRM_ERROR("(%ld) failed to wait for user bo\n", r);
@@ -155,3 +155,89 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
 	mmu_interval_notifier_remove(&bo->notifier);
 	bo->notifier.mm = NULL;
 }
+
+int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,
+			       struct mm_struct *mm, struct page **pages,
+			       uint64_t start, uint64_t npages,
+			       struct hmm_range **phmm_range, bool readonly,
+			       bool mmap_locked)
+{
+	struct hmm_range *hmm_range;
+	unsigned long timeout;
+	unsigned long i;
+	unsigned long *pfns;
+	int r = 0;
+
+	hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL);
+	if (unlikely(!hmm_range))
+		return -ENOMEM;
+
+	pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL);
+	if (unlikely(!pfns)) {
+		r = -ENOMEM;
+		goto out_free_range;
+	}
+
+	hmm_range->notifier = notifier;
+	hmm_range->default_flags = HMM_PFN_REQ_FAULT;
+	if (!readonly)
+		hmm_range->default_flags |= HMM_PFN_REQ_WRITE;
+	hmm_range->hmm_pfns = pfns;
+	hmm_range->start = start;
+	hmm_range->end = start + npages * PAGE_SIZE;
+
+	/* Assuming 512MB takes maxmium 1 second to fault page address */
+	timeout = max(npages >> 17, 1ULL) * HMM_RANGE_DEFAULT_TIMEOUT;
+	timeout = jiffies + msecs_to_jiffies(timeout);
+
+retry:
+	hmm_range->notifier_seq = mmu_interval_read_begin(notifier);
+
+	if (likely(!mmap_locked))
+		mmap_read_lock(mm);
+
+	r = hmm_range_fault(hmm_range);
+
+	if (likely(!mmap_locked))
+		mmap_read_unlock(mm);
+	if (unlikely(r)) {
+		/*
+		 * FIXME: This timeout should encompass the retry from
+		 * mmu_interval_read_retry() as well.
+		 */
+		if (r == -EBUSY && !time_after(jiffies, timeout))
+			goto retry;
+		goto out_free_pfns;
+	}
+
+	/*
+	 * Due to default_flags, all pages are HMM_PFN_VALID or
+	 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
+	 * the notifier_lock, and mmu_interval_read_retry() must be done first.
+	 */
+	for (i = 0; pages && i < npages; i++)
+		pages[i] = hmm_pfn_to_page(pfns[i]);
+
+	*phmm_range = hmm_range;
+
+	return 0;
+
+out_free_pfns:
+	kvfree(pfns);
+out_free_range:
+	kfree(hmm_range);
+
+	return r;
+}
+
+int amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range)
+{
+	int r;
+
+	r = mmu_interval_read_retry(hmm_range->notifier,
+				    hmm_range->notifier_seq);
+	kvfree(hmm_range->hmm_pfns);
+	kfree(hmm_range);
+
+	return r;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
index a292238f75eb..7f7d37a457c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
@@ -30,6 +30,13 @@
 #include <linux/workqueue.h>
 #include <linux/interval_tree.h>
 
+int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,
+			       struct mm_struct *mm, struct page **pages,
+			       uint64_t start, uint64_t npages,
+			       struct hmm_range **phmm_range, bool readonly,
+			       bool mmap_locked);
+int amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range);
+
 #if defined(CONFIG_HMM_MIRROR)
 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index cb0b581bbce7..89fb372ed49c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -344,7 +344,7 @@ struct amdgpu_mode_info {
 	/* pointer to fbdev info structure */
 	struct amdgpu_fbdev *rfbdev;
 	/* firmware flags */
-	u16 firmware_flags;
+	u32 firmware_flags;
 	/* pointer to backlight encoder */
 	struct amdgpu_encoder *bl_encoder;
 	u8 bl_level; /* saved backlight level */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index f9434bc2f9b2..795fa7445abe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -52,55 +52,44 @@
  *
  */
 
-/**
- * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting
- *
- * @bo: &amdgpu_bo buffer object
- *
- * This function is called when a BO stops being pinned, and updates the
- * &amdgpu_device pin_size values accordingly.
- */
-static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo)
+static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
 {
-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
 
-	if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
-		atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
-		atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
-			     &adev->visible_pin_size);
-	} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
-		atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
-	}
+	amdgpu_bo_kunmap(bo);
+
+	if (bo->tbo.base.import_attach)
+		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
+	drm_gem_object_release(&bo->tbo.base);
+	amdgpu_bo_unref(&bo->parent);
+	kvfree(bo);
 }
 
-static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
+static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
 {
-	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
 	struct amdgpu_bo_user *ubo;
 
-	if (bo->tbo.pin_count > 0)
-		amdgpu_bo_subtract_pin_size(bo);
+	ubo = to_amdgpu_bo_user(bo);
+	kfree(ubo->metadata);
+	amdgpu_bo_destroy(tbo);
+}
 
-	amdgpu_bo_kunmap(bo);
+static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
+{
+	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
+	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
+	struct amdgpu_bo_vm *vmbo;
 
-	if (bo->tbo.base.import_attach)
-		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
-	drm_gem_object_release(&bo->tbo.base);
+	vmbo = to_amdgpu_bo_vm(bo);
 	/* in case amdgpu_device_recover_vram got NULL of bo->parent */
-	if (!list_empty(&bo->shadow_list)) {
+	if (!list_empty(&vmbo->shadow_list)) {
 		mutex_lock(&adev->shadow_list_lock);
-		list_del_init(&bo->shadow_list);
+		list_del_init(&vmbo->shadow_list);
 		mutex_unlock(&adev->shadow_list_lock);
 	}
-	amdgpu_bo_unref(&bo->parent);
-
-	if (bo->tbo.type == ttm_bo_type_device) {
-		ubo = to_amdgpu_bo_user(bo);
-		kfree(ubo->metadata);
-	}
 
-	kvfree(bo);
+	amdgpu_bo_destroy(tbo);
 }
 
 /**
@@ -115,8 +104,11 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
  */
 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 {
-	if (bo->destroy == &amdgpu_bo_destroy)
+	if (bo->destroy == &amdgpu_bo_destroy ||
+	    bo->destroy == &amdgpu_bo_user_destroy ||
+	    bo->destroy == &amdgpu_bo_vm_destroy)
 		return true;
+
 	return false;
 }
 
@@ -157,7 +149,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 		places[c].fpfn = 0;
 		places[c].lpfn = 0;
-		places[c].mem_type = TTM_PL_TT;
+		places[c].mem_type =
+			abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
+			AMDGPU_PL_PREEMPT : TTM_PL_TT;
 		places[c].flags = 0;
 		c++;
 	}
@@ -386,14 +380,14 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
 	if (cpu_addr)
 		amdgpu_bo_kunmap(*bo_ptr);
 
-	ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
+	ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
 
 	for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
 		(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
 		(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
 	}
 	r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
-			     &(*bo_ptr)->tbo.mem, &ctx);
+			     &(*bo_ptr)->tbo.resource, &ctx);
 	if (r)
 		goto error;
 
@@ -515,7 +509,18 @@ bool amdgpu_bo_support_uswc(u64 bo_flags)
 #endif
 }
 
-static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+/**
+ * amdgpu_bo_create - create an &amdgpu_bo buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @bo_ptr: pointer to the buffer object pointer
+ *
+ * Creates an &amdgpu_bo buffer object.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+int amdgpu_bo_create(struct amdgpu_device *adev,
 			       struct amdgpu_bo_param *bp,
 			       struct amdgpu_bo **bo_ptr)
 {
@@ -556,7 +561,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 	if (bo == NULL)
 		return -ENOMEM;
 	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
-	INIT_LIST_HEAD(&bo->shadow_list);
 	bo->vm_bo = NULL;
 	bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
 		bp->domain;
@@ -579,22 +583,25 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 	if (bp->type == ttm_bo_type_kernel)
 		bo->tbo.priority = 1;
 
+	if (!bp->destroy)
+		bp->destroy = &amdgpu_bo_destroy;
+
 	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
 				 &bo->placement, page_align, &ctx,  NULL,
-				 bp->resv, &amdgpu_bo_destroy);
+				 bp->resv, bp->destroy);
 	if (unlikely(r != 0))
 		return r;
 
 	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
-	    bo->tbo.mem.mem_type == TTM_PL_VRAM &&
-	    bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
+	    bo->tbo.resource->mem_type == TTM_PL_VRAM &&
+	    bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 					     ctx.bytes_moved);
 	else
 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 
 	if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
-	    bo->tbo.mem.mem_type == TTM_PL_VRAM) {
+	    bo->tbo.resource->mem_type == TTM_PL_VRAM) {
 		struct dma_fence *fence;
 
 		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
@@ -625,108 +632,68 @@ fail_unreserve:
 	return r;
 }
 
-static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
-				   unsigned long size,
-				   struct amdgpu_bo *bo)
-{
-	struct amdgpu_bo_param bp;
-	int r;
-
-	if (bo->shadow)
-		return 0;
-
-	memset(&bp, 0, sizeof(bp));
-	bp.size = size;
-	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
-	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
-		AMDGPU_GEM_CREATE_SHADOW;
-	bp.type = ttm_bo_type_kernel;
-	bp.resv = bo->tbo.base.resv;
-	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
-
-	r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
-	if (!r) {
-		bo->shadow->parent = amdgpu_bo_ref(bo);
-		mutex_lock(&adev->shadow_list_lock);
-		list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
-		mutex_unlock(&adev->shadow_list_lock);
-	}
-
-	return r;
-}
-
 /**
- * amdgpu_bo_create - create an &amdgpu_bo buffer object
+ * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
  * @adev: amdgpu device object
  * @bp: parameters to be used for the buffer object
- * @bo_ptr: pointer to the buffer object pointer
+ * @ubo_ptr: pointer to the buffer object pointer
  *
- * Creates an &amdgpu_bo buffer object; and if requested, also creates a
- * shadow object.
- * Shadow object is used to backup the original buffer object, and is always
- * in GTT.
+ * Create a BO to be used by user application;
  *
  * Returns:
  * 0 for success or a negative error code on failure.
  */
-int amdgpu_bo_create(struct amdgpu_device *adev,
-		     struct amdgpu_bo_param *bp,
-		     struct amdgpu_bo **bo_ptr)
+
+int amdgpu_bo_create_user(struct amdgpu_device *adev,
+			  struct amdgpu_bo_param *bp,
+			  struct amdgpu_bo_user **ubo_ptr)
 {
-	u64 flags = bp->flags;
+	struct amdgpu_bo *bo_ptr;
 	int r;
 
-	bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
-
-	r = amdgpu_bo_do_create(adev, bp, bo_ptr);
+	bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
+	bp->destroy = &amdgpu_bo_user_destroy;
+	r = amdgpu_bo_create(adev, bp, &bo_ptr);
 	if (r)
 		return r;
 
-	if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
-		if (!bp->resv)
-			WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
-							NULL));
-
-		r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
-
-		if (!bp->resv)
-			dma_resv_unlock((*bo_ptr)->tbo.base.resv);
-
-		if (r)
-			amdgpu_bo_unref(bo_ptr);
-	}
-
+	*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
 	return r;
 }
 
 /**
- * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
+ * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
  * @adev: amdgpu device object
  * @bp: parameters to be used for the buffer object
- * @ubo_ptr: pointer to the buffer object pointer
+ * @vmbo_ptr: pointer to the buffer object pointer
  *
- * Create a BO to be used by user application;
+ * Create a BO to be for GPUVM.
  *
  * Returns:
  * 0 for success or a negative error code on failure.
  */
 
-int amdgpu_bo_create_user(struct amdgpu_device *adev,
-			  struct amdgpu_bo_param *bp,
-			  struct amdgpu_bo_user **ubo_ptr)
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+			struct amdgpu_bo_param *bp,
+			struct amdgpu_bo_vm **vmbo_ptr)
 {
 	struct amdgpu_bo *bo_ptr;
 	int r;
 
-	bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
-	bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
-	r = amdgpu_bo_do_create(adev, bp, &bo_ptr);
+	/* bo_ptr_size will be determined by the caller and it depends on
+	 * num of amdgpu_vm_pt entries.
+	 */
+	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
+	bp->destroy = &amdgpu_bo_vm_destroy;
+	r = amdgpu_bo_create(adev, bp, &bo_ptr);
 	if (r)
 		return r;
 
-	*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
+	*vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
+	INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list);
 	return r;
 }
+
 /**
  * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
  * @bo: pointer to the buffer object
@@ -762,6 +729,22 @@ retry:
 }
 
 /**
+ * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
+ *
+ * @bo: BO that will be inserted into the shadow list
+ *
+ * Insert a BO to the shadow list.
+ */
+void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)
+{
+	struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev);
+
+	mutex_lock(&adev->shadow_list_lock);
+	list_add_tail(&vmbo->shadow_list, &adev->shadow_list);
+	mutex_unlock(&adev->shadow_list_lock);
+}
+
+/**
  * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
  *
  * @shadow: &amdgpu_bo shadow to be restored
@@ -815,12 +798,12 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 		return 0;
 	}
 
-	r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false,
-						MAX_SCHEDULE_TIMEOUT);
+	r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false,
+				  MAX_SCHEDULE_TIMEOUT);
 	if (r < 0)
 		return r;
 
-	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.mem.num_pages, &bo->kmap);
+	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);
 	if (r)
 		return r;
 
@@ -943,8 +926,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 	domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
 
 	if (bo->tbo.pin_count) {
-		uint32_t mem_type = bo->tbo.mem.mem_type;
-		uint32_t mem_flags = bo->tbo.mem.placement;
+		uint32_t mem_type = bo->tbo.resource->mem_type;
+		uint32_t mem_flags = bo->tbo.resource->placement;
 
 		if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 			return -EINVAL;
@@ -994,7 +977,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 
 	ttm_bo_pin(&bo->tbo);
 
-	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
+	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
 	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 		atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
 		atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
@@ -1037,14 +1020,22 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
  */
 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
 {
+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
 	ttm_bo_unpin(&bo->tbo);
 	if (bo->tbo.pin_count)
 		return;
 
-	amdgpu_bo_subtract_pin_size(bo);
-
 	if (bo->tbo.base.import_attach)
 		dma_buf_unpin(bo->tbo.base.import_attach);
+
+	if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
+		atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
+		atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
+			     &adev->visible_pin_size);
+	} else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
+		atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
+	}
 }
 
 /**
@@ -1123,10 +1114,6 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
 void amdgpu_bo_fini(struct amdgpu_device *adev)
 {
 	amdgpu_ttm_fini(adev);
-	if (!adev->gmc.xgmi.connected_to_cpu) {
-		arch_phys_wc_del(adev->gmc.vram_mtrr);
-		arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
-	}
 }
 
 /**
@@ -1246,6 +1233,9 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 
 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
 	ubo = to_amdgpu_bo_user(bo);
+	if (metadata_size)
+		*metadata_size = ubo->metadata_size;
+
 	if (buffer) {
 		if (buffer_size < ubo->metadata_size)
 			return -EINVAL;
@@ -1254,8 +1244,6 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 			memcpy(buffer, ubo->metadata, ubo->metadata_size);
 	}
 
-	if (metadata_size)
-		*metadata_size = ubo->metadata_size;
 	if (flags)
 		*flags = ubo->metadata_flags;
 
@@ -1278,7 +1266,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 	struct amdgpu_bo *abo;
-	struct ttm_resource *old_mem = &bo->mem;
+	struct ttm_resource *old_mem = bo->resource;
 
 	if (!amdgpu_bo_is_amdgpu_bo(bo))
 		return;
@@ -1289,7 +1277,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 	amdgpu_bo_kunmap(abo);
 
 	if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
-	    bo->mem.mem_type != TTM_PL_SYSTEM)
+	    bo->resource->mem_type != TTM_PL_SYSTEM)
 		dma_buf_move_notify(abo->tbo.base.dma_buf);
 
 	/* remember the eviction */
@@ -1304,6 +1292,26 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 	trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 }
 
+void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
+				uint64_t *gtt_mem, uint64_t *cpu_mem)
+{
+	unsigned int domain;
+
+	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
+	switch (domain) {
+	case AMDGPU_GEM_DOMAIN_VRAM:
+		*vram_mem += amdgpu_bo_size(bo);
+		break;
+	case AMDGPU_GEM_DOMAIN_GTT:
+		*gtt_mem += amdgpu_bo_size(bo);
+		break;
+	case AMDGPU_GEM_DOMAIN_CPU:
+	default:
+		*cpu_mem += amdgpu_bo_size(bo);
+		break;
+	}
+}
+
 /**
  * amdgpu_bo_release_notify - notification about a BO being released
  * @bo: pointer to a buffer object
@@ -1331,7 +1339,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
 	if (bo->base.resv == &bo->base._resv)
 		amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
 
-	if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
+	if (bo->resource->mem_type != TTM_PL_VRAM ||
 	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
 		return;
 
@@ -1362,18 +1370,17 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 	struct ttm_operation_ctx ctx = { false, false };
 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
-	unsigned long offset, size;
+	unsigned long offset;
 	int r;
 
 	/* Remember that this BO was accessed by the CPU */
 	abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 
-	if (bo->mem.mem_type != TTM_PL_VRAM)
+	if (bo->resource->mem_type != TTM_PL_VRAM)
 		return 0;
 
-	size = bo->mem.num_pages << PAGE_SHIFT;
-	offset = bo->mem.start << PAGE_SHIFT;
-	if ((offset + size) <= adev->gmc.visible_vram_size)
+	offset = bo->resource->start << PAGE_SHIFT;
+	if ((offset + bo->base.size) <= adev->gmc.visible_vram_size)
 		return 0;
 
 	/* Can't move a pinned BO to visible VRAM */
@@ -1395,10 +1402,10 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 	else if (unlikely(r))
 		return VM_FAULT_SIGBUS;
 
-	offset = bo->mem.start << PAGE_SHIFT;
+	offset = bo->resource->start << PAGE_SHIFT;
 	/* this should never happen */
-	if (bo->mem.mem_type == TTM_PL_VRAM &&
-	    (offset + size) > adev->gmc.visible_vram_size)
+	if (bo->resource->mem_type == TTM_PL_VRAM &&
+	    (offset + bo->base.size) > adev->gmc.visible_vram_size)
 		return VM_FAULT_SIGBUS;
 
 	ttm_bo_move_to_lru_tail_unlocked(bo);
@@ -1482,11 +1489,11 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
  */
 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 {
-	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
+	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
 	WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
 		     !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
-	WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
-	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
+	WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
+	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
 		     !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
 
 	return amdgpu_bo_gpu_offset_no_check(bo);
@@ -1504,8 +1511,8 @@ u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 	uint64_t offset;
 
-	offset = (bo->tbo.mem.start << PAGE_SHIFT) +
-		 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
+	offset = (bo->tbo.resource->start << PAGE_SHIFT) +
+		 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
 
 	return amdgpu_gmc_sign_extend(offset);
 }
@@ -1558,7 +1565,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
 	unsigned int pin_count;
 	u64 size;
 
-	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
+	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
 	switch (domain) {
 	case AMDGPU_GEM_DOMAIN_VRAM:
 		placement = "VRAM";
@@ -1592,7 +1599,6 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
 	amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
 	amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
 	amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
-	amdgpu_bo_print_flag(m, bo, SHADOW);
 	amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
 	amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
 	amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 2d1fefbe1e99..38c834d0f930 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -30,6 +30,8 @@
 
 #include <drm/amdgpu_drm.h>
 #include "amdgpu.h"
+#include "amdgpu_res_cursor.h"
+
 #ifdef CONFIG_MMU_NOTIFIER
 #include <linux/mmu_notifier.h>
 #endif
@@ -37,7 +39,12 @@
 #define AMDGPU_BO_INVALID_OFFSET	LONG_MAX
 #define AMDGPU_BO_MAX_PLACEMENTS	3
 
+/* BO flag to indicate a KFD userptr BO */
+#define AMDGPU_AMDKFD_CREATE_USERPTR_BO	(1ULL << 63)
+#define AMDGPU_AMDKFD_CREATE_SVM_BO	(1ULL << 62)
+
 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
+#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
 
 struct amdgpu_bo_param {
 	unsigned long			size;
@@ -48,7 +55,8 @@ struct amdgpu_bo_param {
 	u64				flags;
 	enum ttm_bo_type		type;
 	bool				no_wait_gpu;
-	struct dma_resv	*resv;
+	struct dma_resv			*resv;
+	void				(*destroy)(struct ttm_buffer_object *bo);
 };
 
 /* bo virtual addresses in a vm */
@@ -97,16 +105,10 @@ struct amdgpu_bo {
 	struct amdgpu_vm_bo_base	*vm_bo;
 	/* Constant after initialization */
 	struct amdgpu_bo		*parent;
-	struct amdgpu_bo		*shadow;
-
-
 
 #ifdef CONFIG_MMU_NOTIFIER
 	struct mmu_interval_notifier	notifier;
 #endif
-
-	struct list_head		shadow_list;
-
 	struct kgd_mem                  *kfd_bo;
 };
 
@@ -119,6 +121,13 @@ struct amdgpu_bo_user {
 
 };
 
+struct amdgpu_bo_vm {
+	struct amdgpu_bo		bo;
+	struct amdgpu_bo		*shadow;
+	struct list_head		shadow_list;
+	struct amdgpu_vm_bo_base        entries[];
+};
+
 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
 {
 	return container_of(tbo, struct amdgpu_bo, tbo);
@@ -191,7 +200,7 @@ static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
 
 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
 {
-	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
+	return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
 }
 
 /**
@@ -211,18 +220,19 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
 static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-	unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
-	struct drm_mm_node *node = bo->tbo.mem.mm_node;
-	unsigned long pages_left;
+	struct amdgpu_res_cursor cursor;
 
-	if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
+	if (bo->tbo.resource->mem_type != TTM_PL_VRAM)
 		return false;
 
-	for (pages_left = bo->tbo.mem.num_pages; pages_left;
-	     pages_left -= node->size, node++)
-		if (node->start < fpfn)
+	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
+	while (cursor.remaining) {
+		if (cursor.start < adev->gmc.visible_vram_size)
 			return true;
 
+		amdgpu_res_next(&cursor, cursor.size);
+	}
+
 	return false;
 }
 
@@ -245,6 +255,22 @@ static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
 	return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
 }
 
+/**
+ * amdgpu_bo_shadowed - check if the BO is shadowed
+ *
+ * @bo: BO to be tested.
+ *
+ * Returns:
+ * NULL if not shadowed or else return a BO pointer.
+ */
+static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo)
+{
+	if (bo->tbo.type == ttm_bo_type_kernel)
+		return to_amdgpu_bo_vm(bo)->shadow;
+
+	return NULL;
+}
+
 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
 
@@ -265,6 +291,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
 int amdgpu_bo_create_user(struct amdgpu_device *adev,
 			  struct amdgpu_bo_param *bp,
 			  struct amdgpu_bo_user **ubo_ptr);
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+			struct amdgpu_bo_param *bp,
+			struct amdgpu_bo_vm **ubo_ptr);
 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 			   void **cpu_addr);
 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
@@ -300,6 +329,9 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
 int amdgpu_bo_validate(struct amdgpu_bo *bo);
+void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
+				uint64_t *gtt_mem, uint64_t *cpu_mem);
+void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo);
 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
 			     struct dma_fence **fence);
 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
new file mode 100644
index 000000000000..d02c8637f909
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright 2016-2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Christian König, Felix Kuehling
+ */
+
+#include "amdgpu.h"
+
+static inline struct amdgpu_preempt_mgr *
+to_preempt_mgr(struct ttm_resource_manager *man)
+{
+	return container_of(man, struct amdgpu_preempt_mgr, manager);
+}
+
+/**
+ * DOC: mem_info_preempt_used
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total amount of
+ * used preemptible memory.
+ * The file mem_info_preempt_used is used for this, and returns the current
+ * used size of the preemptible block, in bytes
+ */
+static ssize_t mem_info_preempt_used_show(struct device *dev,
+					  struct device_attribute *attr,
+					  char *buf)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = drm_to_adev(ddev);
+	struct ttm_resource_manager *man;
+
+	man = ttm_manager_type(&adev->mman.bdev, AMDGPU_PL_PREEMPT);
+	return sysfs_emit(buf, "%llu\n", amdgpu_preempt_mgr_usage(man));
+}
+
+static DEVICE_ATTR_RO(mem_info_preempt_used);
+
+/**
+ * amdgpu_preempt_mgr_new - allocate a new node
+ *
+ * @man: TTM memory type manager
+ * @tbo: TTM BO we need this range for
+ * @place: placement flags and restrictions
+ * @mem: the resulting mem object
+ *
+ * Dummy, just count the space used without allocating resources or any limit.
+ */
+static int amdgpu_preempt_mgr_new(struct ttm_resource_manager *man,
+				  struct ttm_buffer_object *tbo,
+				  const struct ttm_place *place,
+				  struct ttm_resource **res)
+{
+	struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
+
+	*res = kzalloc(sizeof(**res), GFP_KERNEL);
+	if (!*res)
+		return -ENOMEM;
+
+	ttm_resource_init(tbo, place, *res);
+	(*res)->start = AMDGPU_BO_INVALID_OFFSET;
+
+	atomic64_add((*res)->num_pages, &mgr->used);
+	return 0;
+}
+
+/**
+ * amdgpu_preempt_mgr_del - free ranges
+ *
+ * @man: TTM memory type manager
+ * @mem: TTM memory object
+ *
+ * Free the allocated GTT again.
+ */
+static void amdgpu_preempt_mgr_del(struct ttm_resource_manager *man,
+				   struct ttm_resource *res)
+{
+	struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
+
+	atomic64_sub(res->num_pages, &mgr->used);
+	kfree(res);
+}
+
+/**
+ * amdgpu_preempt_mgr_usage - return usage of PREEMPT domain
+ *
+ * @man: TTM memory type manager
+ *
+ * Return how many bytes are used in the GTT domain
+ */
+uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man)
+{
+	struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
+	s64 result = atomic64_read(&mgr->used);
+
+	return (result > 0 ? result : 0) * PAGE_SIZE;
+}
+
+/**
+ * amdgpu_preempt_mgr_debug - dump VRAM table
+ *
+ * @man: TTM memory type manager
+ * @printer: DRM printer to use
+ *
+ * Dump the table content using printk.
+ */
+static void amdgpu_preempt_mgr_debug(struct ttm_resource_manager *man,
+				     struct drm_printer *printer)
+{
+	struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
+
+	drm_printf(printer, "man size:%llu pages, preempt used:%lld pages\n",
+		   man->size, (u64)atomic64_read(&mgr->used));
+}
+
+static const struct ttm_resource_manager_func amdgpu_preempt_mgr_func = {
+	.alloc = amdgpu_preempt_mgr_new,
+	.free = amdgpu_preempt_mgr_del,
+	.debug = amdgpu_preempt_mgr_debug
+};
+
+/**
+ * amdgpu_preempt_mgr_init - init PREEMPT manager and DRM MM
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Allocate and initialize the GTT manager.
+ */
+int amdgpu_preempt_mgr_init(struct amdgpu_device *adev)
+{
+	struct amdgpu_preempt_mgr *mgr = &adev->mman.preempt_mgr;
+	struct ttm_resource_manager *man = &mgr->manager;
+	int ret;
+
+	man->use_tt = true;
+	man->func = &amdgpu_preempt_mgr_func;
+
+	ttm_resource_manager_init(man, (1 << 30));
+
+	atomic64_set(&mgr->used, 0);
+
+	ret = device_create_file(adev->dev, &dev_attr_mem_info_preempt_used);
+	if (ret) {
+		DRM_ERROR("Failed to create device file mem_info_preempt_used\n");
+		return ret;
+	}
+
+	ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_PREEMPT,
+			       &mgr->manager);
+	ttm_resource_manager_set_used(man, true);
+	return 0;
+}
+
+/**
+ * amdgpu_preempt_mgr_fini - free and destroy GTT manager
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Destroy and free the GTT manager, returns -EBUSY if ranges are still
+ * allocated inside it.
+ */
+void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev)
+{
+	struct amdgpu_preempt_mgr *mgr = &adev->mman.preempt_mgr;
+	struct ttm_resource_manager *man = &mgr->manager;
+	int ret;
+
+	ttm_resource_manager_set_used(man, false);
+
+	ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
+	if (ret)
+		return;
+
+	device_remove_file(adev->dev, &dev_attr_mem_info_preempt_used);
+
+	ttm_resource_manager_cleanup(man);
+	ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_PREEMPT, NULL);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index a09483beb968..3ec5099ffeb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -25,6 +25,7 @@
 
 #include <linux/firmware.h>
 #include <linux/dma-mapping.h>
+#include <drm/drm_drv.h>
 
 #include "amdgpu.h"
 #include "amdgpu_psp.h"
@@ -38,6 +39,9 @@
 
 #include "amdgpu_ras.h"
 #include "amdgpu_securedisplay.h"
+#include "amdgpu_atomfirmware.h"
+
+#include <drm/drm_drv.h>
 
 static int psp_sysfs_init(struct amdgpu_device *adev);
 static void psp_sysfs_fini(struct amdgpu_device *adev);
@@ -104,6 +108,7 @@ static int psp_early_init(void *handle)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		psp_v11_0_set_psp_funcs(psp);
 		psp->autoload_supported = true;
 		break;
@@ -113,6 +118,10 @@ static int psp_early_init(void *handle)
 	case CHIP_ALDEBARAN:
 		psp_v13_0_set_psp_funcs(psp);
 		break;
+	case CHIP_YELLOW_CARP:
+		psp_v13_0_set_psp_funcs(psp);
+		psp->autoload_supported = true;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -162,11 +171,81 @@ Err_out:
 	return ret;
 }
 
+/*
+ * Helper funciton to query psp runtime database entry
+ *
+ * @adev: amdgpu_device pointer
+ * @entry_type: the type of psp runtime database entry
+ * @db_entry: runtime database entry pointer
+ *
+ * Return false if runtime database doesn't exit or entry is invalid
+ * or true if the specific database entry is found, and copy to @db_entry
+ */
+static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
+				     enum psp_runtime_entry_type entry_type,
+				     void *db_entry)
+{
+	uint64_t db_header_pos, db_dir_pos;
+	struct psp_runtime_data_header db_header = {0};
+	struct psp_runtime_data_directory db_dir = {0};
+	bool ret = false;
+	int i;
+
+	db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
+	db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
+
+	/* read runtime db header from vram */
+	amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
+			sizeof(struct psp_runtime_data_header), false);
+
+	if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
+		/* runtime db doesn't exist, exit */
+		dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
+		return false;
+	}
+
+	/* read runtime database entry from vram */
+	amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
+			sizeof(struct psp_runtime_data_directory), false);
+
+	if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
+		/* invalid db entry count, exit */
+		dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
+		return false;
+	}
+
+	/* look up for requested entry type */
+	for (i = 0; i < db_dir.entry_count && !ret; i++) {
+		if (db_dir.entry_list[i].entry_type == entry_type) {
+			switch (entry_type) {
+			case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
+				if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
+					/* invalid db entry size */
+					dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
+					return false;
+				}
+				/* read runtime database entry */
+				amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
+							  (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
+				ret = true;
+				break;
+			default:
+				ret = false;
+				break;
+			}
+		}
+	}
+
+	return ret;
+}
+
 static int psp_sw_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct psp_context *psp = &adev->psp;
 	int ret;
+	struct psp_runtime_boot_cfg_entry boot_cfg_entry;
+	struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 
 	if (!amdgpu_sriov_vf(adev)) {
 		ret = psp_init_microcode(psp);
@@ -174,17 +253,47 @@ static int psp_sw_init(void *handle)
 			DRM_ERROR("Failed to load psp firmware!\n");
 			return ret;
 		}
+	} else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
+		ret = psp_init_ta_microcode(psp, "aldebaran");
+		if (ret) {
+			DRM_ERROR("Failed to initialize ta microcode!\n");
+			return ret;
+		}
 	}
 
-	ret = psp_memory_training_init(psp);
-	if (ret) {
-		DRM_ERROR("Failed to initialize memory training!\n");
-		return ret;
+	memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
+	if (psp_get_runtime_db_entry(adev,
+				PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
+				&boot_cfg_entry)) {
+		psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
+		if ((psp->boot_cfg_bitmask) &
+		    BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
+			/* If psp runtime database exists, then
+			 * only enable two stage memory training
+			 * when TWO_STAGE_DRAM_TRAINING bit is set
+			 * in runtime database */
+			mem_training_ctx->enable_mem_training = true;
+		}
+
+	} else {
+		/* If psp runtime database doesn't exist or
+		 * is invalid, force enable two stage memory
+		 * training */
+		mem_training_ctx->enable_mem_training = true;
 	}
-	ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
-	if (ret) {
-		DRM_ERROR("Failed to process memory training!\n");
-		return ret;
+
+	if (mem_training_ctx->enable_mem_training) {
+		ret = psp_memory_training_init(psp);
+		if (ret) {
+			DRM_ERROR("Failed to initialize memory training!\n");
+			return ret;
+		}
+
+		ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
+		if (ret) {
+			DRM_ERROR("Failed to process memory training!\n");
+			return ret;
+		}
 	}
 
 	if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
@@ -229,7 +338,7 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 	int i;
 	struct amdgpu_device *adev = psp->adev;
 
-	if (psp->adev->in_pci_err_recovery)
+	if (psp->adev->no_hw_access)
 		return 0;
 
 	for (i = 0; i < adev->usec_timeout; i++) {
@@ -253,12 +362,15 @@ psp_cmd_submit_buf(struct psp_context *psp,
 		   struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 {
 	int ret;
-	int index;
+	int index, idx;
 	int timeout = 20000;
 	bool ras_intr = false;
 	bool skip_unsupport = false;
 
-	if (psp->adev->in_pci_err_recovery)
+	if (psp->adev->no_hw_access)
+		return 0;
+
+	if (!drm_dev_enter(&psp->adev->ddev, &idx))
 		return 0;
 
 	mutex_lock(&psp->mutex);
@@ -271,11 +383,10 @@ psp_cmd_submit_buf(struct psp_context *psp,
 	ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 	if (ret) {
 		atomic_dec(&psp->fence_value);
-		mutex_unlock(&psp->mutex);
-		return ret;
+		goto exit;
 	}
 
-	amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+	amdgpu_device_invalidate_hdp(psp->adev, NULL);
 	while (*((unsigned int *)psp->fence_buf) != index) {
 		if (--timeout == 0)
 			break;
@@ -288,7 +399,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
 		if (ras_intr)
 			break;
 		usleep_range(10, 100);
-		amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+		amdgpu_device_invalidate_hdp(psp->adev, NULL);
 	}
 
 	/* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
@@ -312,8 +423,8 @@ psp_cmd_submit_buf(struct psp_context *psp,
 			 psp->cmd_buf_mem->cmd_id,
 			 psp->cmd_buf_mem->resp.status);
 		if (!timeout) {
-			mutex_unlock(&psp->mutex);
-			return -EINVAL;
+			ret = -EINVAL;
+			goto exit;
 		}
 	}
 
@@ -321,8 +432,10 @@ psp_cmd_submit_buf(struct psp_context *psp,
 		ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 		ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 	}
-	mutex_unlock(&psp->mutex);
 
+exit:
+	mutex_unlock(&psp->mutex);
+	drm_dev_exit(idx);
 	return ret;
 }
 
@@ -366,8 +479,7 @@ static int psp_load_toc(struct psp_context *psp,
 	if (!cmd)
 		return -ENOMEM;
 	/* Copy toc to psp firmware private buffer */
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-	memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
+	psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size);
 
 	psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 
@@ -417,31 +529,12 @@ static int psp_tmr_init(struct psp_context *psp)
 	return ret;
 }
 
-static int psp_clear_vf_fw(struct psp_context *psp)
-{
-	int ret;
-	struct psp_gfx_cmd_resp *cmd;
-
-	if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12)
-		return 0;
-
-	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
-	if (!cmd)
-		return -ENOMEM;
-
-	cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW;
-
-	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
-	kfree(cmd);
-
-	return ret;
-}
-
 static bool psp_skip_tmr(struct psp_context *psp)
 {
 	switch (psp->adev->asic_type) {
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
+	case CHIP_ALDEBARAN:
 		return true;
 	default:
 		return false;
@@ -552,20 +645,43 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 	return ret;
 }
 
-static int psp_boot_config_set(struct amdgpu_device *adev)
+static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 {
 	struct psp_context *psp = &adev->psp;
 	struct psp_gfx_cmd_resp *cmd = psp->cmd;
+	int ret;
 
-	if (adev->asic_type != CHIP_SIENNA_CICHLID || amdgpu_sriov_vf(adev))
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
+	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+
+	cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
+	cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
+
+	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
+	if (!ret) {
+		*boot_cfg =
+			(cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
+	}
+
+	return ret;
+}
+
+static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
+{
+	struct psp_context *psp = &adev->psp;
+	struct psp_gfx_cmd_resp *cmd = psp->cmd;
+
+	if (amdgpu_sriov_vf(adev))
 		return 0;
 
 	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 
 	cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 	cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
-	cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC;
-	cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC;
+	cmd->cmd.boot_cfg.boot_config = boot_cfg;
+	cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 
 	return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 }
@@ -621,8 +737,7 @@ static int psp_asd_load(struct psp_context *psp)
 	if (!cmd)
 		return -ENOMEM;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-	memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
+	psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size);
 
 	psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 				  psp->asd_ucode_size);
@@ -696,6 +811,8 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 
 	psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
+	if (ret)
+		DRM_ERROR("PSP failed to program reg id %d", reg);
 
 	kfree(cmd);
 	return ret;
@@ -777,8 +894,7 @@ static int psp_xgmi_load(struct psp_context *psp)
 	if (!cmd)
 		return -ENOMEM;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-	memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
+	psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 
 	psp_prep_ta_load_cmd_buf(cmd,
 				 psp->fw_pri_mc_addr,
@@ -1034,8 +1150,14 @@ static int psp_ras_load(struct psp_context *psp)
 	if (!cmd)
 		return -ENOMEM;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-	memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
+	psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
+
+	ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
+
+	if (psp->adev->gmc.xgmi.connected_to_cpu)
+		ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
+	else
+		ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
 
 	psp_prep_ta_load_cmd_buf(cmd,
 				 psp->fw_pri_mc_addr,
@@ -1046,8 +1168,6 @@ static int psp_ras_load(struct psp_context *psp)
 	ret = psp_cmd_submit_buf(psp, NULL, cmd,
 			psp->fence_buf_mc_addr);
 
-	ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
-
 	if (!ret) {
 		psp->ras.session_id = cmd->resp.session_id;
 
@@ -1128,6 +1248,31 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 	return ret;
 }
 
+static int psp_ras_status_to_errno(struct amdgpu_device *adev,
+					 enum ta_ras_status ras_status)
+{
+	int ret = -EINVAL;
+
+	switch (ras_status) {
+	case TA_RAS_STATUS__SUCCESS:
+		ret = 0;
+		break;
+	case TA_RAS_STATUS__RESET_NEEDED:
+		ret = -EAGAIN;
+		break;
+	case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
+		dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");
+		break;
+	case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:
+		dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");
+		break;
+	default:
+		dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);
+	}
+
+	return ret;
+}
+
 int psp_ras_enable_features(struct psp_context *psp,
 		union ta_ras_cmd_input *info, bool enable)
 {
@@ -1151,7 +1296,7 @@ int psp_ras_enable_features(struct psp_context *psp,
 	if (ret)
 		return -EINVAL;
 
-	return ras_cmd->ras_status;
+	return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
 }
 
 static int psp_ras_terminate(struct psp_context *psp)
@@ -1184,19 +1329,62 @@ static int psp_ras_terminate(struct psp_context *psp)
 static int psp_ras_initialize(struct psp_context *psp)
 {
 	int ret;
+	uint32_t boot_cfg = 0xFF;
+	struct amdgpu_device *adev = psp->adev;
 
 	/*
 	 * TODO: bypass the initialize in sriov for now
 	 */
-	if (amdgpu_sriov_vf(psp->adev))
+	if (amdgpu_sriov_vf(adev))
 		return 0;
 
-	if (!psp->adev->psp.ta_ras_ucode_size ||
-	    !psp->adev->psp.ta_ras_start_addr) {
-		dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
+	if (!adev->psp.ta_ras_ucode_size ||
+	    !adev->psp.ta_ras_start_addr) {
+		dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
 		return 0;
 	}
 
+	if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
+		/* query GECC enablement status from boot config
+		 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
+		 */
+		ret = psp_boot_config_get(adev, &boot_cfg);
+		if (ret)
+			dev_warn(adev->dev, "PSP get boot config failed\n");
+
+		if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
+			if (!boot_cfg) {
+				dev_info(adev->dev, "GECC is disabled\n");
+			} else {
+				/* disable GECC in next boot cycle if ras is
+				 * disabled by module parameter amdgpu_ras_enable
+				 * and/or amdgpu_ras_mask, or boot_config_get call
+				 * is failed
+				 */
+				ret = psp_boot_config_set(adev, 0);
+				if (ret)
+					dev_warn(adev->dev, "PSP set boot config failed\n");
+				else
+					dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
+						 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
+			}
+		} else {
+			if (1 == boot_cfg) {
+				dev_info(adev->dev, "GECC is enabled\n");
+			} else {
+				/* enable GECC in next boot cycle if it is disabled
+				 * in boot config, or force enable GECC if failed to
+				 * get boot configuration
+				 */
+				ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
+				if (ret)
+					dev_warn(adev->dev, "PSP set boot config failed\n");
+				else
+					dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
+			}
+		}
+	}
+
 	if (!psp->ras.ras_initialized) {
 		ret = psp_ras_init_shared_buf(psp);
 		if (ret)
@@ -1234,7 +1422,7 @@ int psp_ras_trigger_error(struct psp_context *psp,
 	if (amdgpu_ras_intr_triggered())
 		return 0;
 
-	return ras_cmd->ras_status;
+	return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
 }
 // ras end
 
@@ -1271,9 +1459,8 @@ static int psp_hdcp_load(struct psp_context *psp)
 	if (!cmd)
 		return -ENOMEM;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-	memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
-	       psp->ta_hdcp_ucode_size);
+	psp_copy_fw(psp, psp->ta_hdcp_start_addr,
+		    psp->ta_hdcp_ucode_size);
 
 	psp_prep_ta_load_cmd_buf(cmd,
 				 psp->fw_pri_mc_addr,
@@ -1423,8 +1610,7 @@ static int psp_dtm_load(struct psp_context *psp)
 	if (!cmd)
 		return -ENOMEM;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-	memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
+	psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
 
 	psp_prep_ta_load_cmd_buf(cmd,
 				 psp->fw_pri_mc_addr,
@@ -1569,8 +1755,7 @@ static int psp_rap_load(struct psp_context *psp)
 	if (!cmd)
 		return -ENOMEM;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-	memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
+	psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
 
 	psp_prep_ta_load_cmd_buf(cmd,
 				 psp->fw_pri_mc_addr,
@@ -1920,17 +2105,6 @@ static int psp_hw_start(struct psp_context *psp)
 		return ret;
 	}
 
-	ret = psp_clear_vf_fw(psp);
-	if (ret) {
-		DRM_ERROR("PSP clear vf fw!\n");
-		return ret;
-	}
-
-	ret = psp_boot_config_set(adev);
-	if (ret) {
-		DRM_WARN("PSP set boot config@\n");
-	}
-
 	ret = psp_tmr_init(psp);
 	if (ret) {
 		DRM_ERROR("PSP tmr init failed!\n");
@@ -2166,12 +2340,9 @@ static int psp_load_smu_fw(struct psp_context *psp)
 		return 0;
 
 	if ((amdgpu_in_reset(adev) &&
-	     ras && ras->supported &&
+	     ras && adev->ras_enabled &&
 	     (adev->asic_type == CHIP_ARCTURUS ||
-	      adev->asic_type == CHIP_VEGA20)) ||
-	     (adev->in_runpm &&
-	      adev->asic_type >= CHIP_NAVI10 &&
-	      adev->asic_type <= CHIP_NAVI12)) {
+	      adev->asic_type == CHIP_VEGA20))) {
 		ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
 		if (ret) {
 			DRM_WARN("Failed to set MP1 state prepare for reload\n");
@@ -2311,11 +2482,20 @@ static int psp_load_fw(struct amdgpu_device *adev)
 	if (!psp->cmd)
 		return -ENOMEM;
 
-	ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
-					AMDGPU_GEM_DOMAIN_GTT,
-					&psp->fw_pri_bo,
-					&psp->fw_pri_mc_addr,
-					&psp->fw_pri_buf);
+	if (amdgpu_sriov_vf(adev)) {
+		ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
+						AMDGPU_GEM_DOMAIN_VRAM,
+						&psp->fw_pri_bo,
+						&psp->fw_pri_mc_addr,
+						&psp->fw_pri_buf);
+	} else {
+		ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
+						AMDGPU_GEM_DOMAIN_GTT,
+						&psp->fw_pri_bo,
+						&psp->fw_pri_mc_addr,
+						&psp->fw_pri_buf);
+	}
+
 	if (ret)
 		goto failed;
 
@@ -2434,7 +2614,6 @@ static int psp_hw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct psp_context *psp = &adev->psp;
-	int ret;
 
 	if (psp->adev->psp.ta_fw) {
 		psp_ras_terminate(psp);
@@ -2445,11 +2624,6 @@ static int psp_hw_fini(void *handle)
 	}
 
 	psp_asd_unload(psp);
-	ret = psp_clear_vf_fw(psp);
-	if (ret) {
-		DRM_ERROR("PSP clear vf fw!\n");
-		return ret;
-	}
 
 	psp_tmr_terminate(psp);
 	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
@@ -2539,10 +2713,12 @@ static int psp_resume(void *handle)
 
 	DRM_INFO("PSP is resuming...\n");
 
-	ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
-	if (ret) {
-		DRM_ERROR("Failed to process memory training!\n");
-		return ret;
+	if (psp->mem_train_ctx.enable_mem_training) {
+		ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
+		if (ret) {
+			DRM_ERROR("Failed to process memory training!\n");
+			return ret;
+		}
 	}
 
 	mutex_lock(&adev->firmware.mutex);
@@ -2694,7 +2870,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
 	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 	write_frame->fence_value = index;
-	amdgpu_asic_flush_hdp(adev, NULL);
+	amdgpu_device_flush_hdp(adev, NULL);
 
 	/* Update the write Pointer in DWORDs */
 	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
@@ -2726,7 +2902,7 @@ int psp_init_asd_microcode(struct psp_context *psp,
 
 	asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 	adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
-	adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
+	adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
 	adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 	adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 				le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
@@ -2762,7 +2938,7 @@ int psp_init_toc_microcode(struct psp_context *psp,
 
 	toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
 	adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
-	adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
+	adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
 	adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
 	adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
 				le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
@@ -2774,6 +2950,50 @@ out:
 	return err;
 }
 
+static int psp_init_sos_base_fw(struct amdgpu_device *adev)
+{
+	const struct psp_firmware_header_v1_0 *sos_hdr;
+	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
+	uint8_t *ucode_array_start_addr;
+
+	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
+	ucode_array_start_addr = (uint8_t *)sos_hdr +
+		le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
+
+	if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) {
+		adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
+		adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
+
+		adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos.offset_bytes);
+		adev->psp.sys_start_addr = ucode_array_start_addr;
+
+		adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos.size_bytes);
+		adev->psp.sos_start_addr = ucode_array_start_addr +
+				le32_to_cpu(sos_hdr->sos.offset_bytes);
+	} else {
+		/* Load alternate PSP SOS FW */
+		sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
+
+		adev->psp.sos_fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
+		adev->psp.sos_feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
+
+		adev->psp.sys_bin_size = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
+		adev->psp.sys_start_addr = ucode_array_start_addr +
+			le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
+
+		adev->psp.sos_bin_size = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
+		adev->psp.sos_start_addr = ucode_array_start_addr +
+			le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
+	}
+
+	if ((adev->psp.sys_bin_size == 0) || (adev->psp.sos_bin_size == 0)) {
+		dev_warn(adev->dev, "PSP SOS FW not available");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 int psp_init_sos_microcode(struct psp_context *psp,
 			   const char *chip_name)
 {
@@ -2784,6 +3004,7 @@ int psp_init_sos_microcode(struct psp_context *psp,
 	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
 	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
 	int err = 0;
+	uint8_t *ucode_array_start_addr;
 
 	if (!chip_name) {
 		dev_err(adev->dev, "invalid chip name for sos microcode\n");
@@ -2800,47 +3021,45 @@ int psp_init_sos_microcode(struct psp_context *psp,
 		goto out;
 
 	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
+	ucode_array_start_addr = (uint8_t *)sos_hdr +
+		le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
 	amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
 
 	switch (sos_hdr->header.header_version_major) {
 	case 1:
-		adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
-		adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
-		adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
-		adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
-		adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
-				le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
-		adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-				le32_to_cpu(sos_hdr->sos_offset_bytes);
+		err = psp_init_sos_base_fw(adev);
+		if (err)
+			goto out;
+
 		if (sos_hdr->header.header_version_minor == 1) {
 			sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
-			adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
+			adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
 			adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-					le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
-			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
+					le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
+			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
 			adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-					le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
+					le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
 		}
 		if (sos_hdr->header.header_version_minor == 2) {
 			sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
-			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
+			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
 			adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-						    le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
+						    le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
 		}
 		if (sos_hdr->header.header_version_minor == 3) {
 			sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
-			adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
-			adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-				le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
-			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
-			adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-				le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
-			adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
-			adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-				le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
-			adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes);
-			adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
-				le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes);
+			adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
+			adev->psp.toc_start_addr = ucode_array_start_addr +
+				le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
+			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
+			adev->psp.kdb_start_addr = ucode_array_start_addr +
+				le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
+			adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
+			adev->psp.spl_start_addr = ucode_array_start_addr +
+				le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
+			adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
+			adev->psp.rl_start_addr = ucode_array_start_addr +
+				le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
 		}
 		break;
 	default:
@@ -3018,7 +3237,7 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
 	struct amdgpu_device *adev = drm_to_adev(ddev);
 	void *cpu_addr;
 	dma_addr_t dma_addr;
-	int ret;
+	int ret, idx;
 	char fw_name[100];
 	const struct firmware *usbc_pd_fw;
 
@@ -3027,6 +3246,9 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
 		return -EBUSY;
 	}
 
+	if (!drm_dev_enter(ddev, &idx))
+		return -ENODEV;
+
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
 	ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
 	if (ret)
@@ -3058,16 +3280,29 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
 rel_buf:
 	dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
 	release_firmware(usbc_pd_fw);
-
 fail:
 	if (ret) {
 		DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
-		return ret;
+		count = ret;
 	}
 
+	drm_dev_exit(idx);
 	return count;
 }
 
+void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
+{
+	int idx;
+
+	if (!drm_dev_enter(&psp->adev->ddev, &idx))
+		return;
+
+	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+	memcpy(psp->fw_pri_buf, start_addr, bin_size);
+
+	drm_dev_exit(idx);
+}
+
 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
 		   psp_usbc_pd_fw_sysfs_read,
 		   psp_usbc_pd_fw_sysfs_write);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 60aa99a39a74..3030ec24eb3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -225,6 +225,61 @@ struct psp_memory_training_context {
 
 	enum psp_memory_training_init_flag init;
 	u32 training_cnt;
+	bool enable_mem_training;
+};
+
+/** PSP runtime DB **/
+#define PSP_RUNTIME_DB_SIZE_IN_BYTES		0x10000
+#define PSP_RUNTIME_DB_OFFSET			0x100000
+#define PSP_RUNTIME_DB_COOKIE_ID		0x0ed5
+#define PSP_RUNTIME_DB_VER_1			0x0100
+#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT	0x40
+
+enum psp_runtime_entry_type {
+	PSP_RUNTIME_ENTRY_TYPE_INVALID		= 0x0,
+	PSP_RUNTIME_ENTRY_TYPE_TEST		= 0x1,
+	PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON	= 0x2,  /* Common mGPU runtime data */
+	PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL	= 0x3,  /* WAFL runtime data */
+	PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI	= 0x4,  /* XGMI runtime data */
+	PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG	= 0x5,  /* Boot Config runtime data */
+};
+
+/* PSP runtime DB header */
+struct psp_runtime_data_header {
+	/* determine the existence of runtime db */
+	uint16_t cookie;
+	/* version of runtime db */
+	uint16_t version;
+};
+
+/* PSP runtime DB entry */
+struct psp_runtime_entry {
+	/* type of runtime db entry */
+	uint32_t entry_type;
+	/* offset of entry in bytes */
+	uint16_t offset;
+	/* size of entry in bytes */
+	uint16_t size;
+};
+
+/* PSP runtime DB directory */
+struct psp_runtime_data_directory {
+	/* number of valid entries */
+	uint16_t			entry_count;
+	/* db entries*/
+	struct psp_runtime_entry	entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
+};
+
+/* PSP runtime DB boot config feature bitmask */
+enum psp_runtime_boot_cfg_feature {
+	BOOT_CFG_FEATURE_GECC                       = 0x1,
+	BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING    = 0x2,
+};
+
+/* PSP runtime DB boot config entry */
+struct psp_runtime_boot_cfg_entry {
+	uint32_t boot_cfg_bitmask;
+	uint32_t reserved;
 };
 
 struct psp_context
@@ -325,6 +380,8 @@ struct psp_context
 	struct psp_securedisplay_context	securedisplay_context;
 	struct mutex			mutex;
 	struct psp_memory_training_context mem_train_ctx;
+
+	uint32_t			boot_cfg_bitmask;
 };
 
 struct amdgpu_psp_funcs {
@@ -424,4 +481,6 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 
 int psp_load_fw_list(struct psp_context *psp,
 		     struct amdgpu_firmware_info **ucode_list, int ucode_count);
+void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b0d2fc9454ca..c13b02caf8c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -27,12 +27,14 @@
 #include <linux/uaccess.h>
 #include <linux/reboot.h>
 #include <linux/syscalls.h>
+#include <linux/pm_runtime.h>
 
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_atomfirmware.h"
 #include "amdgpu_xgmi.h"
 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
+#include "atom.h"
 
 static const char *RAS_FS_NAME = "ras";
 
@@ -320,11 +322,14 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
  * "disable" requires only the block.
  * "enable" requires the block and error type.
  * "inject" requires the block, error type, address, and value.
+ *
  * The block is one of: umc, sdma, gfx, etc.
  *	see ras_block_string[] for details
+ *
  * The error type is one of: ue, ce, where,
  *	ue is multi-uncorrectable
  *	ce is single-correctable
+ *
  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
  * The address and value are hexadecimal numbers, leading 0x is optional.
  *
@@ -531,7 +536,7 @@ static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct ras_manager *obj;
 
-	if (!adev->ras_features || !con)
+	if (!adev->ras_enabled || !con)
 		return NULL;
 
 	if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
@@ -558,7 +563,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 	struct ras_manager *obj;
 	int i;
 
-	if (!adev->ras_features || !con)
+	if (!adev->ras_enabled || !con)
 		return NULL;
 
 	if (head) {
@@ -585,36 +590,11 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 }
 /* obj end */
 
-static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
-					 const char* invoke_type,
-					 const char* block_name,
-					 enum ta_ras_status ret)
-{
-	switch (ret) {
-	case TA_RAS_STATUS__SUCCESS:
-		return;
-	case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
-		dev_warn(adev->dev,
-			"RAS WARN: %s %s currently unavailable\n",
-			invoke_type,
-			block_name);
-		break;
-	default:
-		dev_err(adev->dev,
-			"RAS ERROR: %s %s error failed ret 0x%X\n",
-			invoke_type,
-			block_name,
-			ret);
-	}
-}
-
 /* feature ctl begin */
 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
-		struct ras_common_if *head)
+					 struct ras_common_if *head)
 {
-	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-
-	return con->hw_supported & BIT(head->block);
+	return adev->ras_hw_enabled & BIT(head->block);
 }
 
 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
@@ -658,11 +638,7 @@ static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 		con->features |= BIT(head->block);
 	} else {
 		if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
-			/* skip clean gfx ras context feature for VEGA20 Gaming.
-			 * will clean later
-			 */
-			if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)))
-				con->features &= ~BIT(head->block);
+			con->features &= ~BIT(head->block);
 			put_obj(obj);
 		}
 	}
@@ -708,15 +684,10 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 	if (!amdgpu_ras_intr_triggered()) {
 		ret = psp_ras_enable_features(&adev->psp, info, enable);
 		if (ret) {
-			amdgpu_ras_parse_status_code(adev,
-						     enable ? "enable":"disable",
-						     ras_block_str(head->block),
-						    (enum ta_ras_status)ret);
-			if (ret == TA_RAS_STATUS__RESET_NEEDED)
-				ret = -EAGAIN;
-			else
-				ret = -EINVAL;
-
+			dev_err(adev->dev, "ras %s %s failed %d\n",
+				enable ? "enable":"disable",
+				ras_block_str(head->block),
+				ret);
 			goto out;
 		}
 	}
@@ -770,6 +741,10 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 				con->features |= BIT(head->block);
 
 			ret = amdgpu_ras_feature_enable(adev, head, 0);
+
+			/* clean gfx block ras features flag */
+			if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
+				con->features &= ~BIT(head->block);
 		}
 	} else
 		ret = amdgpu_ras_feature_enable(adev, head, enable);
@@ -890,6 +865,11 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 		    adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 			adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 		break;
+	case AMDGPU_RAS_BLOCK__HDP:
+		if (adev->hdp.ras_funcs &&
+		    adev->hdp.ras_funcs->query_ras_error_count)
+			adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
+		break;
 	default:
 		break;
 	}
@@ -901,17 +881,42 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 	info->ce_count = obj->err_data.ce_count;
 
 	if (err_data.ce_count) {
-		dev_info(adev->dev, "%ld correctable hardware errors "
+		if (adev->smuio.funcs &&
+		    adev->smuio.funcs->get_socket_id &&
+		    adev->smuio.funcs->get_die_id) {
+			dev_info(adev->dev, "socket: %d, die: %d "
+					"%ld correctable hardware errors "
 					"detected in %s block, no user "
 					"action is needed.\n",
+					adev->smuio.funcs->get_socket_id(adev),
+					adev->smuio.funcs->get_die_id(adev),
 					obj->err_data.ce_count,
 					ras_block_str(info->head.block));
+		} else {
+			dev_info(adev->dev, "%ld correctable hardware errors "
+					"detected in %s block, no user "
+					"action is needed.\n",
+					obj->err_data.ce_count,
+					ras_block_str(info->head.block));
+		}
 	}
 	if (err_data.ue_count) {
-		dev_info(adev->dev, "%ld uncorrectable hardware errors "
+		if (adev->smuio.funcs &&
+		    adev->smuio.funcs->get_socket_id &&
+		    adev->smuio.funcs->get_die_id) {
+			dev_info(adev->dev, "socket: %d, die: %d "
+					"%ld uncorrectable hardware errors "
 					"detected in %s block\n",
+					adev->smuio.funcs->get_socket_id(adev),
+					adev->smuio.funcs->get_die_id(adev),
 					obj->err_data.ue_count,
 					ras_block_str(info->head.block));
+		} else {
+			dev_info(adev->dev, "%ld uncorrectable hardware errors "
+					"detected in %s block\n",
+					obj->err_data.ue_count,
+					ras_block_str(info->head.block));
+		}
 	}
 
 	return 0;
@@ -937,11 +942,20 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 		if (adev->mmhub.ras_funcs &&
 		    adev->mmhub.ras_funcs->reset_ras_error_count)
 			adev->mmhub.ras_funcs->reset_ras_error_count(adev);
+
+		if (adev->mmhub.ras_funcs &&
+		    adev->mmhub.ras_funcs->reset_ras_error_status)
+			adev->mmhub.ras_funcs->reset_ras_error_status(adev);
 		break;
 	case AMDGPU_RAS_BLOCK__SDMA:
 		if (adev->sdma.funcs->reset_ras_error_count)
 			adev->sdma.funcs->reset_ras_error_count(adev);
 		break;
+	case AMDGPU_RAS_BLOCK__HDP:
+		if (adev->hdp.ras_funcs &&
+		    adev->hdp.ras_funcs->reset_ras_error_count)
+			adev->hdp.ras_funcs->reset_ras_error_count(adev);
+		break;
 	default:
 		break;
 	}
@@ -1022,38 +1036,44 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 		ret = -EINVAL;
 	}
 
-	amdgpu_ras_parse_status_code(adev,
-				     "inject",
-				     ras_block_str(info->head.block),
-				     (enum ta_ras_status)ret);
+	if (ret)
+		dev_err(adev->dev, "ras inject %s failed %d\n",
+			ras_block_str(info->head.block), ret);
 
 	return ret;
 }
 
 /* get the total error counts on all IPs */
-unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
-		bool is_ce)
+void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+				  unsigned long *ce_count,
+				  unsigned long *ue_count)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct ras_manager *obj;
-	struct ras_err_data data = {0, 0};
+	unsigned long ce, ue;
 
-	if (!adev->ras_features || !con)
-		return 0;
+	if (!adev->ras_enabled || !con)
+		return;
 
+	ce = 0;
+	ue = 0;
 	list_for_each_entry(obj, &con->head, node) {
 		struct ras_query_if info = {
 			.head = obj->head,
 		};
 
 		if (amdgpu_ras_query_error_status(adev, &info))
-			return 0;
+			return;
 
-		data.ce_count += info.ce_count;
-		data.ue_count += info.ue_count;
+		ce += info.ce_count;
+		ue += info.ue_count;
 	}
 
-	return is_ce ? data.ce_count : data.ue_count;
+	if (ce_count)
+		*ce_count = ce;
+
+	if (ue_count)
+		*ue_count = ue;
 }
 /* query/inject/cure end */
 
@@ -1265,8 +1285,8 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-	struct dentry *dir;
-	struct drm_minor *minor = adev_to_drm(adev)->primary;
+	struct drm_minor  *minor = adev_to_drm(adev)->primary;
+	struct dentry     *dir;
 
 	dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
 	debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
@@ -1275,6 +1295,8 @@ static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *
 			    &amdgpu_ras_debugfs_eeprom_ops);
 	debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
 			   &con->bad_page_cnt_threshold);
+	debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
+	debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
 
 	/*
 	 * After one uncorrectable error happens, usually GPU recovery will
@@ -1561,7 +1583,7 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct ras_manager *obj;
 
-	if (!adev->ras_features || !con)
+	if (!adev->ras_enabled || !con)
 		return;
 
 	list_for_each_entry(obj, &con->head, node) {
@@ -1611,7 +1633,7 @@ static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct ras_manager *obj;
 
-	if (!adev->ras_features || !con)
+	if (!adev->ras_enabled || !con)
 		return;
 
 	list_for_each_entry(obj, &con->head, node) {
@@ -1925,7 +1947,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
 	bool exc_err_limit = false;
 	int ret;
 
-	if (adev->ras_features && con)
+	if (adev->ras_enabled && con)
 		data = &con->eh_data;
 	else
 		return 0;
@@ -1962,6 +1984,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
 		ret = amdgpu_ras_load_bad_pages(adev);
 		if (ret)
 			goto free;
+
+		if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
+			adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
 	}
 
 	return 0;
@@ -2029,6 +2054,25 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
 }
 
 /*
+ * this is workaround for vega20 workstation sku,
+ * force enable gfx ras, ignore vbios gfx ras flag
+ * due to GC EDC can not write
+ */
+static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
+{
+	struct atom_context *ctx = adev->mode_info.atom_context;
+
+	if (!ctx)
+		return;
+
+	if (strnstr(ctx->vbios_version, "D16406",
+		    sizeof(ctx->vbios_version)) ||
+		strnstr(ctx->vbios_version, "D36002",
+			sizeof(ctx->vbios_version)))
+		adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
+}
+
+/*
  * check hardware's ras ability which will be saved in hw_supported.
  * if hardware does not support ras, we can skip some ras initializtion and
  * forbid some ras operations from IP.
@@ -2037,11 +2081,9 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
  * we have to initialize ras as normal. but need check if operation is
  * allowed or not in each function.
  */
-static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
-		uint32_t *hw_supported, uint32_t *supported)
+static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
 {
-	*hw_supported = 0;
-	*supported = 0;
+	adev->ras_hw_enabled = adev->ras_enabled = 0;
 
 	if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
 	    !amdgpu_ras_asic_supported(adev))
@@ -2050,33 +2092,58 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
 	if (!adev->gmc.xgmi.connected_to_cpu) {
 		if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
 			dev_info(adev->dev, "MEM ECC is active.\n");
-			*hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
-					1 << AMDGPU_RAS_BLOCK__DF);
+			adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
+						   1 << AMDGPU_RAS_BLOCK__DF);
 		} else {
 			dev_info(adev->dev, "MEM ECC is not presented.\n");
 		}
 
 		if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
 			dev_info(adev->dev, "SRAM ECC is active.\n");
-			*hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
-					1 << AMDGPU_RAS_BLOCK__DF);
+			adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
+						    1 << AMDGPU_RAS_BLOCK__DF);
 		} else {
 			dev_info(adev->dev, "SRAM ECC is not presented.\n");
 		}
 	} else {
 		/* driver only manages a few IP blocks RAS feature
 		 * when GPU is connected cpu through XGMI */
-		*hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX |
-				1 << AMDGPU_RAS_BLOCK__SDMA |
-				1 << AMDGPU_RAS_BLOCK__MMHUB);
+		adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
+					   1 << AMDGPU_RAS_BLOCK__SDMA |
+					   1 << AMDGPU_RAS_BLOCK__MMHUB);
 	}
 
+	amdgpu_ras_get_quirks(adev);
+
 	/* hw_supported needs to be aligned with RAS block mask. */
-	*hw_supported &= AMDGPU_RAS_BLOCK_MASK;
+	adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
+
+	adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
+		adev->ras_hw_enabled & amdgpu_ras_mask;
+}
+
+static void amdgpu_ras_counte_dw(struct work_struct *work)
+{
+	struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
+					      ras_counte_delay_work.work);
+	struct amdgpu_device *adev = con->adev;
+	struct drm_device *dev = adev_to_drm(adev);
+	unsigned long ce_count, ue_count;
+	int res;
+
+	res = pm_runtime_get_sync(dev->dev);
+	if (res < 0)
+		goto Out;
 
-	*supported = amdgpu_ras_enable == 0 ?
-			0 : *hw_supported & amdgpu_ras_mask;
-	adev->ras_features = *supported;
+	/* Cache new values.
+	 */
+	amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
+	atomic_set(&con->ras_ce_count, ce_count);
+	atomic_set(&con->ras_ue_count, ue_count);
+
+	pm_runtime_mark_last_busy(dev->dev);
+Out:
+	pm_runtime_put_autosuspend(dev->dev);
 }
 
 int amdgpu_ras_init(struct amdgpu_device *adev)
@@ -2093,17 +2160,22 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
 	if (!con)
 		return -ENOMEM;
 
+	con->adev = adev;
+	INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
+	atomic_set(&con->ras_ce_count, 0);
+	atomic_set(&con->ras_ue_count, 0);
+
 	con->objs = (struct ras_manager *)(con + 1);
 
 	amdgpu_ras_set_context(adev, con);
 
-	amdgpu_ras_check_supported(adev, &con->hw_supported,
-			&con->supported);
-	if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
+	amdgpu_ras_check_supported(adev);
+
+	if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
 		/* set gfx block ras context feature for VEGA20 Gaming
 		 * send ras disable cmd to ras ta during ras late init.
 		 */
-		if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
+		if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
 			con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
 
 			return 0;
@@ -2153,8 +2225,9 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
 	}
 
 	dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
-			"hardware ability[%x] ras_mask[%x]\n",
-			con->hw_supported, con->supported);
+		 "hardware ability[%x] ras_mask[%x]\n",
+		 adev->ras_hw_enabled, adev->ras_enabled);
+
 	return 0;
 release_con:
 	amdgpu_ras_set_context(adev, NULL);
@@ -2163,7 +2236,7 @@ release_con:
 	return r;
 }
 
-static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
+int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
 {
 	if (adev->gmc.xgmi.connected_to_cpu)
 		return 1;
@@ -2195,6 +2268,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
 			 struct ras_fs_if *fs_info,
 			 struct ras_ih_if *ih_info)
 {
+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+	unsigned long ue_count, ce_count;
 	int r;
 
 	/* disable RAS feature per IP block if it is not supported */
@@ -2235,6 +2310,12 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
 	if (r)
 		goto sysfs;
 
+	/* Those are the cached values at init.
+	 */
+	amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
+	atomic_set(&con->ras_ce_count, ce_count);
+	atomic_set(&con->ras_ue_count, ue_count);
+
 	return 0;
 cleanup:
 	amdgpu_ras_sysfs_remove(adev, ras_block);
@@ -2268,7 +2349,7 @@ void amdgpu_ras_resume(struct amdgpu_device *adev)
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct ras_manager *obj, *tmp;
 
-	if (!adev->ras_features || !con) {
+	if (!adev->ras_enabled || !con) {
 		/* clean ras context for VEGA20 Gaming after send ras disable cmd */
 		amdgpu_release_ras_context(adev);
 
@@ -2314,7 +2395,7 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 
-	if (!adev->ras_features || !con)
+	if (!adev->ras_enabled || !con)
 		return;
 
 	amdgpu_ras_disable_all_features(adev, 0);
@@ -2328,9 +2409,10 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 
-	if (!adev->ras_features || !con)
+	if (!adev->ras_enabled || !con)
 		return 0;
 
+
 	/* Need disable ras on all IPs here before ip [hw/sw]fini */
 	amdgpu_ras_disable_all_features(adev, 0);
 	amdgpu_ras_recovery_fini(adev);
@@ -2341,7 +2423,7 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 
-	if (!adev->ras_features || !con)
+	if (!adev->ras_enabled || !con)
 		return 0;
 
 	amdgpu_ras_fs_fini(adev);
@@ -2352,6 +2434,8 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
 	if (con->features)
 		amdgpu_ras_disable_all_features(adev, 1);
 
+	cancel_delayed_work_sync(&con->ras_counte_delay_work);
+
 	amdgpu_ras_set_context(adev, NULL);
 	kfree(con);
 
@@ -2360,10 +2444,8 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
 
 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
 {
-	uint32_t hw_supported, supported;
-
-	amdgpu_ras_check_supported(adev, &hw_supported, &supported);
-	if (!hw_supported)
+	amdgpu_ras_check_supported(adev);
+	if (!adev->ras_hw_enabled)
 		return;
 
 	if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
@@ -2392,7 +2474,7 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev)
 	if (!con)
 		return;
 
-	if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
+	if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
 		con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
 		amdgpu_ras_set_context(adev, NULL);
 		kfree(con);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 60df268a0c66..256cea5d34f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -313,9 +313,6 @@ struct ras_common_if {
 struct amdgpu_ras {
 	/* ras infrastructure */
 	/* for ras itself. */
-	uint32_t hw_supported;
-	/* for IP to check its ras ability. */
-	uint32_t supported;
 	uint32_t features;
 	struct list_head head;
 	/* sysfs */
@@ -343,6 +340,11 @@ struct amdgpu_ras {
 
 	/* disable ras error count harvest in recovery */
 	bool disable_ras_err_cnt_harvest;
+
+	/* RAS count errors delayed work */
+	struct delayed_work ras_counte_delay_work;
+	atomic_t ras_ue_count;
+	atomic_t ras_ce_count;
 };
 
 struct ras_fs_data {
@@ -478,7 +480,7 @@ static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
 
 	if (block >= AMDGPU_RAS_BLOCK_COUNT)
 		return 0;
-	return ras && (ras->supported & (1 << block));
+	return ras && (adev->ras_enabled & (1 << block));
 }
 
 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
@@ -488,8 +490,9 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
 void amdgpu_ras_resume(struct amdgpu_device *adev);
 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 
-unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
-		bool is_ce);
+void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+				  unsigned long *ce_count,
+				  unsigned long *ue_count);
 
 /* error handling functions */
 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
@@ -628,4 +631,7 @@ void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 
 void amdgpu_release_ras_context(struct amdgpu_device *adev);
+
+int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 40f2adf305bc..59e0fefb15aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -28,6 +28,7 @@
 
 #include <drm/drm_mm.h>
 #include <drm/ttm/ttm_resource.h>
+#include <drm/ttm/ttm_range_manager.h>
 
 /* state back for walking over vram_mgr and gtt_mgr allocations */
 struct amdgpu_res_cursor {
@@ -53,7 +54,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
 {
 	struct drm_mm_node *node;
 
-	if (!res || !res->mm_node) {
+	if (!res) {
 		cur->start = start;
 		cur->size = size;
 		cur->remaining = size;
@@ -63,7 +64,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
 
 	BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
 
-	node = res->mm_node;
+	node = to_ttm_range_mgr_node(res)->mm_nodes;
 	while (start >= node->size << PAGE_SHIFT)
 		start -= node++->size << PAGE_SHIFT;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 688624ebe421..7b634a1517f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -158,6 +158,7 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring)
  * @irq_src: interrupt source to use for this ring
  * @irq_type: interrupt type to use for this ring
  * @hw_prio: ring priority (NORMAL/HIGH)
+ * @sched_score: optional score atomic shared with other schedulers
  *
  * Initialize the driver information for the selected ring (all asics).
  * Returns 0 on success, error on failure.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index ca1622835296..e7d3d0dbdd96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -107,7 +107,8 @@ struct amdgpu_fence_driver {
 };
 
 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
-void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
+void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev);
+void amdgpu_fence_driver_fini_sw(struct amdgpu_device *adev);
 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
 
 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index 4fc2ce8ce8ab..7a4775ab6804 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
 	void (*reset)(struct amdgpu_device *adev);
 	void (*start)(struct amdgpu_device *adev);
 	void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
-	void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag);
-	u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
+	void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 acc_flags, u32 hwip);
+	u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip);
 	bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
index 5369c8dd0764..123453999093 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
@@ -86,6 +86,8 @@ void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedispla
 	(*cmd)->cmd_id = command_id;
 }
 
+#if defined(CONFIG_DEBUG_FS)
+
 static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __user *buf,
 		size_t size, loff_t *pos)
 {
@@ -162,6 +164,8 @@ static const struct file_operations amdgpu_securedisplay_debugfs_ops = {
 	.llseek = default_llseek
 };
 
+#endif
+
 void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev)
 {
 #if defined(CONFIG_DEBUG_FS)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h
index b860ec913ac5..484bb3dcec47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h
@@ -29,6 +29,7 @@ struct amdgpu_smuio_funcs {
 	void (*update_rom_clock_gating)(struct amdgpu_device *adev, bool enable);
 	void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags);
 	u32 (*get_die_id)(struct amdgpu_device *adev);
+	u32 (*get_socket_id)(struct amdgpu_device *adev);
 	bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev);
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 4e558632a5d2..1b2ceccaf5b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -210,10 +210,10 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,
 		return -EINVAL;
 
 	/* always sync to the exclusive fence */
-	f = dma_resv_get_excl(resv);
+	f = dma_resv_excl_fence(resv);
 	r = amdgpu_sync_fence(sync, f);
 
-	flist = dma_resv_get_list(resv);
+	flist = dma_resv_shared_list(resv);
 	if (!flist || r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 792d20261846..0527772fe1b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -127,8 +127,8 @@ TRACE_EVENT(amdgpu_bo_create,
 
 	    TP_fast_assign(
 			   __entry->bo = bo;
-			   __entry->pages = bo->tbo.mem.num_pages;
-			   __entry->type = bo->tbo.mem.mem_type;
+			   __entry->pages = bo->tbo.resource->num_pages;
+			   __entry->type = bo->tbo.resource->mem_type;
 			   __entry->prefer = bo->preferred_domains;
 			   __entry->allow = bo->allowed_domains;
 			   __entry->visible = bo->flags;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 61c4fb1b87fe..cdfc20b0b2eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -32,7 +32,6 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/iommu.h>
-#include <linux/hmm.h>
 #include <linux/pagemap.h>
 #include <linux/sched/task.h>
 #include <linux/sched/mm.h>
@@ -46,6 +45,7 @@
 #include <drm/ttm/ttm_bo_api.h>
 #include <drm/ttm/ttm_bo_driver.h>
 #include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_range_manager.h>
 
 #include <drm/amdgpu_drm.h>
 
@@ -112,7 +112,22 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 	}
 
 	abo = ttm_to_amdgpu_bo(bo);
-	switch (bo->mem.mem_type) {
+	if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
+		struct dma_fence *fence;
+		struct dma_resv *resv = &bo->base._resv;
+
+		rcu_read_lock();
+		fence = rcu_dereference(resv->fence_excl);
+		if (fence && !fence->ops->signaled)
+			dma_fence_enable_sw_signaling(fence);
+
+		placement->num_placement = 0;
+		placement->num_busy_placement = 0;
+		rcu_read_unlock();
+		return;
+	}
+
+	switch (bo->resource->mem_type) {
 	case AMDGPU_PL_GDS:
 	case AMDGPU_PL_GWS:
 	case AMDGPU_PL_OA:
@@ -145,6 +160,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 		}
 		break;
 	case TTM_PL_TT:
+	case AMDGPU_PL_PREEMPT:
 	default:
 		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 		break;
@@ -153,32 +169,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 }
 
 /**
- * amdgpu_verify_access - Verify access for a mmap call
- *
- * @bo:	The buffer object to map
- * @filp: The file pointer from the process performing the mmap
- *
- * This is called by ttm_bo_mmap() to verify whether a process
- * has the right to mmap a BO to their process space.
- */
-static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
-{
-	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
-
-	/*
-	 * Don't verify access for KFD BOs. They don't have a GEM
-	 * object associated with them.
-	 */
-	if (abo->kfd_bo)
-		return 0;
-
-	if (amdgpu_ttm_tt_get_usermm(bo->ttm))
-		return -EPERM;
-	return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
-					  filp->private_data);
-}
-
-/**
  * amdgpu_ttm_map_buffer - Map memory into the GART windows
  * @bo: buffer object to map
  * @mem: memory object to map
@@ -211,6 +201,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 
 	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
+	BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT);
 
 	/* Map only what can't be accessed directly */
 	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
@@ -288,7 +279,7 @@ error_free:
 }
 
 /**
- * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
+ * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
  * @adev: amdgpu device
  * @src: buffer/address where to read from
  * @dst: buffer/address where to write to
@@ -471,10 +462,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 {
 	struct amdgpu_device *adev;
 	struct amdgpu_bo *abo;
-	struct ttm_resource *old_mem = &bo->mem;
+	struct ttm_resource *old_mem = bo->resource;
 	int r;
 
-	if (new_mem->mem_type == TTM_PL_TT) {
+	if (new_mem->mem_type == TTM_PL_TT ||
+	    new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 		if (r)
 			return r;
@@ -492,18 +484,20 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 		goto out;
 	}
 	if (old_mem->mem_type == TTM_PL_SYSTEM &&
-	    new_mem->mem_type == TTM_PL_TT) {
+	    (new_mem->mem_type == TTM_PL_TT ||
+	     new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 		ttm_bo_move_null(bo, new_mem);
 		goto out;
 	}
-	if (old_mem->mem_type == TTM_PL_TT &&
+	if ((old_mem->mem_type == TTM_PL_TT ||
+	     old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 	    new_mem->mem_type == TTM_PL_SYSTEM) {
 		r = ttm_bo_wait_ctx(bo, ctx);
 		if (r)
 			return r;
 
 		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
-		ttm_resource_free(bo, &bo->mem);
+		ttm_resource_free(bo, &bo->resource);
 		ttm_bo_assign_mem(bo, new_mem);
 		goto out;
 	}
@@ -570,10 +564,10 @@ out:
  *
  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
  */
-static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
+static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
+				     struct ttm_resource *mem)
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
-	struct drm_mm_node *mm_node = mem->mm_node;
 	size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 
 	switch (mem->mem_type) {
@@ -581,18 +575,16 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resourc
 		/* system memory */
 		return 0;
 	case TTM_PL_TT:
+	case AMDGPU_PL_PREEMPT:
 		break;
 	case TTM_PL_VRAM:
 		mem->bus.offset = mem->start << PAGE_SHIFT;
 		/* check if it's visible */
 		if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 			return -EINVAL;
-		/* Only physically contiguous buffers apply. In a contiguous
-		 * buffer, size of the first mm_node would match the number of
-		 * pages in ttm_resource.
-		 */
+
 		if (adev->mman.aper_base_kaddr &&
-		    (mm_node->size == mem->num_pages))
+		    mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 					mem->bus.offset;
 
@@ -615,7 +607,8 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 	struct amdgpu_res_cursor cursor;
 
-	amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
+	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
+			 &cursor);
 	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 }
 
@@ -670,10 +663,8 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
 	unsigned long start = gtt->userptr;
 	struct vm_area_struct *vma;
-	struct hmm_range *range;
-	unsigned long timeout;
 	struct mm_struct *mm;
-	unsigned long i;
+	bool readonly;
 	int r = 0;
 
 	mm = bo->notifier.mm;
@@ -689,25 +680,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 		return -ESRCH;
 
-	range = kzalloc(sizeof(*range), GFP_KERNEL);
-	if (unlikely(!range)) {
-		r = -ENOMEM;
-		goto out;
-	}
-	range->notifier = &bo->notifier;
-	range->start = bo->notifier.interval_tree.start;
-	range->end = bo->notifier.interval_tree.last + 1;
-	range->default_flags = HMM_PFN_REQ_FAULT;
-	if (!amdgpu_ttm_tt_is_readonly(ttm))
-		range->default_flags |= HMM_PFN_REQ_WRITE;
-
-	range->hmm_pfns = kvmalloc_array(ttm->num_pages,
-					 sizeof(*range->hmm_pfns), GFP_KERNEL);
-	if (unlikely(!range->hmm_pfns)) {
-		r = -ENOMEM;
-		goto out_free_ranges;
-	}
-
 	mmap_read_lock(mm);
 	vma = vma_lookup(mm, start);
 	if (unlikely(!vma)) {
@@ -719,46 +691,15 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 		r = -EPERM;
 		goto out_unlock;
 	}
-	mmap_read_unlock(mm);
-	timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
-
-retry:
-	range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
-
-	mmap_read_lock(mm);
-	r = hmm_range_fault(range);
-	mmap_read_unlock(mm);
-	if (unlikely(r)) {
-		/*
-		 * FIXME: This timeout should encompass the retry from
-		 * mmu_interval_read_retry() as well.
-		 */
-		if (r == -EBUSY && !time_after(jiffies, timeout))
-			goto retry;
-		goto out_free_pfns;
-	}
-
-	/*
-	 * Due to default_flags, all pages are HMM_PFN_VALID or
-	 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
-	 * the notifier_lock, and mmu_interval_read_retry() must be done first.
-	 */
-	for (i = 0; i < ttm->num_pages; i++)
-		pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
-
-	gtt->range = range;
-	mmput(mm);
-
-	return 0;
 
+	readonly = amdgpu_ttm_tt_is_readonly(ttm);
+	r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
+				       ttm->num_pages, &gtt->range, readonly,
+				       true);
 out_unlock:
 	mmap_read_unlock(mm);
-out_free_pfns:
-	kvfree(range->hmm_pfns);
-out_free_ranges:
-	kfree(range);
-out:
 	mmput(mm);
+
 	return r;
 }
 
@@ -787,10 +728,7 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 		 * FIXME: Must always hold notifier_lock for this, and must
 		 * not ignore the return code.
 		 */
-		r = mmu_interval_read_retry(gtt->range->notifier,
-					 gtt->range->notifier_seq);
-		kvfree(gtt->range->hmm_pfns);
-		kfree(gtt->range);
+		r = amdgpu_hmm_range_get_pages_done(gtt->range);
 		gtt->range = NULL;
 	}
 
@@ -903,7 +841,7 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 		uint64_t page_idx = 1;
 
 		r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
-				ttm->pages, gtt->ttm.dma_address, flags);
+				gtt->ttm.dma_address, flags);
 		if (r)
 			goto gart_bind_fail;
 
@@ -917,11 +855,10 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 		r = amdgpu_gart_bind(adev,
 				gtt->offset + (page_idx << PAGE_SHIFT),
 				ttm->num_pages - page_idx,
-				&ttm->pages[page_idx],
 				&(gtt->ttm.dma_address[page_idx]), flags);
 	} else {
 		r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
-				     ttm->pages, gtt->ttm.dma_address, flags);
+				     gtt->ttm.dma_address, flags);
 	}
 
 gart_bind_fail:
@@ -959,7 +896,23 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 			DRM_ERROR("failed to pin userptr\n");
 			return r;
 		}
+	} else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
+		if (!ttm->sg) {
+			struct dma_buf_attachment *attach;
+			struct sg_table *sgt;
+
+			attach = gtt->gobj->import_attach;
+			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
+			if (IS_ERR(sgt))
+				return PTR_ERR(sgt);
+
+			ttm->sg = sgt;
+		}
+
+		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
+					       ttm->num_pages);
 	}
+
 	if (!ttm->num_pages) {
 		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 		     ttm->num_pages, bo_mem, ttm);
@@ -981,7 +934,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 	/* bind pages into GART page tables */
 	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 	r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
-		ttm->pages, gtt->ttm.dma_address, flags);
+		gtt->ttm.dma_address, flags);
 
 	if (r)
 		DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
@@ -1003,51 +956,50 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 	struct ttm_operation_ctx ctx = { false, false };
 	struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
-	struct ttm_resource tmp;
 	struct ttm_placement placement;
 	struct ttm_place placements;
+	struct ttm_resource *tmp;
 	uint64_t addr, flags;
 	int r;
 
-	if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
+	if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 		return 0;
 
 	addr = amdgpu_gmc_agp_addr(bo);
 	if (addr != AMDGPU_BO_INVALID_OFFSET) {
-		bo->mem.start = addr >> PAGE_SHIFT;
-	} else {
+		bo->resource->start = addr >> PAGE_SHIFT;
+		return 0;
+	}
 
-		/* allocate GART space */
-		tmp = bo->mem;
-		tmp.mm_node = NULL;
-		placement.num_placement = 1;
-		placement.placement = &placements;
-		placement.num_busy_placement = 1;
-		placement.busy_placement = &placements;
-		placements.fpfn = 0;
-		placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
-		placements.mem_type = TTM_PL_TT;
-		placements.flags = bo->mem.placement;
-
-		r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
-		if (unlikely(r))
-			return r;
+	/* allocate GART space */
+	placement.num_placement = 1;
+	placement.placement = &placements;
+	placement.num_busy_placement = 1;
+	placement.busy_placement = &placements;
+	placements.fpfn = 0;
+	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
+	placements.mem_type = TTM_PL_TT;
+	placements.flags = bo->resource->placement;
 
-		/* compute PTE flags for this buffer object */
-		flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
+	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
+	if (unlikely(r))
+		return r;
 
-		/* Bind pages */
-		gtt->offset = (u64)tmp.start << PAGE_SHIFT;
-		r = amdgpu_ttm_gart_bind(adev, bo, flags);
-		if (unlikely(r)) {
-			ttm_resource_free(bo, &tmp);
-			return r;
-		}
+	/* compute PTE flags for this buffer object */
+	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 
-		ttm_resource_free(bo, &bo->mem);
-		bo->mem = tmp;
+	/* Bind pages */
+	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
+	r = amdgpu_ttm_gart_bind(adev, bo, flags);
+	if (unlikely(r)) {
+		ttm_resource_free(bo, &tmp);
+		return r;
 	}
 
+	amdgpu_gart_invalidate_tlb(adev);
+	ttm_resource_free(bo, &bo->resource);
+	ttm_bo_assign_mem(bo, tmp);
+
 	return 0;
 }
 
@@ -1066,7 +1018,7 @@ int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 	if (!tbo->ttm)
 		return 0;
 
-	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
+	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
 	r = amdgpu_ttm_gart_bind(adev, tbo, flags);
 
 	return r;
@@ -1086,8 +1038,15 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
 	int r;
 
 	/* if the pages have userptr pinning then clear that first */
-	if (gtt->userptr)
+	if (gtt->userptr) {
 		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
+	} else if (ttm->sg && gtt->gobj->import_attach) {
+		struct dma_buf_attachment *attach;
+
+		attach = gtt->gobj->import_attach;
+		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
+		ttm->sg = NULL;
+	}
 
 	if (!gtt->bound)
 		return;
@@ -1169,28 +1128,11 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
 		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 		if (!ttm->sg)
 			return -ENOMEM;
-
-		ttm->page_flags |= TTM_PAGE_FLAG_SG;
 		return 0;
 	}
 
-	if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
-		if (!ttm->sg) {
-			struct dma_buf_attachment *attach;
-			struct sg_table *sgt;
-
-			attach = gtt->gobj->import_attach;
-			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
-			if (IS_ERR(sgt))
-				return PTR_ERR(sgt);
-
-			ttm->sg = sgt;
-		}
-
-		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
-					       ttm->num_pages);
+	if (ttm->page_flags & TTM_PAGE_FLAG_SG)
 		return 0;
-	}
 
 	return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
 }
@@ -1211,16 +1153,6 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
 		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
 		kfree(ttm->sg);
 		ttm->sg = NULL;
-		ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
-		return;
-	}
-
-	if (ttm->sg && gtt->gobj->import_attach) {
-		struct dma_buf_attachment *attach;
-
-		attach = gtt->gobj->import_attach;
-		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
-		ttm->sg = NULL;
 		return;
 	}
 
@@ -1254,6 +1186,9 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
 			return -ENOMEM;
 	}
 
+	/* Set TTM_PAGE_FLAG_SG before populate but after create. */
+	bo->ttm->page_flags |= TTM_PAGE_FLAG_SG;
+
 	gtt = (void *)bo->ttm;
 	gtt->userptr = addr;
 	gtt->userflags = flags;
@@ -1347,7 +1282,8 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
 	if (mem && mem->mem_type != TTM_PL_SYSTEM)
 		flags |= AMDGPU_PTE_VALID;
 
-	if (mem && mem->mem_type == TTM_PL_TT) {
+	if (mem && (mem->mem_type == TTM_PL_TT ||
+		    mem->mem_type == AMDGPU_PL_PREEMPT)) {
 		flags |= AMDGPU_PTE_SYSTEM;
 
 		if (ttm->caching == ttm_cached)
@@ -1396,12 +1332,16 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
 					    const struct ttm_place *place)
 {
-	unsigned long num_pages = bo->mem.num_pages;
+	unsigned long num_pages = bo->resource->num_pages;
 	struct amdgpu_res_cursor cursor;
 	struct dma_resv_list *flist;
 	struct dma_fence *f;
 	int i;
 
+	/* Swapout? */
+	if (bo->resource->mem_type == TTM_PL_SYSTEM)
+		return true;
+
 	if (bo->type == ttm_bo_type_kernel &&
 	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
 		return false;
@@ -1410,7 +1350,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
 	 * If true, then return false as any KFD process needs all its BOs to
 	 * be resident to run successfully
 	 */
-	flist = dma_resv_get_list(bo->base.resv);
+	flist = dma_resv_shared_list(bo->base.resv);
 	if (flist) {
 		for (i = 0; i < flist->shared_count; ++i) {
 			f = rcu_dereference_protected(flist->shared[i],
@@ -1420,7 +1360,16 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
 		}
 	}
 
-	switch (bo->mem.mem_type) {
+	switch (bo->resource->mem_type) {
+	case AMDGPU_PL_PREEMPT:
+		/* Preemptible BOs don't own system resources managed by the
+		 * driver (pages, VRAM, GART space). They point to resources
+		 * owned by someone else (e.g. pageable memory in user mode
+		 * or a DMABuf). They are used in a preemptible context so we
+		 * can guarantee no deadlocks and good QoS in case of MMU
+		 * notifiers or DMABuf move notifiers from the resource owner.
+		 */
+		return false;
 	case TTM_PL_TT:
 		if (amdgpu_bo_is_amdgpu_bo(bo) &&
 		    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
@@ -1429,7 +1378,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
 
 	case TTM_PL_VRAM:
 		/* Check each drm MM node individually */
-		amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT,
+		amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
 				 &cursor);
 		while (cursor.remaining) {
 			if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
@@ -1471,10 +1420,10 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
 	uint32_t value = 0;
 	int ret = 0;
 
-	if (bo->mem.mem_type != TTM_PL_VRAM)
+	if (bo->resource->mem_type != TTM_PL_VRAM)
 		return -EIO;
 
-	amdgpu_res_first(&bo->mem, offset, len, &cursor);
+	amdgpu_res_first(bo->resource, offset, len, &cursor);
 	while (cursor.remaining) {
 		uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
 		uint64_t bytes = 4 - (cursor.start & 3);
@@ -1530,7 +1479,6 @@ static struct ttm_device_funcs amdgpu_bo_driver = {
 	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
 	.evict_flags = &amdgpu_evict_flags,
 	.move = &amdgpu_bo_move,
-	.verify_access = &amdgpu_verify_access,
 	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
 	.release_notify = &amdgpu_bo_release_notify,
 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
@@ -1633,11 +1581,8 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
 	bool mem_train_support = false;
 
 	if (!amdgpu_sriov_vf(adev)) {
-		ret = amdgpu_mem_train_support(adev);
-		if (ret == 1)
+		if (amdgpu_atomfirmware_mem_training_supported(adev))
 			mem_train_support = true;
-		else if (ret == -1)
-			return -EINVAL;
 		else
 			DRM_DEBUG("memory training does not support!\n");
 	}
@@ -1779,6 +1724,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 				       NULL);
 	if (r)
 		return r;
+	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
+				       adev->mman.stolen_reserved_size,
+				       AMDGPU_GEM_DOMAIN_VRAM,
+				       &adev->mman.stolen_reserved_memory,
+				       NULL);
+	if (r)
+		return r;
 
 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
@@ -1805,6 +1757,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
 		 (unsigned)(gtt_size / (1024 * 1024)));
 
+	/* Initialize preemptible memory pool */
+	r = amdgpu_preempt_mgr_init(adev);
+	if (r) {
+		DRM_ERROR("Failed initializing PREEMPT heap.\n");
+		return r;
+	}
+
 	/* Initialize various on-chip memory pools */
 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
 	if (r) {
@@ -1841,14 +1800,14 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
 	amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
 	/* return the IP Discovery TMR memory back to VRAM */
 	amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
+	if (adev->mman.stolen_reserved_size)
+		amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
+				      NULL, NULL);
 	amdgpu_ttm_fw_reserve_vram_fini(adev);
 
-	if (adev->mman.aper_base_kaddr)
-		iounmap(adev->mman.aper_base_kaddr);
-	adev->mman.aper_base_kaddr = NULL;
-
 	amdgpu_vram_mgr_fini(adev);
 	amdgpu_gtt_mgr_fini(adev);
+	amdgpu_preempt_mgr_fini(adev);
 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
 	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
@@ -1905,50 +1864,6 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
 	adev->mman.buffer_funcs_enabled = enable;
 }
 
-static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
-{
-	struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
-	vm_fault_t ret;
-
-	ret = ttm_bo_vm_reserve(bo, vmf);
-	if (ret)
-		return ret;
-
-	ret = amdgpu_bo_fault_reserve_notify(bo);
-	if (ret)
-		goto unlock;
-
-	ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
-				       TTM_BO_VM_NUM_PREFAULT, 1);
-	if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
-		return ret;
-
-unlock:
-	dma_resv_unlock(bo->base.resv);
-	return ret;
-}
-
-static const struct vm_operations_struct amdgpu_ttm_vm_ops = {
-	.fault = amdgpu_ttm_fault,
-	.open = ttm_bo_vm_open,
-	.close = ttm_bo_vm_close,
-	.access = ttm_bo_vm_access
-};
-
-int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
-{
-	struct drm_file *file_priv = filp->private_data;
-	struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
-	int r;
-
-	r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
-	if (unlikely(r != 0))
-		return r;
-
-	vma->vm_ops = &amdgpu_ttm_vm_ops;
-	return 0;
-}
-
 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
 		       uint64_t dst_offset, uint32_t byte_count,
 		       struct dma_resv *resv,
@@ -2043,16 +1958,21 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
 		return -EINVAL;
 	}
 
-	if (bo->tbo.mem.mem_type == TTM_PL_TT) {
+	if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
+		DRM_ERROR("Trying to clear preemptible memory.\n");
+		return -EINVAL;
+	}
+
+	if (bo->tbo.resource->mem_type == TTM_PL_TT) {
 		r = amdgpu_ttm_alloc_gart(&bo->tbo);
 		if (r)
 			return r;
 	}
 
-	num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT;
+	num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT;
 	num_loops = 0;
 
-	amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
+	amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
 	while (cursor.remaining) {
 		num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
 		amdgpu_res_next(&cursor, cursor.size);
@@ -2077,12 +1997,13 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
 		}
 	}
 
-	amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
+	amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
 	while (cursor.remaining) {
 		uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
 		uint64_t dst_addr = cursor.start;
 
-		dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
+		dst_addr += amdgpu_ttm_domain_start(adev,
+						    bo->tbo.resource->mem_type);
 		amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
 					cur_size);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 9e38475e0f8d..e69f3e8e06e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -31,17 +31,13 @@
 #define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)
 #define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)
 #define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)
+#define AMDGPU_PL_PREEMPT	(TTM_PL_PRIV + 3)
 
 #define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2
 
 #define AMDGPU_POISON	0xd0bed0be
 
-struct amdgpu_vram_reservation {
-	struct list_head node;
-	struct drm_mm_node mm_node;
-};
-
 struct amdgpu_vram_mgr {
 	struct ttm_resource_manager manager;
 	struct drm_mm mm;
@@ -59,6 +55,11 @@ struct amdgpu_gtt_mgr {
 	atomic64_t available;
 };
 
+struct amdgpu_preempt_mgr {
+	struct ttm_resource_manager manager;
+	atomic64_t used;
+};
+
 struct amdgpu_mman {
 	struct ttm_device		bdev;
 	bool				initialized;
@@ -75,6 +76,7 @@ struct amdgpu_mman {
 
 	struct amdgpu_vram_mgr vram_mgr;
 	struct amdgpu_gtt_mgr gtt_mgr;
+	struct amdgpu_preempt_mgr preempt_mgr;
 
 	uint64_t		stolen_vga_size;
 	struct amdgpu_bo	*stolen_vga_memory;
@@ -82,6 +84,10 @@ struct amdgpu_mman {
 	struct amdgpu_bo	*stolen_extended_memory;
 	bool			keep_stolen_vga_memory;
 
+	struct amdgpu_bo	*stolen_reserved_memory;
+	uint64_t		stolen_reserved_offset;
+	uint64_t		stolen_reserved_size;
+
 	/* discovery */
 	uint8_t				*discovery_bin;
 	uint32_t			discovery_tmr_size;
@@ -102,6 +108,8 @@ struct amdgpu_copy_mem {
 
 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
+int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
+void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
 int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
 
@@ -109,6 +117,8 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
 uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man);
 int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man);
 
+uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
+
 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
 			      struct ttm_resource *mem,
@@ -147,7 +157,6 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
 			struct dma_resv *resv,
 			struct dma_fence **fence);
 
-int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 9733224117e3..2834981f8c08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -257,36 +257,36 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
 			container_of(hdr, struct psp_firmware_header_v1_0, header);
 
 		DRM_DEBUG("ucode_feature_version: %u\n",
-			  le32_to_cpu(psp_hdr->ucode_feature_version));
+			  le32_to_cpu(psp_hdr->sos.fw_version));
 		DRM_DEBUG("sos_offset_bytes: %u\n",
-			  le32_to_cpu(psp_hdr->sos_offset_bytes));
+			  le32_to_cpu(psp_hdr->sos.offset_bytes));
 		DRM_DEBUG("sos_size_bytes: %u\n",
-			  le32_to_cpu(psp_hdr->sos_size_bytes));
+			  le32_to_cpu(psp_hdr->sos.size_bytes));
 		if (version_minor == 1) {
 			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 				container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 			DRM_DEBUG("toc_header_version: %u\n",
-				  le32_to_cpu(psp_hdr_v1_1->toc_header_version));
+				  le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
 			DRM_DEBUG("toc_offset_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
+				  le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
 			DRM_DEBUG("toc_size_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
+				  le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
 			DRM_DEBUG("kdb_header_version: %u\n",
-				  le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
+				  le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
 			DRM_DEBUG("kdb_offset_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
+				  le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
 			DRM_DEBUG("kdb_size_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
+				  le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
 		}
 		if (version_minor == 2) {
 			const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
 				container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
 			DRM_DEBUG("kdb_header_version: %u\n",
-				  le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
+				  le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
 			DRM_DEBUG("kdb_offset_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
+				  le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
 			DRM_DEBUG("kdb_size_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
+				  le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
 		}
 		if (version_minor == 3) {
 			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
@@ -294,23 +294,23 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
 			const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
 				container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
 			DRM_DEBUG("toc_header_version: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version));
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
 			DRM_DEBUG("toc_offset_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes));
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
 			DRM_DEBUG("toc_size_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes));
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
 			DRM_DEBUG("kdb_header_version: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version));
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
 			DRM_DEBUG("kdb_offset_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes));
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
 			DRM_DEBUG("kdb_size_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes));
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
 			DRM_DEBUG("spl_header_version: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->spl_header_version));
+				  le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
 			DRM_DEBUG("spl_offset_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes));
+				  le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
 			DRM_DEBUG("spl_size_bytes: %u\n",
-				  le32_to_cpu(psp_hdr_v1_3->spl_size_bytes));
+				  le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
 		}
 	} else {
 		DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
@@ -403,6 +403,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_ALDEBARAN:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		if (!load_type)
 			return AMDGPU_FW_LOAD_DIRECT;
 		else
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 2c42874f7784..270309e7f5f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -71,43 +71,39 @@ struct smc_firmware_header_v2_1 {
         uint32_t pptable_entry_offset;
 };
 
+struct psp_fw_bin_desc {
+	uint32_t fw_version;
+	uint32_t offset_bytes;
+	uint32_t size_bytes;
+};
+
 /* version_major=1, version_minor=0 */
 struct psp_firmware_header_v1_0 {
 	struct common_firmware_header header;
-	uint32_t ucode_feature_version;
-	uint32_t sos_offset_bytes;
-	uint32_t sos_size_bytes;
+	struct psp_fw_bin_desc sos;
 };
 
 /* version_major=1, version_minor=1 */
 struct psp_firmware_header_v1_1 {
 	struct psp_firmware_header_v1_0 v1_0;
-	uint32_t toc_header_version;
-	uint32_t toc_offset_bytes;
-	uint32_t toc_size_bytes;
-	uint32_t kdb_header_version;
-	uint32_t kdb_offset_bytes;
-	uint32_t kdb_size_bytes;
+	struct psp_fw_bin_desc toc;
+	struct psp_fw_bin_desc kdb;
 };
 
 /* version_major=1, version_minor=2 */
 struct psp_firmware_header_v1_2 {
 	struct psp_firmware_header_v1_0 v1_0;
-	uint32_t reserve[3];
-	uint32_t kdb_header_version;
-	uint32_t kdb_offset_bytes;
-	uint32_t kdb_size_bytes;
+	struct psp_fw_bin_desc res;
+	struct psp_fw_bin_desc kdb;
 };
 
 /* version_major=1, version_minor=3 */
 struct psp_firmware_header_v1_3 {
 	struct psp_firmware_header_v1_1 v1_1;
-	uint32_t spl_header_version;
-	uint32_t spl_offset_bytes;
-	uint32_t spl_size_bytes;
-	uint32_t rl_header_version;
-	uint32_t rl_offset_bytes;
-	uint32_t rl_size_bytes;
+	struct psp_fw_bin_desc spl;
+	struct psp_fw_bin_desc rl;
+	struct psp_fw_bin_desc sys_drv_aux;
+	struct psp_fw_bin_desc sos_aux;
 };
 
 /* version_major=1, version_minor=0 */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index ea6f99be070b..f4489773715e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -94,6 +94,7 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
 		struct amdgpu_iv_entry *entry)
 {
 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 
 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 	if (adev->umc.ras_funcs &&
@@ -131,6 +132,9 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
 			amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
 						err_data->err_addr_cnt);
 			amdgpu_ras_save_bad_pages(adev);
+
+			if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
+				adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
 		}
 
 		amdgpu_ras_reset_gpu(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index bbcccf53080d..e5a75fb788dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -22,6 +22,11 @@
 #define __AMDGPU_UMC_H__
 
 /*
+ * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
+ * is the index of 4KB block
+ */
+#define ADDR_OF_4KB_BLOCK(addr)			(((addr) & ~0xffULL) << 4)
+/*
  * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
  * is the index of 8KB block
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index c6dbc0801604..0f576f294d8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -32,6 +32,7 @@
 #include <linux/module.h>
 
 #include <drm/drm.h>
+#include <drm/drm_drv.h>
 
 #include "amdgpu.h"
 #include "amdgpu_pm.h"
@@ -375,7 +376,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 {
 	unsigned size;
 	void *ptr;
-	int i, j;
+	int i, j, idx;
 	bool in_ras_intr = amdgpu_ras_intr_triggered();
 
 	cancel_delayed_work_sync(&adev->uvd.idle_work);
@@ -403,11 +404,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 		if (!adev->uvd.inst[j].saved_bo)
 			return -ENOMEM;
 
-		/* re-write 0 since err_event_athub will corrupt VCPU buffer */
-		if (in_ras_intr)
-			memset(adev->uvd.inst[j].saved_bo, 0, size);
-		else
-			memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
+		if (drm_dev_enter(&adev->ddev, &idx)) {
+			/* re-write 0 since err_event_athub will corrupt VCPU buffer */
+			if (in_ras_intr)
+				memset(adev->uvd.inst[j].saved_bo, 0, size);
+			else
+				memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
+
+			drm_dev_exit(idx);
+		}
 	}
 
 	if (in_ras_intr)
@@ -420,7 +425,7 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
 {
 	unsigned size;
 	void *ptr;
-	int i;
+	int i, idx;
 
 	for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 		if (adev->uvd.harvest_config & (1 << i))
@@ -432,7 +437,10 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
 		ptr = adev->uvd.inst[i].cpu_addr;
 
 		if (adev->uvd.inst[i].saved_bo != NULL) {
-			memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
+			if (drm_dev_enter(&adev->ddev, &idx)) {
+				memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
+				drm_dev_exit(idx);
+			}
 			kvfree(adev->uvd.inst[i].saved_bo);
 			adev->uvd.inst[i].saved_bo = NULL;
 		} else {
@@ -442,8 +450,11 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
 			hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-				memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
-					    le32_to_cpu(hdr->ucode_size_bytes));
+				if (drm_dev_enter(&adev->ddev, &idx)) {
+					memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
+						    le32_to_cpu(hdr->ucode_size_bytes));
+					drm_dev_exit(idx);
+				}
 				size -= le32_to_cpu(hdr->ucode_size_bytes);
 				ptr += le32_to_cpu(hdr->ucode_size_bytes);
 			}
@@ -829,9 +840,8 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 
 	default:
 		DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
-		return -EINVAL;
 	}
-	BUG();
+
 	return -EINVAL;
 }
 
@@ -1115,9 +1125,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
 	ib->length_dw = 16;
 
 	if (direct) {
-		r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
-							true, false,
-							msecs_to_jiffies(10));
+		r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false,
+					  msecs_to_jiffies(10));
 		if (r == 0)
 			r = -ETIMEDOUT;
 		if (r < 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index ea6a62f67e38..1ae7f824adc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -29,6 +29,7 @@
 #include <linux/module.h>
 
 #include <drm/drm.h>
+#include <drm/drm_drv.h>
 
 #include "amdgpu.h"
 #include "amdgpu_pm.h"
@@ -87,7 +88,7 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 				      bool direct, struct dma_fence **fence);
 
 /**
- * amdgpu_vce_init - allocate memory, load vce firmware
+ * amdgpu_vce_sw_init - allocate memory, load vce firmware
  *
  * @adev: amdgpu_device pointer
  * @size: size for the new BO
@@ -204,7 +205,7 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
 }
 
 /**
- * amdgpu_vce_fini - free memory
+ * amdgpu_vce_sw_fini - free memory
  *
  * @adev: amdgpu_device pointer
  *
@@ -293,7 +294,7 @@ int amdgpu_vce_resume(struct amdgpu_device *adev)
 	void *cpu_addr;
 	const struct common_firmware_header *hdr;
 	unsigned offset;
-	int r;
+	int r, idx;
 
 	if (adev->vce.vcpu_bo == NULL)
 		return -EINVAL;
@@ -313,8 +314,12 @@ int amdgpu_vce_resume(struct amdgpu_device *adev)
 
 	hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 	offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-	memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
-		    adev->vce.fw->size - offset);
+
+	if (drm_dev_enter(&adev->ddev, &idx)) {
+		memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
+			    adev->vce.fw->size - offset);
+		drm_dev_exit(idx);
+	}
 
 	amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 
@@ -574,7 +579,7 @@ err:
 }
 
 /**
- * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
+ * amdgpu_vce_validate_bo - make sure not to cross 4GB boundary
  *
  * @p: parser context
  * @ib_idx: indirect buffer to use
@@ -715,7 +720,7 @@ static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 }
 
 /**
- * amdgpu_vce_cs_parse - parse and validate the command stream
+ * amdgpu_vce_ring_parse_cs - parse and validate the command stream
  *
  * @p: parser context
  * @ib_idx: indirect buffer to use
@@ -951,7 +956,7 @@ out:
 }
 
 /**
- * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
+ * amdgpu_vce_ring_parse_cs_vm - parse the command stream in VM mode
  *
  * @p: parser context
  * @ib_idx: indirect buffer to use
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 201645963ba5..6780df0fb265 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -27,6 +27,7 @@
 #include <linux/firmware.h>
 #include <linux/module.h>
 #include <linux/pci.h>
+#include <drm/drm_drv.h>
 
 #include "amdgpu.h"
 #include "amdgpu_pm.h"
@@ -48,6 +49,8 @@
 #define FIRMWARE_VANGOGH	"amdgpu/vangogh_vcn.bin"
 #define FIRMWARE_DIMGREY_CAVEFISH	"amdgpu/dimgrey_cavefish_vcn.bin"
 #define FIRMWARE_ALDEBARAN	"amdgpu/aldebaran_vcn.bin"
+#define FIRMWARE_BEIGE_GOBY	"amdgpu/beige_goby_vcn.bin"
+#define FIRMWARE_YELLOW_CARP	"amdgpu/yellow_carp_vcn.bin"
 
 MODULE_FIRMWARE(FIRMWARE_RAVEN);
 MODULE_FIRMWARE(FIRMWARE_PICASSO);
@@ -63,6 +66,8 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
+MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
+MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
 
 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
 
@@ -151,6 +156,18 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 			adev->vcn.indirect_sram = true;
 		break;
+	case CHIP_BEIGE_GOBY:
+		fw_name = FIRMWARE_BEIGE_GOBY;
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+			adev->vcn.indirect_sram = true;
+		break;
+	case CHIP_YELLOW_CARP:
+		fw_name = FIRMWARE_YELLOW_CARP;
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+			adev->vcn.indirect_sram = true;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -271,11 +288,34 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 	return 0;
 }
 
+bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
+{
+	bool ret = false;
+
+	int major;
+	int minor;
+	int revision;
+
+	/* if cannot find IP data, then this VCN does not exist */
+	if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0)
+		return true;
+
+	if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
+		ret = true;
+	} else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) {
+		ret = true;
+	} else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
+		ret = true;
+	}
+
+	return ret;
+}
+
 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 {
 	unsigned size;
 	void *ptr;
-	int i;
+	int i, idx;
 
 	cancel_delayed_work_sync(&adev->vcn.idle_work);
 
@@ -292,7 +332,10 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 		if (!adev->vcn.inst[i].saved_bo)
 			return -ENOMEM;
 
-		memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
+		if (drm_dev_enter(&adev->ddev, &idx)) {
+			memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
+			drm_dev_exit(idx);
+		}
 	}
 	return 0;
 }
@@ -301,7 +344,7 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
 {
 	unsigned size;
 	void *ptr;
-	int i;
+	int i, idx;
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 		if (adev->vcn.harvest_config & (1 << i))
@@ -313,7 +356,10 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
 		ptr = adev->vcn.inst[i].cpu_addr;
 
 		if (adev->vcn.inst[i].saved_bo != NULL) {
-			memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
+			if (drm_dev_enter(&adev->ddev, &idx)) {
+				memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
+				drm_dev_exit(idx);
+			}
 			kvfree(adev->vcn.inst[i].saved_bo);
 			adev->vcn.inst[i].saved_bo = NULL;
 		} else {
@@ -323,8 +369,11 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
 			hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-				memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
-					    le32_to_cpu(hdr->ucode_size_bytes));
+				if (drm_dev_enter(&adev->ddev, &idx)) {
+					memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
+						    le32_to_cpu(hdr->ucode_size_bytes));
+					drm_dev_exit(idx);
+				}
 				size -= le32_to_cpu(hdr->ucode_size_bytes);
 				ptr += le32_to_cpu(hdr->ucode_size_bytes);
 			}
@@ -367,7 +416,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 	}
 
 	if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
-		amdgpu_gfx_off_ctrl(adev, true);
 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 		       AMD_PG_STATE_GATE);
 		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
@@ -387,7 +435,6 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 	atomic_inc(&adev->vcn.total_submission_cnt);
 
 	if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
-		amdgpu_gfx_off_ctrl(adev, false);
 		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 				true);
 		if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index bc76cab67697..d74c62b49795 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -280,6 +280,16 @@ struct amdgpu_vcn_decode_buffer {
 	uint32_t pad[30];
 };
 
+#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
+#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
+#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
+
+enum vcn_ring_type {
+	VCN_ENCODE_RING,
+	VCN_DECODE_RING,
+	VCN_UNIFIED_RING,
+};
+
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
 int amdgpu_vcn_suspend(struct amdgpu_device *adev);
@@ -287,6 +297,9 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev);
 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
 
+bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
+				enum vcn_ring_type type, uint32_t vcn_instance);
+
 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 0c9c5255aa42..b71dd1deeb2d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -50,9 +50,12 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
 	struct drm_device *ddev = adev_to_drm(adev);
 
 	/* enable virtual display */
-	if (adev->mode_info.num_crtc == 0)
-		adev->mode_info.num_crtc = 1;
-	adev->enable_virtual_display = true;
+	if (adev->asic_type != CHIP_ALDEBARAN &&
+	    adev->asic_type != CHIP_ARCTURUS) {
+		if (adev->mode_info.num_crtc == 0)
+			adev->mode_info.num_crtc = 1;
+		adev->enable_virtual_display = true;
+	}
 	ddev->driver_features &= ~DRIVER_ATOMIC;
 	adev->cg_flags = 0;
 	adev->pg_flags = 0;
@@ -429,6 +432,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
 	uint32_t checksum;
 	uint32_t checkval;
 
+	uint32_t i;
+	uint32_t tmp;
+
 	if (adev->virt.fw_reserve.p_pf2vf == NULL)
 		return -EINVAL;
 
@@ -469,6 +475,29 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
 		adev->virt.reg_access =
 			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;
 
+		adev->virt.decode_max_dimension_pixels = 0;
+		adev->virt.decode_max_frame_pixels = 0;
+		adev->virt.encode_max_dimension_pixels = 0;
+		adev->virt.encode_max_frame_pixels = 0;
+		adev->virt.is_mm_bw_enabled = false;
+		for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) {
+			tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;
+			adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);
+
+			tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;
+			adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);
+
+			tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;
+			adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);
+
+			tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
+			adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
+		}
+		if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
+			adev->virt.is_mm_bw_enabled = true;
+
+		adev->unique_id =
+			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;
 		break;
 	default:
 		DRM_ERROR("invalid pf2vf version\n");
@@ -679,6 +708,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
 		case CHIP_VEGA10:
 		case CHIP_VEGA20:
 		case CHIP_ARCTURUS:
+		case CHIP_ALDEBARAN:
 			soc15_set_virt_ops(adev);
 			break;
 		case CHIP_NAVI10:
@@ -740,3 +770,35 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
 
 	return mode;
 }
+
+void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
+			struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
+			struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)
+{
+	uint32_t i;
+
+	if (!adev->virt.is_mm_bw_enabled)
+		return;
+
+	if (encode) {
+		for (i = 0; i < encode_array_size; i++) {
+			encode[i].max_width = adev->virt.encode_max_dimension_pixels;
+			encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;
+			if (encode[i].max_width > 0)
+				encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width;
+			else
+				encode[i].max_height = 0;
+		}
+	}
+
+	if (decode) {
+		for (i = 0; i < decode_array_size; i++) {
+			decode[i].max_width = adev->virt.decode_max_dimension_pixels;
+			decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;
+			if (decode[i].max_width > 0)
+				decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width;
+			else
+				decode[i].max_height = 0;
+		}
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 383d4bdc3fb5..8d4c20bb71c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -233,8 +233,17 @@ struct amdgpu_virt {
 	/* vf2pf message */
 	struct delayed_work vf2pf_work;
 	uint32_t vf2pf_update_interval_ms;
+
+	/* multimedia bandwidth config */
+	bool     is_mm_bw_enabled;
+	uint32_t decode_max_dimension_pixels;
+	uint32_t decode_max_frame_pixels;
+	uint32_t encode_max_dimension_pixels;
+	uint32_t encode_max_frame_pixels;
 };
 
+struct amdgpu_video_codec_info;
+
 #define amdgpu_sriov_enabled(adev) \
 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
 
@@ -307,4 +316,8 @@ int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
 
 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
+
+void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
+			struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
+			struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9acee4a5b2ba..79cfa2d68487 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -25,18 +25,22 @@
  *          Alex Deucher
  *          Jerome Glisse
  */
+
 #include <linux/dma-fence-array.h>
 #include <linux/interval_tree_generic.h>
 #include <linux/idr.h>
 #include <linux/dma-buf.h>
 
 #include <drm/amdgpu_drm.h>
+#include <drm/drm_drv.h>
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_gmc.h"
 #include "amdgpu_xgmi.h"
 #include "amdgpu_dma_buf.h"
+#include "amdgpu_res_cursor.h"
+#include "kfd_svm.h"
 
 /**
  * DOC: GPUVM
@@ -328,7 +332,7 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
 	base->next = bo->vm_bo;
 	bo->vm_bo = base;
 
-	if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
+	if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
 		return;
 
 	vm->bulk_moveable = false;
@@ -338,7 +342,7 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
 		amdgpu_vm_bo_idle(base);
 
 	if (bo->preferred_domains &
-	    amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
+	    amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
 		return;
 
 	/*
@@ -357,14 +361,14 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
  * Helper to get the parent entry for the child page table. NULL if we are at
  * the root page directory.
  */
-static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
+static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
 {
-	struct amdgpu_bo *parent = pt->base.bo->parent;
+	struct amdgpu_bo *parent = pt->bo->parent;
 
 	if (!parent)
 		return NULL;
 
-	return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
+	return parent->vm_bo;
 }
 
 /*
@@ -372,8 +376,8 @@ static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
  */
 struct amdgpu_vm_pt_cursor {
 	uint64_t pfn;
-	struct amdgpu_vm_pt *parent;
-	struct amdgpu_vm_pt *entry;
+	struct amdgpu_vm_bo_base *parent;
+	struct amdgpu_vm_bo_base *entry;
 	unsigned level;
 };
 
@@ -412,17 +416,17 @@ static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
 {
 	unsigned mask, shift, idx;
 
-	if (!cursor->entry->entries)
+	if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
+	    !cursor->entry->bo)
 		return false;
 
-	BUG_ON(!cursor->entry->base.bo);
 	mask = amdgpu_vm_entries_mask(adev, cursor->level);
 	shift = amdgpu_vm_level_shift(adev, cursor->level);
 
 	++cursor->level;
 	idx = (cursor->pfn >> shift) & mask;
 	cursor->parent = cursor->entry;
-	cursor->entry = &cursor->entry->entries[idx];
+	cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
 	return true;
 }
 
@@ -449,7 +453,7 @@ static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
 	shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
 	num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
 
-	if (cursor->entry == &cursor->parent->entries[num_entries - 1])
+	if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
 		return false;
 
 	cursor->pfn += 1ULL << shift;
@@ -535,7 +539,7 @@ static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
  * True when the search should continue, false otherwise.
  */
 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
-				      struct amdgpu_vm_pt *entry)
+				      struct amdgpu_vm_bo_base *entry)
 {
 	return entry && (!start || entry != start->entry);
 }
@@ -586,7 +590,7 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 			 struct amdgpu_bo_list_entry *entry)
 {
 	entry->priority = 0;
-	entry->tv.bo = &vm->root.base.bo->tbo;
+	entry->tv.bo = &vm->root.bo->tbo;
 	/* Two for VM updates, one for TTM and one for the CS job */
 	entry->tv.num_shared = 4;
 	entry->user_pages = NULL;
@@ -618,7 +622,7 @@ void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
 	for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
 		struct amdgpu_vm *vm = bo_base->vm;
 
-		if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
+		if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
 			vm->bulk_moveable = false;
 	}
 
@@ -649,15 +653,16 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
 	spin_lock(&adev->mman.bdev.lru_lock);
 	list_for_each_entry(bo_base, &vm->idle, vm_status) {
 		struct amdgpu_bo *bo = bo_base->bo;
+		struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
 
 		if (!bo->parent)
 			continue;
 
-		ttm_bo_move_to_lru_tail(&bo->tbo, &bo->tbo.mem,
+		ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
 					&vm->lru_bulk_move);
-		if (bo->shadow)
-			ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
-						&bo->shadow->tbo.mem,
+		if (shadow)
+			ttm_bo_move_to_lru_tail(&shadow->tbo,
+						shadow->tbo.resource,
 						&vm->lru_bulk_move);
 	}
 	spin_unlock(&adev->mman.bdev.lru_lock);
@@ -689,15 +694,21 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 
 	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
 		struct amdgpu_bo *bo = bo_base->bo;
+		struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
 
 		r = validate(param, bo);
 		if (r)
 			return r;
+		if (shadow) {
+			r = validate(param, shadow);
+			if (r)
+				return r;
+		}
 
 		if (bo->tbo.type != ttm_bo_type_kernel) {
 			amdgpu_vm_bo_moved(bo_base);
 		} else {
-			vm->update_funcs->map_table(bo);
+			vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
 			amdgpu_vm_bo_relocated(bo_base);
 		}
 	}
@@ -729,7 +740,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
  *
  * @adev: amdgpu_device pointer
  * @vm: VM to clear BO from
- * @bo: BO to clear
+ * @vmbo: BO to clear
  * @immediate: use an immediate update
  *
  * Root PD needs to be reserved when calling this.
@@ -739,13 +750,14 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
  */
 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 			      struct amdgpu_vm *vm,
-			      struct amdgpu_bo *bo,
+			      struct amdgpu_bo_vm *vmbo,
 			      bool immediate)
 {
 	struct ttm_operation_ctx ctx = { true, false };
 	unsigned level = adev->vm_manager.root_level;
 	struct amdgpu_vm_update_params params;
-	struct amdgpu_bo *ancestor = bo;
+	struct amdgpu_bo *ancestor = &vmbo->bo;
+	struct amdgpu_bo *bo = &vmbo->bo;
 	unsigned entries, ats_entries;
 	uint64_t addr;
 	int r;
@@ -769,11 +781,11 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 		entries -= ats_entries;
 
 	} else {
-		struct amdgpu_vm_pt *pt;
+		struct amdgpu_vm_bo_base *pt;
 
-		pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
+		pt = ancestor->vm_bo;
 		ats_entries = amdgpu_vm_num_ats_entries(adev);
-		if ((pt - vm->root.entries) >= ats_entries) {
+		if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
 			ats_entries = 0;
 		} else {
 			ats_entries = entries;
@@ -785,14 +797,15 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 	if (r)
 		return r;
 
-	if (bo->shadow) {
-		r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
-				    &ctx);
+	if (vmbo->shadow) {
+		struct amdgpu_bo *shadow = vmbo->shadow;
+
+		r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx);
 		if (r)
 			return r;
 	}
 
-	r = vm->update_funcs->map_table(bo);
+	r = vm->update_funcs->map_table(vmbo);
 	if (r)
 		return r;
 
@@ -816,7 +829,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 			amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
 		}
 
-		r = vm->update_funcs->update(&params, bo, addr, 0, ats_entries,
+		r = vm->update_funcs->update(&params, vmbo, addr, 0, ats_entries,
 					     value, flags);
 		if (r)
 			return r;
@@ -839,7 +852,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 			}
 		}
 
-		r = vm->update_funcs->update(&params, bo, addr, 0, entries,
+		r = vm->update_funcs->update(&params, vmbo, addr, 0, entries,
 					     value, flags);
 		if (r)
 			return r;
@@ -849,35 +862,85 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 }
 
 /**
- * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
+ * amdgpu_vm_pt_create - create bo for PD/PT
  *
  * @adev: amdgpu_device pointer
  * @vm: requesting vm
  * @level: the page table level
  * @immediate: use a immediate update
- * @bp: resulting BO allocation parameters
+ * @vmbo: pointer to the buffer object pointer
  */
-static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
+			       struct amdgpu_vm *vm,
 			       int level, bool immediate,
-			       struct amdgpu_bo_param *bp)
+			       struct amdgpu_bo_vm **vmbo)
 {
-	memset(bp, 0, sizeof(*bp));
+	struct amdgpu_bo_param bp;
+	struct amdgpu_bo *bo;
+	struct dma_resv *resv;
+	unsigned int num_entries;
+	int r;
 
-	bp->size = amdgpu_vm_bo_size(adev, level);
-	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
-	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
-	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
-	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+	memset(&bp, 0, sizeof(bp));
+
+	bp.size = amdgpu_vm_bo_size(adev, level);
+	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
+	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
+	bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
+	bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
 		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-	bp->bo_ptr_size = sizeof(struct amdgpu_bo);
+
+	if (level < AMDGPU_VM_PTB)
+		num_entries = amdgpu_vm_num_entries(adev, level);
+	else
+		num_entries = 0;
+
+	bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
+
 	if (vm->use_cpu_for_update)
-		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-	else if (!vm->root.base.bo || vm->root.base.bo->shadow)
-		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
-	bp->type = ttm_bo_type_kernel;
-	bp->no_wait_gpu = immediate;
-	if (vm->root.base.bo)
-		bp->resv = vm->root.base.bo->tbo.base.resv;
+		bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
+	bp.type = ttm_bo_type_kernel;
+	bp.no_wait_gpu = immediate;
+	if (vm->root.bo)
+		bp.resv = vm->root.bo->tbo.base.resv;
+
+	r = amdgpu_bo_create_vm(adev, &bp, vmbo);
+	if (r)
+		return r;
+
+	bo = &(*vmbo)->bo;
+	if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
+		(*vmbo)->shadow = NULL;
+		return 0;
+	}
+
+	if (!bp.resv)
+		WARN_ON(dma_resv_lock(bo->tbo.base.resv,
+				      NULL));
+	resv = bp.resv;
+	memset(&bp, 0, sizeof(bp));
+	bp.size = amdgpu_vm_bo_size(adev, level);
+	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+	bp.type = ttm_bo_type_kernel;
+	bp.resv = bo->tbo.base.resv;
+	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
+
+	r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow);
+
+	if (!resv)
+		dma_resv_unlock(bo->tbo.base.resv);
+
+	if (r) {
+		amdgpu_bo_unref(&bo);
+		return r;
+	}
+
+	(*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
+	amdgpu_bo_add_to_shadow_list(*vmbo);
+
+	return 0;
 }
 
 /**
@@ -899,37 +962,24 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
 			       struct amdgpu_vm_pt_cursor *cursor,
 			       bool immediate)
 {
-	struct amdgpu_vm_pt *entry = cursor->entry;
-	struct amdgpu_bo_param bp;
-	struct amdgpu_bo *pt;
+	struct amdgpu_vm_bo_base *entry = cursor->entry;
+	struct amdgpu_bo *pt_bo;
+	struct amdgpu_bo_vm *pt;
 	int r;
 
-	if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
-		unsigned num_entries;
-
-		num_entries = amdgpu_vm_num_entries(adev, cursor->level);
-		entry->entries = kvmalloc_array(num_entries,
-						sizeof(*entry->entries),
-						GFP_KERNEL | __GFP_ZERO);
-		if (!entry->entries)
-			return -ENOMEM;
-	}
-
-	if (entry->base.bo)
+	if (entry->bo)
 		return 0;
 
-	amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, &bp);
-
-	r = amdgpu_bo_create(adev, &bp, &pt);
+	r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
 	if (r)
 		return r;
 
 	/* Keep a reference to the root directory to avoid
 	 * freeing them up in the wrong order.
 	 */
-	pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
-	amdgpu_vm_bo_base_init(&entry->base, vm, pt);
-
+	pt_bo = &pt->bo;
+	pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
+	amdgpu_vm_bo_base_init(entry, vm, pt_bo);
 	r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
 	if (r)
 		goto error_free_pt;
@@ -938,7 +988,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
 
 error_free_pt:
 	amdgpu_bo_unref(&pt->shadow);
-	amdgpu_bo_unref(&pt);
+	amdgpu_bo_unref(&pt_bo);
 	return r;
 }
 
@@ -947,16 +997,17 @@ error_free_pt:
  *
  * @entry: PDE to free
  */
-static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
+static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
 {
-	if (entry->base.bo) {
-		entry->base.bo->vm_bo = NULL;
-		list_del(&entry->base.vm_status);
-		amdgpu_bo_unref(&entry->base.bo->shadow);
-		amdgpu_bo_unref(&entry->base.bo);
-	}
-	kvfree(entry->entries);
-	entry->entries = NULL;
+	struct amdgpu_bo *shadow;
+
+	if (!entry->bo)
+		return;
+	shadow = amdgpu_bo_shadowed(entry->bo);
+	entry->bo->vm_bo = NULL;
+	list_del(&entry->vm_status);
+	amdgpu_bo_unref(&shadow);
+	amdgpu_bo_unref(&entry->bo);
 }
 
 /**
@@ -973,7 +1024,7 @@ static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
 			       struct amdgpu_vm_pt_cursor *start)
 {
 	struct amdgpu_vm_pt_cursor cursor;
-	struct amdgpu_vm_pt *entry;
+	struct amdgpu_vm_bo_base *entry;
 
 	vm->bulk_moveable = false;
 
@@ -1241,10 +1292,10 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
  */
 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
 				struct amdgpu_vm *vm,
-				struct amdgpu_vm_pt *entry)
+				struct amdgpu_vm_bo_base *entry)
 {
-	struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
-	struct amdgpu_bo *bo = parent->base.bo, *pbo;
+	struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
+	struct amdgpu_bo *bo = parent->bo, *pbo;
 	uint64_t pde, pt, flags;
 	unsigned level;
 
@@ -1252,9 +1303,10 @@ static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
 		pbo = pbo->parent;
 
 	level += params->adev->vm_manager.root_level;
-	amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
-	pde = (entry - parent->entries) * 8;
-	return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
+	amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
+	pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
+	return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
+					1, 0, flags);
 }
 
 /**
@@ -1269,11 +1321,11 @@ static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
 				     struct amdgpu_vm *vm)
 {
 	struct amdgpu_vm_pt_cursor cursor;
-	struct amdgpu_vm_pt *entry;
+	struct amdgpu_vm_bo_base *entry;
 
 	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
-		if (entry->base.bo && !entry->base.moved)
-			amdgpu_vm_bo_relocated(&entry->base);
+		if (entry->bo && !entry->moved)
+			amdgpu_vm_bo_relocated(entry);
 }
 
 /**
@@ -1307,11 +1359,12 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
 		return r;
 
 	while (!list_empty(&vm->relocated)) {
-		struct amdgpu_vm_pt *entry;
+		struct amdgpu_vm_bo_base *entry;
 
-		entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
-					 base.vm_status);
-		amdgpu_vm_bo_idle(&entry->base);
+		entry = list_first_entry(&vm->relocated,
+					 struct amdgpu_vm_bo_base,
+					 vm_status);
+		amdgpu_vm_bo_idle(entry);
 
 		r = amdgpu_vm_update_pde(&params, vm, entry);
 		if (r)
@@ -1334,9 +1387,9 @@ error:
  * Make sure to set the right flags for the PTEs at the desired level.
  */
 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
-				   struct amdgpu_bo *bo, unsigned level,
+				   struct amdgpu_bo_vm *pt, unsigned int level,
 				   uint64_t pe, uint64_t addr,
-				   unsigned count, uint32_t incr,
+				   unsigned int count, uint32_t incr,
 				   uint64_t flags)
 
 {
@@ -1352,7 +1405,7 @@ static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
 		flags |= AMDGPU_PTE_EXECUTABLE;
 	}
 
-	params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
+	params->vm->update_funcs->update(params, pt, pe, addr, count, incr,
 					 flags);
 }
 
@@ -1491,7 +1544,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
 			continue;
 		}
 
-		pt = cursor.entry->base.bo;
+		pt = cursor.entry->bo;
 		if (!pt) {
 			/* We need all PDs and PTs for mapping something, */
 			if (flags & AMDGPU_PTE_VALID)
@@ -1503,7 +1556,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
 			if (!amdgpu_vm_pt_ancestor(&cursor))
 				return -EINVAL;
 
-			pt = cursor.entry->base.bo;
+			pt = cursor.entry->bo;
 			shift = parent_shift;
 			frag_end = max(frag_end, ALIGN(frag_start + 1,
 				   1ULL << shift));
@@ -1532,9 +1585,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
 						    nptes, dst, incr, upd_flags,
 						    vm->task_info.pid,
 						    vm->immediate.fence_context);
-			amdgpu_vm_update_flags(params, pt, cursor.level,
-					       pe_start, dst, nptes, incr,
-					       upd_flags);
+			amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
+					       cursor.level, pe_start, dst,
+					       nptes, incr, upd_flags);
 
 			pe_start += nptes * 8;
 			dst += nptes * incr;
@@ -1557,7 +1610,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
 			 * completely covered by the range and so potentially still in use.
 			 */
 			while (cursor.pfn < frag_start) {
-				amdgpu_vm_free_pts(adev, params->vm, &cursor);
+				/* Make sure previous mapping is freed */
+				if (cursor.entry->bo) {
+					params->table_freed = true;
+					amdgpu_vm_free_pts(adev, params->vm, &cursor);
+				}
 				amdgpu_vm_pt_next(adev, &cursor);
 			}
 
@@ -1583,29 +1640,34 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
  * @last: last mapped entry
  * @flags: flags for the entries
  * @offset: offset into nodes and pages_addr
- * @nodes: array of drm_mm_nodes with the MC addresses
+ * @res: ttm_resource to map
  * @pages_addr: DMA addresses to use for mapping
  * @fence: optional resulting fence
+ * @table_freed: return true if page table is freed
  *
  * Fill in the page table entries between @start and @last.
  *
  * Returns:
  * 0 for success, -EINVAL for failure.
  */
-static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
-				       struct amdgpu_device *bo_adev,
-				       struct amdgpu_vm *vm, bool immediate,
-				       bool unlocked, struct dma_resv *resv,
-				       uint64_t start, uint64_t last,
-				       uint64_t flags, uint64_t offset,
-				       struct drm_mm_node *nodes,
-				       dma_addr_t *pages_addr,
-				       struct dma_fence **fence)
+int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
+				struct amdgpu_device *bo_adev,
+				struct amdgpu_vm *vm, bool immediate,
+				bool unlocked, struct dma_resv *resv,
+				uint64_t start, uint64_t last,
+				uint64_t flags, uint64_t offset,
+				struct ttm_resource *res,
+				dma_addr_t *pages_addr,
+				struct dma_fence **fence,
+				bool *table_freed)
 {
 	struct amdgpu_vm_update_params params;
+	struct amdgpu_res_cursor cursor;
 	enum amdgpu_sync_mode sync_mode;
-	uint64_t pfn;
-	int r;
+	int r, idx;
+
+	if (!drm_dev_enter(&adev->ddev, &idx))
+		return -ENODEV;
 
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
@@ -1622,14 +1684,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	else
 		sync_mode = AMDGPU_SYNC_EXPLICIT;
 
-	pfn = offset >> PAGE_SHIFT;
-	if (nodes) {
-		while (pfn >= nodes->size) {
-			pfn -= nodes->size;
-			++nodes;
-		}
-	}
-
 	amdgpu_vm_eviction_lock(vm);
 	if (vm->evicting) {
 		r = -EBUSY;
@@ -1639,7 +1693,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
 		struct dma_fence *tmp = dma_fence_get_stub();
 
-		amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true);
+		amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
 		swap(vm->last_unlocked, tmp);
 		dma_fence_put(tmp);
 	}
@@ -1648,23 +1702,17 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	if (r)
 		goto error_unlock;
 
-	do {
+	amdgpu_res_first(pages_addr ? NULL : res, offset,
+			 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
+	while (cursor.remaining) {
 		uint64_t tmp, num_entries, addr;
 
-
-		num_entries = last - start + 1;
-		if (nodes) {
-			addr = nodes->start << PAGE_SHIFT;
-			num_entries = min((nodes->size - pfn) *
-				AMDGPU_GPU_PAGES_IN_CPU_PAGE, num_entries);
-		} else {
-			addr = 0;
-		}
-
+		num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
 		if (pages_addr) {
 			bool contiguous = true;
 
 			if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
+				uint64_t pfn = cursor.start >> PAGE_SHIFT;
 				uint64_t count;
 
 				contiguous = pages_addr[pfn + 1] ==
@@ -1684,16 +1732,18 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 			}
 
 			if (!contiguous) {
-				addr = pfn << PAGE_SHIFT;
+				addr = cursor.start;
 				params.pages_addr = pages_addr;
 			} else {
-				addr = pages_addr[pfn];
+				addr = pages_addr[cursor.start >> PAGE_SHIFT];
 				params.pages_addr = NULL;
 			}
 
 		} else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
-			addr += bo_adev->vm_manager.vram_base_offset;
-			addr += pfn << PAGE_SHIFT;
+			addr = bo_adev->vm_manager.vram_base_offset +
+				cursor.start;
+		} else {
+			addr = 0;
 		}
 
 		tmp = start + num_entries;
@@ -1701,28 +1751,72 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 		if (r)
 			goto error_unlock;
 
-		pfn += num_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
-		if (nodes && nodes->size == pfn) {
-			pfn = 0;
-			++nodes;
-		}
+		amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
 		start = tmp;
-
-	} while (unlikely(start != last + 1));
+	}
 
 	r = vm->update_funcs->commit(&params, fence);
 
+	if (table_freed)
+		*table_freed = *table_freed || params.table_freed;
+
 error_unlock:
 	amdgpu_vm_eviction_unlock(vm);
+	drm_dev_exit(idx);
 	return r;
 }
 
+void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
+				uint64_t *gtt_mem, uint64_t *cpu_mem)
+{
+	struct amdgpu_bo_va *bo_va, *tmp;
+
+	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
+				gtt_mem, cpu_mem);
+	}
+	list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
+				gtt_mem, cpu_mem);
+	}
+	list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
+				gtt_mem, cpu_mem);
+	}
+	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
+				gtt_mem, cpu_mem);
+	}
+	spin_lock(&vm->invalidated_lock);
+	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
+				gtt_mem, cpu_mem);
+	}
+	list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
+				gtt_mem, cpu_mem);
+	}
+	spin_unlock(&vm->invalidated_lock);
+}
 /**
  * amdgpu_vm_bo_update - update all BO mappings in the vm page table
  *
  * @adev: amdgpu_device pointer
  * @bo_va: requested BO and VM object
  * @clear: if true clear the entries
+ * @table_freed: return true if page table is freed
  *
  * Fill in the page table entries for @bo_va.
  *
@@ -1730,14 +1824,13 @@ error_unlock:
  * 0 for success, -EINVAL for failure.
  */
 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
-			bool clear)
+			bool clear, bool *table_freed)
 {
 	struct amdgpu_bo *bo = bo_va->base.bo;
 	struct amdgpu_vm *vm = bo_va->base.vm;
 	struct amdgpu_bo_va_mapping *mapping;
 	dma_addr_t *pages_addr = NULL;
 	struct ttm_resource *mem;
-	struct drm_mm_node *nodes;
 	struct dma_fence **last_update;
 	struct dma_resv *resv;
 	uint64_t flags;
@@ -1746,8 +1839,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 
 	if (clear || !bo) {
 		mem = NULL;
-		nodes = NULL;
-		resv = vm->root.base.bo->tbo.base.resv;
+		resv = vm->root.bo->tbo.base.resv;
 	} else {
 		struct drm_gem_object *obj = &bo->tbo.base;
 
@@ -1757,12 +1849,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 			struct drm_gem_object *gobj = dma_buf->priv;
 			struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 
-			if (abo->tbo.mem.mem_type == TTM_PL_VRAM)
+			if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
 				bo = gem_to_amdgpu_bo(gobj);
 		}
-		mem = &bo->tbo.mem;
-		nodes = mem->mm_node;
-		if (mem->mem_type == TTM_PL_TT)
+		mem = bo->tbo.resource;
+		if (mem->mem_type == TTM_PL_TT ||
+		    mem->mem_type == AMDGPU_PL_PREEMPT)
 			pages_addr = bo->tbo.ttm->dma_address;
 	}
 
@@ -1778,7 +1870,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 	}
 
 	if (clear || (bo && bo->tbo.base.resv ==
-		      vm->root.base.bo->tbo.base.resv))
+		      vm->root.bo->tbo.base.resv))
 		last_update = &vm->last_update;
 	else
 		last_update = &bo_va->last_pt_update;
@@ -1810,8 +1902,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 		r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
 						resv, mapping->start,
 						mapping->last, update_flags,
-						mapping->offset, nodes,
-						pages_addr, last_update);
+						mapping->offset, mem,
+						pages_addr, last_update, table_freed);
 		if (r)
 			return r;
 	}
@@ -1820,8 +1912,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 	 * the evicted list so that it gets validated again on the
 	 * next command submission.
 	 */
-	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
-		uint32_t mem_type = bo->tbo.mem.mem_type;
+	if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
+		uint32_t mem_type = bo->tbo.resource->mem_type;
 
 		if (!(bo->preferred_domains &
 		      amdgpu_mem_type_to_domain(mem_type)))
@@ -1957,18 +2049,17 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
  */
 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 {
-	struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
 	struct dma_fence *excl, **shared;
 	unsigned i, shared_count;
 	int r;
 
-	r = dma_resv_get_fences_rcu(resv, &excl,
-					      &shared_count, &shared);
+	r = dma_resv_get_fences(resv, &excl, &shared_count, &shared);
 	if (r) {
 		/* Not enough memory to grab the fence list, as last resort
 		 * block for all the fences to complete.
 		 */
-		dma_resv_wait_timeout_rcu(resv, true, false,
+		dma_resv_wait_timeout(resv, true, false,
 						    MAX_SCHEDULE_TIMEOUT);
 		return;
 	}
@@ -2004,7 +2095,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 			  struct amdgpu_vm *vm,
 			  struct dma_fence **fence)
 {
-	struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
 	struct amdgpu_bo_va_mapping *mapping;
 	uint64_t init_pte_value = 0;
 	struct dma_fence *f = NULL;
@@ -2022,7 +2113,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 		r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
 						resv, mapping->start,
 						mapping->last, init_pte_value,
-						0, NULL, NULL, &f);
+						0, NULL, NULL, &f, NULL);
 		amdgpu_vm_free_mapping(adev, vm, mapping, f);
 		if (r) {
 			dma_fence_put(f);
@@ -2064,7 +2155,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 
 	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
 		/* Per VM BOs never need to bo cleared in the page tables */
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			return r;
 	}
@@ -2083,7 +2174,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 		else
 			clear = true;
 
-		r = amdgpu_vm_bo_update(adev, bo_va, clear);
+		r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL);
 		if (r)
 			return r;
 
@@ -2163,7 +2254,7 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
 	if (mapping->flags & AMDGPU_PTE_PRT)
 		amdgpu_vm_prt_get(adev);
 
-	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
+	if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
 	    !bo_va->base.moved) {
 		list_move(&bo_va->base.vm_status, &vm->moved);
 	}
@@ -2525,7 +2616,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 	struct amdgpu_vm_bo_base **base;
 
 	if (bo) {
-		if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
+		if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
 			vm->bulk_moveable = false;
 
 		for (base = &bo_va->base.bo->vm_bo; *base;
@@ -2580,7 +2671,7 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
 		return true;
 
 	/* Don't evict VM page tables while they are busy */
-	if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
+	if (!dma_resv_test_signaled(bo->tbo.base.resv, true))
 		return false;
 
 	/* Try to block ongoing updates */
@@ -2613,13 +2704,13 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 	struct amdgpu_vm_bo_base *bo_base;
 
 	/* shadow bo doesn't have bo base, its validation needs its parent */
-	if (bo->parent && bo->parent->shadow == bo)
+	if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
 		bo = bo->parent;
 
 	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
 		struct amdgpu_vm *vm = bo_base->vm;
 
-		if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
+		if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
 			amdgpu_vm_bo_evicted(bo_base);
 			continue;
 		}
@@ -2630,7 +2721,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 
 		if (bo->tbo.type == ttm_bo_type_kernel)
 			amdgpu_vm_bo_relocated(bo_base);
-		else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
+		else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
 			amdgpu_vm_bo_moved(bo_base);
 		else
 			amdgpu_vm_bo_invalidated(bo_base);
@@ -2760,8 +2851,8 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
  */
 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
 {
-	timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
-					    true, true, timeout);
+	timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
+					true, timeout);
 	if (timeout <= 0)
 		return timeout;
 
@@ -2773,7 +2864,6 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
  *
  * @adev: amdgpu_device pointer
  * @vm: requested vm
- * @vm_context: Indicates if it GFX or Compute context
  * @pasid: Process address space identifier
  *
  * Init @vm fields.
@@ -2781,11 +2871,10 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
  * Returns:
  * 0 for success, error for failure.
  */
-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-		   int vm_context, u32 pasid)
+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
 {
-	struct amdgpu_bo_param bp;
-	struct amdgpu_bo *root;
+	struct amdgpu_bo *root_bo;
+	struct amdgpu_bo_vm *root;
 	int r, i;
 
 	vm->va = RB_ROOT_CACHED;
@@ -2816,16 +2905,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	vm->pte_support_ats = false;
 	vm->is_compute_context = false;
 
-	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
-		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
-						AMDGPU_VM_USE_CPU_FOR_COMPUTE);
+	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
+				    AMDGPU_VM_USE_CPU_FOR_GFX);
 
-		if (adev->asic_type == CHIP_RAVEN)
-			vm->pte_support_ats = true;
-	} else {
-		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
-						AMDGPU_VM_USE_CPU_FOR_GFX);
-	}
 	DRM_DEBUG_DRIVER("VM update mode is %s\n",
 			 vm->use_cpu_for_update ? "CPU" : "SDMA");
 	WARN_ONCE((vm->use_cpu_for_update &&
@@ -2842,28 +2924,26 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	mutex_init(&vm->eviction_lock);
 	vm->evicting = false;
 
-	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, &bp);
-	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
-		bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
-	r = amdgpu_bo_create(adev, &bp, &root);
+	r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
+				false, &root);
 	if (r)
 		goto error_free_delayed;
-
-	r = amdgpu_bo_reserve(root, true);
+	root_bo = &root->bo;
+	r = amdgpu_bo_reserve(root_bo, true);
 	if (r)
 		goto error_free_root;
 
-	r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
+	r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
 	if (r)
 		goto error_unreserve;
 
-	amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
+	amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
 
 	r = amdgpu_vm_clear_bo(adev, vm, root, false);
 	if (r)
 		goto error_unreserve;
 
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 
 	if (pasid) {
 		unsigned long flags;
@@ -2883,12 +2963,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	return 0;
 
 error_unreserve:
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 
 error_free_root:
-	amdgpu_bo_unref(&vm->root.base.bo->shadow);
-	amdgpu_bo_unref(&vm->root.base.bo);
-	vm->root.base.bo = NULL;
+	amdgpu_bo_unref(&root->shadow);
+	amdgpu_bo_unref(&root_bo);
+	vm->root.bo = NULL;
 
 error_free_delayed:
 	dma_fence_put(vm->last_unlocked);
@@ -2914,17 +2994,14 @@ error_free_immediate:
  *	0 if this VM is clean
  */
 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
-	struct amdgpu_vm *vm)
+					  struct amdgpu_vm *vm)
 {
 	enum amdgpu_vm_level root = adev->vm_manager.root_level;
 	unsigned int entries = amdgpu_vm_num_entries(adev, root);
 	unsigned int i = 0;
 
-	if (!(vm->root.entries))
-		return 0;
-
 	for (i = 0; i < entries; i++) {
-		if (vm->root.entries[i].base.bo)
+		if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
 			return -EINVAL;
 	}
 
@@ -2958,7 +3035,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
 	int r;
 
-	r = amdgpu_bo_reserve(vm->root.base.bo, true);
+	r = amdgpu_bo_reserve(vm->root.bo, true);
 	if (r)
 		return r;
 
@@ -2985,7 +3062,9 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	 */
 	if (pte_support_ats != vm->pte_support_ats) {
 		vm->pte_support_ats = pte_support_ats;
-		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
+		r = amdgpu_vm_clear_bo(adev, vm,
+				       to_amdgpu_bo_vm(vm->root.bo),
+				       false);
 		if (r)
 			goto free_idr;
 	}
@@ -3001,7 +3080,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 
 	if (vm->use_cpu_for_update) {
 		/* Sync with last SDMA update/clear before switching to CPU */
-		r = amdgpu_bo_sync_wait(vm->root.base.bo,
+		r = amdgpu_bo_sync_wait(vm->root.bo,
 					AMDGPU_FENCE_OWNER_UNDEFINED, true);
 		if (r)
 			goto free_idr;
@@ -3029,7 +3108,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	}
 
 	/* Free the shadow bo for compute VM */
-	amdgpu_bo_unref(&vm->root.base.bo->shadow);
+	amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
 
 	if (pasid)
 		vm->pasid = pasid;
@@ -3045,7 +3124,7 @@ free_idr:
 		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
 	}
 unreserve_bo:
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 	return r;
 }
 
@@ -3088,7 +3167,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 
 	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
 
-	root = amdgpu_bo_ref(vm->root.base.bo);
+	root = amdgpu_bo_ref(vm->root.bo);
 	amdgpu_bo_reserve(root, true);
 	if (vm->pasid) {
 		unsigned long flags;
@@ -3115,7 +3194,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	amdgpu_vm_free_pts(adev, vm, NULL);
 	amdgpu_bo_unreserve(root);
 	amdgpu_bo_unref(&root);
-	WARN_ON(vm->root.base.bo);
+	WARN_ON(vm->root.bo);
 
 	drm_sched_entity_destroy(&vm->immediate);
 	drm_sched_entity_destroy(&vm->delayed);
@@ -3232,7 +3311,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 		/* Wait vm idle to make sure the vmid set in SPM_VMID is
 		 * not referenced anymore.
 		 */
-		r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true);
+		r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
 		if (r)
 			return r;
 
@@ -3240,7 +3319,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 		if (r < 0)
 			return r;
 
-		amdgpu_bo_unreserve(fpriv->vm.root.base.bo);
+		amdgpu_bo_unreserve(fpriv->vm.root.bo);
 		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
 		break;
 	default:
@@ -3304,47 +3383,57 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
 			    uint64_t addr)
 {
+	bool is_compute_context = false;
 	struct amdgpu_bo *root;
+	unsigned long irqflags;
 	uint64_t value, flags;
 	struct amdgpu_vm *vm;
 	int r;
 
-	spin_lock(&adev->vm_manager.pasid_lock);
+	spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
 	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
-	if (vm)
-		root = amdgpu_bo_ref(vm->root.base.bo);
-	else
+	if (vm) {
+		root = amdgpu_bo_ref(vm->root.bo);
+		is_compute_context = vm->is_compute_context;
+	} else {
 		root = NULL;
-	spin_unlock(&adev->vm_manager.pasid_lock);
+	}
+	spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
 
 	if (!root)
 		return false;
 
+	addr /= AMDGPU_GPU_PAGE_SIZE;
+
+	if (is_compute_context &&
+	    !svm_range_restore_pages(adev, pasid, addr)) {
+		amdgpu_bo_unref(&root);
+		return true;
+	}
+
 	r = amdgpu_bo_reserve(root, true);
 	if (r)
 		goto error_unref;
 
 	/* Double check that the VM still exists */
-	spin_lock(&adev->vm_manager.pasid_lock);
+	spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
 	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
-	if (vm && vm->root.base.bo != root)
+	if (vm && vm->root.bo != root)
 		vm = NULL;
-	spin_unlock(&adev->vm_manager.pasid_lock);
+	spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
 	if (!vm)
 		goto error_unlock;
 
-	addr /= AMDGPU_GPU_PAGE_SIZE;
 	flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
 		AMDGPU_PTE_SYSTEM;
 
-	if (vm->is_compute_context) {
+	if (is_compute_context) {
 		/* Intentionally setting invalid PTE flag
 		 * combination to force a no-retry-fault
 		 */
 		flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
 			AMDGPU_PTE_TF;
 		value = 0;
-
 	} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
 		/* Redirect the access to the dummy page */
 		value = adev->dummy_page_addr;
@@ -3363,7 +3452,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
 	}
 
 	r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
-					addr, flags, value, NULL, NULL,
+					addr, flags, value, NULL, NULL, NULL,
 					NULL);
 	if (r)
 		goto error_unlock;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 4e140288159c..ddb85a85cbba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -39,6 +39,7 @@
 struct amdgpu_bo_va;
 struct amdgpu_job;
 struct amdgpu_bo_list_entry;
+struct amdgpu_bo_vm;
 
 /*
  * GPUVM handling
@@ -121,9 +122,6 @@ struct amdgpu_bo_list_entry;
 /* max vmids dedicated for process */
 #define AMDGPU_VM_MAX_RESERVED_VMID	1
 
-#define AMDGPU_VM_CONTEXT_GFX 0
-#define AMDGPU_VM_CONTEXT_COMPUTE 1
-
 /* See vm_update_mode */
 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
@@ -154,13 +152,6 @@ struct amdgpu_vm_bo_base {
 	bool				moved;
 };
 
-struct amdgpu_vm_pt {
-	struct amdgpu_vm_bo_base	base;
-
-	/* array of page tables, one for each directory entry */
-	struct amdgpu_vm_pt		*entries;
-};
-
 /* provided by hw blocks that can write ptes, e.g., sdma */
 struct amdgpu_vm_pte_funcs {
 	/* number of dw to reserve per operation */
@@ -234,14 +225,19 @@ struct amdgpu_vm_update_params {
 	 * @num_dw_left: number of dw left for the IB
 	 */
 	unsigned int num_dw_left;
+
+	/**
+	 * @table_freed: return true if page table is freed when updating
+	 */
+	bool table_freed;
 };
 
 struct amdgpu_vm_update_funcs {
-	int (*map_table)(struct amdgpu_bo *bo);
+	int (*map_table)(struct amdgpu_bo_vm *bo);
 	int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
 		       enum amdgpu_sync_mode sync_mode);
 	int (*update)(struct amdgpu_vm_update_params *p,
-		      struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
+		      struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
 		      unsigned count, uint32_t incr, uint64_t flags);
 	int (*commit)(struct amdgpu_vm_update_params *p,
 		      struct dma_fence **fence);
@@ -281,7 +277,7 @@ struct amdgpu_vm {
 	struct list_head        done;
 
 	/* contains the page directory */
-	struct amdgpu_vm_pt     root;
+	struct amdgpu_vm_bo_base     root;
 	struct dma_fence	*last_update;
 
 	/* Scheduler entities for page table updates */
@@ -367,6 +363,8 @@ struct amdgpu_vm_manager {
 	spinlock_t				pasid_lock;
 };
 
+struct amdgpu_bo_va_mapping;
+
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
@@ -378,8 +376,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev);
 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
 
 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-		   int vm_context, u32 pasid);
+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid);
 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid);
 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
@@ -398,9 +395,18 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 			  struct dma_fence **fence);
 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 			   struct amdgpu_vm *vm);
+int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
+				struct amdgpu_device *bo_adev,
+				struct amdgpu_vm *vm, bool immediate,
+				bool unlocked, struct dma_resv *resv,
+				uint64_t start, uint64_t last,
+				uint64_t flags, uint64_t offset,
+				struct ttm_resource *res,
+				dma_addr_t *pages_addr,
+				struct dma_fence **fence, bool *free_table);
 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 			struct amdgpu_bo_va *bo_va,
-			bool clear);
+			bool clear, bool *table_freed);
 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 			     struct amdgpu_bo *bo, bool evicted);
@@ -447,6 +453,8 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
 				struct amdgpu_vm *vm);
 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
+void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
+				uint64_t *gtt_mem, uint64_t *cpu_mem);
 
 #if defined(CONFIG_DEBUG_FS)
 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index ac45d9c7a4e9..e3fbf0f10add 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -29,9 +29,9 @@
  *
  * @table: newly allocated or validated PD/PT
  */
-static int amdgpu_vm_cpu_map_table(struct amdgpu_bo *table)
+static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)
 {
-	return amdgpu_bo_kmap(table, NULL);
+	return amdgpu_bo_kmap(&table->bo, NULL);
 }
 
 /**
@@ -58,7 +58,7 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
  * amdgpu_vm_cpu_update - helper to update page tables via CPU
  *
  * @p: see amdgpu_vm_update_params definition
- * @bo: PD/PT to update
+ * @vmbo: PD/PT to update
  * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
  * @addr: dst addr to write into pe
  * @count: number of page entries to update
@@ -68,7 +68,7 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
  * Write count number of PT/PD entries directly.
  */
 static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
-				struct amdgpu_bo *bo, uint64_t pe,
+				struct amdgpu_bo_vm *vmbo, uint64_t pe,
 				uint64_t addr, unsigned count, uint32_t incr,
 				uint64_t flags)
 {
@@ -76,13 +76,13 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
 	uint64_t value;
 	int r;
 
-	if (bo->tbo.moving) {
-		r = dma_fence_wait(bo->tbo.moving, true);
+	if (vmbo->bo.tbo.moving) {
+		r = dma_fence_wait(vmbo->bo.tbo.moving, true);
 		if (r)
 			return r;
 	}
 
-	pe += (unsigned long)amdgpu_bo_kptr(bo);
+	pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo);
 
 	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
 
@@ -110,7 +110,7 @@ static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
 {
 	/* Flush HDP */
 	mb();
-	amdgpu_asic_flush_hdp(p->adev, NULL);
+	amdgpu_device_flush_hdp(p->adev, NULL);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index a83a646759c5..dbb551762805 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -33,11 +33,11 @@
  *
  * @table: newly allocated or validated PD/PT
  */
-static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table)
+static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table)
 {
 	int r;
 
-	r = amdgpu_ttm_alloc_gart(&table->tbo);
+	r = amdgpu_ttm_alloc_gart(&table->bo.tbo);
 	if (r)
 		return r;
 
@@ -112,7 +112,7 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
 		swap(p->vm->last_unlocked, f);
 		dma_fence_put(tmp);
 	} else {
-		amdgpu_bo_fence(p->vm->root.base.bo, f, true);
+		amdgpu_bo_fence(p->vm->root.bo, f, true);
 	}
 
 	if (fence && !p->immediate)
@@ -186,7 +186,7 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
  * amdgpu_vm_sdma_update - execute VM update
  *
  * @p: see amdgpu_vm_update_params definition
- * @bo: PD/PT to update
+ * @vmbo: PD/PT to update
  * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
  * @addr: dst addr to write into pe
  * @count: number of page entries to update
@@ -197,10 +197,11 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
  * the IB.
  */
 static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
-				 struct amdgpu_bo *bo, uint64_t pe,
+				 struct amdgpu_bo_vm *vmbo, uint64_t pe,
 				 uint64_t addr, unsigned count, uint32_t incr,
 				 uint64_t flags)
 {
+	struct amdgpu_bo *bo = &vmbo->bo;
 	enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
 		: AMDGPU_IB_POOL_DELAYED;
 	unsigned int i, ndw, nptes;
@@ -238,8 +239,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
 
 		if (!p->pages_addr) {
 			/* set page commands needed */
-			if (bo->shadow)
-				amdgpu_vm_sdma_set_ptes(p, bo->shadow, pe, addr,
+			if (vmbo->shadow)
+				amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr,
 							count, incr, flags);
 			amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,
 						incr, flags);
@@ -248,7 +249,7 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
 
 		/* copy commands needed */
 		ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw *
-			(bo->shadow ? 2 : 1);
+			(vmbo->shadow ? 2 : 1);
 
 		/* for padding */
 		ndw -= 7;
@@ -263,8 +264,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
 			pte[i] |= flags;
 		}
 
-		if (bo->shadow)
-			amdgpu_vm_sdma_copy_ptes(p, bo->shadow, pe, nptes);
+		if (vmbo->shadow)
+			amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes);
 		amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);
 
 		pe += nptes * 8;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index bce105e2973e..436ec246a7da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -23,18 +23,27 @@
  */
 
 #include <linux/dma-mapping.h>
+#include <drm/ttm/ttm_range_manager.h>
+
 #include "amdgpu.h"
 #include "amdgpu_vm.h"
 #include "amdgpu_res_cursor.h"
 #include "amdgpu_atomfirmware.h"
 #include "atom.h"
 
-static inline struct amdgpu_vram_mgr *to_vram_mgr(struct ttm_resource_manager *man)
+struct amdgpu_vram_reservation {
+	struct list_head node;
+	struct drm_mm_node mm_node;
+};
+
+static inline struct amdgpu_vram_mgr *
+to_vram_mgr(struct ttm_resource_manager *man)
 {
 	return container_of(man, struct amdgpu_vram_mgr, manager);
 }
 
-static inline struct amdgpu_device *to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
+static inline struct amdgpu_device *
+to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
 {
 	return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
 }
@@ -82,12 +91,14 @@ static ssize_t amdgpu_mem_info_vis_vram_total_show(struct device *dev,
  * amount of currently used VRAM in bytes
  */
 static ssize_t amdgpu_mem_info_vram_used_show(struct device *dev,
-		struct device_attribute *attr, char *buf)
+					      struct device_attribute *attr,
+					      char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = drm_to_adev(ddev);
-	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
+	struct ttm_resource_manager *man;
 
+	man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 	return sysfs_emit(buf, "%llu\n", amdgpu_vram_mgr_usage(man));
 }
 
@@ -100,18 +111,28 @@ static ssize_t amdgpu_mem_info_vram_used_show(struct device *dev,
  * amount of currently used visible VRAM in bytes
  */
 static ssize_t amdgpu_mem_info_vis_vram_used_show(struct device *dev,
-		struct device_attribute *attr, char *buf)
+						  struct device_attribute *attr,
+						  char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = drm_to_adev(ddev);
-	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
+	struct ttm_resource_manager *man;
 
+	man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 	return sysfs_emit(buf, "%llu\n", amdgpu_vram_mgr_vis_usage(man));
 }
 
+/**
+ * DOC: mem_info_vram_vendor
+ *
+ * The amdgpu driver provides a sysfs API for reporting the vendor of the
+ * installed VRAM
+ * The file mem_info_vram_vendor is used for this and returns the name of the
+ * vendor.
+ */
 static ssize_t amdgpu_mem_info_vram_vendor(struct device *dev,
-						 struct device_attribute *attr,
-						 char *buf)
+					   struct device_attribute *attr,
+					   char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = drm_to_adev(ddev);
@@ -153,7 +174,7 @@ static DEVICE_ATTR(mem_info_vis_vram_used, S_IRUGO,
 static DEVICE_ATTR(mem_info_vram_vendor, S_IRUGO,
 		   amdgpu_mem_info_vram_vendor, NULL);
 
-static const struct attribute *amdgpu_vram_mgr_attributes[] = {
+static struct attribute *amdgpu_vram_mgr_attributes[] = {
 	&dev_attr_mem_info_vram_total.attr,
 	&dev_attr_mem_info_vis_vram_total.attr,
 	&dev_attr_mem_info_vram_used.attr,
@@ -162,77 +183,9 @@ static const struct attribute *amdgpu_vram_mgr_attributes[] = {
 	NULL
 };
 
-static const struct ttm_resource_manager_func amdgpu_vram_mgr_func;
-
-/**
- * amdgpu_vram_mgr_init - init VRAM manager and DRM MM
- *
- * @adev: amdgpu_device pointer
- *
- * Allocate and initialize the VRAM manager.
- */
-int amdgpu_vram_mgr_init(struct amdgpu_device *adev)
-{
-	struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr;
-	struct ttm_resource_manager *man = &mgr->manager;
-	int ret;
-
-	ttm_resource_manager_init(man, adev->gmc.real_vram_size >> PAGE_SHIFT);
-
-	man->func = &amdgpu_vram_mgr_func;
-
-	drm_mm_init(&mgr->mm, 0, man->size);
-	spin_lock_init(&mgr->lock);
-	INIT_LIST_HEAD(&mgr->reservations_pending);
-	INIT_LIST_HEAD(&mgr->reserved_pages);
-
-	/* Add the two VRAM-related sysfs files */
-	ret = sysfs_create_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes);
-	if (ret)
-		DRM_ERROR("Failed to register sysfs\n");
-
-	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, &mgr->manager);
-	ttm_resource_manager_set_used(man, true);
-	return 0;
-}
-
-/**
- * amdgpu_vram_mgr_fini - free and destroy VRAM manager
- *
- * @adev: amdgpu_device pointer
- *
- * Destroy and free the VRAM manager, returns -EBUSY if ranges are still
- * allocated inside it.
- */
-void amdgpu_vram_mgr_fini(struct amdgpu_device *adev)
-{
-	struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr;
-	struct ttm_resource_manager *man = &mgr->manager;
-	int ret;
-	struct amdgpu_vram_reservation *rsv, *temp;
-
-	ttm_resource_manager_set_used(man, false);
-
-	ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
-	if (ret)
-		return;
-
-	spin_lock(&mgr->lock);
-	list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, node)
-		kfree(rsv);
-
-	list_for_each_entry_safe(rsv, temp, &mgr->reserved_pages, node) {
-		drm_mm_remove_node(&rsv->mm_node);
-		kfree(rsv);
-	}
-	drm_mm_takedown(&mgr->mm);
-	spin_unlock(&mgr->lock);
-
-	sysfs_remove_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes);
-
-	ttm_resource_manager_cleanup(man);
-	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL);
-}
+const struct attribute_group amdgpu_vram_mgr_attr_group = {
+	.attrs = amdgpu_vram_mgr_attributes
+};
 
 /**
  * amdgpu_vram_mgr_vis_size - Calculate visible node size
@@ -266,23 +219,25 @@ static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev,
 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo)
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-	struct ttm_resource *mem = &bo->tbo.mem;
-	struct drm_mm_node *nodes = mem->mm_node;
-	unsigned pages = mem->num_pages;
+	struct ttm_resource *res = bo->tbo.resource;
+	unsigned pages = res->num_pages;
+	struct drm_mm_node *mm;
 	u64 usage;
 
 	if (amdgpu_gmc_vram_full_visible(&adev->gmc))
 		return amdgpu_bo_size(bo);
 
-	if (mem->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT)
+	if (res->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT)
 		return 0;
 
-	for (usage = 0; nodes && pages; pages -= nodes->size, nodes++)
-		usage += amdgpu_vram_mgr_vis_size(adev, nodes);
+	mm = &container_of(res, struct ttm_range_mgr_node, base)->mm_nodes[0];
+	for (usage = 0; pages; pages -= mm->size, mm++)
+		usage += amdgpu_vram_mgr_vis_size(adev, mm);
 
 	return usage;
 }
 
+/* Commit the reservation of VRAM pages */
 static void amdgpu_vram_mgr_do_reserve(struct ttm_resource_manager *man)
 {
 	struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
@@ -413,15 +368,15 @@ static void amdgpu_vram_mgr_virt_start(struct ttm_resource *mem,
 static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
 			       struct ttm_buffer_object *tbo,
 			       const struct ttm_place *place,
-			       struct ttm_resource *mem)
+			       struct ttm_resource **res)
 {
+	unsigned long lpfn, num_nodes, pages_per_node, pages_left, pages;
 	struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
 	struct amdgpu_device *adev = to_amdgpu_device(mgr);
+	uint64_t vis_usage = 0, mem_bytes, max_bytes;
+	struct ttm_range_mgr_node *node;
 	struct drm_mm *mm = &mgr->mm;
-	struct drm_mm_node *nodes;
 	enum drm_mm_insert_mode mode;
-	unsigned long lpfn, num_nodes, pages_per_node, pages_left;
-	uint64_t vis_usage = 0, mem_bytes, max_bytes;
 	unsigned i;
 	int r;
 
@@ -434,10 +389,10 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
 		max_bytes -= AMDGPU_VM_RESERVED_VRAM;
 
 	/* bail out quickly if there's likely not enough VRAM for this BO */
-	mem_bytes = (u64)mem->num_pages << PAGE_SHIFT;
+	mem_bytes = tbo->base.size;
 	if (atomic64_add_return(mem_bytes, &mgr->usage) > max_bytes) {
-		atomic64_sub(mem_bytes, &mgr->usage);
-		return -ENOSPC;
+		r = -ENOSPC;
+		goto error_sub;
 	}
 
 	if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
@@ -448,78 +403,78 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
 		pages_per_node = HPAGE_PMD_NR;
 #else
 		/* default to 2MB */
-		pages_per_node = (2UL << (20UL - PAGE_SHIFT));
+		pages_per_node = 2UL << (20UL - PAGE_SHIFT);
 #endif
-		pages_per_node = max((uint32_t)pages_per_node, mem->page_alignment);
-		num_nodes = DIV_ROUND_UP(mem->num_pages, pages_per_node);
+		pages_per_node = max_t(uint32_t, pages_per_node,
+				       tbo->page_alignment);
+		num_nodes = DIV_ROUND_UP_ULL(PFN_UP(mem_bytes), pages_per_node);
 	}
 
-	nodes = kvmalloc_array((uint32_t)num_nodes, sizeof(*nodes),
-			       GFP_KERNEL | __GFP_ZERO);
-	if (!nodes) {
-		atomic64_sub(mem_bytes, &mgr->usage);
-		return -ENOMEM;
+	node = kvmalloc(struct_size(node, mm_nodes, num_nodes),
+			GFP_KERNEL | __GFP_ZERO);
+	if (!node) {
+		r = -ENOMEM;
+		goto error_sub;
 	}
 
+	ttm_resource_init(tbo, place, &node->base);
+
 	mode = DRM_MM_INSERT_BEST;
 	if (place->flags & TTM_PL_FLAG_TOPDOWN)
 		mode = DRM_MM_INSERT_HIGH;
 
-	mem->start = 0;
-	pages_left = mem->num_pages;
+	pages_left = node->base.num_pages;
 
-	spin_lock(&mgr->lock);
-	for (i = 0; pages_left >= pages_per_node; ++i) {
-		unsigned long pages = rounddown_pow_of_two(pages_left);
-
-		/* Limit maximum size to 2GB due to SG table limitations */
-		pages = min(pages, (2UL << (30 - PAGE_SHIFT)));
-
-		r = drm_mm_insert_node_in_range(mm, &nodes[i], pages,
-						pages_per_node, 0,
-						place->fpfn, lpfn,
-						mode);
-		if (unlikely(r))
-			break;
-
-		vis_usage += amdgpu_vram_mgr_vis_size(adev, &nodes[i]);
-		amdgpu_vram_mgr_virt_start(mem, &nodes[i]);
-		pages_left -= pages;
-	}
+	/* Limit maximum size to 2GB due to SG table limitations */
+	pages = min(pages_left, 2UL << (30 - PAGE_SHIFT));
 
-	for (; pages_left; ++i) {
-		unsigned long pages = min(pages_left, pages_per_node);
-		uint32_t alignment = mem->page_alignment;
+	i = 0;
+	spin_lock(&mgr->lock);
+	while (pages_left) {
+		uint32_t alignment = tbo->page_alignment;
 
-		if (pages == pages_per_node)
+		if (pages >= pages_per_node)
 			alignment = pages_per_node;
 
-		r = drm_mm_insert_node_in_range(mm, &nodes[i],
-						pages, alignment, 0,
-						place->fpfn, lpfn,
-						mode);
-		if (unlikely(r))
-			goto error;
+		r = drm_mm_insert_node_in_range(mm, &node->mm_nodes[i], pages,
+						alignment, 0, place->fpfn,
+						lpfn, mode);
+		if (unlikely(r)) {
+			if (pages > pages_per_node) {
+				if (is_power_of_2(pages))
+					pages = pages / 2;
+				else
+					pages = rounddown_pow_of_two(pages);
+				continue;
+			}
+			goto error_free;
+		}
 
-		vis_usage += amdgpu_vram_mgr_vis_size(adev, &nodes[i]);
-		amdgpu_vram_mgr_virt_start(mem, &nodes[i]);
+		vis_usage += amdgpu_vram_mgr_vis_size(adev, &node->mm_nodes[i]);
+		amdgpu_vram_mgr_virt_start(&node->base, &node->mm_nodes[i]);
 		pages_left -= pages;
+		++i;
+
+		if (pages > pages_left)
+			pages = pages_left;
 	}
 	spin_unlock(&mgr->lock);
 
-	atomic64_add(vis_usage, &mgr->vis_usage);
-
-	mem->mm_node = nodes;
+	if (i == 1)
+		node->base.placement |= TTM_PL_FLAG_CONTIGUOUS;
 
+	atomic64_add(vis_usage, &mgr->vis_usage);
+	*res = &node->base;
 	return 0;
 
-error:
+error_free:
 	while (i--)
-		drm_mm_remove_node(&nodes[i]);
+		drm_mm_remove_node(&node->mm_nodes[i]);
 	spin_unlock(&mgr->lock);
-	atomic64_sub(mem->num_pages << PAGE_SHIFT, &mgr->usage);
+	kvfree(node);
 
-	kvfree(nodes);
+error_sub:
+	atomic64_sub(mem_bytes, &mgr->usage);
 	return r;
 }
 
@@ -532,24 +487,22 @@ error:
  * Free the allocated VRAM again.
  */
 static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man,
-				struct ttm_resource *mem)
+				struct ttm_resource *res)
 {
+	struct ttm_range_mgr_node *node = to_ttm_range_mgr_node(res);
 	struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
 	struct amdgpu_device *adev = to_amdgpu_device(mgr);
-	struct drm_mm_node *nodes = mem->mm_node;
 	uint64_t usage = 0, vis_usage = 0;
-	unsigned pages = mem->num_pages;
-
-	if (!mem->mm_node)
-		return;
+	unsigned i, pages;
 
 	spin_lock(&mgr->lock);
-	while (pages) {
-		pages -= nodes->size;
-		drm_mm_remove_node(nodes);
-		usage += nodes->size << PAGE_SHIFT;
-		vis_usage += amdgpu_vram_mgr_vis_size(adev, nodes);
-		++nodes;
+	for (i = 0, pages = res->num_pages; pages;
+	     pages -= node->mm_nodes[i].size, ++i) {
+		struct drm_mm_node *mm = &node->mm_nodes[i];
+
+		drm_mm_remove_node(mm);
+		usage += mm->size << PAGE_SHIFT;
+		vis_usage += amdgpu_vram_mgr_vis_size(adev, mm);
 	}
 	amdgpu_vram_mgr_do_reserve(man);
 	spin_unlock(&mgr->lock);
@@ -557,8 +510,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man,
 	atomic64_sub(usage, &mgr->usage);
 	atomic64_sub(vis_usage, &mgr->vis_usage);
 
-	kvfree(mem->mm_node);
-	mem->mm_node = NULL;
+	kvfree(node);
 }
 
 /**
@@ -575,7 +527,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man,
  * Allocate and fill a sg table from a VRAM allocation.
  */
 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
-			      struct ttm_resource *mem,
+			      struct ttm_resource *res,
 			      u64 offset, u64 length,
 			      struct device *dev,
 			      enum dma_data_direction dir,
@@ -591,7 +543,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
 		return -ENOMEM;
 
 	/* Determine the number of DRM_MM nodes to export */
-	amdgpu_res_first(mem, offset, length, &cursor);
+	amdgpu_res_first(res, offset, length, &cursor);
 	while (cursor.remaining) {
 		num_entries++;
 		amdgpu_res_next(&cursor, cursor.size);
@@ -611,7 +563,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
 	 * and the number of bytes from it. Access the following
 	 * DRM_MM node(s) if more buffer needs to exported
 	 */
-	amdgpu_res_first(mem, offset, length, &cursor);
+	amdgpu_res_first(res, offset, length, &cursor);
 	for_each_sgtable_sg((*sgt), sg, i) {
 		phys_addr_t phys = cursor.start + adev->gmc.aper_base;
 		size_t size = cursor.size;
@@ -727,3 +679,65 @@ static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = {
 	.free	= amdgpu_vram_mgr_del,
 	.debug	= amdgpu_vram_mgr_debug
 };
+
+/**
+ * amdgpu_vram_mgr_init - init VRAM manager and DRM MM
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Allocate and initialize the VRAM manager.
+ */
+int amdgpu_vram_mgr_init(struct amdgpu_device *adev)
+{
+	struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr;
+	struct ttm_resource_manager *man = &mgr->manager;
+
+	ttm_resource_manager_init(man, adev->gmc.real_vram_size >> PAGE_SHIFT);
+
+	man->func = &amdgpu_vram_mgr_func;
+
+	drm_mm_init(&mgr->mm, 0, man->size);
+	spin_lock_init(&mgr->lock);
+	INIT_LIST_HEAD(&mgr->reservations_pending);
+	INIT_LIST_HEAD(&mgr->reserved_pages);
+
+	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, &mgr->manager);
+	ttm_resource_manager_set_used(man, true);
+	return 0;
+}
+
+/**
+ * amdgpu_vram_mgr_fini - free and destroy VRAM manager
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Destroy and free the VRAM manager, returns -EBUSY if ranges are still
+ * allocated inside it.
+ */
+void amdgpu_vram_mgr_fini(struct amdgpu_device *adev)
+{
+	struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr;
+	struct ttm_resource_manager *man = &mgr->manager;
+	int ret;
+	struct amdgpu_vram_reservation *rsv, *temp;
+
+	ttm_resource_manager_set_used(man, false);
+
+	ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
+	if (ret)
+		return;
+
+	spin_lock(&mgr->lock);
+	list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, node)
+		kfree(rsv);
+
+	list_for_each_entry_safe(rsv, temp, &mgr->reserved_pages, node) {
+		drm_mm_remove_node(&rsv->mm_node);
+		kfree(rsv);
+	}
+	drm_mm_takedown(&mgr->mm);
+	spin_unlock(&mgr->lock);
+
+	ttm_resource_manager_cleanup(man);
+	ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
index 1a8f6d4baab2..a434c71fde8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -56,6 +56,8 @@
 
 #define AMD_SRIOV_MSG_RESERVE_UCODE		24
 
+#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
+
 enum amd_sriov_ucode_engine_id {
 	AMD_SRIOV_UCODE_ID_VCE = 0,
 	AMD_SRIOV_UCODE_ID_UVD,
@@ -98,10 +100,10 @@ union amd_sriov_msg_feature_flags {
 
 union amd_sriov_reg_access_flags {
 	struct {
-		uint32_t vf_reg_access_ih    : 1;
+		uint32_t vf_reg_access_ih 	 : 1;
 		uint32_t vf_reg_access_mmhub : 1;
-		uint32_t vf_reg_access_gc    : 1;
-		uint32_t reserved            : 29;
+		uint32_t vf_reg_access_gc 	 : 1;
+		uint32_t reserved	         : 29;
 	} flags;
 	uint32_t all;
 };
@@ -114,6 +116,37 @@ union amd_sriov_msg_os_info {
 	uint32_t      all;
 };
 
+struct amd_sriov_msg_uuid_info {
+	union {
+		struct {
+			uint32_t did	: 16;
+			uint32_t fcn	: 8;
+			uint32_t asic_7 : 8;
+		};
+		uint32_t time_low;
+	};
+
+	struct {
+		uint32_t time_mid  : 16;
+		uint32_t time_high : 12;
+		uint32_t version   : 4;
+	};
+
+	struct {
+		struct {
+			uint8_t clk_seq_hi : 6;
+			uint8_t variant    : 2;
+		};
+		union {
+			uint8_t clk_seq_low;
+			uint8_t asic_6;
+		};
+		uint16_t asic_4;
+	};
+
+	uint32_t asic_0;
+};
+
 struct amd_sriov_msg_pf2vf_info_header {
 	/* the total structure size in byte */
 	uint32_t size;
@@ -160,10 +193,19 @@ struct amd_sriov_msg_pf2vf_info {
 	/* identification in ROCm SMI */
 	uint64_t uuid;
 	uint32_t fcn_idx;
-	/* flags which indicate the register access method VF should use */
+	/* flags to indicate which register access method VF should use */
 	union amd_sriov_reg_access_flags reg_access_flags;
+	/* MM BW management */
+	struct {
+		uint32_t decode_max_dimension_pixels;
+		uint32_t decode_max_frame_pixels;
+		uint32_t encode_max_dimension_pixels;
+		uint32_t encode_max_frame_pixels;
+	} mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
+	/* UUID info */
+	struct amd_sriov_msg_uuid_info uuid_info;
 	/* reserved */
-	uint32_t reserved[256-27];
+	uint32_t reserved[256 - 47];
 };
 
 struct amd_sriov_msg_vf2pf_info_header {
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
index 2ac4988ea0ff..c12c2900732b 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
@@ -74,6 +74,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE);
 		athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE);
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
index 3dcb8b32f48b..6fa2229b7229 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -31,6 +31,7 @@
 
 #define ATOM_DEBUG
 
+#include "atomfirmware.h"
 #include "atom.h"
 #include "atom-names.h"
 #include "atom-bits.h"
@@ -1299,12 +1300,168 @@ static void atom_index_iio(struct atom_context *ctx, int base)
 	}
 }
 
+static void atom_get_vbios_name(struct atom_context *ctx)
+{
+	unsigned char *p_rom;
+	unsigned char str_num;
+	unsigned short off_to_vbios_str;
+	unsigned char *c_ptr;
+	int name_size;
+	int i;
+
+	const char *na = "--N/A--";
+	char *back;
+
+	p_rom = ctx->bios;
+
+	str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
+	if (str_num != 0) {
+		off_to_vbios_str =
+			*(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START);
+
+		c_ptr = (unsigned char *)(p_rom + off_to_vbios_str);
+	} else {
+		/* do not know where to find name */
+		memcpy(ctx->name, na, 7);
+		ctx->name[7] = 0;
+		return;
+	}
+
+	/*
+	 * skip the atombios strings, usually 4
+	 * 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type
+	 */
+	for (i = 0; i < str_num; i++) {
+		while (*c_ptr != 0)
+			c_ptr++;
+		c_ptr++;
+	}
+
+	/* skip the following 2 chars: 0x0D 0x0A */
+	c_ptr += 2;
+
+	name_size = strnlen(c_ptr, STRLEN_LONG - 1);
+	memcpy(ctx->name, c_ptr, name_size);
+	back = ctx->name + name_size;
+	while ((*--back) == ' ')
+		;
+	*(back + 1) = '\0';
+}
+
+static void atom_get_vbios_date(struct atom_context *ctx)
+{
+	unsigned char *p_rom;
+	unsigned char *date_in_rom;
+
+	p_rom = ctx->bios;
+
+	date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE;
+
+	ctx->date[0] = '2';
+	ctx->date[1] = '0';
+	ctx->date[2] = date_in_rom[6];
+	ctx->date[3] = date_in_rom[7];
+	ctx->date[4] = '/';
+	ctx->date[5] = date_in_rom[0];
+	ctx->date[6] = date_in_rom[1];
+	ctx->date[7] = '/';
+	ctx->date[8] = date_in_rom[3];
+	ctx->date[9] = date_in_rom[4];
+	ctx->date[10] = ' ';
+	ctx->date[11] = date_in_rom[9];
+	ctx->date[12] = date_in_rom[10];
+	ctx->date[13] = date_in_rom[11];
+	ctx->date[14] = date_in_rom[12];
+	ctx->date[15] = date_in_rom[13];
+	ctx->date[16] = '\0';
+}
+
+static unsigned char *atom_find_str_in_rom(struct atom_context *ctx, char *str, int start,
+					   int end, int maxlen)
+{
+	unsigned long str_off;
+	unsigned char *p_rom;
+	unsigned short str_len;
+
+	str_off = 0;
+	str_len = strnlen(str, maxlen);
+	p_rom = ctx->bios;
+
+	for (; start <= end; ++start) {
+		for (str_off = 0; str_off < str_len; ++str_off) {
+			if (str[str_off] != *(p_rom + start + str_off))
+				break;
+		}
+
+		if (str_off == str_len || str[str_off] == 0)
+			return p_rom + start;
+	}
+	return NULL;
+}
+
+static void atom_get_vbios_pn(struct atom_context *ctx)
+{
+	unsigned char *p_rom;
+	unsigned short off_to_vbios_str;
+	unsigned char *vbios_str;
+	int count;
+
+	off_to_vbios_str = 0;
+	p_rom = ctx->bios;
+
+	if (*(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS) != 0) {
+		off_to_vbios_str =
+			*(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START);
+
+		vbios_str = (unsigned char *)(p_rom + off_to_vbios_str);
+	} else {
+		vbios_str = p_rom + OFFSET_TO_VBIOS_PART_NUMBER;
+	}
+
+	if (*vbios_str == 0) {
+		vbios_str = atom_find_str_in_rom(ctx, BIOS_ATOM_PREFIX, 3, 1024, 64);
+		if (vbios_str == NULL)
+			vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1;
+	}
+	if (vbios_str != NULL && *vbios_str == 0)
+		vbios_str++;
+
+	if (vbios_str != NULL) {
+		count = 0;
+		while ((count < BIOS_STRING_LENGTH) && vbios_str[count] >= ' ' &&
+		       vbios_str[count] <= 'z') {
+			ctx->vbios_pn[count] = vbios_str[count];
+			count++;
+		}
+
+		ctx->vbios_pn[count] = 0;
+	}
+}
+
+static void atom_get_vbios_version(struct atom_context *ctx)
+{
+	unsigned char *vbios_ver;
+
+	/* find anchor ATOMBIOSBK-AMD */
+	vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64);
+	if (vbios_ver != NULL) {
+		/* skip ATOMBIOSBK-AMD VER */
+		vbios_ver += 18;
+		memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL);
+	} else {
+		ctx->vbios_ver_str[0] = '\0';
+	}
+}
+
 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
 {
 	int base;
 	struct atom_context *ctx =
 	    kzalloc(sizeof(struct atom_context), GFP_KERNEL);
 	char *str;
+	struct _ATOM_ROM_HEADER *atom_rom_header;
+	struct _ATOM_MASTER_DATA_TABLE *master_table;
+	struct _ATOM_FIRMWARE_INFO *atom_fw_info;
 	u16 idx;
 
 	if (!ctx)
@@ -1353,6 +1510,21 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
 		strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
 	}
 
+	atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base);
+	if (atom_rom_header->usMasterDataTableOffset != 0) {
+		master_table = (struct _ATOM_MASTER_DATA_TABLE *)
+				CSTR(atom_rom_header->usMasterDataTableOffset);
+		if (master_table->ListOfDataTables.FirmwareInfo != 0) {
+			atom_fw_info = (struct _ATOM_FIRMWARE_INFO *)
+					CSTR(master_table->ListOfDataTables.FirmwareInfo);
+			ctx->version = atom_fw_info->ulFirmwareRevision;
+		}
+	}
+
+	atom_get_vbios_name(ctx);
+	atom_get_vbios_pn(ctx);
+	atom_get_vbios_date(ctx);
+	atom_get_vbios_version(ctx);
 
 	return ctx;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h
index d279759cab47..0c1839824520 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -112,6 +112,10 @@ struct drm_device;
 #define ATOM_IO_SYSIO		2
 #define ATOM_IO_IIO		0x80
 
+#define STRLEN_NORMAL		32
+#define STRLEN_LONG		64
+#define STRLEN_VERYLONG		254
+
 struct card_info {
 	struct drm_device *dev;
 	void (* reg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
@@ -140,6 +144,12 @@ struct atom_context {
 	uint32_t *scratch;
 	int scratch_size_bytes;
 	char vbios_version[20];
+
+	uint8_t name[STRLEN_LONG];
+	uint8_t vbios_pn[STRLEN_LONG];
+	uint32_t version;
+	uint8_t vbios_ver_str[STRLEN_NORMAL];
+	uint8_t date[STRLEN_NORMAL];
 };
 
 extern int amdgpu_atom_debug;
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index a3ba9ca11e98..f327becb022f 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -188,6 +188,8 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
 {
 	amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
 	amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
+	amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev;
+
 	drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux);
 	amdgpu_connector->ddc_bus->has_aux = true;
 }
@@ -610,7 +612,7 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i
 	dp_info->tries = 0;
 	voltage = 0xff;
 	while (1) {
-		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
+		drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
 
 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
 						 dp_info->link_status) <= 0) {
@@ -675,7 +677,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i
 	dp_info->tries = 0;
 	channel_eq = false;
 	while (1) {
-		drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
+		drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
 
 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
 						 dp_info->link_status) <= 0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c b/drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c
new file mode 100644
index 000000000000..608a113ce354
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/beige_goby_reg_init.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "beige_goby_ip_offset.h"
+
+int beige_goby_reg_base_init(struct amdgpu_device *adev)
+{
+	/* HW has more IP blocks,  only initialize the block needed by driver */
+	uint32_t i;
+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));
+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+	}
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index d3745711d55f..df385ffc9768 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -309,8 +309,7 @@ static int cik_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 	amdgpu_irq_remove_domain(adev);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index c4bb8eed246d..c8ebd108548d 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -720,7 +720,7 @@ err0:
 }
 
 /**
- * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
+ * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
  *
  * @ib: indirect buffer to fill with commands
  * @pe: addr of the page entry
@@ -746,7 +746,7 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 }
 
 /**
- * cik_sdma_vm_write_pages - update PTEs by writing them manually
+ * cik_sdma_vm_write_pte - update PTEs by writing them manually
  *
  * @ib: indirect buffer to fill with commands
  * @pe: addr of the page entry
@@ -775,7 +775,7 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 }
 
 /**
- * cik_sdma_vm_set_pages - update the page tables using sDMA
+ * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
  *
  * @ib: indirect buffer to fill with commands
  * @pe: addr of the page entry
@@ -804,7 +804,7 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 }
 
 /**
- * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
+ * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
  *
  * @ring: amdgpu_ring structure holding ring information
  * @ib: indirect buffer to fill with padding
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 307c01301c87..b8c47e0cf37a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -301,8 +301,7 @@ static int cz_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 	amdgpu_irq_remove_domain(adev);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index dbcb09cf83e6..c7803dc2b2d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -456,7 +456,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
 }
 
 /**
- * cik_get_number_of_dram_channels - get the number of dram channels
+ * si_get_number_of_dram_channels - get the number of dram channels
  *
  * @adev: amdgpu_device pointer
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 5c11144da051..33324427b555 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -421,6 +421,11 @@ static int dce_virtual_sw_init(void *handle)
 static int dce_virtual_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i = 0;
+
+	for (i = 0; i < adev->mode_info.num_crtc; i++)
+		if (adev->mode_info.crtcs[i])
+			hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
 
 	kfree(adev->mode_info.bios_hardcoded_edid);
 
@@ -480,13 +485,6 @@ static int dce_virtual_hw_init(void *handle)
 
 static int dce_virtual_hw_fini(void *handle)
 {
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	int i = 0;
-
-	for (i = 0; i<adev->mode_info.num_crtc; i++)
-		if (adev->mode_info.crtcs[i])
-			hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 0d8459d63bac..14514a145c17 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -219,11 +219,11 @@ static void df_v3_6_query_hashes(struct amdgpu_device *adev)
 	adev->df.hash_status.hash_2m = false;
 	adev->df.hash_status.hash_1g = false;
 
-	if (adev->asic_type != CHIP_ARCTURUS)
-		return;
-
-	/* encoding for hash-enabled on Arcturus */
-	if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) {
+	/* encoding for hash-enabled on Arcturus and Aldebaran */
+	if ((adev->asic_type == CHIP_ARCTURUS &&
+	     adev->df.funcs->get_fb_channel_number(adev) == 0xe) ||
+	     (adev->asic_type == CHIP_ALDEBARAN &&
+	      adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) {
 		tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
 		adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
 						DF_CS_UMC_AON0_DfGlobalCtrl,
@@ -277,8 +277,14 @@ static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
 {
 	u32 tmp;
 
-	tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
-	tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+	if (adev->asic_type == CHIP_ALDEBARAN) {
+		tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);
+		tmp &=
+		ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+	} else {
+		tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
+		tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+	}
 	tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 
 	return tmp;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0597aeb5f0e8..2d56b60bc058 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -47,7 +47,7 @@
 #include "gfx_v10_0.h"
 #include "nbio_v2_3.h"
 
-/**
+/*
  * Navi10 has two graphic rings to share each graphic pipe.
  * 1. Primary ring
  * 2. Async ring
@@ -235,6 +235,20 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
+
+MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -1428,38 +1442,36 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
 };
 
-static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write)
-{
-	/* always programed by rlcg, only for gc */
-	if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
-	    offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
-	    offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
-	    offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
-	    offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
-	    offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
-		if (!amdgpu_sriov_reg_indirect_gc(adev))
-			*flag = GFX_RLCG_GC_WRITE_OLD;
-		else
-			*flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
+static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
+				 int write, u32 *rlcg_flag)
+{
+	switch (hwip) {
+	case GC_HWIP:
+		if (amdgpu_sriov_reg_indirect_gc(adev)) {
+			*rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
 
-		return true;
-	}
+			return true;
+		/* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
+		} else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
+			*rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
 
-	/* currently support gc read/write, mmhub write */
-	if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
-	    offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
-		if (amdgpu_sriov_reg_indirect_gc(adev))
-			*flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
-		else
-			return false;
-	} else {
-		if (amdgpu_sriov_reg_indirect_mmhub(adev))
-			*flag = GFX_RLCG_MMHUB_WRITE;
-		else
-			return false;
+			return true;
+		}
+
+		break;
+	case MMHUB_HWIP:
+		if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
+		    (acc_flags & AMDGPU_REGS_RLC) && write) {
+			*rlcg_flag = GFX_RLCG_MMHUB_WRITE;
+			return true;
+		}
+
+		break;
+	default:
+		DRM_DEBUG("Not program register by RLCG\n");
 	}
 
-	return true;
+	return false;
 }
 
 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
@@ -1526,36 +1538,34 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 	return ret;
 }
 
-static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag)
+static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
 {
-	uint32_t rlcg_flag;
+	u32 rlcg_flag;
 
-	if (amdgpu_sriov_fullaccess(adev) &&
-	    gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
+	if (!amdgpu_sriov_runtime(adev) &&
+	    gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
 		gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
-
 		return;
 	}
-	if (flag & AMDGPU_REGS_NO_KIQ)
+
+	if (acc_flags & AMDGPU_REGS_NO_KIQ)
 		WREG32_NO_KIQ(offset, value);
 	else
 		WREG32(offset, value);
 }
 
-static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag)
+static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
 {
-	uint32_t rlcg_flag;
+	u32 rlcg_flag;
 
-	if (amdgpu_sriov_fullaccess(adev) &&
-	    gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
+	if (!amdgpu_sriov_runtime(adev) &&
+	    gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
 		return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
 
-	if (flag & AMDGPU_REGS_NO_KIQ)
+	if (acc_flags & AMDGPU_REGS_NO_KIQ)
 		return RREG32_NO_KIQ(offset);
 	else
 		return RREG32(offset);
-
-	return 0;
 }
 
 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
@@ -3377,6 +3387,30 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
 };
 
+static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
+{
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
 {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
@@ -3416,6 +3450,41 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
 };
 
+static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
+};
+
 #define DEFAULT_SH_MEM_CONFIG \
 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3631,11 +3700,21 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 						golden_settings_gc_10_3_vangogh,
 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
 		break;
+	case CHIP_YELLOW_CARP:
+		soc15_program_register_sequence(adev,
+						golden_settings_gc_10_3_3,
+						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
+		break;
 	case CHIP_DIMGREY_CAVEFISH:
 		soc15_program_register_sequence(adev,
                                                 golden_settings_gc_10_3_4,
                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
 		break;
+	case CHIP_BEIGE_GOBY:
+		soc15_program_register_sequence(adev,
+						golden_settings_gc_10_3_5,
+						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
+		break;
 	default:
 		break;
 	}
@@ -3821,6 +3900,8 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.cp_fw_write_wait = true;
 		break;
 	default:
@@ -3897,7 +3978,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 {
 	const char *chip_name;
 	char fw_name[40];
-	char wks[10];
+	char *wks = "";
 	int err;
 	struct amdgpu_firmware_info *info = NULL;
 	const struct common_firmware_header *header = NULL;
@@ -3910,7 +3991,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 
 	DRM_DEBUG("\n");
 
-	memset(wks, 0, sizeof(wks));
 	switch (adev->asic_type) {
 	case CHIP_NAVI10:
 		chip_name = "navi10";
@@ -3919,7 +3999,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 		chip_name = "navi14";
 		if (!(adev->pdev->device == 0x7340 &&
 		      adev->pdev->revision != 0x00))
-			snprintf(wks, sizeof(wks), "_wks");
+			wks = "_wks";
 		break;
 	case CHIP_NAVI12:
 		chip_name = "navi12";
@@ -3936,6 +4016,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 	case CHIP_DIMGREY_CAVEFISH:
 		chip_name = "dimgrey_cavefish";
 		break;
+	case CHIP_BEIGE_GOBY:
+		chip_name = "beige_goby";
+		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
 	default:
 		BUG();
 	}
@@ -4504,6 +4590,8 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.config.max_hw_contexts = 8;
 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4628,6 +4716,8 @@ static int gfx_v10_0_sw_init(void *handle)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.me.num_me = 1;
 		adev->gfx.me.num_pipe_per_me = 1;
 		adev->gfx.me.num_queue_per_pipe = 1;
@@ -4860,7 +4950,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
-			if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+			if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
+				(adev->asic_type == CHIP_YELLOW_CARP)) &&
 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
 				continue;
 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -5190,10 +5281,10 @@ static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
 	uint32_t tmp;
 
 	/* enable Save Restore Machine */
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
+	tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
+	WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
 }
 
 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
@@ -6135,6 +6226,8 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -6270,6 +6363,8 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 		case CHIP_NAVY_FLOUNDER:
 		case CHIP_VANGOGH:
 		case CHIP_DIMGREY_CAVEFISH:
+		case CHIP_BEIGE_GOBY:
+		case CHIP_YELLOW_CARP:
 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
 			break;
 		default:
@@ -6282,6 +6377,8 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 		case CHIP_NAVY_FLOUNDER:
 		case CHIP_VANGOGH:
 		case CHIP_DIMGREY_CAVEFISH:
+		case CHIP_BEIGE_GOBY:
+		case CHIP_YELLOW_CARP:
 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6378,6 +6475,8 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
 		tmp &= 0xffffff00;
 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -7092,6 +7191,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
@@ -7105,6 +7205,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
 		}
 		break;
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		return true;
 	default:
 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
@@ -7126,6 +7227,9 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
 {
 	uint32_t data;
 
+	if (amdgpu_sriov_vf(adev))
+		return;
+
 	/* initialize cam_index to 0
 	 * index will auto-inc after each data writting */
 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
@@ -7135,6 +7239,8 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7344,7 +7450,7 @@ static int gfx_v10_0_hw_fini(void *handle)
 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
 
-	if (!adev->in_pci_err_recovery) {
+	if (!adev->no_hw_access) {
 #ifndef BRING_UP_DEBUG
 		if (amdgpu_async_gfx_ring) {
 			r = gfx_v10_0_kiq_disable_kgq(adev);
@@ -7450,6 +7556,8 @@ static int gfx_v10_0_soft_reset(void *handle)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 							GRBM_SOFT_RESET,
@@ -7503,6 +7611,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
 	mutex_lock(&adev->gfx.gpu_clock_mutex);
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
 			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
 		break;
@@ -7559,6 +7668,8 @@ static int gfx_v10_0_early_init(void *handle)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
 		break;
 	default:
@@ -7615,6 +7726,8 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 
 		/* wait for RLC_SAFE_MODE */
@@ -7649,6 +7762,8 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 		break;
 	default:
@@ -7891,12 +8006,12 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 {
 	u32 reg, data;
-
+	/* not for *_SOC15 */
 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
 	if (amdgpu_sriov_is_pp_one_vf(adev))
 		data = RREG32_NO_KIQ(reg);
 	else
-		data = RREG32(reg);
+		data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
 
 	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
@@ -7951,12 +8066,23 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
 	 * in refclk count. Note that RLC FW is modified to take 16 bits from
 	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
 	 *
-	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
-	 * as part of CGPG enablement starting point.
+	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
+	 * of CGPG enablement starting point.
+	 * Power/performance team will optimize it and might give a new value later.
 	 */
-	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
-		data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
-		WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+		switch (adev->asic_type) {
+		case CHIP_VANGOGH:
+			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+			break;
+		case CHIP_YELLOW_CARP:
+			data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+			break;
+		default:
+			break;
+		}
 	}
 }
 
@@ -8016,9 +8142,11 @@ static int gfx_v10_0_set_powergating_state(void *handle,
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		amdgpu_gfx_off_ctrl(adev, enable);
 		break;
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		gfx_v10_cntl_pg(adev, enable);
 		amdgpu_gfx_off_ctrl(adev, enable);
 		break;
@@ -8044,6 +8172,8 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		gfx_v10_0_update_gfx_clock_gating(adev,
 						 state == AMD_CG_STATE_GATE);
 		break;
@@ -8636,16 +8766,16 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
 
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
-		cp_int_cntl = RREG32(cp_int_cntl_reg);
+		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 					    TIME_STAMP_INT_ENABLE, 0);
-		WREG32(cp_int_cntl_reg, cp_int_cntl);
+		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 		break;
 	case AMDGPU_IRQ_STATE_ENABLE:
-		cp_int_cntl = RREG32(cp_int_cntl_reg);
+		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 					    TIME_STAMP_INT_ENABLE, 1);
-		WREG32(cp_int_cntl_reg, cp_int_cntl);
+		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
 		break;
 	default:
 		break;
@@ -8689,16 +8819,16 @@ static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev
 
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
-		mec_int_cntl = RREG32(mec_int_cntl_reg);
+		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
 					     TIME_STAMP_INT_ENABLE, 0);
-		WREG32(mec_int_cntl_reg, mec_int_cntl);
+		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
 		break;
 	case AMDGPU_IRQ_STATE_ENABLE:
-		mec_int_cntl = RREG32(mec_int_cntl_reg);
+		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
 					     TIME_STAMP_INT_ENABLE, 1);
-		WREG32(mec_int_cntl_reg, mec_int_cntl);
+		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
 		break;
 	default:
 		break;
@@ -8894,20 +9024,20 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
 					    GENERIC2_INT_ENABLE, 0);
 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 
-			tmp = RREG32(target);
+			tmp = RREG32_SOC15_IP(GC, target);
 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
 					    GENERIC2_INT_ENABLE, 0);
-			WREG32(target, tmp);
+			WREG32_SOC15_IP(GC, target, tmp);
 		} else {
 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
 					    GENERIC2_INT_ENABLE, 1);
 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 
-			tmp = RREG32(target);
+			tmp = RREG32_SOC15_IP(GC, target);
 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
 					    GENERIC2_INT_ENABLE, 1);
-			WREG32(target, tmp);
+			WREG32_SOC15_IP(GC, target, tmp);
 		}
 		break;
 	default:
@@ -9150,13 +9280,15 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_NAVI10:
 	case CHIP_NAVI14:
-	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
 		break;
 	case CHIP_NAVI12:
+	case CHIP_SIENNA_CICHLID:
 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
 		break;
 	default:
@@ -9239,7 +9371,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
-			if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+			if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
+				(adev->asic_type == CHIP_YELLOW_CARP)) &&
 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
 				continue;
 			mask = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index c35fdd2ef2d4..685212c3ddae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2116,7 +2116,7 @@ error_free_scratch:
 }
 
 /**
- * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
+ * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp
  *
  * @ring: amdgpu_ring structure holding ring information
  *
@@ -2242,7 +2242,7 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
  * IB stuff
  */
 /**
- * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
+ * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring
  *
  * @ring: amdgpu_ring structure holding ring information
  * @job: job to retrieve vmid from
@@ -3196,7 +3196,7 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
 }
 
 /**
- * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
+ * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP
  *
  * @ring: the ring to emit the commands to
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 516467e962b7..044076ec1d03 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -734,7 +734,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 	mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 };
 
-static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
+static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
 {
 	static void *scratch_reg0;
 	static void *scratch_reg1;
@@ -787,15 +787,17 @@ static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32
 
 }
 
-static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
+static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
+			       u32 v, u32 acc_flags, u32 hwip)
 {
-	if (amdgpu_sriov_fullaccess(adev)) {
-		gfx_v9_0_rlcg_rw(adev, offset, v, flag);
+	if ((acc_flags & AMDGPU_REGS_RLC) &&
+	    amdgpu_sriov_fullaccess(adev)) {
+		gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
 
 		return;
 	}
 
-	if (flag & AMDGPU_REGS_NO_KIQ)
+	if (acc_flags & AMDGPU_REGS_NO_KIQ)
 		WREG32_NO_KIQ(offset, v);
 	else
 		WREG32(offset, v);
@@ -3937,7 +3939,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
 {
 	u32 tmp;
 
-	if (adev->asic_type != CHIP_ARCTURUS)
+	if (adev->asic_type != CHIP_ARCTURUS &&
+	    adev->asic_type != CHIP_ALDEBARAN)
 		return;
 
 	tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
@@ -4559,8 +4562,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
 	if (!ring->sched.ready)
 		return 0;
 
-	if (adev->asic_type == CHIP_ARCTURUS ||
-	    adev->asic_type == CHIP_ALDEBARAN) {
+	if (adev->asic_type == CHIP_ARCTURUS) {
 		vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
 		vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
 		vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
@@ -4745,7 +4747,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
 	}
 
 	/* requires IBs so do in late init after IB pool is initialized */
-	r = gfx_v9_0_do_edc_gpr_workarounds(adev);
+	if (adev->asic_type == CHIP_ALDEBARAN)
+		r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
+	else
+		r = gfx_v9_0_do_edc_gpr_workarounds(adev);
+
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index a30c7c10cd9a..1769c4cba2ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -22,6 +22,7 @@
  */
 #include "amdgpu.h"
 #include "soc15.h"
+#include "soc15d.h"
 
 #include "gc/gc_9_4_2_offset.h"
 #include "gc/gc_9_4_2_sh_mask.h"
@@ -31,6 +32,11 @@
 #include "amdgpu_ras.h"
 #include "amdgpu_gfx.h"
 
+#define SE_ID_MAX 8
+#define CU_ID_MAX 16
+#define SIMD_ID_MAX 4
+#define WAVE_ID_MAX 10
+
 enum gfx_v9_4_2_utc_type {
 	VML2_MEM,
 	VML2_WALKER_MEM,
@@ -79,6 +85,634 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20),
 };
 
+/**
+ * This shader is used to clear VGPRS and LDS, and also write the input
+ * pattern into the write back buffer, which will be used by driver to
+ * check whether all SIMDs have been covered.
+*/
+static const u32 vgpr_init_compute_shader_aldebaran[] = {
+	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
+	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
+	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xd3d94000,
+	0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 0xd3d94003,
+	0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 0xd3d94006,
+	0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 0xd3d94009,
+	0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 0xd3d9400c,
+	0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 0xd3d9400f,
+	0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 0xd3d94012,
+	0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 0xd3d94015,
+	0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 0xd3d94018,
+	0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 0xd3d9401b,
+	0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 0xd3d9401e,
+	0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 0xd3d94021,
+	0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 0xd3d94024,
+	0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 0xd3d94027,
+	0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 0xd3d9402a,
+	0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 0xd3d9402d,
+	0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 0xd3d94030,
+	0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 0xd3d94033,
+	0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 0xd3d94036,
+	0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 0xd3d94039,
+	0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 0xd3d9403c,
+	0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 0xd3d9403f,
+	0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 0xd3d94042,
+	0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 0xd3d94045,
+	0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 0xd3d94048,
+	0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 0xd3d9404b,
+	0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 0xd3d9404e,
+	0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 0xd3d94051,
+	0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 0xd3d94054,
+	0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 0xd3d94057,
+	0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 0xd3d9405a,
+	0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 0xd3d9405d,
+	0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 0xd3d94060,
+	0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 0xd3d94063,
+	0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 0xd3d94066,
+	0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 0xd3d94069,
+	0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 0xd3d9406c,
+	0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 0xd3d9406f,
+	0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 0xd3d94072,
+	0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 0xd3d94075,
+	0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 0xd3d94078,
+	0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 0xd3d9407b,
+	0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 0xd3d9407e,
+	0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 0xd3d94081,
+	0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 0xd3d94084,
+	0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 0xd3d94087,
+	0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 0xd3d9408a,
+	0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 0xd3d9408d,
+	0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 0xd3d94090,
+	0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 0xd3d94093,
+	0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 0xd3d94096,
+	0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 0xd3d94099,
+	0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 0xd3d9409c,
+	0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 0xd3d9409f,
+	0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 0xd3d940a2,
+	0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 0xd3d940a5,
+	0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 0xd3d940a8,
+	0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 0xd3d940ab,
+	0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 0xd3d940ae,
+	0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 0xd3d940b1,
+	0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 0xd3d940b4,
+	0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 0xd3d940b7,
+	0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 0xd3d940ba,
+	0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 0xd3d940bd,
+	0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 0xd3d940c0,
+	0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 0xd3d940c3,
+	0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 0xd3d940c6,
+	0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 0xd3d940c9,
+	0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 0xd3d940cc,
+	0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 0xd3d940cf,
+	0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 0xd3d940d2,
+	0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 0xd3d940d5,
+	0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 0xd3d940d8,
+	0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 0xd3d940db,
+	0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 0xd3d940de,
+	0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 0xd3d940e1,
+	0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 0xd3d940e4,
+	0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 0xd3d940e7,
+	0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 0xd3d940ea,
+	0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 0xd3d940ed,
+	0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 0xd3d940f0,
+	0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 0xd3d940f3,
+	0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 0xd3d940f6,
+	0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 0xd3d940f9,
+	0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 0xd3d940fc,
+	0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 0xd3d940ff,
+	0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 0x7e000280,
+	0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 0x7e0c0280,
+	0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 0xd28c0001,
+	0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xbe8b0004, 0xb78b4000,
+	0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 0x00020201,
+	0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 0xbf84fff8,
+	0xbf810000,
+};
+
+const struct soc15_reg_entry vgpr_init_regs_aldebaran[] = {
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 4 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0xbf },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x400006 },  /* 64KB LDS */
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x3F }, /*  63 - accum-offset = 256 */
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
+};
+
+/**
+ * The below shaders are used to clear SGPRS, and also write the input
+ * pattern into the write back buffer. The first two dispatch should be
+ * scheduled simultaneously which make sure that all SGPRS could be
+ * allocated, so the dispatch 1 need check write back buffer before scheduled,
+ * make sure that waves of dispatch 0 are all dispacthed to all simds
+ * balanced. both dispatch 0 and dispatch 1 should be halted until all waves
+ * are dispatched, and then driver write a pattern to the shared memory to make
+ * all waves continue.
+*/
+static const u32 sgpr112_init_compute_shader_aldebaran[] = {
+	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
+	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
+	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
+	0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
+	0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
+	0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
+	0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
+	0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
+	0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
+	0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
+	0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
+	0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
+	0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
+	0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
+	0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080,
+	0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080,
+	0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080,
+	0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080,
+	0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080,
+	0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080,
+	0xbeda0080, 0xbedb0080, 0xbedc0080, 0xbedd0080, 0xbede0080, 0xbedf0080,
+	0xbee00080, 0xbee10080, 0xbee20080, 0xbee30080, 0xbee40080, 0xbee50080,
+	0xbf810000
+};
+
+const struct soc15_reg_entry sgpr112_init_regs_aldebaran[] = {
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 8 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x340 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
+};
+
+static const u32 sgpr96_init_compute_shader_aldebaran[] = {
+	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
+	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
+	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
+	0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
+	0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
+	0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
+	0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
+	0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
+	0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
+	0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
+	0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
+	0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
+	0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
+	0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
+	0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080,
+	0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080,
+	0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080,
+	0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080,
+	0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080,
+	0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080,
+	0xbf810000,
+};
+
+const struct soc15_reg_entry sgpr96_init_regs_aldebaran[] = {
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0xc },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x2c0 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
+};
+
+/**
+ * This shader is used to clear the uninitiated sgprs after the above
+ * two dispatches, because of hardware feature, dispath 0 couldn't clear
+ * top hole sgprs. Therefore need 4 waves per SIMD to cover these sgprs
+*/
+static const u32 sgpr64_init_compute_shader_aldebaran[] = {
+	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
+	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
+	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
+	0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
+	0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
+	0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
+	0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
+	0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
+	0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
+	0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
+	0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
+	0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
+	0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
+	0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
+	0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbf810000,
+};
+
+const struct soc15_reg_entry sgpr64_init_regs_aldebaran[] = {
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0x10 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x1c0 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
+	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
+};
+
+static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
+				 struct amdgpu_ring *ring,
+				 struct amdgpu_ib *ib,
+				 const u32 *shader_ptr, u32 shader_size,
+				 const struct soc15_reg_entry *init_regs, u32 regs_size,
+				 u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern,
+				 struct dma_fence **fence_ptr)
+{
+	int r, i;
+	uint32_t total_size, shader_offset;
+	u64 gpu_addr;
+
+	total_size = (regs_size * 3 + 4 + 5 + 5) * 4;
+	total_size = ALIGN(total_size, 256);
+	shader_offset = total_size;
+	total_size += ALIGN(shader_size, 256);
+
+	/* allocate an indirect buffer to put the commands in */
+	memset(ib, 0, sizeof(*ib));
+	r = amdgpu_ib_get(adev, NULL, total_size,
+					AMDGPU_IB_POOL_DIRECT, ib);
+	if (r) {
+		dev_err(adev->dev, "failed to get ib (%d).\n", r);
+		return r;
+	}
+
+	/* load the compute shaders */
+	for (i = 0; i < shader_size/sizeof(u32); i++)
+		ib->ptr[i + (shader_offset / 4)] = shader_ptr[i];
+
+	/* init the ib length to 0 */
+	ib->length_dw = 0;
+
+	/* write the register state for the compute dispatch */
+	for (i = 0; i < regs_size; i++) {
+		ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+		ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i])
+								- PACKET3_SET_SH_REG_START;
+		ib->ptr[ib->length_dw++] = init_regs[i].reg_value;
+	}
+
+	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
+	gpu_addr = (ib->gpu_addr + (u64)shader_offset) >> 8;
+	ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
+	ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_PGM_LO)
+							- PACKET3_SET_SH_REG_START;
+	ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
+	ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
+
+	/* write the wb buffer address */
+	ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3);
+	ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_USER_DATA_0)
+							- PACKET3_SET_SH_REG_START;
+	ib->ptr[ib->length_dw++] = lower_32_bits(wb_gpu_addr);
+	ib->ptr[ib->length_dw++] = upper_32_bits(wb_gpu_addr);
+	ib->ptr[ib->length_dw++] = pattern;
+
+	/* write dispatch packet */
+	ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+	ib->ptr[ib->length_dw++] = compute_dim_x; /* x */
+	ib->ptr[ib->length_dw++] = 1; /* y */
+	ib->ptr[ib->length_dw++] = 1; /* z */
+	ib->ptr[ib->length_dw++] =
+		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
+
+	/* shedule the ib on the ring */
+	r = amdgpu_ib_schedule(ring, 1, ib, NULL, fence_ptr);
+	if (r) {
+		dev_err(adev->dev, "ib submit failed (%d).\n", r);
+		amdgpu_ib_free(adev, ib, NULL);
+	}
+	return r;
+}
+
+static void gfx_v9_4_2_log_wave_assignment(struct amdgpu_device *adev, uint32_t *wb_ptr)
+{
+	uint32_t se, cu, simd, wave;
+	uint32_t offset = 0;
+	char *str;
+	int size;
+
+	str = kmalloc(256, GFP_KERNEL);
+	if (!str)
+		return;
+
+	dev_dbg(adev->dev, "wave assignment:\n");
+
+	for (se = 0; se < adev->gfx.config.max_shader_engines; se++) {
+		for (cu = 0; cu < CU_ID_MAX; cu++) {
+			memset(str, 0, 256);
+			size = sprintf(str, "SE[%02d]CU[%02d]: ", se, cu);
+			for (simd = 0; simd < SIMD_ID_MAX; simd++) {
+				size += sprintf(str + size, "[");
+				for (wave = 0; wave < WAVE_ID_MAX; wave++) {
+					size += sprintf(str + size, "%x", wb_ptr[offset]);
+					offset++;
+				}
+				size += sprintf(str + size, "]  ");
+			}
+			dev_dbg(adev->dev, "%s\n", str);
+		}
+	}
+
+	kfree(str);
+}
+
+static int gfx_v9_4_2_wait_for_waves_assigned(struct amdgpu_device *adev,
+					      uint32_t *wb_ptr, uint32_t mask,
+					      uint32_t pattern, uint32_t num_wave, bool wait)
+{
+	uint32_t se, cu, simd, wave;
+	uint32_t loop = 0;
+	uint32_t wave_cnt;
+	uint32_t offset;
+
+	do {
+		wave_cnt = 0;
+		offset = 0;
+
+		for (se = 0; se < adev->gfx.config.max_shader_engines; se++)
+			for (cu = 0; cu < CU_ID_MAX; cu++)
+				for (simd = 0; simd < SIMD_ID_MAX; simd++)
+					for (wave = 0; wave < WAVE_ID_MAX; wave++) {
+						if (((1 << wave) & mask) &&
+						    (wb_ptr[offset] == pattern))
+							wave_cnt++;
+
+						offset++;
+					}
+
+		if (wave_cnt == num_wave)
+			return 0;
+
+		mdelay(1);
+	} while (++loop < 2000 && wait);
+
+	dev_err(adev->dev, "actual wave num: %d, expected wave num: %d\n",
+		wave_cnt, num_wave);
+
+	gfx_v9_4_2_log_wave_assignment(adev, wb_ptr);
+
+	return -EBADSLT;
+}
+
+static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
+{
+	int r;
+	int wb_size = adev->gfx.config.max_shader_engines *
+			 CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
+	struct amdgpu_ib wb_ib;
+	struct amdgpu_ib disp_ibs[3];
+	struct dma_fence *fences[3];
+	u32 pattern[3] = { 0x1, 0x5, 0xa };
+
+	/* bail if the compute ring is not ready */
+	if (!adev->gfx.compute_ring[0].sched.ready ||
+		 !adev->gfx.compute_ring[1].sched.ready)
+		return 0;
+
+	/* allocate the write-back buffer from IB */
+	memset(&wb_ib, 0, sizeof(wb_ib));
+	r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t),
+			  AMDGPU_IB_POOL_DIRECT, &wb_ib);
+	if (r) {
+		dev_err(adev->dev, "failed to get ib (%d) for wb\n", r);
+		return r;
+	}
+	memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
+
+	r = gfx_v9_4_2_run_shader(adev,
+			&adev->gfx.compute_ring[0],
+			&disp_ibs[0],
+			sgpr112_init_compute_shader_aldebaran,
+			sizeof(sgpr112_init_compute_shader_aldebaran),
+			sgpr112_init_regs_aldebaran,
+			ARRAY_SIZE(sgpr112_init_regs_aldebaran),
+			adev->gfx.cu_info.number,
+			wb_ib.gpu_addr, pattern[0], &fences[0]);
+	if (r) {
+		dev_err(adev->dev, "failed to clear first 224 sgprs\n");
+		goto pro_end;
+	}
+
+	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
+			&wb_ib.ptr[1], 0b11,
+			pattern[0],
+			adev->gfx.cu_info.number * SIMD_ID_MAX * 2,
+			true);
+	if (r) {
+		dev_err(adev->dev, "wave coverage failed when clear first 224 sgprs\n");
+		wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
+		goto disp0_failed;
+	}
+
+	r = gfx_v9_4_2_run_shader(adev,
+			&adev->gfx.compute_ring[1],
+			&disp_ibs[1],
+			sgpr96_init_compute_shader_aldebaran,
+			sizeof(sgpr96_init_compute_shader_aldebaran),
+			sgpr96_init_regs_aldebaran,
+			ARRAY_SIZE(sgpr96_init_regs_aldebaran),
+			adev->gfx.cu_info.number * 2,
+			wb_ib.gpu_addr, pattern[1], &fences[1]);
+	if (r) {
+		dev_err(adev->dev, "failed to clear next 576 sgprs\n");
+		goto disp0_failed;
+	}
+
+	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
+			&wb_ib.ptr[1], 0b11111100,
+			pattern[1], adev->gfx.cu_info.number * SIMD_ID_MAX * 6,
+			true);
+	if (r) {
+		dev_err(adev->dev, "wave coverage failed when clear first 576 sgprs\n");
+		wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
+		goto disp1_failed;
+	}
+
+	wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
+
+	/* wait for the GPU to finish processing the IB */
+	r = dma_fence_wait(fences[0], false);
+	if (r) {
+		dev_err(adev->dev, "timeout to clear first 224 sgprs\n");
+		goto disp1_failed;
+	}
+
+	r = dma_fence_wait(fences[1], false);
+	if (r) {
+		dev_err(adev->dev, "timeout to clear first 576 sgprs\n");
+		goto disp1_failed;
+	}
+
+	memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
+	r = gfx_v9_4_2_run_shader(adev,
+			&adev->gfx.compute_ring[0],
+			&disp_ibs[2],
+			sgpr64_init_compute_shader_aldebaran,
+			sizeof(sgpr64_init_compute_shader_aldebaran),
+			sgpr64_init_regs_aldebaran,
+			ARRAY_SIZE(sgpr64_init_regs_aldebaran),
+			adev->gfx.cu_info.number,
+			wb_ib.gpu_addr, pattern[2], &fences[2]);
+	if (r) {
+		dev_err(adev->dev, "failed to clear first 256 sgprs\n");
+		goto disp1_failed;
+	}
+
+	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
+			&wb_ib.ptr[1], 0b1111,
+			pattern[2],
+			adev->gfx.cu_info.number * SIMD_ID_MAX * 4,
+			true);
+	if (r) {
+		dev_err(adev->dev, "wave coverage failed when clear first 256 sgprs\n");
+		wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
+		goto disp2_failed;
+	}
+
+	wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
+
+	r = dma_fence_wait(fences[2], false);
+	if (r) {
+		dev_err(adev->dev, "timeout to clear first 256 sgprs\n");
+		goto disp2_failed;
+	}
+
+disp2_failed:
+	amdgpu_ib_free(adev, &disp_ibs[2], NULL);
+	dma_fence_put(fences[2]);
+disp1_failed:
+	amdgpu_ib_free(adev, &disp_ibs[1], NULL);
+	dma_fence_put(fences[1]);
+disp0_failed:
+	amdgpu_ib_free(adev, &disp_ibs[0], NULL);
+	dma_fence_put(fences[0]);
+pro_end:
+	amdgpu_ib_free(adev, &wb_ib, NULL);
+
+	if (r)
+		dev_info(adev->dev, "Init SGPRS Failed\n");
+	else
+		dev_info(adev->dev, "Init SGPRS Successfully\n");
+
+	return r;
+}
+
+static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
+{
+	int r;
+	/* CU_ID: 0~15, SIMD_ID: 0~3, WAVE_ID: 0 ~ 9 */
+	int wb_size = adev->gfx.config.max_shader_engines *
+			 CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
+	struct amdgpu_ib wb_ib;
+	struct amdgpu_ib disp_ib;
+	struct dma_fence *fence;
+	u32 pattern = 0xa;
+
+	/* bail if the compute ring is not ready */
+	if (!adev->gfx.compute_ring[0].sched.ready)
+		return 0;
+
+	/* allocate the write-back buffer from IB */
+	memset(&wb_ib, 0, sizeof(wb_ib));
+	r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t),
+			  AMDGPU_IB_POOL_DIRECT, &wb_ib);
+	if (r) {
+		dev_err(adev->dev, "failed to get ib (%d) for wb.\n", r);
+		return r;
+	}
+	memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
+
+	r = gfx_v9_4_2_run_shader(adev,
+			&adev->gfx.compute_ring[0],
+			&disp_ib,
+			vgpr_init_compute_shader_aldebaran,
+			sizeof(vgpr_init_compute_shader_aldebaran),
+			vgpr_init_regs_aldebaran,
+			ARRAY_SIZE(vgpr_init_regs_aldebaran),
+			adev->gfx.cu_info.number,
+			wb_ib.gpu_addr, pattern, &fence);
+	if (r) {
+		dev_err(adev->dev, "failed to clear vgprs\n");
+		goto pro_end;
+	}
+
+	/* wait for the GPU to finish processing the IB */
+	r = dma_fence_wait(fence, false);
+	if (r) {
+		dev_err(adev->dev, "timeout to clear vgprs\n");
+		goto disp_failed;
+	}
+
+	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
+			&wb_ib.ptr[1], 0b1,
+			pattern,
+			adev->gfx.cu_info.number * SIMD_ID_MAX,
+			false);
+	if (r) {
+		dev_err(adev->dev, "failed to cover all simds when clearing vgprs\n");
+		goto disp_failed;
+	}
+
+disp_failed:
+	amdgpu_ib_free(adev, &disp_ib, NULL);
+	dma_fence_put(fence);
+pro_end:
+	amdgpu_ib_free(adev, &wb_ib, NULL);
+
+	if (r)
+		dev_info(adev->dev, "Init VGPRS Failed\n");
+	else
+		dev_info(adev->dev, "Init VGPRS Successfully\n");
+
+	return r;
+}
+
+int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+{
+	/* only support when RAS is enabled */
+	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
+		return 0;
+
+	gfx_v9_4_2_do_sgprs_init(adev);
+
+	gfx_v9_4_2_do_vgprs_init(adev);
+
+	return 0;
+}
+
 static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev);
 static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev);
 
@@ -148,11 +782,6 @@ void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)
 	tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
 	WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
 
-	WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
-	tmp = 0;
-	tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1);
-	WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp);
-
 	WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
 	tmp = 0;
 	tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);
@@ -808,8 +1437,9 @@ static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = {
 	  REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) },
 };
 
-static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs =
-	{ SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 };
+static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs = {
+	SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
+};
 
 static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev,
 					  const struct soc15_reg_entry *reg,
@@ -1006,8 +1636,8 @@ static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev,
 	return 0;
 }
 
-int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
-				   void *ras_error_status)
+static int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
+					    void *ras_error_status)
 {
 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 	uint32_t sec_count = 0, ded_count = 0;
@@ -1039,20 +1669,24 @@ static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev)
 static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev)
 {
 	uint32_t i, j;
+	uint32_t value;
 
 	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
 		for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
 		     j++) {
 			gfx_v9_4_2_select_se_sh(adev, i, 0, j);
-			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10);
+			value = RREG32(SOC15_REG_ENTRY_OFFSET(
+				gfx_v9_4_2_ea_err_status_regs));
+			value = REG_SET_FIELD(value, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);
+			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value);
 		}
 	}
 	gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 	mutex_unlock(&adev->grbm_idx_mutex);
 }
 
-void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
+static void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
 {
 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
 		return;
@@ -1061,7 +1695,7 @@ void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
 	gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL);
 }
 
-int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
+static int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
 {
 	struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
 	int ret;
@@ -1096,6 +1730,7 @@ static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
 			gfx_v9_4_2_select_se_sh(adev, i, 0, j);
 			reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
 				gfx_v9_4_2_ea_err_status_regs));
+
 			if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
 			    REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
 			    REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
@@ -1103,7 +1738,9 @@ static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
 						j, reg_value);
 			}
 			/* clear after read */
-			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10);
+			reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
+						  CLEAR_ERROR_STATUS, 0x1);
+			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), reg_value);
 		}
 	}
 
@@ -1134,7 +1771,7 @@ static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev)
 	}
 }
 
-void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
+static void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
 {
 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
 		return;
@@ -1144,7 +1781,7 @@ void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
 	gfx_v9_4_2_query_sq_timeout_status(adev);
 }
 
-void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
+static void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
 {
 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
 		return;
@@ -1154,7 +1791,7 @@ void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
 	gfx_v9_4_2_reset_sq_timeout_status(adev);
 }
 
-void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
+static void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
 {
 	uint32_t i;
 	uint32_t data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h
index 81c5833b6b9f..6db1f88509af 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h
@@ -29,6 +29,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
 void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
 				      uint32_t die_id);
 void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);
+int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev);
 
 extern const struct amdgpu_gfx_ras_funcs gfx_v9_4_2_ras_funcs;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 1e4678cb98f0..bda1542ef1dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -283,10 +283,14 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 				    PAGE_TABLE_BLOCK_SIZE,
 				    block_size);
-		/* Send no-retry XNACK on fault to suppress VM fault storm. */
+		/* Send no-retry XNACK on fault to suppress VM fault storm.
+		 * On Aldebaran, XNACK can be enabled in the SQ per-process.
+		 * Retry faults need to be enabled for that to work.
+		 */
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
-				    !adev->gmc.noretry);
+				    !adev->gmc.noretry ||
+				    adev->asic_type == CHIP_ALDEBARAN);
 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
 				    i * hub->ctx_distance, tmp);
 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
@@ -317,18 +321,6 @@ static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 
 static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
-	if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
-		/*
-		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-		 * VF copy registers so vbios post doesn't program them, for
-		 * SRIOV driver need to program them
-		 */
-		WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
-			     adev->gmc.vram_start >> 24);
-		WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
-			     adev->gmc.vram_end >> 24);
-	}
-
 	/* GART Enable. */
 	gfxhub_v1_0_init_gart_aperture_regs(adev);
 	gfxhub_v1_0_init_system_aperture_regs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 41807817de7d..1a374ec0514a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -31,6 +31,9 @@
 
 #include "soc15_common.h"
 
+#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP				0x16f8
+#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX	0
+
 static const char *gfxhub_client_ids[] = {
 	"CB/DB",
 	"Reserved",
@@ -531,6 +534,42 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
 	return 0;
 }
 
+static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
+{
+	int i;
+	u32 tmp = 0, disabled_sa = 0;
+	u32 efuse_setting, vbios_setting;
+
+	u32 max_sa_mask = amdgpu_gfx_create_bitmask(
+		adev->gfx.config.max_sh_per_se *
+		adev->gfx.config.max_shader_engines);
+
+	if (adev->asic_type == CHIP_YELLOW_CARP) {
+		/* Get SA disabled bitmap from eFuse setting */
+		efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
+		efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
+		efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
+
+		/* Get SA disabled bitmap from VBIOS setting */
+		vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
+		vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
+		vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
+
+		disabled_sa |= efuse_setting | vbios_setting;
+		/* Make sure not to report harvested SAs beyond the max SA count */
+		disabled_sa &= max_sa_mask;
+
+		for (i = 0; disabled_sa > 0; i++) {
+			if (disabled_sa & 1)
+				tmp |= 0x3 << (i * 2);
+			disabled_sa >>= 1;
+		}
+		disabled_sa = tmp;
+
+		WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
+	}
+}
+
 const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
 	.get_fb_location = gfxhub_v2_1_get_fb_location,
 	.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
@@ -540,4 +579,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
 	.set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,
 	.init = gfxhub_v2_1_init,
 	.get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
+	.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 498b28a35f5b..4523df2785d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -229,6 +229,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 	/* Use register 17 for GART */
 	const unsigned eng = 17;
 	unsigned int i;
+	unsigned char hub_ip = 0;
+
+	hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
+		   GC_HWIP : MMHUB_HWIP;
 
 	spin_lock(&adev->gmc.invalidate_lock);
 	/*
@@ -242,8 +246,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 	if (use_semaphore) {
 		for (i = 0; i < adev->usec_timeout; i++) {
 			/* a read return value of 1 means semaphore acuqire */
-			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
-					    hub->eng_distance * eng);
+			tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
+					 hub->eng_distance * eng, hub_ip);
+
 			if (tmp & 0x1)
 				break;
 			udelay(1);
@@ -253,7 +258,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 	}
 
-	WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
+	WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
+			  hub->eng_distance * eng,
+			  inv_req, hub_ip);
 
 	/*
 	 * Issue a dummy read to wait for the ACK register to be cleared
@@ -261,12 +268,14 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 	 */
 	if ((vmhub == AMDGPU_GFXHUB_0) &&
 	    (adev->asic_type < CHIP_SIENNA_CICHLID))
-		RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng);
+		RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
+				  hub->eng_distance * eng, hub_ip);
 
 	/* Wait for ACK with a delay.*/
 	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
-				    hub->eng_distance * eng);
+		tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
+				  hub->eng_distance * eng, hub_ip);
+
 		tmp &= 1 << vmid;
 		if (tmp)
 			break;
@@ -280,15 +289,15 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 		 * add semaphore release after invalidation,
 		 * write with 0 means semaphore release
 		 */
-		WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
-			      hub->eng_distance * eng, 0);
+		WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
+				  hub->eng_distance * eng, 0, hub_ip);
 
 	spin_unlock(&adev->gmc.invalidate_lock);
 
 	if (i < adev->usec_timeout)
 		return;
 
-	DRM_ERROR("Timeout waiting for VM flush ACK!\n");
+	DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
 }
 
 /**
@@ -666,6 +675,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		adev->mmhub.funcs = &mmhub_v2_3_funcs;
 		break;
 	default:
@@ -681,6 +691,8 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
 		break;
 	default:
@@ -796,6 +808,8 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 		case CHIP_NAVY_FLOUNDER:
 		case CHIP_VANGOGH:
 		case CHIP_DIMGREY_CAVEFISH:
+		case CHIP_BEIGE_GOBY:
+		case CHIP_YELLOW_CARP:
 		default:
 			adev->gmc.gart_size = 512ULL << 20;
 			break;
@@ -863,6 +877,8 @@ static int gmc_v10_0_sw_init(void *handle)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->num_vmhubs = 2;
 		/*
 		 * To fulfill 4-level page support,
@@ -920,6 +936,7 @@ static int gmc_v10_0_sw_init(void *handle)
 		return r;
 
 	amdgpu_gmc_get_vbios_allocations(adev);
+	amdgpu_gmc_get_reserved_allocation(adev);
 
 	/* Memory manager */
 	r = amdgpu_bo_init(adev);
@@ -944,7 +961,7 @@ static int gmc_v10_0_sw_init(void *handle)
 }
 
 /**
- * gmc_v8_0_gart_fini - vm fini callback
+ * gmc_v10_0_gart_fini - vm fini callback
  *
  * @adev: amdgpu_device pointer
  *
@@ -953,7 +970,6 @@ static int gmc_v10_0_sw_init(void *handle)
 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
 {
 	amdgpu_gart_table_vram_free(adev);
-	amdgpu_gart_fini(adev);
 }
 
 static int gmc_v10_0_sw_fini(void *handle)
@@ -978,6 +994,8 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		break;
 	default:
 		break;
@@ -1041,6 +1059,13 @@ static int gmc_v10_0_hw_init(void *handle)
 	/* The sequence of these two function calls matters.*/
 	gmc_v10_0_init_golden_registers(adev);
 
+	/*
+	 * harvestable groups in gc_utcl2 need to be programmed before any GFX block
+	 * register setup within GMC, or else system hang when harvesting SA.
+	 */
+	if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
+		adev->gfxhub.funcs->utcl2_harvest(adev);
+
 	r = gmc_v10_0_gart_enable(adev);
 	if (r)
 		return r;
@@ -1133,7 +1158,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
 		return r;
 
 	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
-	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
+	    adev->asic_type <= CHIP_YELLOW_CARP)
 		return athub_v2_1_set_clockgating(adev, state);
 	else
 		return athub_v2_0_set_clockgating(adev, state);
@@ -1146,7 +1171,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
 	adev->mmhub.funcs->get_clockgating(adev, flags);
 
 	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
-	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
+	    adev->asic_type <= CHIP_YELLOW_CARP)
 		athub_v2_1_get_clockgating(adev, flags);
 	else
 		athub_v2_0_get_clockgating(adev, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 405d6ad09022..0e81e03e9b49 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -898,7 +898,6 @@ static int gmc_v6_0_sw_fini(void *handle)
 	amdgpu_vm_manager_fini(adev);
 	amdgpu_gart_table_vram_free(adev);
 	amdgpu_bo_fini(adev);
-	amdgpu_gart_fini(adev);
 	release_firmware(adev->gmc.fw);
 	adev->gmc.fw = NULL;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 210ada2289ec..0a50fdaced7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -516,7 +516,7 @@ static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
 }
 
 /**
- * gmc_v8_0_set_fault_enable_default - update VM fault handling
+ * gmc_v7_0_set_fault_enable_default - update VM fault handling
  *
  * @adev: amdgpu_device pointer
  * @value: true redirects VM faults to the default page
@@ -1085,7 +1085,6 @@ static int gmc_v7_0_sw_fini(void *handle)
 	kfree(adev->gmc.vm_fault_info);
 	amdgpu_gart_table_vram_free(adev);
 	amdgpu_bo_fini(adev);
-	amdgpu_gart_fini(adev);
 	release_firmware(adev->gmc.fw);
 	adev->gmc.fw = NULL;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index e4f27b3f28fb..492ebed2915b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1201,7 +1201,6 @@ static int gmc_v8_0_sw_fini(void *handle)
 	kfree(adev->gmc.vm_fault_info);
 	amdgpu_gart_table_vram_free(adev);
 	amdgpu_bo_fini(adev);
-	amdgpu_gart_fini(adev);
 	release_firmware(adev->gmc.fw);
 	adev->gmc.fw = NULL;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 455bb91060d0..7eb70d69f760 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -53,6 +53,7 @@
 #include "mmhub_v1_7.h"
 #include "umc_v6_1.h"
 #include "umc_v6_0.h"
+#include "hdp_v4_0.h"
 
 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
 
@@ -1210,6 +1211,11 @@ static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 	adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
 }
 
+static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
+{
+	adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs;
+}
+
 static int gmc_v9_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1230,6 +1236,7 @@ static int gmc_v9_0_early_init(void *handle)
 	gmc_v9_0_set_mmhub_funcs(adev);
 	gmc_v9_0_set_mmhub_ras_funcs(adev);
 	gmc_v9_0_set_gfxhub_funcs(adev);
+	gmc_v9_0_set_hdp_ras_funcs(adev);
 
 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 	adev->gmc.shared_aperture_end =
@@ -1255,15 +1262,21 @@ static int gmc_v9_0_late_init(void *handle)
 	 * writes, while disables HBM ECC for vega10.
 	 */
 	if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
-		if (!(adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC))) {
+		if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
 			if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
 				adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
 		}
 	}
 
-	if (adev->mmhub.ras_funcs &&
-	    adev->mmhub.ras_funcs->reset_ras_error_count)
-		adev->mmhub.ras_funcs->reset_ras_error_count(adev);
+	if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
+		if (adev->mmhub.ras_funcs &&
+		    adev->mmhub.ras_funcs->reset_ras_error_count)
+			adev->mmhub.ras_funcs->reset_ras_error_count(adev);
+
+		if (adev->hdp.ras_funcs &&
+		    adev->hdp.ras_funcs->reset_ras_error_count)
+			adev->hdp.ras_funcs->reset_ras_error_count(adev);
+	}
 
 	r = amdgpu_gmc_ras_late_init(adev);
 	if (r)
@@ -1275,10 +1288,7 @@ static int gmc_v9_0_late_init(void *handle)
 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 					struct amdgpu_gmc *mc)
 {
-	u64 base = 0;
-
-	if (!amdgpu_sriov_vf(adev))
-		base = adev->mmhub.funcs->get_fb_location(adev);
+	u64 base = adev->mmhub.funcs->get_fb_location(adev);
 
 	/* add the xgmi offset of the physical node */
 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
@@ -1602,7 +1612,6 @@ static int gmc_v9_0_sw_fini(void *handle)
 	amdgpu_gart_table_vram_free(adev);
 	amdgpu_bo_unref(&adev->gmc.pdb0_bo);
 	amdgpu_bo_fini(adev);
-	amdgpu_gart_fini(adev);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index edbd35d293eb..74b90cc2bf48 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -59,12 +59,31 @@ static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
 			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 }
 
+static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
+					   void *ras_error_status)
+{
+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+
+	err_data->ue_count = 0;
+	err_data->ce_count = 0;
+
+	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
+		return;
+
+	/* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
+	err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
+};
+
 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
 {
 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
 		return;
-	/*read back hdp ras counter to reset it to 0 */
-	RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
+
+	if (adev->asic_type >= CHIP_ALDEBARAN)
+		WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
+	else
+		/*read back hdp ras counter to reset it to 0 */
+		RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
 }
 
 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
@@ -130,10 +149,16 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
 	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
 }
 
+const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs = {
+	.ras_late_init = amdgpu_hdp_ras_late_init,
+	.ras_fini = amdgpu_hdp_ras_fini,
+	.query_ras_error_count = hdp_v4_0_query_ras_error_count,
+	.reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
+};
+
 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
 	.flush_hdp = hdp_v4_0_flush_hdp,
 	.invalidate_hdp = hdp_v4_0_invalidate_hdp,
-	.reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
 	.update_clock_gating = hdp_v4_0_update_clock_gating,
 	.get_clock_gating_state = hdp_v4_0_get_clockgating_state,
 	.init_registers = hdp_v4_0_init_registers,
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h
index d1e6399e8c46..dc3a1b81dd62 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h
@@ -27,5 +27,6 @@
 #include "soc15_common.h"
 
 extern const struct amdgpu_hdp_funcs hdp_v4_0_funcs;
+extern const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index cc957471f31e..ddfe4eaeea05 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -300,8 +300,7 @@ static int iceland_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 	amdgpu_irq_remove_domain(adev);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index bd77794315bc..01c242c5abc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -49,10 +49,13 @@ static int jpeg_v3_0_set_powergating_state(void *handle,
 static int jpeg_v3_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
 
-	if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
-		return -ENOENT;
+	if (adev->asic_type != CHIP_YELLOW_CARP) {
+		u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
+
+		if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
+			return -ENOENT;
+	}
 
 	adev->jpeg.num_jpeg_inst = 1;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index 0103a5ab28e6..f80a14a1b82d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -111,6 +111,9 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
 	WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 	WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
+	if (amdgpu_sriov_vf(adev))
+		return;
+
 	/* Program the system aperture low logical page number. */
 	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
@@ -129,8 +132,6 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
 		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 	}
-	if (amdgpu_sriov_vf(adev))
-		return;
 
 	/* Set default page address. */
 	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
@@ -296,10 +297,12 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 				    PAGE_TABLE_BLOCK_SIZE,
 				    block_size);
-		/* Send no-retry XNACK on fault to suppress VM fault storm. */
+		/* On Aldebaran, XNACK can be enabled in the SQ per-process.
+		 * Retry faults need to be enabled for that to work.
+		 */
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
-				    !adev->gmc.noretry);
+				    1);
 		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
 				    i * hub->ctx_distance, tmp);
 		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
@@ -330,18 +333,6 @@ static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
 
 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
 {
-	if (amdgpu_sriov_vf(adev)) {
-		/*
-		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-		 * VF copy registers so vbios post doesn't program them, for
-		 * SRIOV driver need to program them
-		 */
-		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE,
-			     adev->gmc.vram_start >> 24);
-		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP,
-			     adev->gmc.vram_end >> 24);
-	}
-
 	/* GART Enable. */
 	mmhub_v1_7_init_gart_aperture_regs(adev);
 	mmhub_v1_7_init_system_aperture_regs(adev);
@@ -1313,12 +1304,31 @@ static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
 	}
 }
 
+static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev)
+{
+	int i;
+	uint32_t reg_value;
+
+	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
+		reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
+			mmhub_v1_7_ea_err_status_regs[i]));
+		reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,
+					  CLEAR_ERROR_STATUS, 0x01);
+		WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]),
+		       reg_value);
+	}
+}
+
 const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs = {
 	.ras_late_init = amdgpu_mmhub_ras_late_init,
 	.ras_fini = amdgpu_mmhub_ras_fini,
 	.query_ras_error_count = mmhub_v1_7_query_ras_error_count,
 	.reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
 	.query_ras_error_status = mmhub_v1_7_query_ras_error_status,
+	.reset_ras_error_status = mmhub_v1_7_reset_ras_error_status,
 };
 
 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index ac76081b91d5..f7e93bbc4e15 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -29,6 +29,7 @@
 #include "mmhub/mmhub_2_0_0_default.h"
 #include "navi10_enum.h"
 
+#include "gc/gc_10_1_0_offset.h"
 #include "soc15_common.h"
 
 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid                      0x064d
@@ -93,6 +94,30 @@ static const char *mmhub_client_ids_sienna_cichlid[][2] = {
 	[15][1] = "OSS",
 };
 
+static const char *mmhub_client_ids_beige_goby[][2] = {
+	[3][0] = "DCEDMC",
+	[4][0] = "DCEVGA",
+	[5][0] = "MP0",
+	[6][0] = "MP1",
+	[8][0] = "VMC",
+	[9][0] = "VCNU0",
+	[11][0] = "VCN0",
+	[14][0] = "HDP",
+	[15][0] = "OSS",
+	[0][1] = "DBGU0",
+	[1][1] = "DBGU1",
+	[2][1] = "DCEDWB",
+	[3][1] = "DCEDMC",
+	[4][1] = "DCEVGA",
+	[5][1] = "MP0",
+	[6][1] = "MP1",
+	[7][1] = "XDP",
+	[9][1] = "VCNU0",
+	[11][1] = "VCN0",
+	[14][1] = "HDP",
+	[15][1] = "OSS",
+};
+
 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
 					      uint32_t flush_type)
 {
@@ -139,6 +164,9 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
 	case CHIP_DIMGREY_CAVEFISH:
 		mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
 		break;
+	case CHIP_BEIGE_GOBY:
+		mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];
+		break;
 	default:
 		mmhub_cid = NULL;
 		break;
@@ -165,11 +193,11 @@ static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi
 {
 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 
-	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+	WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 			    hub->ctx_addr_distance * vmid,
 			    lower_32_bits(page_table_base));
 
-	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+	WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 			    hub->ctx_addr_distance * vmid,
 			    upper_32_bits(page_table_base));
 }
@@ -180,14 +208,14 @@ static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 
 	mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
 
-	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 		     (u32)(adev->gmc.gart_start >> 12));
-	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 		     (u32)(adev->gmc.gart_start >> 44));
 
-	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 		     (u32)(adev->gmc.gart_end >> 12));
-	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 		     (u32)(adev->gmc.gart_end >> 44));
 }
 
@@ -196,12 +224,12 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
 	uint64_t value;
 	uint32_t tmp;
 
-	/* Program the AGP BAR */
-	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
-	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
-
 	if (!amdgpu_sriov_vf(adev)) {
+		/* Program the AGP BAR */
+		WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+		WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+		WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+
 		/* Program the system aperture low logical page number. */
 		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 			     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
@@ -308,7 +336,7 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
-	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
+	WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
 }
 
 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
@@ -370,16 +398,16 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 				    !adev->gmc.noretry);
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
 				    i * hub->ctx_distance, tmp);
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 				    i * hub->ctx_addr_distance, 0);
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 				    i * hub->ctx_addr_distance, 0);
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 				    i * hub->ctx_addr_distance,
 				    lower_32_bits(adev->vm_manager.max_pfn - 1));
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 				    i * hub->ctx_addr_distance,
 				    upper_32_bits(adev->vm_manager.max_pfn - 1));
 	}
@@ -391,9 +419,9 @@ static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 	unsigned i;
 
 	for (i = 0; i < 18; ++i) {
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 				    i * hub->eng_addr_distance, 0xffffffff);
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 				    i * hub->eng_addr_distance, 0x1f);
 	}
 }
@@ -422,7 +450,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
 
 	/* Disable all tables */
 	for (i = 0; i < AMDGPU_NUM_VMID; i++)
-		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
+		WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
 				    i * hub->ctx_distance, 0);
 
 	/* Setup TLB control */
@@ -544,6 +572,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 		break;
@@ -578,6 +607,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		if (def != data)
 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 		if (def1 != data1)
@@ -601,6 +631,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 		break;
 	default:
@@ -618,6 +649,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
 		case CHIP_SIENNA_CICHLID:
 		case CHIP_NAVY_FLOUNDER:
 		case CHIP_DIMGREY_CAVEFISH:
+		case CHIP_BEIGE_GOBY:
 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 			break;
 		default:
@@ -640,6 +672,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		mmhub_v2_0_update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE);
 		mmhub_v2_0_update_medium_grain_light_sleep(adev,
@@ -663,6 +696,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 		data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index a9899335d0b1..88e457a150e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -92,6 +92,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
 		status);
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
 		break;
 	default:
@@ -569,9 +570,9 @@ static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev,
 		return 0;
 
 	mmhub_v2_3_update_medium_grain_clock_gating(adev,
-			state == AMD_CG_STATE_GATE ? true : false);
+				state == AMD_CG_STATE_GATE);
 	mmhub_v2_3_update_medium_grain_light_sleep(adev,
-			state == AMD_CG_STATE_GATE ? true : false);
+				state == AMD_CG_STATE_GATE);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 47c8dd9d1c78..c4ef822bbe8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -436,7 +436,7 @@ static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 }
 
 /**
- * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
+ * mmhub_v9_4_set_fault_enable_default - update GART/VM fault handling
  *
  * @adev: amdgpu_device pointer
  * @value: true redirects VM faults to the default page
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..530011622801 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
 				   RB_USED_INT_THRESHOLD, threshold);
 
-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
+			return;
+	} else {
+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+	}
+
 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
 				   RB_USED_INT_THRESHOLD, threshold);
-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
+			return;
+	} else {
+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+	}
+
 	WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
 }
 
@@ -151,7 +163,13 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
 	/* enable_intr field is only valid in ring0 */
 	if (ih == &adev->irq.ih)
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
-	WREG32(ih_regs->ih_rb_cntl, tmp);
+
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
+			return -ETIMEDOUT;
+	} else {
+		WREG32(ih_regs->ih_rb_cntl, tmp);
+	}
 
 	if (enable) {
 		ih->enabled = true;
@@ -261,7 +279,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev,
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
 	}
-	WREG32(ih_regs->ih_rb_cntl, tmp);
+
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+			return -ETIMEDOUT;
+		}
+	} else {
+		WREG32(ih_regs->ih_rb_cntl, tmp);
+	}
 
 	if (ih == &adev->irq.ih) {
 		/* set the ih ring 0 writeback address whether it's enabled or not */
@@ -311,6 +337,8 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
 			case CHIP_NAVY_FLOUNDER:
 			case CHIP_VANGOGH:
 			case CHIP_DIMGREY_CAVEFISH:
+			case CHIP_BEIGE_GOBY:
+			case CHIP_YELLOW_CARP:
 				ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
 				ih_chicken = REG_SET_FIELD(ih_chicken,
 						IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
@@ -569,11 +597,7 @@ static int navi10_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index 598ce0e93627..8f2a315e7c73 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -28,6 +28,25 @@
 #include "nbio/nbio_7_2_0_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
 
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC				0x0015
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX		2
+#define regBIF_BX0_BIF_FB_EN_YC								0x0100
+#define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX					2
+#define regBIF1_PCIE_MST_CTRL_3								0x4601c6
+#define regBIF1_PCIE_MST_CTRL_3_BASE_IDX					5
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \
+			0x1b
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \
+			0x1c
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \
+			0x08000000L
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \
+			0x30000000L
+#define regBIF1_PCIE_TX_POWER_CTRL_1						0x460187
+#define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX				5
+#define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK		0x00000001L
+#define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK	0x00000008L
+
 static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
 {
 	WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -38,7 +57,12 @@ static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
 
 static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 {
-	u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+	u32 tmp;
+
+	if (adev->asic_type == CHIP_YELLOW_CARP)
+		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
+	else
+		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
 
 	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
 	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -49,11 +73,19 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
 	if (enable)
-		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
-			     BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
-			     BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+		if (adev->asic_type == CHIP_YELLOW_CARP)
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
+				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+		else
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
+				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
 	else
-		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+		if (adev->asic_type == CHIP_YELLOW_CARP)
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
+		else
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
 }
 
 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
@@ -92,13 +124,13 @@ static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do
 
 	if (use_doorbell) {
 		doorbell_range = REG_SET_FIELD(doorbell_range,
-					       GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
-					       doorbell_index);
+							GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
+							doorbell_index);
 		doorbell_range = REG_SET_FIELD(doorbell_range,
-					       GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
+							GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
 	} else {
 		doorbell_range = REG_SET_FIELD(doorbell_range,
-					       GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
+							GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
 	}
 
 	WREG32_PCIE_PORT(reg, doorbell_range);
@@ -123,22 +155,22 @@ static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *ad
 
 	if (enable) {
 		tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-				    DOORBELL_SELFRING_GPA_APER_EN, 1) |
-		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-				    DOORBELL_SELFRING_GPA_APER_MODE, 1) |
-		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-				    DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+				DOORBELL_SELFRING_GPA_APER_EN, 1) |
+			REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+			REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 
 		WREG32_SOC15(NBIO, 0,
-			     regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
-			     lower_32_bits(adev->doorbell.base));
+			regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
+			lower_32_bits(adev->doorbell.base));
 		WREG32_SOC15(NBIO, 0,
-			     regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
-			     upper_32_bits(adev->doorbell.base));
+			regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+			upper_32_bits(adev->doorbell.base));
 	}
 
 	WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-		     tmp);
+		tmp);
 }
 
 
@@ -218,19 +250,42 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 {
 	uint32_t def, data;
 
-	def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
-		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
-			 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
-			 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+	if (adev->asic_type == CHIP_YELLOW_CARP) {
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+			data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
+		else
+			data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
+
+		data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));
+		def = data;
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+			data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
+				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
+		else
+			data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
+				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
+				data);
 	} else {
-		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
-			  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
-			  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+			data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+				 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+				 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+		else
+			data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+				  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+				  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
 	}
-
-	if (def != data)
-		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
 }
 
 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
@@ -297,14 +352,25 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
 {
 	uint32_t def, data;
-
-	def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
-	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
-	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
-
-	if (def != data)
-		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),
-				 data);
+	if (adev->asic_type == CHIP_YELLOW_CARP) {
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
+		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
+	} else {
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
+		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
+	}
 }
 
 const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index d290ca0b06da..455d0425787c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -218,14 +218,118 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode =
 	.codec_array = sc_video_codecs_decode_array,
 };
 
+/* SRIOV Sienna Cichlid, not const since data is controlled by host */
+static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
+{
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
+		.max_width = 4096,
+		.max_height = 2304,
+		.max_pixels_per_frame = 4096 * 2304,
+		.max_level = 0,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
+		.max_width = 4096,
+		.max_height = 2304,
+		.max_pixels_per_frame = 4096 * 2304,
+		.max_level = 0,
+	},
+};
+
+static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
+{
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
+		.max_width = 4096,
+		.max_height = 4096,
+		.max_pixels_per_frame = 4096 * 4096,
+		.max_level = 3,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
+		.max_width = 4096,
+		.max_height = 4096,
+		.max_pixels_per_frame = 4096 * 4096,
+		.max_level = 5,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
+		.max_width = 4096,
+		.max_height = 4096,
+		.max_pixels_per_frame = 4096 * 4096,
+		.max_level = 52,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
+		.max_width = 4096,
+		.max_height = 4096,
+		.max_pixels_per_frame = 4096 * 4096,
+		.max_level = 4,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
+		.max_width = 8192,
+		.max_height = 4352,
+		.max_pixels_per_frame = 8192 * 4352,
+		.max_level = 186,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
+		.max_width = 4096,
+		.max_height = 4096,
+		.max_pixels_per_frame = 4096 * 4096,
+		.max_level = 0,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
+		.max_width = 8192,
+		.max_height = 4352,
+		.max_pixels_per_frame = 8192 * 4352,
+		.max_level = 0,
+	},
+	{
+		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
+		.max_width = 8192,
+		.max_height = 4352,
+		.max_pixels_per_frame = 8192 * 4352,
+		.max_level = 0,
+	},
+};
+
+static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
+{
+	.codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
+	.codec_array = sriov_sc_video_codecs_encode_array,
+};
+
+static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
+{
+	.codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
+	.codec_array = sriov_sc_video_codecs_decode_array,
+};
+
 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 				 const struct amdgpu_video_codecs **codecs)
 {
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
+		if (amdgpu_sriov_vf(adev)) {
+			if (encode)
+				*codecs = &sriov_sc_video_codecs_encode;
+			else
+				*codecs = &sriov_sc_video_codecs_decode;
+		} else {
+			if (encode)
+				*codecs = &nv_video_codecs_encode;
+			else
+				*codecs = &sc_video_codecs_decode;
+		}
+		return 0;
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		if (encode)
 			*codecs = &nv_video_codecs_encode;
 		else
@@ -363,7 +467,7 @@ void nv_grbm_select(struct amdgpu_device *adev,
 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
+	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 }
 
 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
@@ -530,10 +634,12 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		return AMD_RESET_METHOD_MODE2;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		return AMD_RESET_METHOD_MODE1;
 	default:
 		if (amdgpu_dpm_is_baco_supported(adev))
@@ -598,7 +704,7 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 
 static void nv_program_aspm(struct amdgpu_device *adev)
 {
-	if (amdgpu_aspm != 1)
+	if (!amdgpu_aspm)
 		return;
 
 	if (!(adev->flags & AMD_IS_APU) &&
@@ -675,6 +781,12 @@ legacy_init:
 	case CHIP_DIMGREY_CAVEFISH:
 		dimgrey_cavefish_reg_base_init(adev);
 		break;
+	case CHIP_BEIGE_GOBY:
+		beige_goby_reg_base_init(adev);
+		break;
+	case CHIP_YELLOW_CARP:
+		yellow_carp_reg_base_init(adev);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -742,8 +854,13 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 	case CHIP_NAVI12:
 		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
-		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
-		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		if (!amdgpu_sriov_vf(adev)) {
+			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		} else {
+			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+		}
 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
@@ -764,9 +881,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 	case CHIP_SIENNA_CICHLID:
 		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
-		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
-		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
-			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		if (!amdgpu_sriov_vf(adev)) {
+			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		} else {
+			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+		}
 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 		    is_support_sw_smu(adev))
 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
@@ -845,6 +968,48 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 		break;
+	case CHIP_BEIGE_GOBY:
+		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+		    is_support_sw_smu(adev))
+			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+		else if (amdgpu_device_has_dc_support(adev))
+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
+		    is_support_sw_smu(adev))
+			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+		break;
+	case CHIP_YELLOW_CARP:
+		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+			amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+		else if (amdgpu_device_has_dc_support(adev))
+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
+		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -1068,6 +1233,7 @@ static int nv_common_early_init(void *handle)
 	case CHIP_SIENNA_CICHLID:
 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
 			AMD_CG_SUPPORT_GFX_3D_CGCG |
 			AMD_CG_SUPPORT_MC_MGCG |
 			AMD_CG_SUPPORT_VCN_MGCG |
@@ -1091,6 +1257,7 @@ static int nv_common_early_init(void *handle)
 	case CHIP_NAVY_FLOUNDER:
 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
 			AMD_CG_SUPPORT_GFX_3D_CGCG |
 			AMD_CG_SUPPORT_VCN_MGCG |
 			AMD_CG_SUPPORT_JPEG_MGCG |
@@ -1121,6 +1288,8 @@ static int nv_common_early_init(void *handle)
 			AMD_CG_SUPPORT_MC_LS |
 			AMD_CG_SUPPORT_GFX_FGCG |
 			AMD_CG_SUPPORT_VCN_MGCG |
+			AMD_CG_SUPPORT_SDMA_MGCG |
+			AMD_CG_SUPPORT_SDMA_LS |
 			AMD_CG_SUPPORT_JPEG_MGCG;
 		adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 			AMD_PG_SUPPORT_VCN |
@@ -1132,6 +1301,7 @@ static int nv_common_early_init(void *handle)
 	case CHIP_DIMGREY_CAVEFISH:
 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
 			AMD_CG_SUPPORT_GFX_3D_CGCG |
 			AMD_CG_SUPPORT_VCN_MGCG |
 			AMD_CG_SUPPORT_JPEG_MGCG |
@@ -1147,6 +1317,49 @@ static int nv_common_early_init(void *handle)
 			AMD_PG_SUPPORT_MMHUB;
 		adev->external_rev_id = adev->rev_id + 0x3c;
 		break;
+	case CHIP_BEIGE_GOBY:
+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_GFX_3D_CGCG |
+			AMD_CG_SUPPORT_MC_MGCG |
+			AMD_CG_SUPPORT_MC_LS |
+			AMD_CG_SUPPORT_HDP_MGCG |
+			AMD_CG_SUPPORT_HDP_LS |
+			AMD_CG_SUPPORT_IH_CG |
+			AMD_CG_SUPPORT_VCN_MGCG;
+		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+			AMD_PG_SUPPORT_VCN_DPG |
+			AMD_PG_SUPPORT_ATHUB |
+			AMD_PG_SUPPORT_MMHUB;
+		adev->external_rev_id = adev->rev_id + 0x46;
+		break;
+	case CHIP_YELLOW_CARP:
+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+			AMD_CG_SUPPORT_GFX_MGLS |
+			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_GFX_3D_CGCG |
+			AMD_CG_SUPPORT_GFX_3D_CGLS |
+			AMD_CG_SUPPORT_GFX_RLC_LS |
+			AMD_CG_SUPPORT_GFX_CP_LS |
+			AMD_CG_SUPPORT_GFX_FGCG |
+			AMD_CG_SUPPORT_MC_MGCG |
+			AMD_CG_SUPPORT_MC_LS |
+			AMD_CG_SUPPORT_SDMA_LS |
+			AMD_CG_SUPPORT_HDP_MGCG |
+			AMD_CG_SUPPORT_HDP_LS |
+			AMD_CG_SUPPORT_ATHUB_MGCG |
+			AMD_CG_SUPPORT_ATHUB_LS |
+			AMD_CG_SUPPORT_IH_CG |
+			AMD_CG_SUPPORT_VCN_MGCG |
+			AMD_CG_SUPPORT_JPEG_MGCG;
+		adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
+			AMD_PG_SUPPORT_VCN |
+			AMD_PG_SUPPORT_VCN_DPG |
+			AMD_PG_SUPPORT_JPEG;
+		adev->external_rev_id = adev->rev_id + 0x01;
+		break;
 	default:
 		/* FIXME: not supported yet */
 		return -EINVAL;
@@ -1169,8 +1382,12 @@ static int nv_common_late_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (amdgpu_sriov_vf(adev))
+	if (amdgpu_sriov_vf(adev)) {
 		xgpu_nv_mailbox_get_irq(adev);
+		amdgpu_virt_update_sriov_video_codec(adev,
+				sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
+				sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
+	}
 
 	return 0;
 }
@@ -1266,6 +1483,7 @@ static int nv_common_set_clockgating_state(void *handle,
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE);
 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index 515d67bf249f..eb9aff1e7253 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -36,4 +36,7 @@ int navi12_reg_base_init(struct amdgpu_device *adev);
 int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
 void vangogh_reg_base_init(struct amdgpu_device *adev);
 int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev);
+int beige_goby_reg_base_init(struct amdgpu_device *adev);
+int yellow_carp_reg_base_init(struct amdgpu_device *adev);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index 96064c343163..dd0dce254901 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -97,7 +97,6 @@ enum psp_gfx_cmd_id
     GFX_CMD_ID_SETUP_VMR          = 0x00000009,   /* setup VMR region */
     GFX_CMD_ID_DESTROY_VMR        = 0x0000000A,   /* destroy VMR region */
     GFX_CMD_ID_PROG_REG           = 0x0000000B,   /* program regs */
-    GFX_CMD_ID_CLEAR_VF_FW        = 0x0000000D,   /* Clear VF FW, to be used on VF shutdown. */
     GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F,   /* Query GPUVA of the Fw Attestation DB */
     /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
     GFX_CMD_ID_LOAD_TOC           = 0x00000020,   /* Load TOC and obtain TMR size */
@@ -333,11 +332,16 @@ struct psp_gfx_uresp_fwar_db_info
     uint32_t fwar_db_addr_hi;
 };
 
+/* Command-specific response for boot config. */
+struct psp_gfx_uresp_bootcfg {
+	uint32_t boot_cfg;	/* boot config data */
+};
+
 /* Union of command-specific responses for GPCOM ring. */
-union psp_gfx_uresp
-{
-    struct psp_gfx_uresp_reserved reserved;
-    struct psp_gfx_uresp_fwar_db_info fwar_db_info;
+union psp_gfx_uresp {
+	struct psp_gfx_uresp_reserved		reserved;
+	struct psp_gfx_uresp_bootcfg		boot_cfg;
+	struct psp_gfx_uresp_fwar_db_info	fwar_db_info;
 };
 
 /* Structure of GFX Response buffer.
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 02bba1f3c42e..bc133db2d538 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -23,6 +23,7 @@
 #include <linux/firmware.h>
 #include <linux/module.h>
 #include <linux/vmalloc.h>
+#include <drm/drm_drv.h>
 
 #include "amdgpu.h"
 #include "amdgpu_psp.h"
@@ -63,6 +64,8 @@ MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS		0x3010024
@@ -115,6 +118,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 	case CHIP_DIMGREY_CAVEFISH:
 		chip_name = "dimgrey_cavefish";
 		break;
+	case CHIP_BEIGE_GOBY:
+		chip_name = "beige_goby";
+		break;
 	default:
 		BUG();
 	}
@@ -200,6 +206,14 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 		if (err)
 			return err;
 		break;
+	case CHIP_BEIGE_GOBY:
+		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_ta_microcode(psp, chip_name);
+		if (err)
+			return err;
+		break;
 	case CHIP_VANGOGH:
 		err = psp_init_asd_microcode(psp, chip_name);
 		if (err)
@@ -269,10 +283,8 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy PSP KDB binary to memory */
-	memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
+	psp_copy_fw(psp, psp->kdb_start_addr, psp->kdb_bin_size);
 
 	/* Provide the PSP KDB to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
@@ -302,10 +314,8 @@ static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy PSP SPL binary to memory */
-	memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size);
+	psp_copy_fw(psp, psp->spl_start_addr, psp->spl_bin_size);
 
 	/* Provide the PSP SPL to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
@@ -335,10 +345,8 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy PSP System Driver binary to memory */
-	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
+	psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size);
 
 	/* Provide the sys driver to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
@@ -371,10 +379,8 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy Secure OS binary to PSP memory */
-	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
+	psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size);
 
 	/* Provide the PSP secure OS to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
@@ -455,6 +461,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
 	struct amdgpu_device *adev = psp->adev;
 
 	if (amdgpu_sriov_vf(adev)) {
+		ring->ring_wptr = 0;
 		ret = psp_v11_0_ring_stop(psp, ring_type);
 		if (ret) {
 			DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
@@ -608,7 +615,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 	uint32_t p2c_header[4];
 	uint32_t sz;
 	void *buf;
-	int ret;
+	int ret, idx;
 
 	if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 		DRM_DEBUG("Memory training is not supported.\n");
@@ -681,17 +688,24 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 			return -ENOMEM;
 		}
 
-		memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
-		ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
-		if (ret) {
-			DRM_ERROR("Send long training msg failed.\n");
+		if (drm_dev_enter(&adev->ddev, &idx)) {
+			memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
+			ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
+			if (ret) {
+				DRM_ERROR("Send long training msg failed.\n");
+				vfree(buf);
+				drm_dev_exit(idx);
+				return ret;
+			}
+
+			memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
+			adev->hdp.funcs->flush_hdp(adev, NULL);
 			vfree(buf);
-			return ret;
+			drm_dev_exit(idx);
+		} else {
+			vfree(buf);
+			return -ENODEV;
 		}
-
-		memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-		adev->hdp.funcs->flush_hdp(adev, NULL);
-		vfree(buf);
 	}
 
 	if (ops & PSP_MEM_TRAIN_SAVE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index c4828bd3264b..618e5b6b85d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -138,10 +138,8 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy PSP System Driver binary to memory */
-	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
+	psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size);
 
 	/* Provide the sys driver to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
@@ -179,10 +177,8 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy Secure OS binary to PSP memory */
-	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
+	psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size);
 
 	/* Provide the PSP secure OS to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index fcdce46445d6..c8949add88f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -31,6 +31,9 @@
 
 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
 
 static int psp_v13_0_init_microcode(struct psp_context *psp)
 {
@@ -42,17 +45,37 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
 	case CHIP_ALDEBARAN:
 		chip_name = "aldebaran";
 		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
+	default:
+		BUG();
+	}
+	switch (adev->asic_type) {
+	case CHIP_ALDEBARAN:
+		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_ta_microcode(&adev->psp, chip_name);
+		if (err)
+			return err;
+		break;
+	case CHIP_YELLOW_CARP:
+		err = psp_init_asd_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_toc_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_ta_microcode(psp, chip_name);
+		if (err)
+			return err;
+		break;
 	default:
 		BUG();
 	}
 
-	err = psp_init_sos_microcode(psp, chip_name);
-	if (err)
-		return err;
-
-	err = psp_init_ta_microcode(&adev->psp, chip_name);
-
-	return err;
+	return 0;
 }
 
 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 908664a5774b..b86dcbabb635 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -102,10 +102,8 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy PSP System Driver binary to memory */
-	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
+	psp_copy_fw(psp, psp->sys_start_addr, psp->sys_bin_size);
 
 	/* Provide the sys driver to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
@@ -143,10 +141,8 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
 	if (ret)
 		return ret;
 
-	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
 	/* Copy Secure OS binary to PSP memory */
-	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
+	psp_copy_fw(psp, psp->sos_start_addr, psp->sos_bin_size);
 
 	/* Provide the PSP secure OS to bootloader */
 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
@@ -231,6 +227,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
 	psp_v3_1_reroute_ih(psp);
 
 	if (amdgpu_sriov_vf(adev)) {
+		ring->ring_wptr = 0;
 		ret = psp_v3_1_ring_stop(psp, ring_type);
 		if (ret) {
 			DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 9f0dda040ec8..4509bd4cce2d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -271,7 +271,7 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 }
 
 /**
- * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
+ * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
  *
  * @ring: amdgpu ring pointer
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 5715be6770ec..ae5464e2535a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -754,7 +754,7 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 }
 
 /**
- * sdma_v4_0_page_ring_set_wptr - commit the write pointer
+ * sdma_v4_0_ring_set_wptr - commit the write pointer
  *
  * @ring: amdgpu ring pointer
  *
@@ -820,7 +820,7 @@ static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 }
 
 /**
- * sdma_v4_0_ring_set_wptr - commit the write pointer
+ * sdma_v4_0_page_ring_set_wptr - commit the write pointer
  *
  * @ring: amdgpu ring pointer
  *
@@ -1109,6 +1109,8 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 		if (adev->asic_type == CHIP_ARCTURUS &&
 		    adev->sdma.instance[i].fw_version >= 14)
 			WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
+		/* Extend page fault timeout to avoid interrupt storm */
+		WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080);
 	}
 
 }
@@ -2227,7 +2229,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
 	memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 	amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 
-	dev_info(adev->dev,
+	dev_dbg_ratelimited(adev->dev,
 		   "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
 		   "pasid:%u, for process %s pid %d thread %s pid %d\n",
 		   instance, addr, entry->src_id, entry->ring_id, entry->vmid,
@@ -2240,7 +2242,7 @@ static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
 					      struct amdgpu_irq_src *source,
 					      struct amdgpu_iv_entry *entry)
 {
-	dev_err(adev->dev, "MC or SEM address in VM hole\n");
+	dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
 	sdma_v4_0_print_iv_entry(adev, entry);
 	return 0;
 }
@@ -2249,7 +2251,7 @@ static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
 					      struct amdgpu_irq_src *source,
 					      struct amdgpu_iv_entry *entry)
 {
-	dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
+	dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
 	sdma_v4_0_print_iv_entry(adev, entry);
 	return 0;
 }
@@ -2258,7 +2260,7 @@ static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
 					      struct amdgpu_irq_src *source,
 					      struct amdgpu_iv_entry *entry)
 {
-	dev_err(adev->dev,
+	dev_dbg_ratelimited(adev->dev,
 		"Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
 	sdma_v4_0_print_iv_entry(adev, entry);
 	return 0;
@@ -2268,7 +2270,7 @@ static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
 					      struct amdgpu_irq_src *source,
 					      struct amdgpu_iv_entry *entry)
 {
-	dev_err(adev->dev,
+	dev_dbg_ratelimited(adev->dev,
 		"SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
 	sdma_v4_0_print_iv_entry(adev, entry);
 	return 0;
@@ -2597,27 +2599,18 @@ static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
 
 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
 {
+	adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
+	adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
+	/*For Arcturus and Aldebaran, add another 4 irq handler*/
 	switch (adev->sdma.num_instances) {
-	case 1:
-		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
-		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
-		break;
 	case 5:
-		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
-		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
-		break;
 	case 8:
-		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
-		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
-		adev->sdma.vm_hole_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
-		adev->sdma.doorbell_invalid_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
-		adev->sdma.pool_timeout_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
-		adev->sdma.srbm_write_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+		adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
+		adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
+		adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
+		adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
 		break;
-	case 2:
 	default:
-		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
-		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
 		break;
 	}
 	adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 8859133ce37e..6117ba8a4c3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -328,9 +328,9 @@ static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 	} else {
-		wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
+		wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 		wptr = wptr << 32;
-		wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
+		wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 	}
 
@@ -371,9 +371,9 @@ static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 				lower_32_bits(ring->wptr << 2),
 				ring->me,
 				upper_32_bits(ring->wptr << 2));
-		WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 			lower_32_bits(ring->wptr << 2));
-		WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 			upper_32_bits(ring->wptr << 2));
 	}
 }
@@ -409,18 +409,6 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 
-	/* Invalidate L2, because if we don't do it, we might get stale cache
-	 * lines from previous IBs.
-	 */
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
-				 SDMA_GCR_GL2_WB |
-				 SDMA_GCR_GLM_INV |
-				 SDMA_GCR_GLM_WB) << 16);
-	amdgpu_ring_write(ring, 0xffffff80);
-	amdgpu_ring_write(ring, 0xffff);
-
 	/* An IB packet must end on a 8 DW boundary--the next dword
 	 * must be on a 8-dword boundary. Our IB packet below is 6
 	 * dwords long, thus add x number of NOPs, such that, in
@@ -442,6 +430,32 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 }
 
 /**
+ * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
+ *
+ * @ring: amdgpu ring pointer
+ * @job: job to retrieve vmid from
+ * @ib: IB object to schedule
+ *
+ * flush the IB by graphics cache rinse.
+ */
+static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
+{
+	uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
+			    SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
+			    SDMA_GCR_GLI_INV(1);
+
+	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
+			  SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
+			  SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
+			  SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
+}
+
+/**
  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
  *
  * @ring: amdgpu ring pointer
@@ -534,12 +548,12 @@ static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 		amdgpu_ttm_set_buffer_funcs_status(adev, false);
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
-		rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
-		ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 	}
 }
 
@@ -556,7 +570,7 @@ static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 }
 
 /**
- * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
+ * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
  *
  * @adev: amdgpu_device pointer
  * @enable: enable/disable the DMA MEs context switch.
@@ -600,11 +614,11 @@ static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 		}
 
 		if (enable && amdgpu_sdma_phase_quantum) {
-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 			       phase_quantum);
-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 			       phase_quantum);
-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 			       phase_quantum);
 		}
 		if (!amdgpu_sriov_vf(adev))
@@ -671,58 +685,63 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 
 		/* Set ring buffer size in dwords */
 		rb_bufsz = order_base_2(ring->ring_size / 4);
-		rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 #ifdef __BIG_ENDIAN
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
 #endif
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 
 		/* Initialize the ring buffer's read and write pointers */
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 
 		/* setup the wptr shadow polling */
 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 		       lower_32_bits(wptr_gpu_addr));
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 		       upper_32_bits(wptr_gpu_addr));
-		wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
+		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
 					       F32_POLL_ENABLE, 1);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 		       wptr_poll_cntl);
 
 		/* set the wb address whether it's enabled or not */
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
+		       ring->gpu_addr >> 8);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
+		       ring->gpu_addr >> 40);
 
 		ring->wptr = 0;
 
 		/* before programing wptr to a less value, need set minor_ptr_update first */
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 
 		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
+			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
+			       lower_32_bits(ring->wptr) << 2);
+			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
+			       upper_32_bits(ring->wptr) << 2);
 		}
 
-		doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
-		doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
+		doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
+		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
+						mmSDMA0_GFX_DOORBELL_OFFSET));
 
 		if (ring->use_doorbell) {
 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
@@ -731,8 +750,9 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 		} else {
 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 		}
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
+		       doorbell_offset);
 
 		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 						      ring->doorbell_index, 20);
@@ -741,7 +761,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 			sdma_v5_0_ring_set_wptr(ring);
 
 		/* set minor_ptr_update to 0 after wptr programed */
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 
 		if (!amdgpu_sriov_vf(adev)) {
 			/* set utc l1 enable flag always to 1 */
@@ -775,15 +795,15 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 
 		/* enable DMA RB */
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 
-		ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 #ifdef __BIG_ENDIAN
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 #endif
 		/* enable DMA IBs */
-		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 
 		ring->sched.ready = true;
 
@@ -1647,6 +1667,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
 		10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
 	.emit_ib = sdma_v5_0_ring_emit_ib,
+	.emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
 	.emit_fence = sdma_v5_0_ring_emit_fence,
 	.emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
 	.emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 240596b25fe4..7486e5306786 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -47,8 +47,10 @@
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
 
 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
 
 #define SDMA1_REG_OFFSET 0x600
 #define SDMA3_REG_OFFSET 0x400
@@ -92,6 +94,8 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		break;
 	default:
 		break;
@@ -145,9 +149,6 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 	struct amdgpu_firmware_info *info = NULL;
 	const struct common_firmware_header *header = NULL;
 
-	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
-		return 0;
-
 	DRM_DEBUG("\n");
 
 	switch (adev->asic_type) {
@@ -163,6 +164,12 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 	case CHIP_DIMGREY_CAVEFISH:
 		chip_name = "dimgrey_cavefish";
 		break;
+	case CHIP_BEIGE_GOBY:
+		chip_name = "beige_goby";
+		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
 	default:
 		BUG();
 	}
@@ -182,6 +189,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 		       (void *)&adev->sdma.instance[0],
 		       sizeof(struct amdgpu_sdma_instance));
 
+	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
+		return 0;
+
 	DRM_DEBUG("psp_load == '%s'\n",
 		  adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 
@@ -490,12 +500,12 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 		amdgpu_ttm_set_buffer_funcs_status(adev, false);
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
-		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
-		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 	}
 }
 
@@ -512,7 +522,7 @@ static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 }
 
 /**
- * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
+ * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
  *
  * @adev: amdgpu_device pointer
  * @enable: enable/disable the DMA MEs context switch.
@@ -553,11 +563,11 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 		if (enable && amdgpu_sdma_phase_quantum) {
-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 			       phase_quantum);
-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 			       phase_quantum);
-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 			       phase_quantum);
 		}
 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
@@ -615,62 +625,62 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 		ring = &adev->sdma.instance[i].ring;
 		wb_offset = (ring->rptr_offs * 4);
 
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 
 		/* Set ring buffer size in dwords */
 		rb_bufsz = order_base_2(ring->ring_size / 4);
-		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 #ifdef __BIG_ENDIAN
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
 #endif
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 
 		/* Initialize the ring buffer's read and write pointers */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 
 		/* setup the wptr shadow polling */
 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 		       lower_32_bits(wptr_gpu_addr));
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 		       upper_32_bits(wptr_gpu_addr));
-		wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
+		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
 							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
 					       F32_POLL_ENABLE, 1);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 		       wptr_poll_cntl);
 
 		/* set the wb address whether it's enabled or not */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 
 		ring->wptr = 0;
 
 		/* before programing wptr to a less value, need set minor_ptr_update first */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 
 		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 		}
 
-		doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
-		doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
+		doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
+		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 
 		if (ring->use_doorbell) {
 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
@@ -679,8 +689,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 		} else {
 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 		}
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 
 		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 						      ring->doorbell_index,
@@ -690,7 +700,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 			sdma_v5_2_ring_set_wptr(ring);
 
 		/* set minor_ptr_update to 0 after wptr programed */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 
 		/* set utc l1 enable flag always to 1 */
 		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
@@ -701,19 +711,19 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 
 		/* Set up RESP_MODE to non-copy addresses */
-		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
+		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 
 		/* program default cache read and write policy */
-		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
+		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 		/* clean read policy and write policy bits */
 		temp &= 0xFF0FFF;
 		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 
 		if (!amdgpu_sriov_vf(adev)) {
 			/* unhalt engine */
@@ -724,15 +734,15 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 
 		/* enable DMA RB */
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 
-		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 #ifdef __BIG_ENDIAN
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 #endif
 		/* enable DMA IBs */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 
 		ring->sched.ready = true;
 
@@ -1223,6 +1233,8 @@ static int sdma_v5_2_early_init(void *handle)
 		adev->sdma.num_instances = 2;
 		break;
 	case CHIP_VANGOGH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->sdma.num_instances = 1;
 		break;
 	default:
@@ -1551,6 +1563,10 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
 	int i;
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
+
+		if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
+			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
+
 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 			/* Enable sdma clock gating */
 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
@@ -1584,6 +1600,10 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 	int i;
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
+
+		if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
+			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
+
 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 			/* Enable sdma mem light sleep */
 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
@@ -1615,6 +1635,8 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		sdma_v5_2_update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE);
 		sdma_v5_2_update_medium_grain_light_sleep(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index cb703e307238..195b45bcb8ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -305,7 +305,7 @@ err0:
 }
 
 /**
- * cik_dma_vm_copy_pte - update PTEs by copying them from the GART
+ * si_dma_vm_copy_pte - update PTEs by copying them from the GART
  *
  * @ib: indirect buffer to fill with commands
  * @pe: addr of the page entry
@@ -402,7 +402,7 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib,
 }
 
 /**
- * si_dma_pad_ib - pad the IB to the required number of dw
+ * si_dma_ring_pad_ib - pad the IB to the required number of dw
  *
  * @ring: amdgpu_ring pointer
  * @ib: indirect buffer to fill with padding
@@ -415,7 +415,7 @@ static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 }
 
 /**
- * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
+ * si_dma_ring_emit_pipeline_sync - sync the pipeline
  *
  * @ring: amdgpu_ring pointer
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 51880f6ef634..9a24f17a5750 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -175,8 +175,7 @@ static int si_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
index 079b094c48ad..39b7c206770f 100644
--- a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
@@ -89,7 +89,24 @@ static u32 smuio_v13_0_get_die_id(struct amdgpu_device *adev)
 }
 
 /**
- * smuio_v13_0_supports_host_gpu_xgmi - detect xgmi interface between cpu and gpu/s.
+ * smuio_v13_0_get_socket_id - query socket id from FCH
+ *
+ * @adev: amdgpu device pointer
+ *
+ * Returns socket id
+ */
+static u32 smuio_v13_0_get_socket_id(struct amdgpu_device *adev)
+{
+	u32 data, socket_id;
+
+	data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
+	socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID);
+
+	return socket_id;
+}
+
+/**
+ * smuio_v13_0_is_host_gpu_xgmi_supported - detect xgmi interface between cpu and gpu/s.
  *
  * @adev: amdgpu device pointer
  *
@@ -115,6 +132,7 @@ const struct amdgpu_smuio_funcs smuio_v13_0_funcs = {
 	.get_rom_index_offset = smuio_v13_0_get_rom_index_offset,
 	.get_rom_data_offset = smuio_v13_0_get_rom_data_offset,
 	.get_die_id = smuio_v13_0_get_die_id,
+	.get_socket_id = smuio_v13_0_get_socket_id,
 	.is_host_gpu_xgmi_supported = smuio_v13_0_is_host_gpu_xgmi_supported,
 	.update_rom_clock_gating = smuio_v13_0_update_rom_clock_gating,
 	.get_clock_gating_state = smuio_v13_0_get_clock_gating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e65c286f93a6..de85577c9cfd 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -633,7 +633,9 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
 		if (entry->and_mask == 0xffffffff) {
 			tmp = entry->or_mask;
 		} else {
-			tmp = RREG32(reg);
+			tmp = (entry->hwip == GC_HWIP) ?
+				RREG32_SOC15_IP(GC, reg) : RREG32(reg);
+
 			tmp &= ~(entry->and_mask);
 			tmp |= (entry->or_mask & entry->and_mask);
 		}
@@ -644,7 +646,8 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
 			reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 			WREG32_RLC(reg, tmp);
 		else
-			WREG32(reg, tmp);
+			(entry->hwip == GC_HWIP) ?
+				WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
 
 	}
 
@@ -656,7 +659,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 	int ret = 0;
 
 	/* avoid NBIF got stuck when do RAS recovery in BACO reset */
-	if (ras && ras->supported)
+	if (ras && adev->ras_enabled)
 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 
 	ret = amdgpu_dpm_baco_reset(adev);
@@ -664,7 +667,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 		return ret;
 
 	/* re-enable doorbell interrupt after BACO exit */
-	if (ras && ras->supported)
+	if (ras && adev->ras_enabled)
 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 
 	return 0;
@@ -711,7 +714,8 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
 		 * 1. PMFW version > 0x284300: all cases use baco
 		 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 		 */
-		if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
+		if (ras && adev->ras_enabled &&
+		    adev->pm.fw_version <= 0x283400)
 			baco_reset = false;
 		break;
 	case CHIP_ALDEBARAN:
@@ -817,7 +821,7 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 
 static void soc15_program_aspm(struct amdgpu_device *adev)
 {
-	if (amdgpu_aspm != 1)
+	if (!amdgpu_aspm)
 		return;
 
 	if (!(adev->flags & AMD_IS_APU) &&
@@ -1521,9 +1525,6 @@ static int soc15_common_late_init(void *handle)
 	if (amdgpu_sriov_vf(adev))
 		xgpu_ai_mailbox_get_irq(adev);
 
-	if (adev->hdp.funcs->reset_ras_error_count)
-		adev->hdp.funcs->reset_ras_error_count(adev);
-
 	if (adev->nbio.ras_funcs &&
 	    adev->nbio.ras_funcs->ras_late_init)
 		r = adev->nbio.ras_funcs->ras_late_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 14bd794bbea6..0eeb5e073be8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -27,28 +27,51 @@
 /* Register Access Macros */
 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
 
+#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
+	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_wreg) ? \
+	 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
+	 WREG32(reg, value))
+
+#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
+	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_rreg) ? \
+	 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
+	 RREG32(reg))
+
 #define WREG32_FIELD15(ip, idx, reg, field, val)	\
-	WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
-	(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg)	\
-	& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+	 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
+				(__RREG32_SOC15_RLC__( \
+					adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
+					0, ip##_HWIP) & \
+				~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
+			      0, ip##_HWIP)
 
 #define RREG32_SOC15(ip, inst, reg) \
-	RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
+			 0, ip##_HWIP)
+
+#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)
 
 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
-	RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
+			 AMDGPU_REGS_NO_KIQ, ip##_HWIP)
 
 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
-	RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
+	 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP)
 
 #define WREG32_SOC15(ip, inst, reg, value) \
-	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
+	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
+			  value, 0, ip##_HWIP)
+
+#define WREG32_SOC15_IP(ip, reg, value) \
+	 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
 
 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
-	WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
+	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
+			     value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
 
 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
-	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
+	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
+			  value, 0, ip##_HWIP)
 
 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
 ({	int ret = 0;						\
@@ -77,12 +100,7 @@
 })
 
 #define WREG32_RLC(reg, value) \
-	do { \
-		if (adev->gfx.rlc.funcs->rlcg_wreg) \
-			adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \
-		else \
-			WREG32(reg, value);	\
-	} while (0)
+	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
 
 #define WREG32_RLC_EX(prefix, reg, value) \
 	do {							\
@@ -108,24 +126,19 @@
 		}	\
 	} while (0)
 
+/* shadow the registers in the callback function */
 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
-	WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
+	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)
 
+/* for GC only */
 #define RREG32_RLC(reg) \
-	(adev->gfx.rlc.funcs->rlcg_rreg ? \
-		adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg))
-
-#define WREG32_RLC_NO_KIQ(reg, value) \
-	do { \
-		if (adev->gfx.rlc.funcs->rlcg_wreg) \
-			adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, AMDGPU_REGS_NO_KIQ); \
-		else \
-			WREG32_NO_KIQ(reg, value);	\
-	} while (0)
+	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
+
+#define WREG32_RLC_NO_KIQ(reg, value, hwip) \
+	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
 
-#define RREG32_RLC_NO_KIQ(reg) \
-	(adev->gfx.rlc.funcs->rlcg_rreg ? \
-		adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg))
+#define RREG32_RLC_NO_KIQ(reg, hwip) \
+	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
 
 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
 	do {							\
@@ -146,12 +159,12 @@
 	} while (0)
 
 #define RREG32_SOC15_RLC(ip, inst, reg) \
-	RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP)
 
 #define WREG32_SOC15_RLC(ip, inst, reg, value) \
 	do {							\
 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
-		WREG32_RLC(target_reg, value); \
+		__WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \
 	} while (0)
 
 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \
@@ -161,14 +174,16 @@
 	} while (0)
 
 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \
-	WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
-	(RREG32_RLC(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
-	& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
+			     (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
+						   AMDGPU_REGS_RLC, ip##_HWIP) & \
+			      ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
+			     AMDGPU_REGS_RLC, ip##_HWIP)
 
 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
-	WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
+	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP)
 
 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
-	RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset))
+	__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP)
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
index 745ed0fba1ed..0f214a398dd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
@@ -105,6 +105,12 @@ struct ta_ras_trigger_error_input {
 	uint64_t		value;			// method if error injection. i.e persistent, coherent etc.
 };
 
+struct ta_ras_init_flags
+{
+    uint8_t     poison_mode_en;
+    uint8_t     dgpu_mode;
+};
+
 struct ta_ras_output_flags
 {
 	uint8_t    ras_init_success_flag;
@@ -115,6 +121,7 @@ struct ta_ras_output_flags
 /* Common input structure for RAS callbacks */
 /**********************************************************/
 union ta_ras_cmd_input {
+	struct ta_ras_init_flags		init_flags;
 	struct ta_ras_enable_features_input	enable_features;
 	struct ta_ras_disable_features_input	disable_features;
 	struct ta_ras_trigger_error_input	trigger_error;
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 249fcbee7871..b08905d1c00f 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -312,8 +312,7 @@ static int tonga_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 	amdgpu_irq_remove_domain(adev);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
index 89d20adfa001..af59a35788e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
@@ -234,7 +234,7 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
 		err_addr &= ~((0x1ULL << lsb) - 1);
 
 		/* translate umc channel address to soc pa, 3 parts are included */
-		retired_page = ADDR_OF_8KB_BLOCK(err_addr) |
+		retired_page = ADDR_OF_4KB_BLOCK(err_addr) |
 				ADDR_OF_256B_BLOCK(channel_index) |
 				OFFSET_IN_256B_BLOCK(err_addr);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 284447d7a579..6c0e91495365 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -340,7 +340,7 @@ static int uvd_v3_1_start(struct amdgpu_device *adev)
 	/* enable VCPU clock */
 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 
-	/* disable interupt */
+	/* disable interrupt */
 	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 
 #ifdef __BIG_ENDIAN
@@ -405,7 +405,7 @@ static int uvd_v3_1_start(struct amdgpu_device *adev)
 		return r;
 	}
 
-	/* enable interupt */
+	/* enable interrupt */
 	WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
 
 	WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 0cd98fcb1f9f..939bcfa2a4ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -363,6 +363,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
 error:
 	dma_fence_put(fence);
+	amdgpu_bo_unpin(bo);
 	amdgpu_bo_unreserve(bo);
 	amdgpu_bo_unref(&bo);
 	return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 8e238dea7bef..90910d19db12 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -25,6 +25,7 @@
  */
 
 #include <linux/firmware.h>
+#include <drm/drm_drv.h>
 
 #include "amdgpu.h"
 #include "amdgpu_vce.h"
@@ -555,16 +556,19 @@ static int vce_v4_0_hw_fini(void *handle)
 static int vce_v4_0_suspend(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	int r;
+	int r, idx;
 
 	if (adev->vce.vcpu_bo == NULL)
 		return 0;
 
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);
-		void *ptr = adev->vce.cpu_addr;
+	if (drm_dev_enter(&adev->ddev, &idx)) {
+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+			unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);
+			void *ptr = adev->vce.cpu_addr;
 
-		memcpy_fromio(adev->vce.saved_bo, ptr, size);
+			memcpy_fromio(adev->vce.saved_bo, ptr, size);
+		}
+		drm_dev_exit(idx);
 	}
 
 	r = vce_v4_0_hw_fini(adev);
@@ -577,16 +581,20 @@ static int vce_v4_0_suspend(void *handle)
 static int vce_v4_0_resume(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	int r;
+	int r, idx;
 
 	if (adev->vce.vcpu_bo == NULL)
 		return -EINVAL;
 
 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);
-		void *ptr = adev->vce.cpu_addr;
 
-		memcpy_toio(ptr, adev->vce.saved_bo, size);
+		if (drm_dev_enter(&adev->ddev, &idx)) {
+			unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);
+			void *ptr = adev->vce.cpu_addr;
+
+			memcpy_toio(ptr, adev->vce.saved_bo, size);
+			drm_dev_exit(idx);
+		}
 	} else {
 		r = amdgpu_vce_resume(adev);
 		if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 27b1ced145d2..284bb42d6c86 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -769,7 +769,7 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 }
 
 /**
- * vcn_v1_0_start - start VCN block
+ * vcn_v1_0_start_spg_mode - start VCN block
  *
  * @adev: amdgpu_device pointer
  *
@@ -1105,7 +1105,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
 }
 
 /**
- * vcn_v1_0_stop - stop VCN block
+ * vcn_v1_0_stop_spg_mode - stop VCN block
  *
  * @adev: amdgpu_device pointer
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 3b23de996db2..47d4f04cbd69 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -34,6 +34,8 @@
 #include "vcn/vcn_3_0_0_sh_mask.h"
 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
 
+#include <drm/drm_drv.h>
+
 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27
 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f
 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET			0x10
@@ -85,16 +87,18 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
 static int vcn_v3_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i;
 
 	if (amdgpu_sriov_vf(adev)) {
-		adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
+		for (i = 0; i < VCN_INSTANCES_SIENNA_CICHLID; i++)
+			if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i))
+				adev->vcn.num_vcn_inst++;
 		adev->vcn.harvest_config = 0;
 		adev->vcn.num_enc_rings = 1;
 
 	} else {
 		if (adev->asic_type == CHIP_SIENNA_CICHLID) {
 			u32 harvest;
-			int i;
 
 			adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
 			for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@@ -110,7 +114,10 @@ static int vcn_v3_0_early_init(void *handle)
 		} else
 			adev->vcn.num_vcn_inst = 1;
 
-		adev->vcn.num_enc_rings = 2;
+		if (adev->asic_type == CHIP_BEIGE_GOBY)
+			adev->vcn.num_enc_rings = 0;
+		else
+			adev->vcn.num_enc_rings = 2;
 	}
 
 	vcn_v3_0_set_dec_ring_funcs(adev);
@@ -146,7 +153,8 @@ static int vcn_v3_0_sw_init(void *handle)
 		adev->firmware.fw_size +=
 			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 
-		if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
+		if ((adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) ||
+		    (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)) {
 			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
 			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
 			adev->firmware.fw_size +=
@@ -268,16 +276,20 @@ static int vcn_v3_0_sw_init(void *handle)
 static int vcn_v3_0_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	int i, r;
+	int i, r, idx;
 
-	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-		volatile struct amdgpu_fw_shared *fw_shared;
+	if (drm_dev_enter(&adev->ddev, &idx)) {
+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+			volatile struct amdgpu_fw_shared *fw_shared;
 
-		if (adev->vcn.harvest_config & (1 << i))
-			continue;
-		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
-		fw_shared->present_flag_0 = 0;
-		fw_shared->sw_ring.is_enabled = false;
+			if (adev->vcn.harvest_config & (1 << i))
+				continue;
+			fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+			fw_shared->present_flag_0 = 0;
+			fw_shared->sw_ring.is_enabled = false;
+		}
+
+		drm_dev_exit(idx);
 	}
 
 	if (amdgpu_sriov_vf(adev))
@@ -316,19 +328,17 @@ static int vcn_v3_0_hw_init(void *handle)
 				continue;
 
 			ring = &adev->vcn.inst[i].ring_dec;
-			if (ring->sched.ready) {
-				ring->wptr = 0;
-				ring->wptr_old = 0;
-				vcn_v3_0_dec_ring_set_wptr(ring);
-			}
+			ring->wptr = 0;
+			ring->wptr_old = 0;
+			vcn_v3_0_dec_ring_set_wptr(ring);
+			ring->sched.ready = true;
 
 			for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 				ring = &adev->vcn.inst[i].ring_enc[j];
-				if (ring->sched.ready) {
-					ring->wptr = 0;
-					ring->wptr_old = 0;
-					vcn_v3_0_enc_ring_set_wptr(ring);
-				}
+				ring->wptr = 0;
+				ring->wptr_old = 0;
+				vcn_v3_0_enc_ring_set_wptr(ring);
+				ring->sched.ready = true;
 			}
 		}
 	} else {
@@ -1254,23 +1264,25 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
 		fw_shared->rb.wptr = lower_32_bits(ring->wptr);
 		fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
 
-		fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
-		ring = &adev->vcn.inst[i].ring_enc[0];
-		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
-		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
-		fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
-
-		fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
-		ring = &adev->vcn.inst[i].ring_enc[1];
-		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
-		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
-		fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+		if (adev->asic_type != CHIP_BEIGE_GOBY) {
+			fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+			ring = &adev->vcn.inst[i].ring_enc[0];
+			WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+			WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
+			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+			WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
+			fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+
+			fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+			ring = &adev->vcn.inst[i].ring_enc[1];
+			WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+			WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+			WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+			fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+		}
 	}
 
 	return 0;
@@ -1293,8 +1305,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
 	uint32_t table_size;
 	uint32_t size, size_dw;
 
-	bool is_vcn_ready;
-
 	struct mmsch_v3_0_cmd_direct_write
 		direct_wt = { {0} };
 	struct mmsch_v3_0_cmd_direct_read_modify_write
@@ -1486,30 +1496,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
 		}
 	}
 
-	/* 6, check each VCN's init_status
-	 * if it remains as 0, then this VCN is not assigned to current VF
-	 * do not start ring for this VCN
-	 */
-	size = sizeof(struct mmsch_v3_0_init_header);
-	table_loc = (uint32_t *)table->cpu_addr;
-	memcpy(&header, (void *)table_loc, size);
-
-	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-		if (adev->vcn.harvest_config & (1 << i))
-			continue;
-
-		is_vcn_ready = (header.inst[i].init_status == 1);
-		if (!is_vcn_ready)
-			DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i);
-
-		ring = &adev->vcn.inst[i].ring_dec;
-		ring->sched.ready = is_vcn_ready;
-		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-			ring = &adev->vcn.inst[i].ring_enc[j];
-			ring->sched.ready = is_vcn_ready;
-		}
-	}
-
 	return 0;
 }
 
@@ -1650,31 +1636,33 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
 					UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
 					~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
 
-				/* Restore */
-				fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
-				fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
-				ring = &adev->vcn.inst[inst_idx].ring_enc[0];
-				ring->wptr = 0;
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
-				fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
-
-				fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
-				ring = &adev->vcn.inst[inst_idx].ring_enc[1];
-				ring->wptr = 0;
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
-				fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
-
-				/* restore wptr/rptr with pointers saved in FW shared memory*/
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
-				WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);
+				if (adev->asic_type != CHIP_BEIGE_GOBY) {
+					/* Restore */
+					fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
+					fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+					ring = &adev->vcn.inst[inst_idx].ring_enc[0];
+					ring->wptr = 0;
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+					fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+
+					fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+					ring = &adev->vcn.inst[inst_idx].ring_enc[1];
+					ring->wptr = 0;
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+					fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+
+					/* restore wptr/rptr with pointers saved in FW shared memory*/
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
+					WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);
+				}
 
 				/* Unstall DPG */
 				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
@@ -2131,7 +2119,8 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
 			adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
 			adev->vcn.inst[i].ring_enc[j].me = i;
 		}
-		DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
+		if (adev->vcn.num_enc_rings > 0)
+			DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index ca8efa5c6978..a9ca6988009e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -104,6 +104,7 @@ static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
 
 	tmp = RREG32(ih_regs->ih_rb_cntl);
 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
+	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
 	/* enable_intr field is only valid in ring0 */
 	if (ih == &adev->irq.ih)
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
@@ -513,11 +514,7 @@ static int vega10_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index 8a122b413bf5..f51dfc38ac65 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -565,11 +565,7 @@ static int vega20_ih_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	amdgpu_irq_fini(adev);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
-	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
+	amdgpu_irq_fini_sw(adev);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 735ebbd1148f..3d21c0799037 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1136,7 +1136,7 @@ static void vi_program_aspm(struct amdgpu_device *adev)
 	bool bL1SS = false;
 	bool bClkReqSupport = true;
 
-	if (amdgpu_aspm != 1)
+	if (!amdgpu_aspm)
 		return;
 
 	if (adev->flags & AMD_IS_APU ||
diff --git a/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c b/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c
new file mode 100644
index 000000000000..3d89421275ed
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "yellow_carp_offset.h"
+
+int yellow_carp_reg_base_init(struct amdgpu_device *adev)
+{
+	/* HW has more IP blocks,  only initialized the block needed by driver */
+	uint32_t i;
+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+	}
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig
index f02c938f75da..8cc0a76ddf9f 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -12,3 +12,16 @@ config HSA_AMD
 	select DRM_AMDGPU_USERPTR
 	help
 	  Enable this if you want to use HSA features on AMD GPU devices.
+
+config HSA_AMD_SVM
+	bool "Enable HMM-based shared virtual memory manager"
+	depends on HSA_AMD && DEVICE_PRIVATE
+	default y
+	select HMM_MIRROR
+	select MMU_NOTIFIER
+	help
+	  Enable this to use unified memory and managed memory in HIP. This
+	  memory manager supports two modes of operation. One based on
+	  preemptions and one based on page faults. To enable page fault
+	  based memory management on most GFXv9 GPUs, set the module
+	  parameter amdgpu.noretry=0.
diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
index e1e4115dcf78..c4f3aff11072 100644
--- a/drivers/gpu/drm/amd/amdkfd/Makefile
+++ b/drivers/gpu/drm/amd/amdkfd/Makefile
@@ -63,3 +63,8 @@ endif
 ifneq ($(CONFIG_DEBUG_FS),)
 AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o
 endif
+
+ifneq ($(CONFIG_HSA_AMD_SVM),)
+AMDKFD_FILES += $(AMDKFD_PATH)/kfd_svm.o \
+		$(AMDKFD_PATH)/kfd_migrate.o
+endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 43de260b2230..67541c30327a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -38,6 +38,7 @@
 #include "kfd_priv.h"
 #include "kfd_device_queue_manager.h"
 #include "kfd_dbgmgr.h"
+#include "kfd_svm.h"
 #include "amdgpu_amdkfd.h"
 #include "kfd_smi_events.h"
 
@@ -1297,7 +1298,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
 
 	err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		dev->kgd, args->va_addr, args->size,
-		pdd->vm, (struct kgd_mem **) &mem, &offset,
+		pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
 		flags);
 
 	if (err)
@@ -1328,7 +1329,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
 	return 0;
 
 err_free:
-	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL);
+	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem,
+					       pdd->drm_priv, NULL);
 err_unlock:
 	mutex_unlock(&p->mutex);
 	return err;
@@ -1365,7 +1367,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
 	}
 
 	ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd,
-						(struct kgd_mem *)mem, &size);
+				(struct kgd_mem *)mem, pdd->drm_priv, &size);
 
 	/* If freeing the buffer failed, leave the handle in place for
 	 * clean-up during process tear-down.
@@ -1391,6 +1393,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
 	long err = 0;
 	int i;
 	uint32_t *devices_arr = NULL;
+	bool table_freed = false;
 
 	dev = kfd_device_by_id(GET_GPU_ID(args->handle));
 	if (!dev)
@@ -1448,7 +1451,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
 			goto get_mem_obj_from_handle_failed;
 		}
 		err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
-			peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
+			peer->kgd, (struct kgd_mem *)mem,
+			peer_pdd->drm_priv, &table_freed);
 		if (err) {
 			pr_err("Failed to map to gpu %d/%d\n",
 			       i, args->n_devices);
@@ -1466,16 +1470,17 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
 	}
 
 	/* Flush TLBs after waiting for the page table updates to complete */
-	for (i = 0; i < args->n_devices; i++) {
-		peer = kfd_device_by_id(devices_arr[i]);
-		if (WARN_ON_ONCE(!peer))
-			continue;
-		peer_pdd = kfd_get_process_device_data(peer, p);
-		if (WARN_ON_ONCE(!peer_pdd))
-			continue;
-		kfd_flush_tlb(peer_pdd);
+	if (table_freed) {
+		for (i = 0; i < args->n_devices; i++) {
+			peer = kfd_device_by_id(devices_arr[i]);
+			if (WARN_ON_ONCE(!peer))
+				continue;
+			peer_pdd = kfd_get_process_device_data(peer, p);
+			if (WARN_ON_ONCE(!peer_pdd))
+				continue;
+			kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
+		}
 	}
-
 	kfree(devices_arr);
 
 	return err;
@@ -1555,7 +1560,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
 			goto get_mem_obj_from_handle_failed;
 		}
 		err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
-			peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
+			peer->kgd, (struct kgd_mem *)mem, peer_pdd->drm_priv);
 		if (err) {
 			pr_err("Failed to unmap from gpu %d/%d\n",
 			       i, args->n_devices);
@@ -1563,10 +1568,27 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
 		}
 		args->n_success = i+1;
 	}
-	kfree(devices_arr);
-
 	mutex_unlock(&p->mutex);
 
+	err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
+	if (err) {
+		pr_debug("Sync memory failed, wait interrupted by user signal\n");
+		goto sync_memory_failed;
+	}
+
+	/* Flush TLBs after waiting for the page table updates to complete */
+	for (i = 0; i < args->n_devices; i++) {
+		peer = kfd_device_by_id(devices_arr[i]);
+		if (WARN_ON_ONCE(!peer))
+			continue;
+		peer_pdd = kfd_get_process_device_data(peer, p);
+		if (WARN_ON_ONCE(!peer_pdd))
+			continue;
+		kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
+	}
+
+	kfree(devices_arr);
+
 	return 0;
 
 bind_process_to_device_failed:
@@ -1574,6 +1596,7 @@ get_mem_obj_from_handle_failed:
 unmap_memory_from_gpu_failed:
 	mutex_unlock(&p->mutex);
 copy_from_user_failed:
+sync_memory_failed:
 	kfree(devices_arr);
 	return err;
 }
@@ -1701,7 +1724,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
 	}
 
 	r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf,
-					      args->va_addr, pdd->vm,
+					      args->va_addr, pdd->drm_priv,
 					      (struct kgd_mem **)&mem, &size,
 					      NULL);
 	if (r)
@@ -1721,7 +1744,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
 	return 0;
 
 err_free:
-	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL);
+	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem,
+					       pdd->drm_priv, NULL);
 err_unlock:
 	mutex_unlock(&p->mutex);
 	dma_buf_put(dmabuf);
@@ -1742,6 +1766,61 @@ static int kfd_ioctl_smi_events(struct file *filep,
 	return kfd_smi_event_open(dev, &args->anon_fd);
 }
 
+static int kfd_ioctl_set_xnack_mode(struct file *filep,
+				    struct kfd_process *p, void *data)
+{
+	struct kfd_ioctl_set_xnack_mode_args *args = data;
+	int r = 0;
+
+	mutex_lock(&p->mutex);
+	if (args->xnack_enabled >= 0) {
+		if (!list_empty(&p->pqm.queues)) {
+			pr_debug("Process has user queues running\n");
+			mutex_unlock(&p->mutex);
+			return -EBUSY;
+		}
+		if (args->xnack_enabled && !kfd_process_xnack_mode(p, true))
+			r = -EPERM;
+		else
+			p->xnack_enabled = args->xnack_enabled;
+	} else {
+		args->xnack_enabled = p->xnack_enabled;
+	}
+	mutex_unlock(&p->mutex);
+
+	return r;
+}
+
+#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
+static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
+{
+	struct kfd_ioctl_svm_args *args = data;
+	int r = 0;
+
+	pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
+		 args->start_addr, args->size, args->op, args->nattr);
+
+	if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK))
+		return -EINVAL;
+	if (!args->start_addr || !args->size)
+		return -EINVAL;
+
+	mutex_lock(&p->mutex);
+
+	r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
+		      args->attrs);
+
+	mutex_unlock(&p->mutex);
+
+	return r;
+}
+#else
+static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
+{
+	return -EPERM;
+}
+#endif
+
 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
 	[_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
 			    .cmd_drv = 0, .name = #ioctl}
@@ -1840,6 +1919,11 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
 
 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
 			kfd_ioctl_smi_events, 0),
+
+	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
+
+	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
+			kfd_ioctl_set_xnack_mode, 0),
 };
 
 #define AMDKFD_CORE_IOCTL_COUNT	ARRAY_SIZE(amdkfd_ioctls)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index c60e82697385..c6b02aee4993 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -55,7 +55,7 @@ struct kfd_gpu_cache_info {
 	uint32_t	cache_level;
 	uint32_t	flags;
 	/* Indicates how many Compute Units share this cache
-	 * Value = 1 indicates the cache is not shared
+	 * within a SA. Value = 1 indicates the cache is not shared
 	 */
 	uint32_t	num_cu_shared;
 };
@@ -69,7 +69,6 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
 				CRAT_CACHE_FLAGS_DATA_CACHE |
 				CRAT_CACHE_FLAGS_SIMD_CACHE),
 		.num_cu_shared = 1,
-
 	},
 	{
 		/* Scalar L1 Instruction Cache (in SQC module) per bank */
@@ -126,9 +125,6 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
 	/* TODO: Add L2 Cache information */
 };
 
-/* NOTE: In future if more information is added to struct kfd_gpu_cache_info
- * the following ASICs may need a separate table.
- */
 #define hawaii_cache_info kaveri_cache_info
 #define tonga_cache_info carrizo_cache_info
 #define fiji_cache_info  carrizo_cache_info
@@ -136,13 +132,667 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
 #define polaris11_cache_info carrizo_cache_info
 #define polaris12_cache_info carrizo_cache_info
 #define vegam_cache_info carrizo_cache_info
-/* TODO - check & update Vega10 cache details */
-#define vega10_cache_info carrizo_cache_info
-#define raven_cache_info carrizo_cache_info
-#define renoir_cache_info carrizo_cache_info
-/* TODO - check & update Navi10 cache details */
-#define navi10_cache_info carrizo_cache_info
-#define vangogh_cache_info carrizo_cache_info
+
+/* NOTE: L1 cache information has been updated and L2/L3
+ * cache information has been added for Vega10 and
+ * newer ASICs. The unit for cache_size is KiB.
+ * In future,  check & update cache details
+ * for every new ASIC is required.
+ */
+
+static struct kfd_gpu_cache_info vega10_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 4096,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 16,
+	},
+};
+
+static struct kfd_gpu_cache_info raven_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 1024,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 11,
+	},
+};
+
+static struct kfd_gpu_cache_info renoir_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 1024,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+};
+
+static struct kfd_gpu_cache_info vega12_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 2048,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 5,
+	},
+};
+
+static struct kfd_gpu_cache_info vega20_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 3,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 8192,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 16,
+	},
+};
+
+static struct kfd_gpu_cache_info aldebaran_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 8192,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 14,
+	},
+};
+
+static struct kfd_gpu_cache_info navi10_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 4096,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+};
+
+static struct kfd_gpu_cache_info vangogh_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 1024,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+};
+
+static struct kfd_gpu_cache_info navi14_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 12,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 2048,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 12,
+	},
+};
+
+static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 4096,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+	{
+		/* L3 Data Cache per GPU */
+		.cache_size = 128*1024,
+		.cache_level = 3,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+};
+
+static struct kfd_gpu_cache_info navy_flounder_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 3072,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+	{
+		/* L3 Data Cache per GPU */
+		.cache_size = 96*1024,
+		.cache_level = 3,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 10,
+	},
+};
+
+static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 2048,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+	{
+		/* L3 Data Cache per GPU */
+		.cache_size = 32*1024,
+		.cache_level = 3,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+};
+
+static struct kfd_gpu_cache_info beige_goby_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 1024,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+	{
+		/* L3 Data Cache per GPU */
+		.cache_size = 16*1024,
+		.cache_level = 3,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 8,
+	},
+};
+
+static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 6,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 2048,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 6,
+	},
+};
 
 static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
 		struct crat_subtype_computeunit *cu)
@@ -544,7 +1194,7 @@ err:
 }
 
 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */
-static int fill_in_pcache(struct crat_subtype_cache *pcache,
+static int fill_in_l1_pcache(struct crat_subtype_cache *pcache,
 				struct kfd_gpu_cache_info *pcache_info,
 				struct kfd_cu_info *cu_info,
 				int mem_available,
@@ -597,6 +1247,70 @@ static int fill_in_pcache(struct crat_subtype_cache *pcache,
 	return 1;
 }
 
+/* Helper function. See kfd_fill_gpu_cache_info for parameter description */
+static int fill_in_l2_l3_pcache(struct crat_subtype_cache *pcache,
+				struct kfd_gpu_cache_info *pcache_info,
+				struct kfd_cu_info *cu_info,
+				int mem_available,
+				int cache_type, unsigned int cu_processor_id)
+{
+	unsigned int cu_sibling_map_mask;
+	int first_active_cu;
+	int i, j, k;
+
+	/* First check if enough memory is available */
+	if (sizeof(struct crat_subtype_cache) > mem_available)
+		return -ENOMEM;
+
+	cu_sibling_map_mask = cu_info->cu_bitmap[0][0];
+	cu_sibling_map_mask &=
+		((1 << pcache_info[cache_type].num_cu_shared) - 1);
+	first_active_cu = ffs(cu_sibling_map_mask);
+
+	/* CU could be inactive. In case of shared cache find the first active
+	 * CU. and incase of non-shared cache check if the CU is inactive. If
+	 * inactive active skip it
+	 */
+	if (first_active_cu) {
+		memset(pcache, 0, sizeof(struct crat_subtype_cache));
+		pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY;
+		pcache->length = sizeof(struct crat_subtype_cache);
+		pcache->flags = pcache_info[cache_type].flags;
+		pcache->processor_id_low = cu_processor_id
+					 + (first_active_cu - 1);
+		pcache->cache_level = pcache_info[cache_type].cache_level;
+		pcache->cache_size = pcache_info[cache_type].cache_size;
+
+		/* Sibling map is w.r.t processor_id_low, so shift out
+		 * inactive CU
+		 */
+		cu_sibling_map_mask =
+			cu_sibling_map_mask >> (first_active_cu - 1);
+		k = 0;
+		for (i = 0; i < cu_info->num_shader_engines; i++) {
+			for (j = 0; j < cu_info->num_shader_arrays_per_engine;
+				j++) {
+				pcache->sibling_map[k] =
+				 (uint8_t)(cu_sibling_map_mask & 0xFF);
+				pcache->sibling_map[k+1] =
+				 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
+				pcache->sibling_map[k+2] =
+				 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
+				pcache->sibling_map[k+3] =
+				 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
+				k += 4;
+				cu_sibling_map_mask =
+					cu_info->cu_bitmap[i % 4][j + i / 4];
+				cu_sibling_map_mask &= (
+				 (1 << pcache_info[cache_type].num_cu_shared)
+				 - 1);
+			}
+		}
+		return 0;
+	}
+	return 1;
+}
+
 /* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info
  * tables
  *
@@ -624,6 +1338,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 	int mem_available = available_size;
 	unsigned int cu_processor_id;
 	int ret;
+	unsigned int num_cu_shared;
 
 	switch (kdev->device_info->asic_family) {
 	case CHIP_KAVERI:
@@ -663,12 +1378,21 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 		num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
 		break;
 	case CHIP_VEGA10:
+		pcache_info = vega10_cache_info;
+		num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
+		break;
 	case CHIP_VEGA12:
+		pcache_info = vega12_cache_info;
+		num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
+		break;
 	case CHIP_VEGA20:
 	case CHIP_ARCTURUS:
+		pcache_info = vega20_cache_info;
+		num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
+		break;
 	case CHIP_ALDEBARAN:
-		pcache_info = vega10_cache_info;
-		num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
+		pcache_info = aldebaran_cache_info;
+		num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
 		break;
 	case CHIP_RAVEN:
 		pcache_info = raven_cache_info;
@@ -680,17 +1404,37 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 		break;
 	case CHIP_NAVI10:
 	case CHIP_NAVI12:
+		pcache_info = navi10_cache_info;
+		num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
+		break;
 	case CHIP_NAVI14:
+		pcache_info = navi14_cache_info;
+		num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
+		break;
 	case CHIP_SIENNA_CICHLID:
+		pcache_info = sienna_cichlid_cache_info;
+		num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
+		break;
 	case CHIP_NAVY_FLOUNDER:
+		pcache_info = navy_flounder_cache_info;
+		num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
+		break;
 	case CHIP_DIMGREY_CAVEFISH:
-		pcache_info = navi10_cache_info;
-		num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
+		pcache_info = dimgrey_cavefish_cache_info;
+		num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
 		break;
 	case CHIP_VANGOGH:
 		pcache_info = vangogh_cache_info;
 		num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
 		break;
+	case CHIP_BEIGE_GOBY:
+		pcache_info = beige_goby_cache_info;
+		num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
+		break;
+	case CHIP_YELLOW_CARP:
+		pcache_info = yellow_carp_cache_info;
+		num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -709,40 +1453,58 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 	 */
 
 	for (ct = 0; ct < num_of_cache_types; ct++) {
-		cu_processor_id = gpu_processor_id;
-		for (i = 0; i < cu_info->num_shader_engines; i++) {
-			for (j = 0; j < cu_info->num_shader_arrays_per_engine;
-				j++) {
-				for (k = 0; k < cu_info->num_cu_per_sh;
-					k += pcache_info[ct].num_cu_shared) {
-
-					ret = fill_in_pcache(pcache,
-						pcache_info,
-						cu_info,
-						mem_available,
-						cu_info->cu_bitmap[i % 4][j + i / 4],
-						ct,
-						cu_processor_id,
-						k);
-
-					if (ret < 0)
-						break;
-
-					if (!ret) {
-						pcache++;
-						(*num_of_entries)++;
-						mem_available -=
-							sizeof(*pcache);
-						(*size_filled) +=
-							sizeof(*pcache);
-					}
-
-					/* Move to next CU block */
-					cu_processor_id +=
-						pcache_info[ct].num_cu_shared;
-				}
-			}
+	  cu_processor_id = gpu_processor_id;
+	  if (pcache_info[ct].cache_level == 1) {
+	    for (i = 0; i < cu_info->num_shader_engines; i++) {
+	      for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) {
+	        for (k = 0; k < cu_info->num_cu_per_sh;
+		  k += pcache_info[ct].num_cu_shared) {
+		  ret = fill_in_l1_pcache(pcache,
+					pcache_info,
+					cu_info,
+					mem_available,
+					cu_info->cu_bitmap[i % 4][j + i / 4],
+					ct,
+					cu_processor_id,
+					k);
+
+		  if (ret < 0)
+			break;
+
+		  if (!ret) {
+				pcache++;
+				(*num_of_entries)++;
+				mem_available -= sizeof(*pcache);
+				(*size_filled) += sizeof(*pcache);
+		  }
+
+		  /* Move to next CU block */
+		  num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
+					cu_info->num_cu_per_sh) ?
+					pcache_info[ct].num_cu_shared :
+					(cu_info->num_cu_per_sh - k);
+		  cu_processor_id += num_cu_shared;
 		}
+	      }
+	    }
+	  } else {
+			ret = fill_in_l2_l3_pcache(pcache,
+				pcache_info,
+				cu_info,
+				mem_available,
+				ct,
+				cu_processor_id);
+
+			if (ret < 0)
+				break;
+
+			if (!ret) {
+				pcache++;
+				(*num_of_entries)++;
+				mem_available -= sizeof(*pcache);
+				(*size_filled) += sizeof(*pcache);
+			}
+	  }
 	}
 
 	pr_debug("Added [%d] GPU cache entries\n", *num_of_entries);
@@ -1100,6 +1862,92 @@ static int kfd_fill_gpu_memory_affinity(int *avail_size,
 	return 0;
 }
 
+#ifdef CONFIG_ACPI_NUMA
+static void kfd_find_numa_node_in_srat(struct kfd_dev *kdev)
+{
+	struct acpi_table_header *table_header = NULL;
+	struct acpi_subtable_header *sub_header = NULL;
+	unsigned long table_end, subtable_len;
+	u32 pci_id = pci_domain_nr(kdev->pdev->bus) << 16 |
+			pci_dev_id(kdev->pdev);
+	u32 bdf;
+	acpi_status status;
+	struct acpi_srat_cpu_affinity *cpu;
+	struct acpi_srat_generic_affinity *gpu;
+	int pxm = 0, max_pxm = 0;
+	int numa_node = NUMA_NO_NODE;
+	bool found = false;
+
+	/* Fetch the SRAT table from ACPI */
+	status = acpi_get_table(ACPI_SIG_SRAT, 0, &table_header);
+	if (status == AE_NOT_FOUND) {
+		pr_warn("SRAT table not found\n");
+		return;
+	} else if (ACPI_FAILURE(status)) {
+		const char *err = acpi_format_exception(status);
+		pr_err("SRAT table error: %s\n", err);
+		return;
+	}
+
+	table_end = (unsigned long)table_header + table_header->length;
+
+	/* Parse all entries looking for a match. */
+	sub_header = (struct acpi_subtable_header *)
+			((unsigned long)table_header +
+			sizeof(struct acpi_table_srat));
+	subtable_len = sub_header->length;
+
+	while (((unsigned long)sub_header) + subtable_len  < table_end) {
+		/*
+		 * If length is 0, break from this loop to avoid
+		 * infinite loop.
+		 */
+		if (subtable_len == 0) {
+			pr_err("SRAT invalid zero length\n");
+			break;
+		}
+
+		switch (sub_header->type) {
+		case ACPI_SRAT_TYPE_CPU_AFFINITY:
+			cpu = (struct acpi_srat_cpu_affinity *)sub_header;
+			pxm = *((u32 *)cpu->proximity_domain_hi) << 8 |
+					cpu->proximity_domain_lo;
+			if (pxm > max_pxm)
+				max_pxm = pxm;
+			break;
+		case ACPI_SRAT_TYPE_GENERIC_AFFINITY:
+			gpu = (struct acpi_srat_generic_affinity *)sub_header;
+			bdf = *((u16 *)(&gpu->device_handle[0])) << 16 |
+					*((u16 *)(&gpu->device_handle[2]));
+			if (bdf == pci_id) {
+				found = true;
+				numa_node = pxm_to_node(gpu->proximity_domain);
+			}
+			break;
+		default:
+			break;
+		}
+
+		if (found)
+			break;
+
+		sub_header = (struct acpi_subtable_header *)
+				((unsigned long)sub_header + subtable_len);
+		subtable_len = sub_header->length;
+	}
+
+	acpi_put_table(table_header);
+
+	/* Workaround bad cpu-gpu binding case */
+	if (found && (numa_node < 0 ||
+			numa_node > pxm_to_node(max_pxm)))
+		numa_node = 0;
+
+	if (numa_node != NUMA_NO_NODE)
+		set_dev_node(&kdev->pdev->dev, numa_node);
+}
+#endif
+
 /* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU
  * to its NUMA node
  *	@avail_size: Available size in the memory
@@ -1140,11 +1988,17 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
 		 */
 		sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
 		sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
+		sub_type_hdr->num_hops_xgmi = 1;
 	} else {
 		sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
 	}
 
 	sub_type_hdr->proximity_domain_from = proximity_domain;
+
+#ifdef CONFIG_ACPI_NUMA
+	if (kdev->pdev->dev.numa_node == NUMA_NO_NODE)
+		kfd_find_numa_node_in_srat(kdev);
+#endif
 #ifdef CONFIG_NUMA
 	if (kdev->pdev->dev.numa_node == NUMA_NO_NODE)
 		sub_type_hdr->proximity_domain_to = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 357b9bf62a1c..6b57dfd2cd2a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -26,10 +26,12 @@
 #include "kfd_priv.h"
 #include "kfd_device_queue_manager.h"
 #include "kfd_pm4_headers_vi.h"
+#include "kfd_pm4_headers_aldebaran.h"
 #include "cwsr_trap_handler.h"
 #include "kfd_iommu.h"
 #include "amdgpu_amdkfd.h"
 #include "kfd_smi_events.h"
+#include "kfd_migrate.h"
 
 #define MQD_SIZE_ALIGNED 768
 
@@ -80,6 +82,8 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
 	[CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
 	[CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
 	[CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
+	[CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd,
+	[CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd,
 };
 
 #ifdef KFD_SUPPORT_IOMMU_V2
@@ -556,6 +560,41 @@ static const struct kfd_device_info dimgrey_cavefish_device_info = {
 	.num_sdma_queues_per_engine = 8,
 };
 
+static const struct kfd_device_info beige_goby_device_info = {
+	.asic_family = CHIP_BEIGE_GOBY,
+	.asic_name = "beige_goby",
+	.max_pasid_bits = 16,
+	.max_no_of_hqd  = 24,
+	.doorbell_size  = 8,
+	.ih_ring_entry_size = 8 * sizeof(uint32_t),
+	.event_interrupt_class = &event_interrupt_class_v9,
+	.num_of_watch_points = 4,
+	.mqd_size_aligned = MQD_SIZE_ALIGNED,
+	.needs_iommu_device = false,
+	.supports_cwsr = true,
+	.needs_pci_atomics = true,
+	.num_sdma_engines = 1,
+	.num_xgmi_sdma_engines = 0,
+	.num_sdma_queues_per_engine = 8,
+};
+
+static const struct kfd_device_info yellow_carp_device_info = {
+	.asic_family = CHIP_YELLOW_CARP,
+	.asic_name = "yellow_carp",
+	.max_pasid_bits = 16,
+	.max_no_of_hqd  = 24,
+	.doorbell_size  = 8,
+	.ih_ring_entry_size = 8 * sizeof(uint32_t),
+	.event_interrupt_class = &event_interrupt_class_v9,
+	.num_of_watch_points = 4,
+	.mqd_size_aligned = MQD_SIZE_ALIGNED,
+	.needs_iommu_device = false,
+	.supports_cwsr = true,
+	.needs_pci_atomics = false,
+	.num_sdma_engines = 1,
+	.num_xgmi_sdma_engines = 0,
+	.num_sdma_queues_per_engine = 2,
+};
 
 /* For each entry, [0] is regular and [1] is virtualisation device. */
 static const struct kfd_device_info *kfd_supported_devices[][2] = {
@@ -576,7 +615,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
 	[CHIP_VEGA20] = {&vega20_device_info, NULL},
 	[CHIP_RENOIR] = {&renoir_device_info, NULL},
 	[CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
-	[CHIP_ALDEBARAN] = {&aldebaran_device_info, NULL},
+	[CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info},
 	[CHIP_NAVI10] = {&navi10_device_info, NULL},
 	[CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
 	[CHIP_NAVI14] = {&navi14_device_info, NULL},
@@ -584,6 +623,8 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
 	[CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
 	[CHIP_VANGOGH] = {&vangogh_device_info, NULL},
 	[CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
+	[CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info},
+	[CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL},
 };
 
 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
@@ -697,7 +738,9 @@ static int kfd_gws_init(struct kfd_dev *kfd)
 			&& kfd->device_info->asic_family <= CHIP_RAVEN
 			&& kfd->mec2_fw_version >= 0x1b3)
 		|| (kfd->device_info->asic_family == CHIP_ARCTURUS
-			&& kfd->mec2_fw_version >= 0x30))
+			&& kfd->mec2_fw_version >= 0x30)
+		|| (kfd->device_info->asic_family == CHIP_ALDEBARAN
+			&& kfd->mec2_fw_version >= 0x28))
 		ret = amdgpu_amdkfd_alloc_gws(kfd->kgd,
 				amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws);
 
@@ -713,7 +756,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 			 struct drm_device *ddev,
 			 const struct kgd2kfd_shared_resources *gpu_resources)
 {
-	unsigned int size;
+	unsigned int size, map_process_packet_size;
 
 	kfd->ddev = ddev;
 	kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
@@ -748,7 +791,11 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 	 * calculate max size of runlist packet.
 	 * There can be only 2 packets at once
 	 */
-	size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
+	map_process_packet_size =
+			kfd->device_info->asic_family == CHIP_ALDEBARAN ?
+				sizeof(struct pm4_mes_map_process_aldebaran) :
+					sizeof(struct pm4_mes_map_process);
+	size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
 		max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
 		+ sizeof(struct pm4_mes_runlist)) * 2;
 
@@ -814,6 +861,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 
 	kfd_cwsr_init(kfd);
 
+	svm_migrate_init((struct amdgpu_device *)kfd->kgd);
+
 	if (kfd_resume(kfd))
 		goto kfd_resume_error;
 
@@ -861,7 +910,7 @@ out:
 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 {
 	if (kfd->init_complete) {
-		kgd2kfd_suspend(kfd, false);
+		svm_migrate_fini((struct amdgpu_device *)kfd->kgd);
 		device_queue_manager_uninit(kfd->dqm);
 		kfd_interrupt_exit(kfd);
 		kfd_topology_remove_device(kfd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index d3eaa1549bd7..16a1713808c2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -248,7 +248,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,
 			qpd->vmid,
 			qpd->page_table_base);
 	/* invalidate the VM context after pasid and vmid mapping is set up */
-	kfd_flush_tlb(qpd_to_pdd(qpd));
+	kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
 
 	if (dqm->dev->kfd2kgd->set_scratch_backing_va)
 		dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd,
@@ -284,7 +284,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
 		if (flush_texture_cache_nocpsch(q->device, qpd))
 			pr_err("Failed to flush TC\n");
 
-	kfd_flush_tlb(qpd_to_pdd(qpd));
+	kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
 
 	/* Release the vmid mapping */
 	set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
@@ -486,9 +486,6 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
 	if (retval == -ETIME)
 		qpd->reset_wavefronts = true;
 
-
-	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
-
 	list_del(&q->list);
 	if (list_empty(&qpd->queues_list)) {
 		if (qpd->reset_wavefronts) {
@@ -523,6 +520,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
 	int retval;
 	uint64_t sdma_val = 0;
 	struct kfd_process_device *pdd = qpd_to_pdd(qpd);
+	struct mqd_manager *mqd_mgr =
+		dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
 
 	/* Get the SDMA queue stats */
 	if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
@@ -540,6 +539,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
 		pdd->sdma_past_activity_counter += sdma_val;
 	dqm_unlock(dqm);
 
+	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
+
 	return retval;
 }
 
@@ -738,7 +739,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
 
 	pdd = qpd_to_pdd(qpd);
 	/* Retrieve PD base */
-	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
+	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
 
 	dqm_lock(dqm);
 	if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
@@ -760,7 +761,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
 				dqm->dev->kgd,
 				qpd->vmid,
 				qpd->page_table_base);
-		kfd_flush_tlb(pdd);
+		kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
 	}
 
 	/* Take a safe reference to the mm_struct, which may otherwise
@@ -821,7 +822,7 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
 
 	pdd = qpd_to_pdd(qpd);
 	/* Retrieve PD base */
-	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
+	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
 
 	dqm_lock(dqm);
 	if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
@@ -873,7 +874,7 @@ static int register_process(struct device_queue_manager *dqm,
 
 	pdd = qpd_to_pdd(qpd);
 	/* Retrieve PD base */
-	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
+	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
 
 	dqm_lock(dqm);
 	list_add(&n->list, &dqm->queues);
@@ -1629,7 +1630,7 @@ out:
 static int process_termination_nocpsch(struct device_queue_manager *dqm,
 		struct qcm_process_device *qpd)
 {
-	struct queue *q, *next;
+	struct queue *q;
 	struct device_process_node *cur, *next_dpn;
 	int retval = 0;
 	bool found = false;
@@ -1637,12 +1638,19 @@ static int process_termination_nocpsch(struct device_queue_manager *dqm,
 	dqm_lock(dqm);
 
 	/* Clear all user mode queues */
-	list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
+	while (!list_empty(&qpd->queues_list)) {
+		struct mqd_manager *mqd_mgr;
 		int ret;
 
+		q = list_first_entry(&qpd->queues_list, struct queue, list);
+		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+				q->properties.type)];
 		ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
 		if (ret)
 			retval = ret;
+		dqm_unlock(dqm);
+		mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
+		dqm_lock(dqm);
 	}
 
 	/* Unregister process */
@@ -1674,36 +1682,34 @@ static int get_wave_state(struct device_queue_manager *dqm,
 			  u32 *save_area_used_size)
 {
 	struct mqd_manager *mqd_mgr;
-	int r;
 
 	dqm_lock(dqm);
 
-	if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
-	    q->properties.is_active || !q->device->cwsr_enabled) {
-		r = -EINVAL;
-		goto dqm_unlock;
-	}
-
 	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
 
-	if (!mqd_mgr->get_wave_state) {
-		r = -EINVAL;
-		goto dqm_unlock;
+	if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
+	    q->properties.is_active || !q->device->cwsr_enabled ||
+	    !mqd_mgr->get_wave_state) {
+		dqm_unlock(dqm);
+		return -EINVAL;
 	}
 
-	r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
-			ctl_stack_used_size, save_area_used_size);
-
-dqm_unlock:
 	dqm_unlock(dqm);
-	return r;
+
+	/*
+	 * get_wave_state is outside the dqm lock to prevent circular locking
+	 * and the queue should be protected against destruction by the process
+	 * lock.
+	 */
+	return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
+			ctl_stack_used_size, save_area_used_size);
 }
 
 static int process_termination_cpsch(struct device_queue_manager *dqm,
 		struct qcm_process_device *qpd)
 {
 	int retval;
-	struct queue *q, *next;
+	struct queue *q;
 	struct kernel_queue *kq, *kq_next;
 	struct mqd_manager *mqd_mgr;
 	struct device_process_node *cur, *next_dpn;
@@ -1760,24 +1766,26 @@ static int process_termination_cpsch(struct device_queue_manager *dqm,
 		qpd->reset_wavefronts = false;
 	}
 
-	dqm_unlock(dqm);
-
-	/* Outside the DQM lock because under the DQM lock we can't do
-	 * reclaim or take other locks that others hold while reclaiming.
-	 */
-	if (found)
-		kfd_dec_compute_active(dqm->dev);
-
 	/* Lastly, free mqd resources.
 	 * Do free_mqd() after dqm_unlock to avoid circular locking.
 	 */
-	list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
+	while (!list_empty(&qpd->queues_list)) {
+		q = list_first_entry(&qpd->queues_list, struct queue, list);
 		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
 				q->properties.type)];
 		list_del(&q->list);
 		qpd->queue_count--;
+		dqm_unlock(dqm);
 		mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
+		dqm_lock(dqm);
 	}
+	dqm_unlock(dqm);
+
+	/* Outside the DQM lock because under the DQM lock we can't do
+	 * reclaim or take other locks that others hold while reclaiming.
+	 */
+	if (found)
+		kfd_dec_compute_active(dqm->dev);
 
 	return retval;
 }
@@ -1936,6 +1944,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		device_queue_manager_init_v10_navi10(&dqm->asic_ops);
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
index eca6331efa94..b5c3d13643f1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
@@ -61,10 +61,19 @@ static int update_qpd_v9(struct device_queue_manager *dqm,
 		qpd->sh_mem_config =
 				SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 					SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
-		if (dqm->dev->noretry &&
-		    !dqm->dev->use_iommu_v2)
+
+		if (dqm->dev->device_info->asic_family == CHIP_ALDEBARAN) {
+			/* Aldebaran can safely support different XNACK modes
+			 * per process
+			 */
+			if (!pdd->process->xnack_enabled)
+				qpd->sh_mem_config |=
+					1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
+		} else if (dqm->dev->noretry &&
+			   !dqm->dev->use_iommu_v2) {
 			qpd->sh_mem_config |=
 				1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
+		}
 
 		qpd->sh_mem_ape1_limit = 0;
 		qpd->sh_mem_ape1_base = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index ba2c2ce0c55a..3eea4edee355 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -1050,3 +1050,44 @@ void kfd_signal_reset_event(struct kfd_dev *dev)
 	}
 	srcu_read_unlock(&kfd_processes_srcu, idx);
 }
+
+void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid)
+{
+	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
+	struct kfd_hsa_memory_exception_data memory_exception_data;
+	struct kfd_hsa_hw_exception_data hw_exception_data;
+	struct kfd_event *ev;
+	uint32_t id = KFD_FIRST_NONSIGNAL_EVENT_ID;
+
+	if (!p)
+		return; /* Presumably process exited. */
+
+	memset(&hw_exception_data, 0, sizeof(hw_exception_data));
+	hw_exception_data.gpu_id = dev->id;
+	hw_exception_data.memory_lost = 1;
+	hw_exception_data.reset_cause = KFD_HW_EXCEPTION_ECC;
+
+	memset(&memory_exception_data, 0, sizeof(memory_exception_data));
+	memory_exception_data.ErrorType = KFD_MEM_ERR_POISON_CONSUMED;
+	memory_exception_data.gpu_id = dev->id;
+	memory_exception_data.failure.imprecise = true;
+
+	mutex_lock(&p->event_mutex);
+	idr_for_each_entry_continue(&p->event_idr, ev, id) {
+		if (ev->type == KFD_EVENT_TYPE_HW_EXCEPTION) {
+			ev->hw_exception_data = hw_exception_data;
+			set_event(ev);
+		}
+
+		if (ev->type == KFD_EVENT_TYPE_MEMORY) {
+			ev->memory_exception_data = memory_exception_data;
+			set_event(ev);
+		}
+	}
+	mutex_unlock(&p->event_mutex);
+
+	/* user application will handle SIGBUS signal */
+	send_sig(SIGBUS, p->lead_thread, 0);
+
+	kfd_unref_process(p);
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index a2c9063076cc..a9b329f0f862 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -420,6 +420,8 @@ int kfd_init_apertures(struct kfd_process *process)
 			case CHIP_NAVY_FLOUNDER:
 			case CHIP_VANGOGH:
 			case CHIP_DIMGREY_CAVEFISH:
+			case CHIP_BEIGE_GOBY:
+			case CHIP_YELLOW_CARP:
 				kfd_init_apertures_v9(pdd, id);
 				break;
 			default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
index 696944fa0177..12d91e53556c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
@@ -25,7 +25,6 @@
 #include "soc15_int.h"
 #include "kfd_device_queue_manager.h"
 #include "kfd_smi_events.h"
-#include "amdgpu.h"
 
 enum SQ_INTERRUPT_WORD_ENCODING {
 	SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
@@ -231,7 +230,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
 					sq_intr_err);
 				if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
 					sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
-					kfd_signal_hw_exception_event(pasid);
+					kfd_signal_poison_consumed_event(dev, pasid);
 					amdgpu_amdkfd_gpu_reset(dev->kgd);
 					return;
 				}
@@ -250,8 +249,13 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
 		   client_id == SOC15_IH_CLIENTID_SDMA5 ||
 		   client_id == SOC15_IH_CLIENTID_SDMA6 ||
 		   client_id == SOC15_IH_CLIENTID_SDMA7) {
-		if (source_id == SOC15_INTSRC_SDMA_TRAP)
+		if (source_id == SOC15_INTSRC_SDMA_TRAP) {
 			kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
+		} else if (source_id == SOC15_INTSRC_SDMA_ECC) {
+			kfd_signal_poison_consumed_event(dev, pasid);
+			amdgpu_amdkfd_gpu_reset(dev->kgd);
+			return;
+		}
 	} else if (client_id == SOC15_IH_CLIENTID_VMC ||
 		   client_id == SOC15_IH_CLIENTID_VMC1 ||
 		   client_id == SOC15_IH_CLIENTID_UTCL2) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
new file mode 100644
index 000000000000..2660f03e63a7
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -0,0 +1,889 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright 2020-2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/types.h>
+#include <linux/hmm.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include "amdgpu_sync.h"
+#include "amdgpu_object.h"
+#include "amdgpu_vm.h"
+#include "amdgpu_mn.h"
+#include "amdgpu_res_cursor.h"
+#include "kfd_priv.h"
+#include "kfd_svm.h"
+#include "kfd_migrate.h"
+
+static uint64_t
+svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, uint64_t addr)
+{
+	return addr + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM);
+}
+
+static int
+svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages,
+		     dma_addr_t *addr, uint64_t *gart_addr, uint64_t flags)
+{
+	struct amdgpu_device *adev = ring->adev;
+	struct amdgpu_job *job;
+	unsigned int num_dw, num_bytes;
+	struct dma_fence *fence;
+	uint64_t src_addr, dst_addr;
+	uint64_t pte_flags;
+	void *cpu_addr;
+	int r;
+
+	/* use gart window 0 */
+	*gart_addr = adev->gmc.gart_start;
+
+	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
+	num_bytes = npages * 8;
+
+	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
+				     AMDGPU_IB_POOL_DELAYED, &job);
+	if (r)
+		return r;
+
+	src_addr = num_dw * 4;
+	src_addr += job->ibs[0].gpu_addr;
+
+	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
+				dst_addr, num_bytes, false);
+
+	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+	WARN_ON(job->ibs[0].length_dw > num_dw);
+
+	pte_flags = AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
+	pte_flags |= AMDGPU_PTE_SYSTEM | AMDGPU_PTE_SNOOPED;
+	if (!(flags & KFD_IOCTL_SVM_FLAG_GPU_RO))
+		pte_flags |= AMDGPU_PTE_WRITEABLE;
+	pte_flags |= adev->gart.gart_pte_flags;
+
+	cpu_addr = &job->ibs[0].ptr[num_dw];
+
+	r = amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr);
+	if (r)
+		goto error_free;
+
+	r = amdgpu_job_submit(job, &adev->mman.entity,
+			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
+	if (r)
+		goto error_free;
+
+	dma_fence_put(fence);
+
+	return r;
+
+error_free:
+	amdgpu_job_free(job);
+	return r;
+}
+
+/**
+ * svm_migrate_copy_memory_gart - sdma copy data between ram and vram
+ *
+ * @adev: amdgpu device the sdma ring running
+ * @src: source page address array
+ * @dst: destination page address array
+ * @npages: number of pages to copy
+ * @direction: enum MIGRATION_COPY_DIR
+ * @mfence: output, sdma fence to signal after sdma is done
+ *
+ * ram address uses GART table continuous entries mapping to ram pages,
+ * vram address uses direct mapping of vram pages, which must have npages
+ * number of continuous pages.
+ * GART update and sdma uses same buf copy function ring, sdma is splited to
+ * multiple GTT_MAX_PAGES transfer, all sdma operations are serialized, wait for
+ * the last sdma finish fence which is returned to check copy memory is done.
+ *
+ * Context: Process context, takes and releases gtt_window_lock
+ *
+ * Return:
+ * 0 - OK, otherwise error code
+ */
+
+static int
+svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
+			     uint64_t *vram, uint64_t npages,
+			     enum MIGRATION_COPY_DIR direction,
+			     struct dma_fence **mfence)
+{
+	const uint64_t GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;
+	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+	uint64_t gart_s, gart_d;
+	struct dma_fence *next;
+	uint64_t size;
+	int r;
+
+	mutex_lock(&adev->mman.gtt_window_lock);
+
+	while (npages) {
+		size = min(GTT_MAX_PAGES, npages);
+
+		if (direction == FROM_VRAM_TO_RAM) {
+			gart_s = svm_migrate_direct_mapping_addr(adev, *vram);
+			r = svm_migrate_gart_map(ring, size, sys, &gart_d, 0);
+
+		} else if (direction == FROM_RAM_TO_VRAM) {
+			r = svm_migrate_gart_map(ring, size, sys, &gart_s,
+						 KFD_IOCTL_SVM_FLAG_GPU_RO);
+			gart_d = svm_migrate_direct_mapping_addr(adev, *vram);
+		}
+		if (r) {
+			pr_debug("failed %d to create gart mapping\n", r);
+			goto out_unlock;
+		}
+
+		r = amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE,
+				       NULL, &next, false, true, false);
+		if (r) {
+			pr_debug("failed %d to copy memory\n", r);
+			goto out_unlock;
+		}
+
+		dma_fence_put(*mfence);
+		*mfence = next;
+		npages -= size;
+		if (npages) {
+			sys += size;
+			vram += size;
+		}
+	}
+
+out_unlock:
+	mutex_unlock(&adev->mman.gtt_window_lock);
+
+	return r;
+}
+
+/**
+ * svm_migrate_copy_done - wait for memory copy sdma is done
+ *
+ * @adev: amdgpu device the sdma memory copy is executing on
+ * @mfence: migrate fence
+ *
+ * Wait for dma fence is signaled, if the copy ssplit into multiple sdma
+ * operations, this is the last sdma operation fence.
+ *
+ * Context: called after svm_migrate_copy_memory
+ *
+ * Return:
+ * 0		- success
+ * otherwise	- error code from dma fence signal
+ */
+static int
+svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence)
+{
+	int r = 0;
+
+	if (mfence) {
+		r = dma_fence_wait(mfence, false);
+		dma_fence_put(mfence);
+		pr_debug("sdma copy memory fence done\n");
+	}
+
+	return r;
+}
+
+unsigned long
+svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr)
+{
+	return (addr + adev->kfd.dev->pgmap.range.start) >> PAGE_SHIFT;
+}
+
+static void
+svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn)
+{
+	struct page *page;
+
+	page = pfn_to_page(pfn);
+	page->zone_device_data = prange;
+	get_page(page);
+	lock_page(page);
+}
+
+static void
+svm_migrate_put_vram_page(struct amdgpu_device *adev, unsigned long addr)
+{
+	struct page *page;
+
+	page = pfn_to_page(svm_migrate_addr_to_pfn(adev, addr));
+	unlock_page(page);
+	put_page(page);
+}
+
+static unsigned long
+svm_migrate_addr(struct amdgpu_device *adev, struct page *page)
+{
+	unsigned long addr;
+
+	addr = page_to_pfn(page) << PAGE_SHIFT;
+	return (addr - adev->kfd.dev->pgmap.range.start);
+}
+
+static struct page *
+svm_migrate_get_sys_page(struct vm_area_struct *vma, unsigned long addr)
+{
+	struct page *page;
+
+	page = alloc_page_vma(GFP_HIGHUSER, vma, addr);
+	if (page)
+		lock_page(page);
+
+	return page;
+}
+
+static void svm_migrate_put_sys_page(unsigned long addr)
+{
+	struct page *page;
+
+	page = pfn_to_page(addr >> PAGE_SHIFT);
+	unlock_page(page);
+	put_page(page);
+}
+
+static int
+svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
+			 struct migrate_vma *migrate, struct dma_fence **mfence,
+			 dma_addr_t *scratch)
+{
+	uint64_t npages = migrate->cpages;
+	struct device *dev = adev->dev;
+	struct amdgpu_res_cursor cursor;
+	dma_addr_t *src;
+	uint64_t *dst;
+	uint64_t i, j;
+	int r;
+
+	pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start,
+		 prange->last);
+
+	src = scratch;
+	dst = (uint64_t *)(scratch + npages);
+
+	r = svm_range_vram_node_new(adev, prange, true);
+	if (r) {
+		pr_debug("failed %d get 0x%llx pages from vram\n", r, npages);
+		goto out;
+	}
+
+	amdgpu_res_first(prange->ttm_res, prange->offset << PAGE_SHIFT,
+			 npages << PAGE_SHIFT, &cursor);
+	for (i = j = 0; i < npages; i++) {
+		struct page *spage;
+
+		dst[i] = cursor.start + (j << PAGE_SHIFT);
+		migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);
+		svm_migrate_get_vram_page(prange, migrate->dst[i]);
+
+		migrate->dst[i] = migrate_pfn(migrate->dst[i]);
+		migrate->dst[i] |= MIGRATE_PFN_LOCKED;
+
+		if (migrate->src[i] & MIGRATE_PFN_VALID) {
+			spage = migrate_pfn_to_page(migrate->src[i]);
+			src[i] = dma_map_page(dev, spage, 0, PAGE_SIZE,
+					      DMA_TO_DEVICE);
+			r = dma_mapping_error(dev, src[i]);
+			if (r) {
+				pr_debug("failed %d dma_map_page\n", r);
+				goto out_free_vram_pages;
+			}
+		} else {
+			if (j) {
+				r = svm_migrate_copy_memory_gart(
+						adev, src + i - j,
+						dst + i - j, j,
+						FROM_RAM_TO_VRAM,
+						mfence);
+				if (r)
+					goto out_free_vram_pages;
+				amdgpu_res_next(&cursor, j << PAGE_SHIFT);
+				j = 0;
+			} else {
+				amdgpu_res_next(&cursor, PAGE_SIZE);
+			}
+			continue;
+		}
+
+		pr_debug("dma mapping src to 0x%llx, page_to_pfn 0x%lx\n",
+			 src[i] >> PAGE_SHIFT, page_to_pfn(spage));
+
+		if (j >= (cursor.size >> PAGE_SHIFT) - 1 && i < npages - 1) {
+			r = svm_migrate_copy_memory_gart(adev, src + i - j,
+							 dst + i - j, j + 1,
+							 FROM_RAM_TO_VRAM,
+							 mfence);
+			if (r)
+				goto out_free_vram_pages;
+			amdgpu_res_next(&cursor, (j + 1) * PAGE_SIZE);
+			j= 0;
+		} else {
+			j++;
+		}
+	}
+
+	r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j,
+					 FROM_RAM_TO_VRAM, mfence);
+
+out_free_vram_pages:
+	if (r) {
+		pr_debug("failed %d to copy memory to vram\n", r);
+		while (i--) {
+			svm_migrate_put_vram_page(adev, dst[i]);
+			migrate->dst[i] = 0;
+		}
+	}
+
+out:
+	return r;
+}
+
+static int
+svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
+			struct vm_area_struct *vma, uint64_t start,
+			uint64_t end)
+{
+	uint64_t npages = (end - start) >> PAGE_SHIFT;
+	struct dma_fence *mfence = NULL;
+	struct migrate_vma migrate;
+	dma_addr_t *scratch;
+	size_t size;
+	void *buf;
+	int r = -ENOMEM;
+	int retry = 0;
+
+	memset(&migrate, 0, sizeof(migrate));
+	migrate.vma = vma;
+	migrate.start = start;
+	migrate.end = end;
+	migrate.flags = MIGRATE_VMA_SELECT_SYSTEM;
+	migrate.pgmap_owner = adev;
+
+	size = 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t);
+	size *= npages;
+	buf = kvmalloc(size, GFP_KERNEL | __GFP_ZERO);
+	if (!buf)
+		goto out;
+
+	migrate.src = buf;
+	migrate.dst = migrate.src + npages;
+	scratch = (dma_addr_t *)(migrate.dst + npages);
+
+retry:
+	r = migrate_vma_setup(&migrate);
+	if (r) {
+		pr_debug("failed %d prepare migrate svms 0x%p [0x%lx 0x%lx]\n",
+			 r, prange->svms, prange->start, prange->last);
+		goto out_free;
+	}
+	if (migrate.cpages != npages) {
+		pr_debug("collect 0x%lx/0x%llx pages, retry\n", migrate.cpages,
+			 npages);
+		migrate_vma_finalize(&migrate);
+		if (retry++ >= 3) {
+			r = -ENOMEM;
+			pr_debug("failed %d migrate svms 0x%p [0x%lx 0x%lx]\n",
+				 r, prange->svms, prange->start, prange->last);
+			goto out_free;
+		}
+
+		goto retry;
+	}
+
+	if (migrate.cpages) {
+		r = svm_migrate_copy_to_vram(adev, prange, &migrate, &mfence,
+					     scratch);
+		migrate_vma_pages(&migrate);
+		svm_migrate_copy_done(adev, mfence);
+		migrate_vma_finalize(&migrate);
+	}
+
+	svm_range_dma_unmap(adev->dev, scratch, 0, npages);
+	svm_range_free_dma_mappings(prange);
+
+out_free:
+	kvfree(buf);
+out:
+	return r;
+}
+
+/**
+ * svm_migrate_ram_to_vram - migrate svm range from system to device
+ * @prange: range structure
+ * @best_loc: the device to migrate to
+ * @mm: the process mm structure
+ *
+ * Context: Process context, caller hold mmap read lock, svms lock, prange lock
+ *
+ * Return:
+ * 0 - OK, otherwise error code
+ */
+static int
+svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,
+			struct mm_struct *mm)
+{
+	unsigned long addr, start, end;
+	struct vm_area_struct *vma;
+	struct amdgpu_device *adev;
+	int r = 0;
+
+	if (prange->actual_loc == best_loc) {
+		pr_debug("svms 0x%p [0x%lx 0x%lx] already on best_loc 0x%x\n",
+			 prange->svms, prange->start, prange->last, best_loc);
+		return 0;
+	}
+
+	adev = svm_range_get_adev_by_id(prange, best_loc);
+	if (!adev) {
+		pr_debug("failed to get device by id 0x%x\n", best_loc);
+		return -ENODEV;
+	}
+
+	pr_debug("svms 0x%p [0x%lx 0x%lx] to gpu 0x%x\n", prange->svms,
+		 prange->start, prange->last, best_loc);
+
+	/* FIXME: workaround for page locking bug with invalid pages */
+	svm_range_prefault(prange, mm);
+
+	start = prange->start << PAGE_SHIFT;
+	end = (prange->last + 1) << PAGE_SHIFT;
+
+	for (addr = start; addr < end;) {
+		unsigned long next;
+
+		vma = find_vma(mm, addr);
+		if (!vma || addr < vma->vm_start)
+			break;
+
+		next = min(vma->vm_end, end);
+		r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next);
+		if (r) {
+			pr_debug("failed to migrate\n");
+			break;
+		}
+		addr = next;
+	}
+
+	if (!r)
+		prange->actual_loc = best_loc;
+
+	return r;
+}
+
+static void svm_migrate_page_free(struct page *page)
+{
+	/* Keep this function to avoid warning */
+}
+
+static int
+svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
+			struct migrate_vma *migrate, struct dma_fence **mfence,
+			dma_addr_t *scratch)
+{
+	uint64_t npages = migrate->cpages;
+	struct device *dev = adev->dev;
+	uint64_t *src;
+	dma_addr_t *dst;
+	struct page *dpage;
+	uint64_t i = 0, j;
+	uint64_t addr;
+	int r = 0;
+
+	pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start,
+		 prange->last);
+
+	addr = prange->start << PAGE_SHIFT;
+
+	src = (uint64_t *)(scratch + npages);
+	dst = scratch;
+
+	for (i = 0, j = 0; i < npages; i++, j++, addr += PAGE_SIZE) {
+		struct page *spage;
+
+		spage = migrate_pfn_to_page(migrate->src[i]);
+		if (!spage) {
+			pr_debug("failed get spage svms 0x%p [0x%lx 0x%lx]\n",
+				 prange->svms, prange->start, prange->last);
+			r = -ENOMEM;
+			goto out_oom;
+		}
+		src[i] = svm_migrate_addr(adev, spage);
+		if (i > 0 && src[i] != src[i - 1] + PAGE_SIZE) {
+			r = svm_migrate_copy_memory_gart(adev, dst + i - j,
+							 src + i - j, j,
+							 FROM_VRAM_TO_RAM,
+							 mfence);
+			if (r)
+				goto out_oom;
+			j = 0;
+		}
+
+		dpage = svm_migrate_get_sys_page(migrate->vma, addr);
+		if (!dpage) {
+			pr_debug("failed get page svms 0x%p [0x%lx 0x%lx]\n",
+				 prange->svms, prange->start, prange->last);
+			r = -ENOMEM;
+			goto out_oom;
+		}
+
+		dst[i] = dma_map_page(dev, dpage, 0, PAGE_SIZE, DMA_FROM_DEVICE);
+		r = dma_mapping_error(dev, dst[i]);
+		if (r) {
+			pr_debug("failed %d dma_map_page\n", r);
+			goto out_oom;
+		}
+
+		pr_debug("dma mapping dst to 0x%llx, page_to_pfn 0x%lx\n",
+			      dst[i] >> PAGE_SHIFT, page_to_pfn(dpage));
+
+		migrate->dst[i] = migrate_pfn(page_to_pfn(dpage));
+		migrate->dst[i] |= MIGRATE_PFN_LOCKED;
+	}
+
+	r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j,
+					 FROM_VRAM_TO_RAM, mfence);
+
+out_oom:
+	if (r) {
+		pr_debug("failed %d copy to ram\n", r);
+		while (i--) {
+			svm_migrate_put_sys_page(dst[i]);
+			migrate->dst[i] = 0;
+		}
+	}
+
+	return r;
+}
+
+static int
+svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
+		       struct vm_area_struct *vma, uint64_t start, uint64_t end)
+{
+	uint64_t npages = (end - start) >> PAGE_SHIFT;
+	struct dma_fence *mfence = NULL;
+	struct migrate_vma migrate;
+	dma_addr_t *scratch;
+	size_t size;
+	void *buf;
+	int r = -ENOMEM;
+
+	memset(&migrate, 0, sizeof(migrate));
+	migrate.vma = vma;
+	migrate.start = start;
+	migrate.end = end;
+	migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
+	migrate.pgmap_owner = adev;
+
+	size = 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t);
+	size *= npages;
+	buf = kvmalloc(size, GFP_KERNEL | __GFP_ZERO);
+	if (!buf)
+		goto out;
+
+	migrate.src = buf;
+	migrate.dst = migrate.src + npages;
+	scratch = (dma_addr_t *)(migrate.dst + npages);
+
+	r = migrate_vma_setup(&migrate);
+	if (r) {
+		pr_debug("failed %d prepare migrate svms 0x%p [0x%lx 0x%lx]\n",
+			 r, prange->svms, prange->start, prange->last);
+		goto out_free;
+	}
+
+	pr_debug("cpages %ld\n", migrate.cpages);
+
+	if (migrate.cpages) {
+		r = svm_migrate_copy_to_ram(adev, prange, &migrate, &mfence,
+					    scratch);
+		migrate_vma_pages(&migrate);
+		svm_migrate_copy_done(adev, mfence);
+		migrate_vma_finalize(&migrate);
+	} else {
+		pr_debug("failed collect migrate device pages [0x%lx 0x%lx]\n",
+			 prange->start, prange->last);
+	}
+
+	svm_range_dma_unmap(adev->dev, scratch, 0, npages);
+
+out_free:
+	kvfree(buf);
+out:
+	return r;
+}
+
+/**
+ * svm_migrate_vram_to_ram - migrate svm range from device to system
+ * @prange: range structure
+ * @mm: process mm, use current->mm if NULL
+ *
+ * Context: Process context, caller hold mmap read lock, svms lock, prange lock
+ *
+ * Return:
+ * 0 - OK, otherwise error code
+ */
+int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm)
+{
+	struct amdgpu_device *adev;
+	struct vm_area_struct *vma;
+	unsigned long addr;
+	unsigned long start;
+	unsigned long end;
+	int r = 0;
+
+	if (!prange->actual_loc) {
+		pr_debug("[0x%lx 0x%lx] already migrated to ram\n",
+			 prange->start, prange->last);
+		return 0;
+	}
+
+	adev = svm_range_get_adev_by_id(prange, prange->actual_loc);
+	if (!adev) {
+		pr_debug("failed to get device by id 0x%x\n",
+			 prange->actual_loc);
+		return -ENODEV;
+	}
+
+	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] from gpu 0x%x to ram\n",
+		 prange->svms, prange, prange->start, prange->last,
+		 prange->actual_loc);
+
+	start = prange->start << PAGE_SHIFT;
+	end = (prange->last + 1) << PAGE_SHIFT;
+
+	for (addr = start; addr < end;) {
+		unsigned long next;
+
+		vma = find_vma(mm, addr);
+		if (!vma || addr < vma->vm_start)
+			break;
+
+		next = min(vma->vm_end, end);
+		r = svm_migrate_vma_to_ram(adev, prange, vma, addr, next);
+		if (r) {
+			pr_debug("failed %d to migrate\n", r);
+			break;
+		}
+		addr = next;
+	}
+
+	if (!r) {
+		svm_range_vram_node_free(prange);
+		prange->actual_loc = 0;
+	}
+	return r;
+}
+
+/**
+ * svm_migrate_vram_to_vram - migrate svm range from device to device
+ * @prange: range structure
+ * @best_loc: the device to migrate to
+ * @mm: process mm, use current->mm if NULL
+ *
+ * Context: Process context, caller hold mmap read lock, svms lock, prange lock
+ *
+ * Return:
+ * 0 - OK, otherwise error code
+ */
+static int
+svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,
+			 struct mm_struct *mm)
+{
+	int r;
+
+	/*
+	 * TODO: for both devices with PCIe large bar or on same xgmi hive, skip
+	 * system memory as migration bridge
+	 */
+
+	pr_debug("from gpu 0x%x to gpu 0x%x\n", prange->actual_loc, best_loc);
+
+	r = svm_migrate_vram_to_ram(prange, mm);
+	if (r)
+		return r;
+
+	return svm_migrate_ram_to_vram(prange, best_loc, mm);
+}
+
+int
+svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,
+		    struct mm_struct *mm)
+{
+	if  (!prange->actual_loc)
+		return svm_migrate_ram_to_vram(prange, best_loc, mm);
+	else
+		return svm_migrate_vram_to_vram(prange, best_loc, mm);
+
+}
+
+/**
+ * svm_migrate_to_ram - CPU page fault handler
+ * @vmf: CPU vm fault vma, address
+ *
+ * Context: vm fault handler, caller holds the mmap read lock
+ *
+ * Return:
+ * 0 - OK
+ * VM_FAULT_SIGBUS - notice application to have SIGBUS page fault
+ */
+static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
+{
+	unsigned long addr = vmf->address;
+	struct vm_area_struct *vma;
+	enum svm_work_list_ops op;
+	struct svm_range *parent;
+	struct svm_range *prange;
+	struct kfd_process *p;
+	struct mm_struct *mm;
+	int r = 0;
+
+	vma = vmf->vma;
+	mm = vma->vm_mm;
+
+	p = kfd_lookup_process_by_mm(vma->vm_mm);
+	if (!p) {
+		pr_debug("failed find process at fault address 0x%lx\n", addr);
+		return VM_FAULT_SIGBUS;
+	}
+	addr >>= PAGE_SHIFT;
+	pr_debug("CPU page fault svms 0x%p address 0x%lx\n", &p->svms, addr);
+
+	mutex_lock(&p->svms.lock);
+
+	prange = svm_range_from_addr(&p->svms, addr, &parent);
+	if (!prange) {
+		pr_debug("cannot find svm range at 0x%lx\n", addr);
+		r = -EFAULT;
+		goto out;
+	}
+
+	mutex_lock(&parent->migrate_mutex);
+	if (prange != parent)
+		mutex_lock_nested(&prange->migrate_mutex, 1);
+
+	if (!prange->actual_loc)
+		goto out_unlock_prange;
+
+	svm_range_lock(parent);
+	if (prange != parent)
+		mutex_lock_nested(&prange->lock, 1);
+	r = svm_range_split_by_granularity(p, mm, addr, parent, prange);
+	if (prange != parent)
+		mutex_unlock(&prange->lock);
+	svm_range_unlock(parent);
+	if (r) {
+		pr_debug("failed %d to split range by granularity\n", r);
+		goto out_unlock_prange;
+	}
+
+	r = svm_migrate_vram_to_ram(prange, mm);
+	if (r)
+		pr_debug("failed %d migrate 0x%p [0x%lx 0x%lx] to ram\n", r,
+			 prange, prange->start, prange->last);
+
+	/* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */
+	if (p->xnack_enabled && parent == prange)
+		op = SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP;
+	else
+		op = SVM_OP_UPDATE_RANGE_NOTIFIER;
+	svm_range_add_list_work(&p->svms, parent, mm, op);
+	schedule_deferred_list_work(&p->svms);
+
+out_unlock_prange:
+	if (prange != parent)
+		mutex_unlock(&prange->migrate_mutex);
+	mutex_unlock(&parent->migrate_mutex);
+out:
+	mutex_unlock(&p->svms.lock);
+	kfd_unref_process(p);
+
+	pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr);
+
+	return r ? VM_FAULT_SIGBUS : 0;
+}
+
+static const struct dev_pagemap_ops svm_migrate_pgmap_ops = {
+	.page_free		= svm_migrate_page_free,
+	.migrate_to_ram		= svm_migrate_to_ram,
+};
+
+/* Each VRAM page uses sizeof(struct page) on system memory */
+#define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page))
+
+int svm_migrate_init(struct amdgpu_device *adev)
+{
+	struct kfd_dev *kfddev = adev->kfd.dev;
+	struct dev_pagemap *pgmap;
+	struct resource *res;
+	unsigned long size;
+	void *r;
+
+	/* Page migration works on Vega10 or newer */
+	if (kfddev->device_info->asic_family < CHIP_VEGA10)
+		return -EINVAL;
+
+	pgmap = &kfddev->pgmap;
+	memset(pgmap, 0, sizeof(*pgmap));
+
+	/* TODO: register all vram to HMM for now.
+	 * should remove reserved size
+	 */
+	size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20);
+	res = devm_request_free_mem_region(adev->dev, &iomem_resource, size);
+	if (IS_ERR(res))
+		return -ENOMEM;
+
+	pgmap->type = MEMORY_DEVICE_PRIVATE;
+	pgmap->nr_range = 1;
+	pgmap->range.start = res->start;
+	pgmap->range.end = res->end;
+	pgmap->ops = &svm_migrate_pgmap_ops;
+	pgmap->owner = adev;
+	pgmap->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
+	r = devm_memremap_pages(adev->dev, pgmap);
+	if (IS_ERR(r)) {
+		pr_err("failed to register HMM device memory\n");
+		devm_release_mem_region(adev->dev, res->start,
+					res->end - res->start + 1);
+		return PTR_ERR(r);
+	}
+
+	pr_debug("reserve %ldMB system memory for VRAM pages struct\n",
+		 SVM_HMM_PAGE_STRUCT_SIZE(size) >> 20);
+
+	amdgpu_amdkfd_reserve_system_mem(SVM_HMM_PAGE_STRUCT_SIZE(size));
+
+	pr_info("HMM registered %ldMB device memory\n", size >> 20);
+
+	return 0;
+}
+
+void svm_migrate_fini(struct amdgpu_device *adev)
+{
+	struct dev_pagemap *pgmap = &adev->kfd.dev->pgmap;
+
+	devm_memunmap_pages(adev->dev, pgmap);
+	devm_release_mem_region(adev->dev, pgmap->range.start,
+				pgmap->range.end - pgmap->range.start + 1);
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
new file mode 100644
index 000000000000..0de76b5d4973
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2020-2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef KFD_MIGRATE_H_
+#define KFD_MIGRATE_H_
+
+#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
+
+#include <linux/rwsem.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/sched/mm.h>
+#include <linux/hmm.h>
+#include "kfd_priv.h"
+#include "kfd_svm.h"
+
+enum MIGRATION_COPY_DIR {
+	FROM_RAM_TO_VRAM = 0,
+	FROM_VRAM_TO_RAM
+};
+
+int svm_migrate_to_vram(struct svm_range *prange,  uint32_t best_loc,
+			struct mm_struct *mm);
+int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm);
+unsigned long
+svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr);
+
+int svm_migrate_init(struct amdgpu_device *adev);
+void svm_migrate_fini(struct amdgpu_device *adev);
+
+#else
+
+static inline int svm_migrate_init(struct amdgpu_device *adev)
+{
+	return 0;
+}
+static inline void svm_migrate_fini(struct amdgpu_device *adev)
+{
+	/* empty */
+}
+
+#endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */
+
+#endif /* KFD_MIGRATE_H_ */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index e840dd581719..d8e940f03102 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -124,14 +124,14 @@ static int pm_create_runlist_ib(struct packet_manager *pm,
 {
 	unsigned int alloc_size_bytes;
 	unsigned int *rl_buffer, rl_wptr, i;
-	int retval, proccesses_mapped;
+	int retval, processes_mapped;
 	struct device_process_node *cur;
 	struct qcm_process_device *qpd;
 	struct queue *q;
 	struct kernel_queue *kq;
 	bool is_over_subscription;
 
-	rl_wptr = retval = proccesses_mapped = 0;
+	rl_wptr = retval = processes_mapped = 0;
 
 	retval = pm_allocate_runlist_ib(pm, &rl_buffer, rl_gpu_addr,
 				&alloc_size_bytes, &is_over_subscription);
@@ -148,7 +148,7 @@ static int pm_create_runlist_ib(struct packet_manager *pm,
 	list_for_each_entry(cur, queues, list) {
 		qpd = cur->qpd;
 		/* build map process packet */
-		if (proccesses_mapped >= pm->dqm->processes_count) {
+		if (processes_mapped >= pm->dqm->processes_count) {
 			pr_debug("Not enough space left in runlist IB\n");
 			pm_release_ib(pm);
 			return -ENOMEM;
@@ -158,7 +158,7 @@ static int pm_create_runlist_ib(struct packet_manager *pm,
 		if (retval)
 			return retval;
 
-		proccesses_mapped++;
+		processes_mapped++;
 		inc_wptr(&rl_wptr, pm->pmf->map_process_size,
 				alloc_size_bytes);
 
@@ -242,7 +242,6 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
 	case CHIP_RAVEN:
 	case CHIP_RENOIR:
 	case CHIP_ARCTURUS:
-	case CHIP_ALDEBARAN:
 	case CHIP_NAVI10:
 	case CHIP_NAVI12:
 	case CHIP_NAVI14:
@@ -250,8 +249,13 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		pm->pmf = &kfd_v9_pm_funcs;
 		break;
+	case CHIP_ALDEBARAN:
+		pm->pmf = &kfd_aldebaran_pm_funcs;
+		break;
 	default:
 		WARN(1, "Unexpected ASIC family %u",
 		     dqm->dev->device_info->asic_family);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
index e3ba0cd3b6fa..7ea3f671b325 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
@@ -24,6 +24,7 @@
 #include "kfd_kernel_queue.h"
 #include "kfd_device_queue_manager.h"
 #include "kfd_pm4_headers_ai.h"
+#include "kfd_pm4_headers_aldebaran.h"
 #include "kfd_pm4_opcodes.h"
 #include "gc/gc_10_1_0_sh_mask.h"
 
@@ -35,7 +36,6 @@ static int pm_map_process_v9(struct packet_manager *pm,
 
 	packet = (struct pm4_mes_map_process *)buffer;
 	memset(buffer, 0, sizeof(struct pm4_mes_map_process));
-
 	packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
 					sizeof(struct pm4_mes_map_process));
 	packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
@@ -73,6 +73,45 @@ static int pm_map_process_v9(struct packet_manager *pm,
 	return 0;
 }
 
+static int pm_map_process_aldebaran(struct packet_manager *pm,
+		uint32_t *buffer, struct qcm_process_device *qpd)
+{
+	struct pm4_mes_map_process_aldebaran *packet;
+	uint64_t vm_page_table_base_addr = qpd->page_table_base;
+
+	packet = (struct pm4_mes_map_process_aldebaran *)buffer;
+	memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran));
+	packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
+			sizeof(struct pm4_mes_map_process_aldebaran));
+	packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
+	packet->bitfields2.process_quantum = 10;
+	packet->bitfields2.pasid = qpd->pqm->process->pasid;
+	packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
+	packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
+	packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
+	packet->bitfields14.num_oac = qpd->num_oac;
+	packet->bitfields14.sdma_enable = 1;
+	packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
+
+	packet->sh_mem_config = qpd->sh_mem_config;
+	packet->sh_mem_bases = qpd->sh_mem_bases;
+	if (qpd->tba_addr) {
+		packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
+		packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
+		packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
+	}
+
+	packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
+	packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
+
+	packet->vm_context_page_table_base_addr_lo32 =
+			lower_32_bits(vm_page_table_base_addr);
+	packet->vm_context_page_table_base_addr_hi32 =
+			upper_32_bits(vm_page_table_base_addr);
+
+	return 0;
+}
+
 static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,
 			uint64_t ib, size_t ib_size_in_dwords, bool chain)
 {
@@ -324,3 +363,20 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = {
 	.query_status_size	= sizeof(struct pm4_mes_query_status),
 	.release_mem_size	= 0,
 };
+
+const struct packet_manager_funcs kfd_aldebaran_pm_funcs = {
+	.map_process		= pm_map_process_aldebaran,
+	.runlist		= pm_runlist_v9,
+	.set_resources		= pm_set_resources_v9,
+	.map_queues		= pm_map_queues_v9,
+	.unmap_queues		= pm_unmap_queues_v9,
+	.query_status		= pm_query_status_v9,
+	.release_mem		= NULL,
+	.map_process_size	= sizeof(struct pm4_mes_map_process_aldebaran),
+	.runlist_size		= sizeof(struct pm4_mes_runlist),
+	.set_resources_size	= sizeof(struct pm4_mes_set_resources),
+	.map_queues_size	= sizeof(struct pm4_mes_map_queues),
+	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),
+	.query_status_size	= sizeof(struct pm4_mes_query_status),
+	.release_mem_size	= 0,
+};
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h
new file mode 100644
index 000000000000..f795ec815e2a
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*--------------------MES_MAP_PROCESS (PER DEBUG VMID)--------------------*/
+
+#ifndef PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
+#define PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
+
+struct pm4_mes_map_process_aldebaran {
+	union {
+		union PM4_MES_TYPE_3_HEADER header;	/* header */
+		uint32_t ordinal1;
+	};
+
+	union {
+		struct {
+			uint32_t pasid:16;	    /* 0 - 15  */
+			uint32_t single_memops:1;   /* 16      */
+			uint32_t reserved1:1;	    /* 17      */
+			uint32_t debug_vmid:4;	    /* 18 - 21 */
+			uint32_t new_debug:1;	    /* 22      */
+			uint32_t tmz:1;		    /* 23      */
+			uint32_t diq_enable:1;      /* 24      */
+			uint32_t process_quantum:7; /* 25 - 31 */
+		} bitfields2;
+		uint32_t ordinal2;
+	};
+
+	uint32_t vm_context_page_table_base_addr_lo32;
+
+	uint32_t vm_context_page_table_base_addr_hi32;
+
+	uint32_t sh_mem_bases;
+
+	uint32_t sh_mem_config;
+
+	uint32_t sq_shader_tba_lo;
+
+	uint32_t sq_shader_tba_hi;
+
+	uint32_t sq_shader_tma_lo;
+
+	uint32_t sq_shader_tma_hi;
+
+	uint32_t reserved6;
+
+	uint32_t gds_addr_lo;
+
+	uint32_t gds_addr_hi;
+
+	union {
+		struct {
+			uint32_t num_gws:7;
+			uint32_t sdma_enable:1;
+			uint32_t num_oac:4;
+			uint32_t gds_size_hi:4;
+			uint32_t gds_size:6;
+			uint32_t num_queues:10;
+		} bitfields14;
+		uint32_t ordinal14;
+	};
+
+	uint32_t spi_gdbg_per_vmid_cntl;
+
+	uint32_t tcp_watch_cntl[4];
+
+	uint32_t completion_signal_lo;
+
+	uint32_t completion_signal_hi;
+
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 0b6595f7acda..6dc22fa1e555 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -322,6 +322,9 @@ struct kfd_dev {
 	unsigned int max_doorbell_slices;
 
 	int noretry;
+
+	/* HMM page migration MEMORY_DEVICE_PRIVATE mapping */
+	struct dev_pagemap pgmap;
 };
 
 enum kfd_mempool {
@@ -669,7 +672,7 @@ struct kfd_process_device {
 
 	/* VM context for GPUVM allocations */
 	struct file *drm_file;
-	void *vm;
+	void *drm_priv;
 
 	/* GPUVM allocations storage */
 	struct idr alloc_idr;
@@ -731,6 +734,18 @@ struct kfd_process_device {
 
 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
 
+struct svm_range_list {
+	struct mutex			lock;
+	struct rb_root_cached		objects;
+	struct list_head		list;
+	struct work_struct		deferred_list_work;
+	struct list_head		deferred_range_list;
+	spinlock_t			deferred_list_lock;
+	atomic_t			evicted_ranges;
+	struct delayed_work		restore_work;
+	DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
+};
+
 /* Process data */
 struct kfd_process {
 	/*
@@ -809,6 +824,11 @@ struct kfd_process {
 	struct kobject *kobj;
 	struct kobject *kobj_queues;
 	struct attribute attr_pasid;
+
+	/* shared virtual memory registered by this process */
+	struct svm_range_list svms;
+
+	bool xnack_enabled;
 };
 
 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */
@@ -842,6 +862,20 @@ struct kfd_process *kfd_create_process(struct file *filep);
 struct kfd_process *kfd_get_process(const struct task_struct *);
 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid);
 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);
+
+int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id);
+int kfd_process_gpuid_from_kgd(struct kfd_process *p,
+			       struct amdgpu_device *adev, uint32_t *gpuid,
+			       uint32_t *gpuidx);
+static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p,
+				uint32_t gpuidx, uint32_t *gpuid) {
+	return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL;
+}
+static inline struct kfd_process_device *kfd_process_device_from_gpuidx(
+				struct kfd_process *p, uint32_t gpuidx) {
+	return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL;
+}
+
 void kfd_unref_process(struct kfd_process *p);
 int kfd_process_evict_queues(struct kfd_process *p);
 int kfd_process_restore_queues(struct kfd_process *p);
@@ -857,6 +891,8 @@ struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev,
 struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev,
 							struct kfd_process *p);
 
+bool kfd_process_xnack_mode(struct kfd_process *p, bool supported);
+
 int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process,
 			  struct vm_area_struct *vma);
 
@@ -1052,6 +1088,7 @@ struct packet_manager_funcs {
 
 extern const struct packet_manager_funcs kfd_vi_pm_funcs;
 extern const struct packet_manager_funcs kfd_v9_pm_funcs;
+extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs;
 
 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
 void pm_uninit(struct packet_manager *pm, bool hanging);
@@ -1107,7 +1144,9 @@ void kfd_signal_vm_fault_event(struct kfd_dev *dev, u32 pasid,
 
 void kfd_signal_reset_event(struct kfd_dev *dev);
 
-void kfd_flush_tlb(struct kfd_process_device *pdd);
+void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid);
+
+void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type);
 
 int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index d97e330a5022..09b98a83f670 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -42,6 +42,7 @@ struct mm_struct;
 #include "kfd_device_queue_manager.h"
 #include "kfd_dbgmgr.h"
 #include "kfd_iommu.h"
+#include "kfd_svm.h"
 
 /*
  * List of struct kfd_process (field kfd_process).
@@ -108,8 +109,6 @@ static void kfd_sdma_activity_worker(struct work_struct *work)
 
 	workarea = container_of(work, struct kfd_sdma_activity_handler_workarea,
 				sdma_activity_work);
-	if (!workarea)
-		return;
 
 	pdd = workarea->pdd;
 	if (!pdd)
@@ -250,7 +249,7 @@ cleanup:
 }
 
 /**
- * @kfd_get_cu_occupancy() - Collect number of waves in-flight on this device
+ * @kfd_get_cu_occupancy - Collect number of waves in-flight on this device
  * by current process. Translates acquired wave count into number of compute units
  * that are occupied.
  *
@@ -647,8 +646,9 @@ static void kfd_process_free_gpuvm(struct kgd_mem *mem,
 {
 	struct kfd_dev *dev = pdd->dev;
 
-	amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(dev->kgd, mem, pdd->vm);
-	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, mem, NULL);
+	amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(dev->kgd, mem, pdd->drm_priv);
+	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, mem, pdd->drm_priv,
+					       NULL);
 }
 
 /* kfd_process_alloc_gpuvm - Allocate GPU VM for the KFD process
@@ -667,11 +667,12 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd,
 	int err;
 
 	err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, gpu_va, size,
-						 pdd->vm, &mem, NULL, flags);
+						 pdd->drm_priv, &mem, NULL, flags);
 	if (err)
 		goto err_alloc_mem;
 
-	err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem, pdd->vm);
+	err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem,
+			pdd->drm_priv, NULL);
 	if (err)
 		goto err_map_mem;
 
@@ -712,7 +713,8 @@ sync_memory_failed:
 	return err;
 
 err_map_mem:
-	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, mem, NULL);
+	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, mem, pdd->drm_priv,
+					       NULL);
 err_alloc_mem:
 	*kptr = NULL;
 	return err;
@@ -901,13 +903,14 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd)
 		for (i = 0; i < p->n_pdds; i++) {
 			struct kfd_process_device *peer_pdd = p->pdds[i];
 
-			if (!peer_pdd->vm)
+			if (!peer_pdd->drm_priv)
 				continue;
 			amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
-				peer_pdd->dev->kgd, mem, peer_pdd->vm);
+				peer_pdd->dev->kgd, mem, peer_pdd->drm_priv);
 		}
 
-		amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->kgd, mem, NULL);
+		amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->kgd, mem,
+						       pdd->drm_priv, NULL);
 		kfd_process_device_remove_obj_handle(pdd, id);
 	}
 }
@@ -932,7 +935,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
 
 		if (pdd->drm_file) {
 			amdgpu_amdkfd_gpuvm_release_process_vm(
-					pdd->dev->kgd, pdd->vm);
+					pdd->dev->kgd, pdd->drm_priv);
 			fput(pdd->drm_file);
 		}
 
@@ -1000,6 +1003,7 @@ static void kfd_process_wq_release(struct work_struct *work)
 	kfd_iommu_unbind_process(p);
 
 	kfd_process_free_outstanding_kfd_bos(p);
+	svm_range_list_fini(p);
 
 	kfd_process_destroy_pdds(p);
 	dma_fence_put(p->ef);
@@ -1058,6 +1062,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn,
 
 	cancel_delayed_work_sync(&p->eviction_work);
 	cancel_delayed_work_sync(&p->restore_work);
+	cancel_delayed_work_sync(&p->svms.restore_work);
 
 	mutex_lock(&p->mutex);
 
@@ -1186,6 +1191,56 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd,
 	}
 }
 
+bool kfd_process_xnack_mode(struct kfd_process *p, bool supported)
+{
+	int i;
+
+	/* On most GFXv9 GPUs, the retry mode in the SQ must match the
+	 * boot time retry setting. Mixing processes with different
+	 * XNACK/retry settings can hang the GPU.
+	 *
+	 * Different GPUs can have different noretry settings depending
+	 * on HW bugs or limitations. We need to find at least one
+	 * XNACK mode for this process that's compatible with all GPUs.
+	 * Fortunately GPUs with retry enabled (noretry=0) can run code
+	 * built for XNACK-off. On GFXv9 it may perform slower.
+	 *
+	 * Therefore applications built for XNACK-off can always be
+	 * supported and will be our fallback if any GPU does not
+	 * support retry.
+	 */
+	for (i = 0; i < p->n_pdds; i++) {
+		struct kfd_dev *dev = p->pdds[i]->dev;
+
+		/* Only consider GFXv9 and higher GPUs. Older GPUs don't
+		 * support the SVM APIs and don't need to be considered
+		 * for the XNACK mode selection.
+		 */
+		if (dev->device_info->asic_family < CHIP_VEGA10)
+			continue;
+		/* Aldebaran can always support XNACK because it can support
+		 * per-process XNACK mode selection. But let the dev->noretry
+		 * setting still influence the default XNACK mode.
+		 */
+		if (supported &&
+		    dev->device_info->asic_family == CHIP_ALDEBARAN)
+			continue;
+
+		/* GFXv10 and later GPUs do not support shader preemption
+		 * during page faults. This can lead to poor QoS for queue
+		 * management and memory-manager-related preemptions or
+		 * even deadlocks.
+		 */
+		if (dev->device_info->asic_family >= CHIP_NAVI10)
+			return false;
+
+		if (dev->noretry)
+			return false;
+	}
+
+	return true;
+}
+
 /*
  * On return the kfd_process is fully operational and will be freed when the
  * mm is released
@@ -1224,6 +1279,13 @@ static struct kfd_process *create_process(const struct task_struct *thread)
 	if (err != 0)
 		goto err_init_apertures;
 
+	/* Check XNACK support after PDDs are created in kfd_init_apertures */
+	process->xnack_enabled = kfd_process_xnack_mode(process, false);
+
+	err = svm_range_list_init(process);
+	if (err)
+		goto err_init_svm_range_list;
+
 	/* alloc_notifier needs to find the process in the hash table */
 	hash_add_rcu(kfd_processes_table, &process->kfd_processes,
 			(uintptr_t)process->mm);
@@ -1246,6 +1308,8 @@ static struct kfd_process *create_process(const struct task_struct *thread)
 
 err_register_notifier:
 	hash_del_rcu(&process->kfd_processes);
+	svm_range_list_fini(process);
+err_init_svm_range_list:
 	kfd_process_free_outstanding_kfd_bos(process);
 	kfd_process_destroy_pdds(process);
 err_init_apertures:
@@ -1375,7 +1439,7 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,
 	if (!drm_file)
 		return -EINVAL;
 
-	if (pdd->vm)
+	if (pdd->drm_priv)
 		return -EBUSY;
 
 	p = pdd->process;
@@ -1383,13 +1447,12 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,
 
 	ret = amdgpu_amdkfd_gpuvm_acquire_process_vm(
 		dev->kgd, drm_file, p->pasid,
-		&pdd->vm, &p->kgd_process_info, &p->ef);
+		&p->kgd_process_info, &p->ef);
 	if (ret) {
 		pr_err("Failed to create process VM object\n");
 		return ret;
 	}
-
-	amdgpu_vm_set_task_info(pdd->vm);
+	pdd->drm_priv = drm_file->private_data;
 
 	ret = kfd_process_device_reserve_ib_mem(pdd);
 	if (ret)
@@ -1405,7 +1468,7 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,
 err_init_cwsr:
 err_reserve_ib_mem:
 	kfd_process_device_free_bos(pdd);
-	pdd->vm = NULL;
+	pdd->drm_priv = NULL;
 
 	return ret;
 }
@@ -1429,7 +1492,7 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev,
 		return ERR_PTR(-ENOMEM);
 	}
 
-	if (!pdd->vm)
+	if (!pdd->drm_priv)
 		return ERR_PTR(-ENODEV);
 
 	/*
@@ -1600,6 +1663,32 @@ int kfd_process_restore_queues(struct kfd_process *p)
 	return ret;
 }
 
+int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id)
+{
+	int i;
+
+	for (i = 0; i < p->n_pdds; i++)
+		if (p->pdds[i] && gpu_id == p->pdds[i]->dev->id)
+			return i;
+	return -EINVAL;
+}
+
+int
+kfd_process_gpuid_from_kgd(struct kfd_process *p, struct amdgpu_device *adev,
+			   uint32_t *gpuid, uint32_t *gpuidx)
+{
+	struct kgd_dev *kgd = (struct kgd_dev *)adev;
+	int i;
+
+	for (i = 0; i < p->n_pdds; i++)
+		if (p->pdds[i] && p->pdds[i]->dev->kgd == kgd) {
+			*gpuid = p->pdds[i]->dev->id;
+			*gpuidx = i;
+			return 0;
+		}
+	return -EINVAL;
+}
+
 static void evict_process_worker(struct work_struct *work)
 {
 	int ret;
@@ -1748,7 +1837,7 @@ int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process,
 			       KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot);
 }
 
-void kfd_flush_tlb(struct kfd_process_device *pdd)
+void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type)
 {
 	struct kfd_dev *dev = pdd->dev;
 
@@ -1761,7 +1850,7 @@ void kfd_flush_tlb(struct kfd_process_device *pdd)
 							pdd->qpd.vmid);
 	} else {
 		amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd,
-						pdd->process->pasid);
+					pdd->process->pasid, type);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
new file mode 100644
index 000000000000..dff1011dd7ee
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -0,0 +1,3102 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright 2020-2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/types.h>
+#include <linux/sched/task.h>
+#include "amdgpu_sync.h"
+#include "amdgpu_object.h"
+#include "amdgpu_vm.h"
+#include "amdgpu_mn.h"
+#include "amdgpu.h"
+#include "amdgpu_xgmi.h"
+#include "kfd_priv.h"
+#include "kfd_svm.h"
+#include "kfd_migrate.h"
+
+#define AMDGPU_SVM_RANGE_RESTORE_DELAY_MS 1
+
+/* Long enough to ensure no retry fault comes after svm range is restored and
+ * page table is updated.
+ */
+#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING	2000
+
+static void svm_range_evict_svm_bo_worker(struct work_struct *work);
+static bool
+svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni,
+				    const struct mmu_notifier_range *range,
+				    unsigned long cur_seq);
+
+static const struct mmu_interval_notifier_ops svm_range_mn_ops = {
+	.invalidate = svm_range_cpu_invalidate_pagetables,
+};
+
+/**
+ * svm_range_unlink - unlink svm_range from lists and interval tree
+ * @prange: svm range structure to be removed
+ *
+ * Remove the svm_range from the svms and svm_bo lists and the svms
+ * interval tree.
+ *
+ * Context: The caller must hold svms->lock
+ */
+static void svm_range_unlink(struct svm_range *prange)
+{
+	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms,
+		 prange, prange->start, prange->last);
+
+	if (prange->svm_bo) {
+		spin_lock(&prange->svm_bo->list_lock);
+		list_del(&prange->svm_bo_list);
+		spin_unlock(&prange->svm_bo->list_lock);
+	}
+
+	list_del(&prange->list);
+	if (prange->it_node.start != 0 && prange->it_node.last != 0)
+		interval_tree_remove(&prange->it_node, &prange->svms->objects);
+}
+
+static void
+svm_range_add_notifier_locked(struct mm_struct *mm, struct svm_range *prange)
+{
+	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms,
+		 prange, prange->start, prange->last);
+
+	mmu_interval_notifier_insert_locked(&prange->notifier, mm,
+				     prange->start << PAGE_SHIFT,
+				     prange->npages << PAGE_SHIFT,
+				     &svm_range_mn_ops);
+}
+
+/**
+ * svm_range_add_to_svms - add svm range to svms
+ * @prange: svm range structure to be added
+ *
+ * Add the svm range to svms interval tree and link list
+ *
+ * Context: The caller must hold svms->lock
+ */
+static void svm_range_add_to_svms(struct svm_range *prange)
+{
+	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms,
+		 prange, prange->start, prange->last);
+
+	list_add_tail(&prange->list, &prange->svms->list);
+	prange->it_node.start = prange->start;
+	prange->it_node.last = prange->last;
+	interval_tree_insert(&prange->it_node, &prange->svms->objects);
+}
+
+static void svm_range_remove_notifier(struct svm_range *prange)
+{
+	pr_debug("remove notifier svms 0x%p prange 0x%p [0x%lx 0x%lx]\n",
+		 prange->svms, prange,
+		 prange->notifier.interval_tree.start >> PAGE_SHIFT,
+		 prange->notifier.interval_tree.last >> PAGE_SHIFT);
+
+	if (prange->notifier.interval_tree.start != 0 &&
+	    prange->notifier.interval_tree.last != 0)
+		mmu_interval_notifier_remove(&prange->notifier);
+}
+
+static int
+svm_range_dma_map_dev(struct device *dev, dma_addr_t **dma_addr,
+		      unsigned long *hmm_pfns, uint64_t npages)
+{
+	enum dma_data_direction dir = DMA_BIDIRECTIONAL;
+	dma_addr_t *addr = *dma_addr;
+	struct page *page;
+	int i, r;
+
+	if (!addr) {
+		addr = kvmalloc_array(npages, sizeof(*addr),
+				      GFP_KERNEL | __GFP_ZERO);
+		if (!addr)
+			return -ENOMEM;
+		*dma_addr = addr;
+	}
+
+	for (i = 0; i < npages; i++) {
+		if (WARN_ONCE(addr[i] && !dma_mapping_error(dev, addr[i]),
+			      "leaking dma mapping\n"))
+			dma_unmap_page(dev, addr[i], PAGE_SIZE, dir);
+
+		page = hmm_pfn_to_page(hmm_pfns[i]);
+		addr[i] = dma_map_page(dev, page, 0, PAGE_SIZE, dir);
+		r = dma_mapping_error(dev, addr[i]);
+		if (r) {
+			pr_debug("failed %d dma_map_page\n", r);
+			return r;
+		}
+		pr_debug("dma mapping 0x%llx for page addr 0x%lx\n",
+			 addr[i] >> PAGE_SHIFT, page_to_pfn(page));
+	}
+	return 0;
+}
+
+static int
+svm_range_dma_map(struct svm_range *prange, unsigned long *bitmap,
+		  unsigned long *hmm_pfns)
+{
+	struct kfd_process *p;
+	uint32_t gpuidx;
+	int r;
+
+	p = container_of(prange->svms, struct kfd_process, svms);
+
+	for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
+		struct kfd_process_device *pdd;
+		struct amdgpu_device *adev;
+
+		pr_debug("mapping to gpu idx 0x%x\n", gpuidx);
+		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
+		if (!pdd) {
+			pr_debug("failed to find device idx %d\n", gpuidx);
+			return -EINVAL;
+		}
+		adev = (struct amdgpu_device *)pdd->dev->kgd;
+
+		r = svm_range_dma_map_dev(adev->dev, &prange->dma_addr[gpuidx],
+					  hmm_pfns, prange->npages);
+		if (r)
+			break;
+	}
+
+	return r;
+}
+
+void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr,
+			 unsigned long offset, unsigned long npages)
+{
+	enum dma_data_direction dir = DMA_BIDIRECTIONAL;
+	int i;
+
+	if (!dma_addr)
+		return;
+
+	for (i = offset; i < offset + npages; i++) {
+		if (!dma_addr[i] || dma_mapping_error(dev, dma_addr[i]))
+			continue;
+		pr_debug("dma unmapping 0x%llx\n", dma_addr[i] >> PAGE_SHIFT);
+		dma_unmap_page(dev, dma_addr[i], PAGE_SIZE, dir);
+		dma_addr[i] = 0;
+	}
+}
+
+void svm_range_free_dma_mappings(struct svm_range *prange)
+{
+	struct kfd_process_device *pdd;
+	dma_addr_t *dma_addr;
+	struct device *dev;
+	struct kfd_process *p;
+	uint32_t gpuidx;
+
+	p = container_of(prange->svms, struct kfd_process, svms);
+
+	for (gpuidx = 0; gpuidx < MAX_GPU_INSTANCE; gpuidx++) {
+		dma_addr = prange->dma_addr[gpuidx];
+		if (!dma_addr)
+			continue;
+
+		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
+		if (!pdd) {
+			pr_debug("failed to find device idx %d\n", gpuidx);
+			continue;
+		}
+		dev = &pdd->dev->pdev->dev;
+		svm_range_dma_unmap(dev, dma_addr, 0, prange->npages);
+		kvfree(dma_addr);
+		prange->dma_addr[gpuidx] = NULL;
+	}
+}
+
+static void svm_range_free(struct svm_range *prange)
+{
+	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, prange,
+		 prange->start, prange->last);
+
+	svm_range_vram_node_free(prange);
+	svm_range_free_dma_mappings(prange);
+	mutex_destroy(&prange->lock);
+	mutex_destroy(&prange->migrate_mutex);
+	kfree(prange);
+}
+
+static void
+svm_range_set_default_attributes(int32_t *location, int32_t *prefetch_loc,
+				 uint8_t *granularity, uint32_t *flags)
+{
+	*location = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
+	*prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
+	*granularity = 9;
+	*flags =
+		KFD_IOCTL_SVM_FLAG_HOST_ACCESS | KFD_IOCTL_SVM_FLAG_COHERENT;
+}
+
+static struct
+svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start,
+			 uint64_t last)
+{
+	uint64_t size = last - start + 1;
+	struct svm_range *prange;
+	struct kfd_process *p;
+
+	prange = kzalloc(sizeof(*prange), GFP_KERNEL);
+	if (!prange)
+		return NULL;
+	prange->npages = size;
+	prange->svms = svms;
+	prange->start = start;
+	prange->last = last;
+	INIT_LIST_HEAD(&prange->list);
+	INIT_LIST_HEAD(&prange->update_list);
+	INIT_LIST_HEAD(&prange->remove_list);
+	INIT_LIST_HEAD(&prange->insert_list);
+	INIT_LIST_HEAD(&prange->svm_bo_list);
+	INIT_LIST_HEAD(&prange->deferred_list);
+	INIT_LIST_HEAD(&prange->child_list);
+	atomic_set(&prange->invalid, 0);
+	prange->validate_timestamp = 0;
+	mutex_init(&prange->migrate_mutex);
+	mutex_init(&prange->lock);
+
+	p = container_of(svms, struct kfd_process, svms);
+	if (p->xnack_enabled)
+		bitmap_copy(prange->bitmap_access, svms->bitmap_supported,
+			    MAX_GPU_INSTANCE);
+
+	svm_range_set_default_attributes(&prange->preferred_loc,
+					 &prange->prefetch_loc,
+					 &prange->granularity, &prange->flags);
+
+	pr_debug("svms 0x%p [0x%llx 0x%llx]\n", svms, start, last);
+
+	return prange;
+}
+
+static bool svm_bo_ref_unless_zero(struct svm_range_bo *svm_bo)
+{
+	if (!svm_bo || !kref_get_unless_zero(&svm_bo->kref))
+		return false;
+
+	return true;
+}
+
+static struct svm_range_bo *svm_range_bo_ref(struct svm_range_bo *svm_bo)
+{
+	if (svm_bo)
+		kref_get(&svm_bo->kref);
+
+	return svm_bo;
+}
+
+static void svm_range_bo_release(struct kref *kref)
+{
+	struct svm_range_bo *svm_bo;
+
+	svm_bo = container_of(kref, struct svm_range_bo, kref);
+	spin_lock(&svm_bo->list_lock);
+	while (!list_empty(&svm_bo->range_list)) {
+		struct svm_range *prange =
+				list_first_entry(&svm_bo->range_list,
+						struct svm_range, svm_bo_list);
+		/* list_del_init tells a concurrent svm_range_vram_node_new when
+		 * it's safe to reuse the svm_bo pointer and svm_bo_list head.
+		 */
+		list_del_init(&prange->svm_bo_list);
+		spin_unlock(&svm_bo->list_lock);
+
+		pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms,
+			 prange->start, prange->last);
+		mutex_lock(&prange->lock);
+		prange->svm_bo = NULL;
+		mutex_unlock(&prange->lock);
+
+		spin_lock(&svm_bo->list_lock);
+	}
+	spin_unlock(&svm_bo->list_lock);
+	if (!dma_fence_is_signaled(&svm_bo->eviction_fence->base)) {
+		/* We're not in the eviction worker.
+		 * Signal the fence and synchronize with any
+		 * pending eviction work.
+		 */
+		dma_fence_signal(&svm_bo->eviction_fence->base);
+		cancel_work_sync(&svm_bo->eviction_work);
+	}
+	dma_fence_put(&svm_bo->eviction_fence->base);
+	amdgpu_bo_unref(&svm_bo->bo);
+	kfree(svm_bo);
+}
+
+static void svm_range_bo_unref(struct svm_range_bo *svm_bo)
+{
+	if (!svm_bo)
+		return;
+
+	kref_put(&svm_bo->kref, svm_range_bo_release);
+}
+
+static bool
+svm_range_validate_svm_bo(struct amdgpu_device *adev, struct svm_range *prange)
+{
+	struct amdgpu_device *bo_adev;
+
+	mutex_lock(&prange->lock);
+	if (!prange->svm_bo) {
+		mutex_unlock(&prange->lock);
+		return false;
+	}
+	if (prange->ttm_res) {
+		/* We still have a reference, all is well */
+		mutex_unlock(&prange->lock);
+		return true;
+	}
+	if (svm_bo_ref_unless_zero(prange->svm_bo)) {
+		/*
+		 * Migrate from GPU to GPU, remove range from source bo_adev
+		 * svm_bo range list, and return false to allocate svm_bo from
+		 * destination adev.
+		 */
+		bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev);
+		if (bo_adev != adev) {
+			mutex_unlock(&prange->lock);
+
+			spin_lock(&prange->svm_bo->list_lock);
+			list_del_init(&prange->svm_bo_list);
+			spin_unlock(&prange->svm_bo->list_lock);
+
+			svm_range_bo_unref(prange->svm_bo);
+			return false;
+		}
+		if (READ_ONCE(prange->svm_bo->evicting)) {
+			struct dma_fence *f;
+			struct svm_range_bo *svm_bo;
+			/* The BO is getting evicted,
+			 * we need to get a new one
+			 */
+			mutex_unlock(&prange->lock);
+			svm_bo = prange->svm_bo;
+			f = dma_fence_get(&svm_bo->eviction_fence->base);
+			svm_range_bo_unref(prange->svm_bo);
+			/* wait for the fence to avoid long spin-loop
+			 * at list_empty_careful
+			 */
+			dma_fence_wait(f, false);
+			dma_fence_put(f);
+		} else {
+			/* The BO was still around and we got
+			 * a new reference to it
+			 */
+			mutex_unlock(&prange->lock);
+			pr_debug("reuse old bo svms 0x%p [0x%lx 0x%lx]\n",
+				 prange->svms, prange->start, prange->last);
+
+			prange->ttm_res = prange->svm_bo->bo->tbo.resource;
+			return true;
+		}
+
+	} else {
+		mutex_unlock(&prange->lock);
+	}
+
+	/* We need a new svm_bo. Spin-loop to wait for concurrent
+	 * svm_range_bo_release to finish removing this range from
+	 * its range list. After this, it is safe to reuse the
+	 * svm_bo pointer and svm_bo_list head.
+	 */
+	while (!list_empty_careful(&prange->svm_bo_list))
+		;
+
+	return false;
+}
+
+static struct svm_range_bo *svm_range_bo_new(void)
+{
+	struct svm_range_bo *svm_bo;
+
+	svm_bo = kzalloc(sizeof(*svm_bo), GFP_KERNEL);
+	if (!svm_bo)
+		return NULL;
+
+	kref_init(&svm_bo->kref);
+	INIT_LIST_HEAD(&svm_bo->range_list);
+	spin_lock_init(&svm_bo->list_lock);
+
+	return svm_bo;
+}
+
+int
+svm_range_vram_node_new(struct amdgpu_device *adev, struct svm_range *prange,
+			bool clear)
+{
+	struct amdgpu_bo_param bp;
+	struct svm_range_bo *svm_bo;
+	struct amdgpu_bo_user *ubo;
+	struct amdgpu_bo *bo;
+	struct kfd_process *p;
+	struct mm_struct *mm;
+	int r;
+
+	p = container_of(prange->svms, struct kfd_process, svms);
+	pr_debug("pasid: %x svms 0x%p [0x%lx 0x%lx]\n", p->pasid, prange->svms,
+		 prange->start, prange->last);
+
+	if (svm_range_validate_svm_bo(adev, prange))
+		return 0;
+
+	svm_bo = svm_range_bo_new();
+	if (!svm_bo) {
+		pr_debug("failed to alloc svm bo\n");
+		return -ENOMEM;
+	}
+	mm = get_task_mm(p->lead_thread);
+	if (!mm) {
+		pr_debug("failed to get mm\n");
+		kfree(svm_bo);
+		return -ESRCH;
+	}
+	svm_bo->svms = prange->svms;
+	svm_bo->eviction_fence =
+		amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
+					   mm,
+					   svm_bo);
+	mmput(mm);
+	INIT_WORK(&svm_bo->eviction_work, svm_range_evict_svm_bo_worker);
+	svm_bo->evicting = 0;
+	memset(&bp, 0, sizeof(bp));
+	bp.size = prange->npages * PAGE_SIZE;
+	bp.byte_align = PAGE_SIZE;
+	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
+	bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+	bp.flags |= clear ? AMDGPU_GEM_CREATE_VRAM_CLEARED : 0;
+	bp.flags |= AMDGPU_AMDKFD_CREATE_SVM_BO;
+	bp.type = ttm_bo_type_device;
+	bp.resv = NULL;
+
+	r = amdgpu_bo_create_user(adev, &bp, &ubo);
+	if (r) {
+		pr_debug("failed %d to create bo\n", r);
+		goto create_bo_failed;
+	}
+	bo = &ubo->bo;
+	r = amdgpu_bo_reserve(bo, true);
+	if (r) {
+		pr_debug("failed %d to reserve bo\n", r);
+		goto reserve_bo_failed;
+	}
+
+	r = dma_resv_reserve_shared(bo->tbo.base.resv, 1);
+	if (r) {
+		pr_debug("failed %d to reserve bo\n", r);
+		amdgpu_bo_unreserve(bo);
+		goto reserve_bo_failed;
+	}
+	amdgpu_bo_fence(bo, &svm_bo->eviction_fence->base, true);
+
+	amdgpu_bo_unreserve(bo);
+
+	svm_bo->bo = bo;
+	prange->svm_bo = svm_bo;
+	prange->ttm_res = bo->tbo.resource;
+	prange->offset = 0;
+
+	spin_lock(&svm_bo->list_lock);
+	list_add(&prange->svm_bo_list, &svm_bo->range_list);
+	spin_unlock(&svm_bo->list_lock);
+
+	return 0;
+
+reserve_bo_failed:
+	amdgpu_bo_unref(&bo);
+create_bo_failed:
+	dma_fence_put(&svm_bo->eviction_fence->base);
+	kfree(svm_bo);
+	prange->ttm_res = NULL;
+
+	return r;
+}
+
+void svm_range_vram_node_free(struct svm_range *prange)
+{
+	svm_range_bo_unref(prange->svm_bo);
+	prange->ttm_res = NULL;
+}
+
+struct amdgpu_device *
+svm_range_get_adev_by_id(struct svm_range *prange, uint32_t gpu_id)
+{
+	struct kfd_process_device *pdd;
+	struct kfd_process *p;
+	int32_t gpu_idx;
+
+	p = container_of(prange->svms, struct kfd_process, svms);
+
+	gpu_idx = kfd_process_gpuidx_from_gpuid(p, gpu_id);
+	if (gpu_idx < 0) {
+		pr_debug("failed to get device by id 0x%x\n", gpu_id);
+		return NULL;
+	}
+	pdd = kfd_process_device_from_gpuidx(p, gpu_idx);
+	if (!pdd) {
+		pr_debug("failed to get device by idx 0x%x\n", gpu_idx);
+		return NULL;
+	}
+
+	return (struct amdgpu_device *)pdd->dev->kgd;
+}
+
+static int svm_range_bo_validate(void *param, struct amdgpu_bo *bo)
+{
+	struct ttm_operation_ctx ctx = { false, false };
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
+
+	return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+}
+
+static int
+svm_range_check_attr(struct kfd_process *p,
+		     uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs)
+{
+	uint32_t i;
+
+	for (i = 0; i < nattr; i++) {
+		uint32_t val = attrs[i].value;
+		int gpuidx = MAX_GPU_INSTANCE;
+
+		switch (attrs[i].type) {
+		case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
+			if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM &&
+			    val != KFD_IOCTL_SVM_LOCATION_UNDEFINED)
+				gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
+			break;
+		case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC:
+			if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM)
+				gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
+			break;
+		case KFD_IOCTL_SVM_ATTR_ACCESS:
+		case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE:
+		case KFD_IOCTL_SVM_ATTR_NO_ACCESS:
+			gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
+			break;
+		case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
+			break;
+		case KFD_IOCTL_SVM_ATTR_CLR_FLAGS:
+			break;
+		case KFD_IOCTL_SVM_ATTR_GRANULARITY:
+			break;
+		default:
+			pr_debug("unknown attr type 0x%x\n", attrs[i].type);
+			return -EINVAL;
+		}
+
+		if (gpuidx < 0) {
+			pr_debug("no GPU 0x%x found\n", val);
+			return -EINVAL;
+		} else if (gpuidx < MAX_GPU_INSTANCE &&
+			   !test_bit(gpuidx, p->svms.bitmap_supported)) {
+			pr_debug("GPU 0x%x not supported\n", val);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static void
+svm_range_apply_attrs(struct kfd_process *p, struct svm_range *prange,
+		      uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs)
+{
+	uint32_t i;
+	int gpuidx;
+
+	for (i = 0; i < nattr; i++) {
+		switch (attrs[i].type) {
+		case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
+			prange->preferred_loc = attrs[i].value;
+			break;
+		case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC:
+			prange->prefetch_loc = attrs[i].value;
+			break;
+		case KFD_IOCTL_SVM_ATTR_ACCESS:
+		case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE:
+		case KFD_IOCTL_SVM_ATTR_NO_ACCESS:
+			gpuidx = kfd_process_gpuidx_from_gpuid(p,
+							       attrs[i].value);
+			if (attrs[i].type == KFD_IOCTL_SVM_ATTR_NO_ACCESS) {
+				bitmap_clear(prange->bitmap_access, gpuidx, 1);
+				bitmap_clear(prange->bitmap_aip, gpuidx, 1);
+			} else if (attrs[i].type == KFD_IOCTL_SVM_ATTR_ACCESS) {
+				bitmap_set(prange->bitmap_access, gpuidx, 1);
+				bitmap_clear(prange->bitmap_aip, gpuidx, 1);
+			} else {
+				bitmap_clear(prange->bitmap_access, gpuidx, 1);
+				bitmap_set(prange->bitmap_aip, gpuidx, 1);
+			}
+			break;
+		case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
+			prange->flags |= attrs[i].value;
+			break;
+		case KFD_IOCTL_SVM_ATTR_CLR_FLAGS:
+			prange->flags &= ~attrs[i].value;
+			break;
+		case KFD_IOCTL_SVM_ATTR_GRANULARITY:
+			prange->granularity = attrs[i].value;
+			break;
+		default:
+			WARN_ONCE(1, "svm_range_check_attrs wasn't called?");
+		}
+	}
+}
+
+/**
+ * svm_range_debug_dump - print all range information from svms
+ * @svms: svm range list header
+ *
+ * debug output svm range start, end, prefetch location from svms
+ * interval tree and link list
+ *
+ * Context: The caller must hold svms->lock
+ */
+static void svm_range_debug_dump(struct svm_range_list *svms)
+{
+	struct interval_tree_node *node;
+	struct svm_range *prange;
+
+	pr_debug("dump svms 0x%p list\n", svms);
+	pr_debug("range\tstart\tpage\tend\t\tlocation\n");
+
+	list_for_each_entry(prange, &svms->list, list) {
+		pr_debug("0x%p 0x%lx\t0x%llx\t0x%llx\t0x%x\n",
+			 prange, prange->start, prange->npages,
+			 prange->start + prange->npages - 1,
+			 prange->actual_loc);
+	}
+
+	pr_debug("dump svms 0x%p interval tree\n", svms);
+	pr_debug("range\tstart\tpage\tend\t\tlocation\n");
+	node = interval_tree_iter_first(&svms->objects, 0, ~0ULL);
+	while (node) {
+		prange = container_of(node, struct svm_range, it_node);
+		pr_debug("0x%p 0x%lx\t0x%llx\t0x%llx\t0x%x\n",
+			 prange, prange->start, prange->npages,
+			 prange->start + prange->npages - 1,
+			 prange->actual_loc);
+		node = interval_tree_iter_next(node, 0, ~0ULL);
+	}
+}
+
+static bool
+svm_range_is_same_attrs(struct svm_range *old, struct svm_range *new)
+{
+	return (old->prefetch_loc == new->prefetch_loc &&
+		old->flags == new->flags &&
+		old->granularity == new->granularity);
+}
+
+static int
+svm_range_split_array(void *ppnew, void *ppold, size_t size,
+		      uint64_t old_start, uint64_t old_n,
+		      uint64_t new_start, uint64_t new_n)
+{
+	unsigned char *new, *old, *pold;
+	uint64_t d;
+
+	if (!ppold)
+		return 0;
+	pold = *(unsigned char **)ppold;
+	if (!pold)
+		return 0;
+
+	new = kvmalloc_array(new_n, size, GFP_KERNEL);
+	if (!new)
+		return -ENOMEM;
+
+	d = (new_start - old_start) * size;
+	memcpy(new, pold + d, new_n * size);
+
+	old = kvmalloc_array(old_n, size, GFP_KERNEL);
+	if (!old) {
+		kvfree(new);
+		return -ENOMEM;
+	}
+
+	d = (new_start == old_start) ? new_n * size : 0;
+	memcpy(old, pold + d, old_n * size);
+
+	kvfree(pold);
+	*(void **)ppold = old;
+	*(void **)ppnew = new;
+
+	return 0;
+}
+
+static int
+svm_range_split_pages(struct svm_range *new, struct svm_range *old,
+		      uint64_t start, uint64_t last)
+{
+	uint64_t npages = last - start + 1;
+	int i, r;
+
+	for (i = 0; i < MAX_GPU_INSTANCE; i++) {
+		r = svm_range_split_array(&new->dma_addr[i], &old->dma_addr[i],
+					  sizeof(*old->dma_addr[i]), old->start,
+					  npages, new->start, new->npages);
+		if (r)
+			return r;
+	}
+
+	return 0;
+}
+
+static int
+svm_range_split_nodes(struct svm_range *new, struct svm_range *old,
+		      uint64_t start, uint64_t last)
+{
+	uint64_t npages = last - start + 1;
+
+	pr_debug("svms 0x%p new prange 0x%p start 0x%lx [0x%llx 0x%llx]\n",
+		 new->svms, new, new->start, start, last);
+
+	if (new->start == old->start) {
+		new->offset = old->offset;
+		old->offset += new->npages;
+	} else {
+		new->offset = old->offset + npages;
+	}
+
+	new->svm_bo = svm_range_bo_ref(old->svm_bo);
+	new->ttm_res = old->ttm_res;
+
+	spin_lock(&new->svm_bo->list_lock);
+	list_add(&new->svm_bo_list, &new->svm_bo->range_list);
+	spin_unlock(&new->svm_bo->list_lock);
+
+	return 0;
+}
+
+/**
+ * svm_range_split_adjust - split range and adjust
+ *
+ * @new: new range
+ * @old: the old range
+ * @start: the old range adjust to start address in pages
+ * @last: the old range adjust to last address in pages
+ *
+ * Copy system memory dma_addr or vram ttm_res in old range to new
+ * range from new_start up to size new->npages, the remaining old range is from
+ * start to last
+ *
+ * Return:
+ * 0 - OK, -ENOMEM - out of memory
+ */
+static int
+svm_range_split_adjust(struct svm_range *new, struct svm_range *old,
+		      uint64_t start, uint64_t last)
+{
+	int r;
+
+	pr_debug("svms 0x%p new 0x%lx old [0x%lx 0x%lx] => [0x%llx 0x%llx]\n",
+		 new->svms, new->start, old->start, old->last, start, last);
+
+	if (new->start < old->start ||
+	    new->last > old->last) {
+		WARN_ONCE(1, "invalid new range start or last\n");
+		return -EINVAL;
+	}
+
+	r = svm_range_split_pages(new, old, start, last);
+	if (r)
+		return r;
+
+	if (old->actual_loc && old->ttm_res) {
+		r = svm_range_split_nodes(new, old, start, last);
+		if (r)
+			return r;
+	}
+
+	old->npages = last - start + 1;
+	old->start = start;
+	old->last = last;
+	new->flags = old->flags;
+	new->preferred_loc = old->preferred_loc;
+	new->prefetch_loc = old->prefetch_loc;
+	new->actual_loc = old->actual_loc;
+	new->granularity = old->granularity;
+	bitmap_copy(new->bitmap_access, old->bitmap_access, MAX_GPU_INSTANCE);
+	bitmap_copy(new->bitmap_aip, old->bitmap_aip, MAX_GPU_INSTANCE);
+
+	return 0;
+}
+
+/**
+ * svm_range_split - split a range in 2 ranges
+ *
+ * @prange: the svm range to split
+ * @start: the remaining range start address in pages
+ * @last: the remaining range last address in pages
+ * @new: the result new range generated
+ *
+ * Two cases only:
+ * case 1: if start == prange->start
+ *         prange ==> prange[start, last]
+ *         new range [last + 1, prange->last]
+ *
+ * case 2: if last == prange->last
+ *         prange ==> prange[start, last]
+ *         new range [prange->start, start - 1]
+ *
+ * Return:
+ * 0 - OK, -ENOMEM - out of memory, -EINVAL - invalid start, last
+ */
+static int
+svm_range_split(struct svm_range *prange, uint64_t start, uint64_t last,
+		struct svm_range **new)
+{
+	uint64_t old_start = prange->start;
+	uint64_t old_last = prange->last;
+	struct svm_range_list *svms;
+	int r = 0;
+
+	pr_debug("svms 0x%p [0x%llx 0x%llx] to [0x%llx 0x%llx]\n", prange->svms,
+		 old_start, old_last, start, last);
+
+	if (old_start != start && old_last != last)
+		return -EINVAL;
+	if (start < old_start || last > old_last)
+		return -EINVAL;
+
+	svms = prange->svms;
+	if (old_start == start)
+		*new = svm_range_new(svms, last + 1, old_last);
+	else
+		*new = svm_range_new(svms, old_start, start - 1);
+	if (!*new)
+		return -ENOMEM;
+
+	r = svm_range_split_adjust(*new, prange, start, last);
+	if (r) {
+		pr_debug("failed %d split [0x%llx 0x%llx] to [0x%llx 0x%llx]\n",
+			 r, old_start, old_last, start, last);
+		svm_range_free(*new);
+		*new = NULL;
+	}
+
+	return r;
+}
+
+static int
+svm_range_split_tail(struct svm_range *prange, struct svm_range *new,
+		     uint64_t new_last, struct list_head *insert_list)
+{
+	struct svm_range *tail;
+	int r = svm_range_split(prange, prange->start, new_last, &tail);
+
+	if (!r)
+		list_add(&tail->insert_list, insert_list);
+	return r;
+}
+
+static int
+svm_range_split_head(struct svm_range *prange, struct svm_range *new,
+		     uint64_t new_start, struct list_head *insert_list)
+{
+	struct svm_range *head;
+	int r = svm_range_split(prange, new_start, prange->last, &head);
+
+	if (!r)
+		list_add(&head->insert_list, insert_list);
+	return r;
+}
+
+static void
+svm_range_add_child(struct svm_range *prange, struct mm_struct *mm,
+		    struct svm_range *pchild, enum svm_work_list_ops op)
+{
+	pr_debug("add child 0x%p [0x%lx 0x%lx] to prange 0x%p child list %d\n",
+		 pchild, pchild->start, pchild->last, prange, op);
+
+	pchild->work_item.mm = mm;
+	pchild->work_item.op = op;
+	list_add_tail(&pchild->child_list, &prange->child_list);
+}
+
+/**
+ * svm_range_split_by_granularity - collect ranges within granularity boundary
+ *
+ * @p: the process with svms list
+ * @mm: mm structure
+ * @addr: the vm fault address in pages, to split the prange
+ * @parent: parent range if prange is from child list
+ * @prange: prange to split
+ *
+ * Trims @prange to be a single aligned block of prange->granularity if
+ * possible. The head and tail are added to the child_list in @parent.
+ *
+ * Context: caller must hold mmap_read_lock and prange->lock
+ *
+ * Return:
+ * 0 - OK, otherwise error code
+ */
+int
+svm_range_split_by_granularity(struct kfd_process *p, struct mm_struct *mm,
+			       unsigned long addr, struct svm_range *parent,
+			       struct svm_range *prange)
+{
+	struct svm_range *head, *tail;
+	unsigned long start, last, size;
+	int r;
+
+	/* Align splited range start and size to granularity size, then a single
+	 * PTE will be used for whole range, this reduces the number of PTE
+	 * updated and the L1 TLB space used for translation.
+	 */
+	size = 1UL << prange->granularity;
+	start = ALIGN_DOWN(addr, size);
+	last = ALIGN(addr + 1, size) - 1;
+
+	pr_debug("svms 0x%p split [0x%lx 0x%lx] to [0x%lx 0x%lx] size 0x%lx\n",
+		 prange->svms, prange->start, prange->last, start, last, size);
+
+	if (start > prange->start) {
+		r = svm_range_split(prange, start, prange->last, &head);
+		if (r)
+			return r;
+		svm_range_add_child(parent, mm, head, SVM_OP_ADD_RANGE);
+	}
+
+	if (last < prange->last) {
+		r = svm_range_split(prange, prange->start, last, &tail);
+		if (r)
+			return r;
+		svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE);
+	}
+
+	/* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */
+	if (p->xnack_enabled && prange->work_item.op == SVM_OP_ADD_RANGE) {
+		prange->work_item.op = SVM_OP_ADD_RANGE_AND_MAP;
+		pr_debug("change prange 0x%p [0x%lx 0x%lx] op %d\n",
+			 prange, prange->start, prange->last,
+			 SVM_OP_ADD_RANGE_AND_MAP);
+	}
+	return 0;
+}
+
+static uint64_t
+svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange)
+{
+	struct amdgpu_device *bo_adev;
+	uint32_t flags = prange->flags;
+	uint32_t mapping_flags = 0;
+	uint64_t pte_flags;
+	bool snoop = !prange->ttm_res;
+	bool coherent = flags & KFD_IOCTL_SVM_FLAG_COHERENT;
+
+	if (prange->svm_bo && prange->ttm_res)
+		bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev);
+
+	switch (adev->asic_type) {
+	case CHIP_ARCTURUS:
+		if (prange->svm_bo && prange->ttm_res) {
+			if (bo_adev == adev) {
+				mapping_flags |= coherent ?
+					AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
+			} else {
+				mapping_flags |= coherent ?
+					AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
+				if (amdgpu_xgmi_same_hive(adev, bo_adev))
+					snoop = true;
+			}
+		} else {
+			mapping_flags |= coherent ?
+				AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
+		}
+		break;
+	case CHIP_ALDEBARAN:
+		if (prange->svm_bo && prange->ttm_res) {
+			if (bo_adev == adev) {
+				mapping_flags |= coherent ?
+					AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
+				if (adev->gmc.xgmi.connected_to_cpu)
+					snoop = true;
+			} else {
+				mapping_flags |= coherent ?
+					AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
+				if (amdgpu_xgmi_same_hive(adev, bo_adev))
+					snoop = true;
+			}
+		} else {
+			mapping_flags |= coherent ?
+				AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
+		}
+		break;
+	default:
+		mapping_flags |= coherent ?
+			AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
+	}
+
+	mapping_flags |= AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE;
+
+	if (flags & KFD_IOCTL_SVM_FLAG_GPU_RO)
+		mapping_flags &= ~AMDGPU_VM_PAGE_WRITEABLE;
+	if (flags & KFD_IOCTL_SVM_FLAG_GPU_EXEC)
+		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
+
+	pte_flags = AMDGPU_PTE_VALID;
+	pte_flags |= prange->ttm_res ? 0 : AMDGPU_PTE_SYSTEM;
+	pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
+
+	pte_flags |= amdgpu_gem_va_map_flags(adev, mapping_flags);
+
+	pr_debug("svms 0x%p [0x%lx 0x%lx] vram %d PTE 0x%llx mapping 0x%x\n",
+		 prange->svms, prange->start, prange->last,
+		 prange->ttm_res ? 1:0, pte_flags, mapping_flags);
+
+	return pte_flags;
+}
+
+static int
+svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+			 uint64_t start, uint64_t last,
+			 struct dma_fence **fence)
+{
+	uint64_t init_pte_value = 0;
+
+	pr_debug("[0x%llx 0x%llx]\n", start, last);
+
+	return amdgpu_vm_bo_update_mapping(adev, adev, vm, false, true, NULL,
+					   start, last, init_pte_value, 0,
+					   NULL, NULL, fence, NULL);
+}
+
+static int
+svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start,
+			  unsigned long last)
+{
+	DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE);
+	struct kfd_process_device *pdd;
+	struct dma_fence *fence = NULL;
+	struct amdgpu_device *adev;
+	struct kfd_process *p;
+	uint32_t gpuidx;
+	int r = 0;
+
+	bitmap_or(bitmap, prange->bitmap_access, prange->bitmap_aip,
+		  MAX_GPU_INSTANCE);
+	p = container_of(prange->svms, struct kfd_process, svms);
+
+	for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
+		pr_debug("unmap from gpu idx 0x%x\n", gpuidx);
+		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
+		if (!pdd) {
+			pr_debug("failed to find device idx %d\n", gpuidx);
+			return -EINVAL;
+		}
+		adev = (struct amdgpu_device *)pdd->dev->kgd;
+
+		r = svm_range_unmap_from_gpu(adev, drm_priv_to_vm(pdd->drm_priv),
+					     start, last, &fence);
+		if (r)
+			break;
+
+		if (fence) {
+			r = dma_fence_wait(fence, false);
+			dma_fence_put(fence);
+			fence = NULL;
+			if (r)
+				break;
+		}
+		amdgpu_amdkfd_flush_gpu_tlb_pasid((struct kgd_dev *)adev,
+					p->pasid, TLB_FLUSH_HEAVYWEIGHT);
+	}
+
+	return r;
+}
+
+static int
+svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+		     struct svm_range *prange, dma_addr_t *dma_addr,
+		     struct amdgpu_device *bo_adev, struct dma_fence **fence)
+{
+	struct amdgpu_bo_va bo_va;
+	bool table_freed = false;
+	uint64_t pte_flags;
+	int r = 0;
+
+	pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start,
+		 prange->last);
+
+	if (prange->svm_bo && prange->ttm_res) {
+		bo_va.is_xgmi = amdgpu_xgmi_same_hive(adev, bo_adev);
+		prange->mapping.bo_va = &bo_va;
+	}
+
+	prange->mapping.start = prange->start;
+	prange->mapping.last = prange->last;
+	prange->mapping.offset = prange->ttm_res ? prange->offset : 0;
+	pte_flags = svm_range_get_pte_flags(adev, prange);
+
+	r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false, NULL,
+					prange->mapping.start,
+					prange->mapping.last, pte_flags,
+					prange->mapping.offset,
+					prange->ttm_res,
+					dma_addr, &vm->last_update,
+					&table_freed);
+	if (r) {
+		pr_debug("failed %d to map to gpu 0x%lx\n", r, prange->start);
+		goto out;
+	}
+
+	r = amdgpu_vm_update_pdes(adev, vm, false);
+	if (r) {
+		pr_debug("failed %d to update directories 0x%lx\n", r,
+			 prange->start);
+		goto out;
+	}
+
+	if (fence)
+		*fence = dma_fence_get(vm->last_update);
+
+	if (table_freed) {
+		struct kfd_process *p;
+
+		p = container_of(prange->svms, struct kfd_process, svms);
+		amdgpu_amdkfd_flush_gpu_tlb_pasid((struct kgd_dev *)adev,
+						p->pasid, TLB_FLUSH_LEGACY);
+	}
+out:
+	prange->mapping.bo_va = NULL;
+	return r;
+}
+
+static int svm_range_map_to_gpus(struct svm_range *prange,
+				 unsigned long *bitmap, bool wait)
+{
+	struct kfd_process_device *pdd;
+	struct amdgpu_device *bo_adev;
+	struct amdgpu_device *adev;
+	struct kfd_process *p;
+	struct dma_fence *fence = NULL;
+	uint32_t gpuidx;
+	int r = 0;
+
+	if (prange->svm_bo && prange->ttm_res)
+		bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev);
+	else
+		bo_adev = NULL;
+
+	p = container_of(prange->svms, struct kfd_process, svms);
+	for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
+		pr_debug("mapping to gpu idx 0x%x\n", gpuidx);
+		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
+		if (!pdd) {
+			pr_debug("failed to find device idx %d\n", gpuidx);
+			return -EINVAL;
+		}
+		adev = (struct amdgpu_device *)pdd->dev->kgd;
+
+		pdd = kfd_bind_process_to_device(pdd->dev, p);
+		if (IS_ERR(pdd))
+			return -EINVAL;
+
+		if (bo_adev && adev != bo_adev &&
+		    !amdgpu_xgmi_same_hive(adev, bo_adev)) {
+			pr_debug("cannot map to device idx %d\n", gpuidx);
+			continue;
+		}
+
+		r = svm_range_map_to_gpu(adev, drm_priv_to_vm(pdd->drm_priv),
+					 prange, prange->dma_addr[gpuidx],
+					 bo_adev, wait ? &fence : NULL);
+		if (r)
+			break;
+
+		if (fence) {
+			r = dma_fence_wait(fence, false);
+			dma_fence_put(fence);
+			fence = NULL;
+			if (r) {
+				pr_debug("failed %d to dma fence wait\n", r);
+				break;
+			}
+		}
+	}
+
+	return r;
+}
+
+struct svm_validate_context {
+	struct kfd_process *process;
+	struct svm_range *prange;
+	bool intr;
+	unsigned long bitmap[MAX_GPU_INSTANCE];
+	struct ttm_validate_buffer tv[MAX_GPU_INSTANCE+1];
+	struct list_head validate_list;
+	struct ww_acquire_ctx ticket;
+};
+
+static int svm_range_reserve_bos(struct svm_validate_context *ctx)
+{
+	struct kfd_process_device *pdd;
+	struct amdgpu_device *adev;
+	struct amdgpu_vm *vm;
+	uint32_t gpuidx;
+	int r;
+
+	INIT_LIST_HEAD(&ctx->validate_list);
+	for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) {
+		pdd = kfd_process_device_from_gpuidx(ctx->process, gpuidx);
+		if (!pdd) {
+			pr_debug("failed to find device idx %d\n", gpuidx);
+			return -EINVAL;
+		}
+		adev = (struct amdgpu_device *)pdd->dev->kgd;
+		vm = drm_priv_to_vm(pdd->drm_priv);
+
+		ctx->tv[gpuidx].bo = &vm->root.bo->tbo;
+		ctx->tv[gpuidx].num_shared = 4;
+		list_add(&ctx->tv[gpuidx].head, &ctx->validate_list);
+	}
+	if (ctx->prange->svm_bo && ctx->prange->ttm_res) {
+		ctx->tv[MAX_GPU_INSTANCE].bo = &ctx->prange->svm_bo->bo->tbo;
+		ctx->tv[MAX_GPU_INSTANCE].num_shared = 1;
+		list_add(&ctx->tv[MAX_GPU_INSTANCE].head, &ctx->validate_list);
+	}
+
+	r = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->validate_list,
+				   ctx->intr, NULL);
+	if (r) {
+		pr_debug("failed %d to reserve bo\n", r);
+		return r;
+	}
+
+	for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) {
+		pdd = kfd_process_device_from_gpuidx(ctx->process, gpuidx);
+		if (!pdd) {
+			pr_debug("failed to find device idx %d\n", gpuidx);
+			r = -EINVAL;
+			goto unreserve_out;
+		}
+		adev = (struct amdgpu_device *)pdd->dev->kgd;
+
+		r = amdgpu_vm_validate_pt_bos(adev, drm_priv_to_vm(pdd->drm_priv),
+					      svm_range_bo_validate, NULL);
+		if (r) {
+			pr_debug("failed %d validate pt bos\n", r);
+			goto unreserve_out;
+		}
+	}
+
+	return 0;
+
+unreserve_out:
+	ttm_eu_backoff_reservation(&ctx->ticket, &ctx->validate_list);
+	return r;
+}
+
+static void svm_range_unreserve_bos(struct svm_validate_context *ctx)
+{
+	ttm_eu_backoff_reservation(&ctx->ticket, &ctx->validate_list);
+}
+
+/*
+ * Validation+GPU mapping with concurrent invalidation (MMU notifiers)
+ *
+ * To prevent concurrent destruction or change of range attributes, the
+ * svm_read_lock must be held. The caller must not hold the svm_write_lock
+ * because that would block concurrent evictions and lead to deadlocks. To
+ * serialize concurrent migrations or validations of the same range, the
+ * prange->migrate_mutex must be held.
+ *
+ * For VRAM ranges, the SVM BO must be allocated and valid (protected by its
+ * eviction fence.
+ *
+ * The following sequence ensures race-free validation and GPU mapping:
+ *
+ * 1. Reserve page table (and SVM BO if range is in VRAM)
+ * 2. hmm_range_fault to get page addresses (if system memory)
+ * 3. DMA-map pages (if system memory)
+ * 4-a. Take notifier lock
+ * 4-b. Check that pages still valid (mmu_interval_read_retry)
+ * 4-c. Check that the range was not split or otherwise invalidated
+ * 4-d. Update GPU page table
+ * 4.e. Release notifier lock
+ * 5. Release page table (and SVM BO) reservation
+ */
+static int svm_range_validate_and_map(struct mm_struct *mm,
+				      struct svm_range *prange,
+				      int32_t gpuidx, bool intr, bool wait)
+{
+	struct svm_validate_context ctx;
+	struct hmm_range *hmm_range;
+	int r = 0;
+
+	ctx.process = container_of(prange->svms, struct kfd_process, svms);
+	ctx.prange = prange;
+	ctx.intr = intr;
+
+	if (gpuidx < MAX_GPU_INSTANCE) {
+		bitmap_zero(ctx.bitmap, MAX_GPU_INSTANCE);
+		bitmap_set(ctx.bitmap, gpuidx, 1);
+	} else if (ctx.process->xnack_enabled) {
+		bitmap_copy(ctx.bitmap, prange->bitmap_aip, MAX_GPU_INSTANCE);
+
+		/* If prefetch range to GPU, or GPU retry fault migrate range to
+		 * GPU, which has ACCESS attribute to the range, create mapping
+		 * on that GPU.
+		 */
+		if (prange->actual_loc) {
+			gpuidx = kfd_process_gpuidx_from_gpuid(ctx.process,
+							prange->actual_loc);
+			if (gpuidx < 0) {
+				WARN_ONCE(1, "failed get device by id 0x%x\n",
+					 prange->actual_loc);
+				return -EINVAL;
+			}
+			if (test_bit(gpuidx, prange->bitmap_access))
+				bitmap_set(ctx.bitmap, gpuidx, 1);
+		}
+	} else {
+		bitmap_or(ctx.bitmap, prange->bitmap_access,
+			  prange->bitmap_aip, MAX_GPU_INSTANCE);
+	}
+
+	if (bitmap_empty(ctx.bitmap, MAX_GPU_INSTANCE))
+		return 0;
+
+	if (prange->actual_loc && !prange->ttm_res) {
+		/* This should never happen. actual_loc gets set by
+		 * svm_migrate_ram_to_vram after allocating a BO.
+		 */
+		WARN(1, "VRAM BO missing during validation\n");
+		return -EINVAL;
+	}
+
+	svm_range_reserve_bos(&ctx);
+
+	if (!prange->actual_loc) {
+		r = amdgpu_hmm_range_get_pages(&prange->notifier, mm, NULL,
+					       prange->start << PAGE_SHIFT,
+					       prange->npages, &hmm_range,
+					       false, true);
+		if (r) {
+			pr_debug("failed %d to get svm range pages\n", r);
+			goto unreserve_out;
+		}
+
+		r = svm_range_dma_map(prange, ctx.bitmap,
+				      hmm_range->hmm_pfns);
+		if (r) {
+			pr_debug("failed %d to dma map range\n", r);
+			goto unreserve_out;
+		}
+
+		prange->validated_once = true;
+	}
+
+	svm_range_lock(prange);
+	if (!prange->actual_loc) {
+		if (amdgpu_hmm_range_get_pages_done(hmm_range)) {
+			pr_debug("hmm update the range, need validate again\n");
+			r = -EAGAIN;
+			goto unlock_out;
+		}
+	}
+	if (!list_empty(&prange->child_list)) {
+		pr_debug("range split by unmap in parallel, validate again\n");
+		r = -EAGAIN;
+		goto unlock_out;
+	}
+
+	r = svm_range_map_to_gpus(prange, ctx.bitmap, wait);
+
+unlock_out:
+	svm_range_unlock(prange);
+unreserve_out:
+	svm_range_unreserve_bos(&ctx);
+
+	if (!r)
+		prange->validate_timestamp = ktime_to_us(ktime_get());
+
+	return r;
+}
+
+/**
+ * svm_range_list_lock_and_flush_work - flush pending deferred work
+ *
+ * @svms: the svm range list
+ * @mm: the mm structure
+ *
+ * Context: Returns with mmap write lock held, pending deferred work flushed
+ *
+ */
+static void
+svm_range_list_lock_and_flush_work(struct svm_range_list *svms,
+				   struct mm_struct *mm)
+{
+retry_flush_work:
+	flush_work(&svms->deferred_list_work);
+	mmap_write_lock(mm);
+
+	if (list_empty(&svms->deferred_range_list))
+		return;
+	mmap_write_unlock(mm);
+	pr_debug("retry flush\n");
+	goto retry_flush_work;
+}
+
+static void svm_range_restore_work(struct work_struct *work)
+{
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct amdkfd_process_info *process_info;
+	struct svm_range_list *svms;
+	struct svm_range *prange;
+	struct kfd_process *p;
+	struct mm_struct *mm;
+	int evicted_ranges;
+	int invalid;
+	int r;
+
+	svms = container_of(dwork, struct svm_range_list, restore_work);
+	evicted_ranges = atomic_read(&svms->evicted_ranges);
+	if (!evicted_ranges)
+		return;
+
+	pr_debug("restore svm ranges\n");
+
+	/* kfd_process_notifier_release destroys this worker thread. So during
+	 * the lifetime of this thread, kfd_process and mm will be valid.
+	 */
+	p = container_of(svms, struct kfd_process, svms);
+	process_info = p->kgd_process_info;
+	mm = p->mm;
+	if (!mm)
+		return;
+
+	mutex_lock(&process_info->lock);
+	svm_range_list_lock_and_flush_work(svms, mm);
+	mutex_lock(&svms->lock);
+
+	evicted_ranges = atomic_read(&svms->evicted_ranges);
+
+	list_for_each_entry(prange, &svms->list, list) {
+		invalid = atomic_read(&prange->invalid);
+		if (!invalid)
+			continue;
+
+		pr_debug("restoring svms 0x%p prange 0x%p [0x%lx %lx] inv %d\n",
+			 prange->svms, prange, prange->start, prange->last,
+			 invalid);
+
+		/*
+		 * If range is migrating, wait for migration is done.
+		 */
+		mutex_lock(&prange->migrate_mutex);
+
+		r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,
+					       false, true);
+		if (r)
+			pr_debug("failed %d to map 0x%lx to gpus\n", r,
+				 prange->start);
+
+		mutex_unlock(&prange->migrate_mutex);
+		if (r)
+			goto out_reschedule;
+
+		if (atomic_cmpxchg(&prange->invalid, invalid, 0) != invalid)
+			goto out_reschedule;
+	}
+
+	if (atomic_cmpxchg(&svms->evicted_ranges, evicted_ranges, 0) !=
+	    evicted_ranges)
+		goto out_reschedule;
+
+	evicted_ranges = 0;
+
+	r = kgd2kfd_resume_mm(mm);
+	if (r) {
+		/* No recovery from this failure. Probably the CP is
+		 * hanging. No point trying again.
+		 */
+		pr_debug("failed %d to resume KFD\n", r);
+	}
+
+	pr_debug("restore svm ranges successfully\n");
+
+out_reschedule:
+	mutex_unlock(&svms->lock);
+	mmap_write_unlock(mm);
+	mutex_unlock(&process_info->lock);
+
+	/* If validation failed, reschedule another attempt */
+	if (evicted_ranges) {
+		pr_debug("reschedule to restore svm range\n");
+		schedule_delayed_work(&svms->restore_work,
+			msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS));
+	}
+}
+
+/**
+ * svm_range_evict - evict svm range
+ *
+ * Stop all queues of the process to ensure GPU doesn't access the memory, then
+ * return to let CPU evict the buffer and proceed CPU pagetable update.
+ *
+ * Don't need use lock to sync cpu pagetable invalidation with GPU execution.
+ * If invalidation happens while restore work is running, restore work will
+ * restart to ensure to get the latest CPU pages mapping to GPU, then start
+ * the queues.
+ */
+static int
+svm_range_evict(struct svm_range *prange, struct mm_struct *mm,
+		unsigned long start, unsigned long last)
+{
+	struct svm_range_list *svms = prange->svms;
+	struct kfd_process *p;
+	int r = 0;
+
+	p = container_of(svms, struct kfd_process, svms);
+
+	pr_debug("invalidate svms 0x%p prange [0x%lx 0x%lx] [0x%lx 0x%lx]\n",
+		 svms, prange->start, prange->last, start, last);
+
+	if (!p->xnack_enabled) {
+		int evicted_ranges;
+
+		atomic_inc(&prange->invalid);
+		evicted_ranges = atomic_inc_return(&svms->evicted_ranges);
+		if (evicted_ranges != 1)
+			return r;
+
+		pr_debug("evicting svms 0x%p range [0x%lx 0x%lx]\n",
+			 prange->svms, prange->start, prange->last);
+
+		/* First eviction, stop the queues */
+		r = kgd2kfd_quiesce_mm(mm);
+		if (r)
+			pr_debug("failed to quiesce KFD\n");
+
+		pr_debug("schedule to restore svm %p ranges\n", svms);
+		schedule_delayed_work(&svms->restore_work,
+			msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS));
+	} else {
+		struct svm_range *pchild;
+		unsigned long s, l;
+
+		pr_debug("invalidate unmap svms 0x%p [0x%lx 0x%lx] from GPUs\n",
+			 prange->svms, start, last);
+		list_for_each_entry(pchild, &prange->child_list, child_list) {
+			mutex_lock_nested(&pchild->lock, 1);
+			s = max(start, pchild->start);
+			l = min(last, pchild->last);
+			if (l >= s)
+				svm_range_unmap_from_gpus(pchild, s, l);
+			mutex_unlock(&pchild->lock);
+		}
+		s = max(start, prange->start);
+		l = min(last, prange->last);
+		if (l >= s)
+			svm_range_unmap_from_gpus(prange, s, l);
+	}
+
+	return r;
+}
+
+static struct svm_range *svm_range_clone(struct svm_range *old)
+{
+	struct svm_range *new;
+
+	new = svm_range_new(old->svms, old->start, old->last);
+	if (!new)
+		return NULL;
+
+	if (old->svm_bo) {
+		new->ttm_res = old->ttm_res;
+		new->offset = old->offset;
+		new->svm_bo = svm_range_bo_ref(old->svm_bo);
+		spin_lock(&new->svm_bo->list_lock);
+		list_add(&new->svm_bo_list, &new->svm_bo->range_list);
+		spin_unlock(&new->svm_bo->list_lock);
+	}
+	new->flags = old->flags;
+	new->preferred_loc = old->preferred_loc;
+	new->prefetch_loc = old->prefetch_loc;
+	new->actual_loc = old->actual_loc;
+	new->granularity = old->granularity;
+	bitmap_copy(new->bitmap_access, old->bitmap_access, MAX_GPU_INSTANCE);
+	bitmap_copy(new->bitmap_aip, old->bitmap_aip, MAX_GPU_INSTANCE);
+
+	return new;
+}
+
+/**
+ * svm_range_handle_overlap - split overlap ranges
+ * @svms: svm range list header
+ * @new: range added with this attributes
+ * @start: range added start address, in pages
+ * @last: range last address, in pages
+ * @update_list: output, the ranges attributes are updated. For set_attr, this
+ *               will do validation and map to GPUs. For unmap, this will be
+ *               removed and unmap from GPUs
+ * @insert_list: output, the ranges will be inserted into svms, attributes are
+ *               not changes. For set_attr, this will add into svms.
+ * @remove_list:output, the ranges will be removed from svms
+ * @left: the remaining range after overlap, For set_attr, this will be added
+ *        as new range.
+ *
+ * Total have 5 overlap cases.
+ *
+ * This function handles overlap of an address interval with existing
+ * struct svm_ranges for applying new attributes. This may require
+ * splitting existing struct svm_ranges. All changes should be applied to
+ * the range_list and interval tree transactionally. If any split operation
+ * fails, the entire update fails. Therefore the existing overlapping
+ * svm_ranges are cloned and the original svm_ranges left unchanged. If the
+ * transaction succeeds, the modified clones are added and the originals
+ * freed. Otherwise the clones are removed and the old svm_ranges remain.
+ *
+ * Context: The caller must hold svms->lock
+ */
+static int
+svm_range_handle_overlap(struct svm_range_list *svms, struct svm_range *new,
+			 unsigned long start, unsigned long last,
+			 struct list_head *update_list,
+			 struct list_head *insert_list,
+			 struct list_head *remove_list,
+			 unsigned long *left)
+{
+	struct interval_tree_node *node;
+	struct svm_range *prange;
+	struct svm_range *tmp;
+	int r = 0;
+
+	INIT_LIST_HEAD(update_list);
+	INIT_LIST_HEAD(insert_list);
+	INIT_LIST_HEAD(remove_list);
+
+	node = interval_tree_iter_first(&svms->objects, start, last);
+	while (node) {
+		struct interval_tree_node *next;
+		struct svm_range *old;
+		unsigned long next_start;
+
+		pr_debug("found overlap node [0x%lx 0x%lx]\n", node->start,
+			 node->last);
+
+		old = container_of(node, struct svm_range, it_node);
+		next = interval_tree_iter_next(node, start, last);
+		next_start = min(node->last, last) + 1;
+
+		if (node->start < start || node->last > last) {
+			/* node intersects the updated range, clone+split it */
+			prange = svm_range_clone(old);
+			if (!prange) {
+				r = -ENOMEM;
+				goto out;
+			}
+
+			list_add(&old->remove_list, remove_list);
+			list_add(&prange->insert_list, insert_list);
+
+			if (node->start < start) {
+				pr_debug("change old range start\n");
+				r = svm_range_split_head(prange, new, start,
+							 insert_list);
+				if (r)
+					goto out;
+			}
+			if (node->last > last) {
+				pr_debug("change old range last\n");
+				r = svm_range_split_tail(prange, new, last,
+							 insert_list);
+				if (r)
+					goto out;
+			}
+		} else {
+			/* The node is contained within start..last,
+			 * just update it
+			 */
+			prange = old;
+		}
+
+		if (!svm_range_is_same_attrs(prange, new))
+			list_add(&prange->update_list, update_list);
+
+		/* insert a new node if needed */
+		if (node->start > start) {
+			prange = svm_range_new(prange->svms, start,
+					       node->start - 1);
+			if (!prange) {
+				r = -ENOMEM;
+				goto out;
+			}
+
+			list_add(&prange->insert_list, insert_list);
+			list_add(&prange->update_list, update_list);
+		}
+
+		node = next;
+		start = next_start;
+	}
+
+	if (left && start <= last)
+		*left = last - start + 1;
+
+out:
+	if (r)
+		list_for_each_entry_safe(prange, tmp, insert_list, insert_list)
+			svm_range_free(prange);
+
+	return r;
+}
+
+static void
+svm_range_update_notifier_and_interval_tree(struct mm_struct *mm,
+					    struct svm_range *prange)
+{
+	unsigned long start;
+	unsigned long last;
+
+	start = prange->notifier.interval_tree.start >> PAGE_SHIFT;
+	last = prange->notifier.interval_tree.last >> PAGE_SHIFT;
+
+	if (prange->start == start && prange->last == last)
+		return;
+
+	pr_debug("up notifier 0x%p prange 0x%p [0x%lx 0x%lx] [0x%lx 0x%lx]\n",
+		  prange->svms, prange, start, last, prange->start,
+		  prange->last);
+
+	if (start != 0 && last != 0) {
+		interval_tree_remove(&prange->it_node, &prange->svms->objects);
+		svm_range_remove_notifier(prange);
+	}
+	prange->it_node.start = prange->start;
+	prange->it_node.last = prange->last;
+
+	interval_tree_insert(&prange->it_node, &prange->svms->objects);
+	svm_range_add_notifier_locked(mm, prange);
+}
+
+static void
+svm_range_handle_list_op(struct svm_range_list *svms, struct svm_range *prange)
+{
+	struct mm_struct *mm = prange->work_item.mm;
+
+	switch (prange->work_item.op) {
+	case SVM_OP_NULL:
+		pr_debug("NULL OP 0x%p prange 0x%p [0x%lx 0x%lx]\n",
+			 svms, prange, prange->start, prange->last);
+		break;
+	case SVM_OP_UNMAP_RANGE:
+		pr_debug("remove 0x%p prange 0x%p [0x%lx 0x%lx]\n",
+			 svms, prange, prange->start, prange->last);
+		svm_range_unlink(prange);
+		svm_range_remove_notifier(prange);
+		svm_range_free(prange);
+		break;
+	case SVM_OP_UPDATE_RANGE_NOTIFIER:
+		pr_debug("update notifier 0x%p prange 0x%p [0x%lx 0x%lx]\n",
+			 svms, prange, prange->start, prange->last);
+		svm_range_update_notifier_and_interval_tree(mm, prange);
+		break;
+	case SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP:
+		pr_debug("update and map 0x%p prange 0x%p [0x%lx 0x%lx]\n",
+			 svms, prange, prange->start, prange->last);
+		svm_range_update_notifier_and_interval_tree(mm, prange);
+		/* TODO: implement deferred validation and mapping */
+		break;
+	case SVM_OP_ADD_RANGE:
+		pr_debug("add 0x%p prange 0x%p [0x%lx 0x%lx]\n", svms, prange,
+			 prange->start, prange->last);
+		svm_range_add_to_svms(prange);
+		svm_range_add_notifier_locked(mm, prange);
+		break;
+	case SVM_OP_ADD_RANGE_AND_MAP:
+		pr_debug("add and map 0x%p prange 0x%p [0x%lx 0x%lx]\n", svms,
+			 prange, prange->start, prange->last);
+		svm_range_add_to_svms(prange);
+		svm_range_add_notifier_locked(mm, prange);
+		/* TODO: implement deferred validation and mapping */
+		break;
+	default:
+		WARN_ONCE(1, "Unknown prange 0x%p work op %d\n", prange,
+			 prange->work_item.op);
+	}
+}
+
+static void svm_range_drain_retry_fault(struct svm_range_list *svms)
+{
+	struct kfd_process_device *pdd;
+	struct amdgpu_device *adev;
+	struct kfd_process *p;
+	uint32_t i;
+
+	p = container_of(svms, struct kfd_process, svms);
+
+	for_each_set_bit(i, svms->bitmap_supported, p->n_pdds) {
+		pdd = p->pdds[i];
+		if (!pdd)
+			continue;
+
+		pr_debug("drain retry fault gpu %d svms %p\n", i, svms);
+		adev = (struct amdgpu_device *)pdd->dev->kgd;
+
+		amdgpu_ih_wait_on_checkpoint_process(adev, &adev->irq.ih1);
+		pr_debug("drain retry fault gpu %d svms 0x%p done\n", i, svms);
+	}
+}
+
+static void svm_range_deferred_list_work(struct work_struct *work)
+{
+	struct svm_range_list *svms;
+	struct svm_range *prange;
+	struct mm_struct *mm;
+
+	svms = container_of(work, struct svm_range_list, deferred_list_work);
+	pr_debug("enter svms 0x%p\n", svms);
+
+	spin_lock(&svms->deferred_list_lock);
+	while (!list_empty(&svms->deferred_range_list)) {
+		prange = list_first_entry(&svms->deferred_range_list,
+					  struct svm_range, deferred_list);
+		spin_unlock(&svms->deferred_list_lock);
+		pr_debug("prange 0x%p [0x%lx 0x%lx] op %d\n", prange,
+			 prange->start, prange->last, prange->work_item.op);
+
+		/* Make sure no stale retry fault coming after range is freed */
+		if (prange->work_item.op == SVM_OP_UNMAP_RANGE)
+			svm_range_drain_retry_fault(prange->svms);
+
+		mm = prange->work_item.mm;
+		mmap_write_lock(mm);
+		mutex_lock(&svms->lock);
+
+		/* Remove from deferred_list must be inside mmap write lock,
+		 * otherwise, svm_range_list_lock_and_flush_work may hold mmap
+		 * write lock, and continue because deferred_list is empty, then
+		 * deferred_list handle is blocked by mmap write lock.
+		 */
+		spin_lock(&svms->deferred_list_lock);
+		list_del_init(&prange->deferred_list);
+		spin_unlock(&svms->deferred_list_lock);
+
+		mutex_lock(&prange->migrate_mutex);
+		while (!list_empty(&prange->child_list)) {
+			struct svm_range *pchild;
+
+			pchild = list_first_entry(&prange->child_list,
+						struct svm_range, child_list);
+			pr_debug("child prange 0x%p op %d\n", pchild,
+				 pchild->work_item.op);
+			list_del_init(&pchild->child_list);
+			svm_range_handle_list_op(svms, pchild);
+		}
+		mutex_unlock(&prange->migrate_mutex);
+
+		svm_range_handle_list_op(svms, prange);
+		mutex_unlock(&svms->lock);
+		mmap_write_unlock(mm);
+
+		spin_lock(&svms->deferred_list_lock);
+	}
+	spin_unlock(&svms->deferred_list_lock);
+
+	pr_debug("exit svms 0x%p\n", svms);
+}
+
+void
+svm_range_add_list_work(struct svm_range_list *svms, struct svm_range *prange,
+			struct mm_struct *mm, enum svm_work_list_ops op)
+{
+	spin_lock(&svms->deferred_list_lock);
+	/* if prange is on the deferred list */
+	if (!list_empty(&prange->deferred_list)) {
+		pr_debug("update exist prange 0x%p work op %d\n", prange, op);
+		WARN_ONCE(prange->work_item.mm != mm, "unmatch mm\n");
+		if (op != SVM_OP_NULL &&
+		    prange->work_item.op != SVM_OP_UNMAP_RANGE)
+			prange->work_item.op = op;
+	} else {
+		prange->work_item.op = op;
+		prange->work_item.mm = mm;
+		list_add_tail(&prange->deferred_list,
+			      &prange->svms->deferred_range_list);
+		pr_debug("add prange 0x%p [0x%lx 0x%lx] to work list op %d\n",
+			 prange, prange->start, prange->last, op);
+	}
+	spin_unlock(&svms->deferred_list_lock);
+}
+
+void schedule_deferred_list_work(struct svm_range_list *svms)
+{
+	spin_lock(&svms->deferred_list_lock);
+	if (!list_empty(&svms->deferred_range_list))
+		schedule_work(&svms->deferred_list_work);
+	spin_unlock(&svms->deferred_list_lock);
+}
+
+static void
+svm_range_unmap_split(struct mm_struct *mm, struct svm_range *parent,
+		      struct svm_range *prange, unsigned long start,
+		      unsigned long last)
+{
+	struct svm_range *head;
+	struct svm_range *tail;
+
+	if (prange->work_item.op == SVM_OP_UNMAP_RANGE) {
+		pr_debug("prange 0x%p [0x%lx 0x%lx] is already freed\n", prange,
+			 prange->start, prange->last);
+		return;
+	}
+	if (start > prange->last || last < prange->start)
+		return;
+
+	head = tail = prange;
+	if (start > prange->start)
+		svm_range_split(prange, prange->start, start - 1, &tail);
+	if (last < tail->last)
+		svm_range_split(tail, last + 1, tail->last, &head);
+
+	if (head != prange && tail != prange) {
+		svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE);
+		svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE);
+	} else if (tail != prange) {
+		svm_range_add_child(parent, mm, tail, SVM_OP_UNMAP_RANGE);
+	} else if (head != prange) {
+		svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE);
+	} else if (parent != prange) {
+		prange->work_item.op = SVM_OP_UNMAP_RANGE;
+	}
+}
+
+static void
+svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange,
+			 unsigned long start, unsigned long last)
+{
+	struct svm_range_list *svms;
+	struct svm_range *pchild;
+	struct kfd_process *p;
+	unsigned long s, l;
+	bool unmap_parent;
+
+	p = kfd_lookup_process_by_mm(mm);
+	if (!p)
+		return;
+	svms = &p->svms;
+
+	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] [0x%lx 0x%lx]\n", svms,
+		 prange, prange->start, prange->last, start, last);
+
+	unmap_parent = start <= prange->start && last >= prange->last;
+
+	list_for_each_entry(pchild, &prange->child_list, child_list) {
+		mutex_lock_nested(&pchild->lock, 1);
+		s = max(start, pchild->start);
+		l = min(last, pchild->last);
+		if (l >= s)
+			svm_range_unmap_from_gpus(pchild, s, l);
+		svm_range_unmap_split(mm, prange, pchild, start, last);
+		mutex_unlock(&pchild->lock);
+	}
+	s = max(start, prange->start);
+	l = min(last, prange->last);
+	if (l >= s)
+		svm_range_unmap_from_gpus(prange, s, l);
+	svm_range_unmap_split(mm, prange, prange, start, last);
+
+	if (unmap_parent)
+		svm_range_add_list_work(svms, prange, mm, SVM_OP_UNMAP_RANGE);
+	else
+		svm_range_add_list_work(svms, prange, mm,
+					SVM_OP_UPDATE_RANGE_NOTIFIER);
+	schedule_deferred_list_work(svms);
+
+	kfd_unref_process(p);
+}
+
+/**
+ * svm_range_cpu_invalidate_pagetables - interval notifier callback
+ *
+ * If event is MMU_NOTIFY_UNMAP, this is from CPU unmap range, otherwise, it
+ * is from migration, or CPU page invalidation callback.
+ *
+ * For unmap event, unmap range from GPUs, remove prange from svms in a delayed
+ * work thread, and split prange if only part of prange is unmapped.
+ *
+ * For invalidation event, if GPU retry fault is not enabled, evict the queues,
+ * then schedule svm_range_restore_work to update GPU mapping and resume queues.
+ * If GPU retry fault is enabled, unmap the svm range from GPU, retry fault will
+ * update GPU mapping to recover.
+ *
+ * Context: mmap lock, notifier_invalidate_start lock are held
+ *          for invalidate event, prange lock is held if this is from migration
+ */
+static bool
+svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni,
+				    const struct mmu_notifier_range *range,
+				    unsigned long cur_seq)
+{
+	struct svm_range *prange;
+	unsigned long start;
+	unsigned long last;
+
+	if (range->event == MMU_NOTIFY_RELEASE)
+		return true;
+
+	start = mni->interval_tree.start;
+	last = mni->interval_tree.last;
+	start = (start > range->start ? start : range->start) >> PAGE_SHIFT;
+	last = (last < (range->end - 1) ? last : range->end - 1) >> PAGE_SHIFT;
+	pr_debug("[0x%lx 0x%lx] range[0x%lx 0x%lx] notifier[0x%lx 0x%lx] %d\n",
+		 start, last, range->start >> PAGE_SHIFT,
+		 (range->end - 1) >> PAGE_SHIFT,
+		 mni->interval_tree.start >> PAGE_SHIFT,
+		 mni->interval_tree.last >> PAGE_SHIFT, range->event);
+
+	prange = container_of(mni, struct svm_range, notifier);
+
+	svm_range_lock(prange);
+	mmu_interval_set_seq(mni, cur_seq);
+
+	switch (range->event) {
+	case MMU_NOTIFY_UNMAP:
+		svm_range_unmap_from_cpu(mni->mm, prange, start, last);
+		break;
+	default:
+		svm_range_evict(prange, mni->mm, start, last);
+		break;
+	}
+
+	svm_range_unlock(prange);
+
+	return true;
+}
+
+/**
+ * svm_range_from_addr - find svm range from fault address
+ * @svms: svm range list header
+ * @addr: address to search range interval tree, in pages
+ * @parent: parent range if range is on child list
+ *
+ * Context: The caller must hold svms->lock
+ *
+ * Return: the svm_range found or NULL
+ */
+struct svm_range *
+svm_range_from_addr(struct svm_range_list *svms, unsigned long addr,
+		    struct svm_range **parent)
+{
+	struct interval_tree_node *node;
+	struct svm_range *prange;
+	struct svm_range *pchild;
+
+	node = interval_tree_iter_first(&svms->objects, addr, addr);
+	if (!node)
+		return NULL;
+
+	prange = container_of(node, struct svm_range, it_node);
+	pr_debug("address 0x%lx prange [0x%lx 0x%lx] node [0x%lx 0x%lx]\n",
+		 addr, prange->start, prange->last, node->start, node->last);
+
+	if (addr >= prange->start && addr <= prange->last) {
+		if (parent)
+			*parent = prange;
+		return prange;
+	}
+	list_for_each_entry(pchild, &prange->child_list, child_list)
+		if (addr >= pchild->start && addr <= pchild->last) {
+			pr_debug("found address 0x%lx pchild [0x%lx 0x%lx]\n",
+				 addr, pchild->start, pchild->last);
+			if (parent)
+				*parent = prange;
+			return pchild;
+		}
+
+	return NULL;
+}
+
+/* svm_range_best_restore_location - decide the best fault restore location
+ * @prange: svm range structure
+ * @adev: the GPU on which vm fault happened
+ *
+ * This is only called when xnack is on, to decide the best location to restore
+ * the range mapping after GPU vm fault. Caller uses the best location to do
+ * migration if actual loc is not best location, then update GPU page table
+ * mapping to the best location.
+ *
+ * If vm fault gpu is range preferred loc, the best_loc is preferred loc.
+ * If vm fault gpu idx is on range ACCESSIBLE bitmap, best_loc is vm fault gpu
+ * If vm fault gpu idx is on range ACCESSIBLE_IN_PLACE bitmap, then
+ *    if range actual loc is cpu, best_loc is cpu
+ *    if vm fault gpu is on xgmi same hive of range actual loc gpu, best_loc is
+ *    range actual loc.
+ * Otherwise, GPU no access, best_loc is -1.
+ *
+ * Return:
+ * -1 means vm fault GPU no access
+ * 0 for CPU or GPU id
+ */
+static int32_t
+svm_range_best_restore_location(struct svm_range *prange,
+				struct amdgpu_device *adev,
+				int32_t *gpuidx)
+{
+	struct amdgpu_device *bo_adev;
+	struct kfd_process *p;
+	uint32_t gpuid;
+	int r;
+
+	p = container_of(prange->svms, struct kfd_process, svms);
+
+	r = kfd_process_gpuid_from_kgd(p, adev, &gpuid, gpuidx);
+	if (r < 0) {
+		pr_debug("failed to get gpuid from kgd\n");
+		return -1;
+	}
+
+	if (prange->preferred_loc == gpuid)
+		return prange->preferred_loc;
+
+	if (test_bit(*gpuidx, prange->bitmap_access))
+		return gpuid;
+
+	if (test_bit(*gpuidx, prange->bitmap_aip)) {
+		if (!prange->actual_loc)
+			return 0;
+
+		bo_adev = svm_range_get_adev_by_id(prange, prange->actual_loc);
+		if (amdgpu_xgmi_same_hive(adev, bo_adev))
+			return prange->actual_loc;
+		else
+			return 0;
+	}
+
+	return -1;
+}
+static int
+svm_range_get_range_boundaries(struct kfd_process *p, int64_t addr,
+				unsigned long *start, unsigned long *last)
+{
+	struct vm_area_struct *vma;
+	struct interval_tree_node *node;
+	unsigned long start_limit, end_limit;
+
+	vma = find_vma(p->mm, addr << PAGE_SHIFT);
+	if (!vma || (addr << PAGE_SHIFT) < vma->vm_start) {
+		pr_debug("VMA does not exist in address [0x%llx]\n", addr);
+		return -EFAULT;
+	}
+	start_limit = max(vma->vm_start >> PAGE_SHIFT,
+		      (unsigned long)ALIGN_DOWN(addr, 2UL << 8));
+	end_limit = min(vma->vm_end >> PAGE_SHIFT,
+		    (unsigned long)ALIGN(addr + 1, 2UL << 8));
+	/* First range that starts after the fault address */
+	node = interval_tree_iter_first(&p->svms.objects, addr + 1, ULONG_MAX);
+	if (node) {
+		end_limit = min(end_limit, node->start);
+		/* Last range that ends before the fault address */
+		node = container_of(rb_prev(&node->rb),
+				    struct interval_tree_node, rb);
+	} else {
+		/* Last range must end before addr because
+		 * there was no range after addr
+		 */
+		node = container_of(rb_last(&p->svms.objects.rb_root),
+				    struct interval_tree_node, rb);
+	}
+	if (node) {
+		if (node->last >= addr) {
+			WARN(1, "Overlap with prev node and page fault addr\n");
+			return -EFAULT;
+		}
+		start_limit = max(start_limit, node->last + 1);
+	}
+
+	*start = start_limit;
+	*last = end_limit - 1;
+
+	pr_debug("vma start: 0x%lx start: 0x%lx vma end: 0x%lx last: 0x%lx\n",
+		  vma->vm_start >> PAGE_SHIFT, *start,
+		  vma->vm_end >> PAGE_SHIFT, *last);
+
+	return 0;
+
+}
+static struct
+svm_range *svm_range_create_unregistered_range(struct amdgpu_device *adev,
+						struct kfd_process *p,
+						struct mm_struct *mm,
+						int64_t addr)
+{
+	struct svm_range *prange = NULL;
+	unsigned long start, last;
+	uint32_t gpuid, gpuidx;
+
+	if (svm_range_get_range_boundaries(p, addr, &start, &last))
+		return NULL;
+
+	prange = svm_range_new(&p->svms, start, last);
+	if (!prange) {
+		pr_debug("Failed to create prange in address [0x%llx]\n", addr);
+		return NULL;
+	}
+	if (kfd_process_gpuid_from_kgd(p, adev, &gpuid, &gpuidx)) {
+		pr_debug("failed to get gpuid from kgd\n");
+		svm_range_free(prange);
+		return NULL;
+	}
+
+	svm_range_add_to_svms(prange);
+	svm_range_add_notifier_locked(mm, prange);
+
+	return prange;
+}
+
+/* svm_range_skip_recover - decide if prange can be recovered
+ * @prange: svm range structure
+ *
+ * GPU vm retry fault handle skip recover the range for cases:
+ * 1. prange is on deferred list to be removed after unmap, it is stale fault,
+ *    deferred list work will drain the stale fault before free the prange.
+ * 2. prange is on deferred list to add interval notifier after split, or
+ * 3. prange is child range, it is split from parent prange, recover later
+ *    after interval notifier is added.
+ *
+ * Return: true to skip recover, false to recover
+ */
+static bool svm_range_skip_recover(struct svm_range *prange)
+{
+	struct svm_range_list *svms = prange->svms;
+
+	spin_lock(&svms->deferred_list_lock);
+	if (list_empty(&prange->deferred_list) &&
+	    list_empty(&prange->child_list)) {
+		spin_unlock(&svms->deferred_list_lock);
+		return false;
+	}
+	spin_unlock(&svms->deferred_list_lock);
+
+	if (prange->work_item.op == SVM_OP_UNMAP_RANGE) {
+		pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] unmapped\n",
+			 svms, prange, prange->start, prange->last);
+		return true;
+	}
+	if (prange->work_item.op == SVM_OP_ADD_RANGE_AND_MAP ||
+	    prange->work_item.op == SVM_OP_ADD_RANGE) {
+		pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] not added yet\n",
+			 svms, prange, prange->start, prange->last);
+		return true;
+	}
+	return false;
+}
+
+int
+svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,
+			uint64_t addr)
+{
+	struct mm_struct *mm = NULL;
+	struct svm_range_list *svms;
+	struct svm_range *prange;
+	struct kfd_process *p;
+	uint64_t timestamp;
+	int32_t best_loc, gpuidx;
+	bool write_locked = false;
+	int r = 0;
+
+	if (!KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev)) {
+		pr_debug("device does not support SVM\n");
+		return -EFAULT;
+	}
+
+	p = kfd_lookup_process_by_pasid(pasid);
+	if (!p) {
+		pr_debug("kfd process not founded pasid 0x%x\n", pasid);
+		return -ESRCH;
+	}
+	if (!p->xnack_enabled) {
+		pr_debug("XNACK not enabled for pasid 0x%x\n", pasid);
+		return -EFAULT;
+	}
+	svms = &p->svms;
+
+	pr_debug("restoring svms 0x%p fault address 0x%llx\n", svms, addr);
+
+	mm = get_task_mm(p->lead_thread);
+	if (!mm) {
+		pr_debug("svms 0x%p failed to get mm\n", svms);
+		r = -ESRCH;
+		goto out;
+	}
+
+	mmap_read_lock(mm);
+retry_write_locked:
+	mutex_lock(&svms->lock);
+	prange = svm_range_from_addr(svms, addr, NULL);
+	if (!prange) {
+		pr_debug("failed to find prange svms 0x%p address [0x%llx]\n",
+			 svms, addr);
+		if (!write_locked) {
+			/* Need the write lock to create new range with MMU notifier.
+			 * Also flush pending deferred work to make sure the interval
+			 * tree is up to date before we add a new range
+			 */
+			mutex_unlock(&svms->lock);
+			mmap_read_unlock(mm);
+			mmap_write_lock(mm);
+			write_locked = true;
+			goto retry_write_locked;
+		}
+		prange = svm_range_create_unregistered_range(adev, p, mm, addr);
+		if (!prange) {
+			pr_debug("failed to create unregistered range svms 0x%p address [0x%llx]\n",
+				 svms, addr);
+			mmap_write_downgrade(mm);
+			r = -EFAULT;
+			goto out_unlock_svms;
+		}
+	}
+	if (write_locked)
+		mmap_write_downgrade(mm);
+
+	mutex_lock(&prange->migrate_mutex);
+
+	if (svm_range_skip_recover(prange)) {
+		amdgpu_gmc_filter_faults_remove(adev, addr, pasid);
+		goto out_unlock_range;
+	}
+
+	timestamp = ktime_to_us(ktime_get()) - prange->validate_timestamp;
+	/* skip duplicate vm fault on different pages of same range */
+	if (timestamp < AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING) {
+		pr_debug("svms 0x%p [0x%lx %lx] already restored\n",
+			 svms, prange->start, prange->last);
+		goto out_unlock_range;
+	}
+
+	best_loc = svm_range_best_restore_location(prange, adev, &gpuidx);
+	if (best_loc == -1) {
+		pr_debug("svms %p failed get best restore loc [0x%lx 0x%lx]\n",
+			 svms, prange->start, prange->last);
+		r = -EACCES;
+		goto out_unlock_range;
+	}
+
+	pr_debug("svms %p [0x%lx 0x%lx] best restore 0x%x, actual loc 0x%x\n",
+		 svms, prange->start, prange->last, best_loc,
+		 prange->actual_loc);
+
+	if (prange->actual_loc != best_loc) {
+		if (best_loc) {
+			r = svm_migrate_to_vram(prange, best_loc, mm);
+			if (r) {
+				pr_debug("svm_migrate_to_vram failed (%d) at %llx, falling back to system memory\n",
+					 r, addr);
+				/* Fallback to system memory if migration to
+				 * VRAM failed
+				 */
+				if (prange->actual_loc)
+					r = svm_migrate_vram_to_ram(prange, mm);
+				else
+					r = 0;
+			}
+		} else {
+			r = svm_migrate_vram_to_ram(prange, mm);
+		}
+		if (r) {
+			pr_debug("failed %d to migrate svms %p [0x%lx 0x%lx]\n",
+				 r, svms, prange->start, prange->last);
+			goto out_unlock_range;
+		}
+	}
+
+	r = svm_range_validate_and_map(mm, prange, gpuidx, false, false);
+	if (r)
+		pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n",
+			 r, svms, prange->start, prange->last);
+
+out_unlock_range:
+	mutex_unlock(&prange->migrate_mutex);
+out_unlock_svms:
+	mutex_unlock(&svms->lock);
+	mmap_read_unlock(mm);
+	mmput(mm);
+out:
+	kfd_unref_process(p);
+
+	if (r == -EAGAIN) {
+		pr_debug("recover vm fault later\n");
+		amdgpu_gmc_filter_faults_remove(adev, addr, pasid);
+		r = 0;
+	}
+	return r;
+}
+
+void svm_range_list_fini(struct kfd_process *p)
+{
+	struct svm_range *prange;
+	struct svm_range *next;
+
+	pr_debug("pasid 0x%x svms 0x%p\n", p->pasid, &p->svms);
+
+	/* Ensure list work is finished before process is destroyed */
+	flush_work(&p->svms.deferred_list_work);
+
+	list_for_each_entry_safe(prange, next, &p->svms.list, list) {
+		svm_range_unlink(prange);
+		svm_range_remove_notifier(prange);
+		svm_range_free(prange);
+	}
+
+	mutex_destroy(&p->svms.lock);
+
+	pr_debug("pasid 0x%x svms 0x%p done\n", p->pasid, &p->svms);
+}
+
+int svm_range_list_init(struct kfd_process *p)
+{
+	struct svm_range_list *svms = &p->svms;
+	int i;
+
+	svms->objects = RB_ROOT_CACHED;
+	mutex_init(&svms->lock);
+	INIT_LIST_HEAD(&svms->list);
+	atomic_set(&svms->evicted_ranges, 0);
+	INIT_DELAYED_WORK(&svms->restore_work, svm_range_restore_work);
+	INIT_WORK(&svms->deferred_list_work, svm_range_deferred_list_work);
+	INIT_LIST_HEAD(&svms->deferred_range_list);
+	spin_lock_init(&svms->deferred_list_lock);
+
+	for (i = 0; i < p->n_pdds; i++)
+		if (KFD_IS_SVM_API_SUPPORTED(p->pdds[i]->dev))
+			bitmap_set(svms->bitmap_supported, i, 1);
+
+	return 0;
+}
+
+/**
+ * svm_range_is_valid - check if virtual address range is valid
+ * @mm: current process mm_struct
+ * @start: range start address, in pages
+ * @size: range size, in pages
+ *
+ * Valid virtual address range means it belongs to one or more VMAs
+ *
+ * Context: Process context
+ *
+ * Return:
+ *  true - valid svm range
+ *  false - invalid svm range
+ */
+static bool
+svm_range_is_valid(struct mm_struct *mm, uint64_t start, uint64_t size)
+{
+	const unsigned long device_vma = VM_IO | VM_PFNMAP | VM_MIXEDMAP;
+	struct vm_area_struct *vma;
+	unsigned long end;
+
+	start <<= PAGE_SHIFT;
+	end = start + (size << PAGE_SHIFT);
+
+	do {
+		vma = find_vma(mm, start);
+		if (!vma || start < vma->vm_start ||
+		    (vma->vm_flags & device_vma))
+			return false;
+		start = min(end, vma->vm_end);
+	} while (start < end);
+
+	return true;
+}
+
+/**
+ * svm_range_add - add svm range and handle overlap
+ * @p: the range add to this process svms
+ * @start: page size aligned
+ * @size: page size aligned
+ * @nattr: number of attributes
+ * @attrs: array of attributes
+ * @update_list: output, the ranges need validate and update GPU mapping
+ * @insert_list: output, the ranges need insert to svms
+ * @remove_list: output, the ranges are replaced and need remove from svms
+ *
+ * Check if the virtual address range has overlap with the registered ranges,
+ * split the overlapped range, copy and adjust pages address and vram nodes in
+ * old and new ranges.
+ *
+ * Context: Process context, caller must hold svms->lock
+ *
+ * Return:
+ * 0 - OK, otherwise error code
+ */
+static int
+svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
+	      uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs,
+	      struct list_head *update_list, struct list_head *insert_list,
+	      struct list_head *remove_list)
+{
+	uint64_t last = start + size - 1UL;
+	struct svm_range_list *svms;
+	struct svm_range new = {0};
+	struct svm_range *prange;
+	unsigned long left = 0;
+	int r = 0;
+
+	pr_debug("svms 0x%p [0x%llx 0x%llx]\n", &p->svms, start, last);
+
+	svm_range_apply_attrs(p, &new, nattr, attrs);
+
+	svms = &p->svms;
+
+	r = svm_range_handle_overlap(svms, &new, start, last, update_list,
+				     insert_list, remove_list, &left);
+	if (r)
+		return r;
+
+	if (left) {
+		prange = svm_range_new(svms, last - left + 1, last);
+		list_add(&prange->insert_list, insert_list);
+		list_add(&prange->update_list, update_list);
+	}
+
+	return 0;
+}
+
+/* svm_range_best_prefetch_location - decide the best prefetch location
+ * @prange: svm range structure
+ *
+ * For xnack off:
+ * If range map to single GPU, the best acutal location is prefetch loc, which
+ * can be CPU or GPU.
+ *
+ * If range map to multiple GPUs, only if mGPU connection on xgmi same hive,
+ * the best actual location could be prefetch_loc GPU. If mGPU connection on
+ * PCIe, the best actual location is always CPU, because GPU cannot access vram
+ * of other GPUs, assuming PCIe small bar (large bar support is not upstream).
+ *
+ * For xnack on:
+ * The best actual location is prefetch location. If mGPU connection on xgmi
+ * same hive, range map to multiple GPUs. Otherwise, the range only map to
+ * actual location GPU. Other GPU access vm fault will trigger migration.
+ *
+ * Context: Process context
+ *
+ * Return:
+ * 0 for CPU or GPU id
+ */
+static uint32_t
+svm_range_best_prefetch_location(struct svm_range *prange)
+{
+	DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE);
+	uint32_t best_loc = prange->prefetch_loc;
+	struct kfd_process_device *pdd;
+	struct amdgpu_device *bo_adev;
+	struct amdgpu_device *adev;
+	struct kfd_process *p;
+	uint32_t gpuidx;
+
+	p = container_of(prange->svms, struct kfd_process, svms);
+
+	/* xnack on */
+	if (p->xnack_enabled)
+		goto out;
+
+	/* xnack off */
+	if (!best_loc || best_loc == KFD_IOCTL_SVM_LOCATION_UNDEFINED)
+		goto out;
+
+	bo_adev = svm_range_get_adev_by_id(prange, best_loc);
+	if (!bo_adev) {
+		WARN_ONCE(1, "failed to get device by id 0x%x\n", best_loc);
+		best_loc = 0;
+		goto out;
+	}
+	bitmap_or(bitmap, prange->bitmap_access, prange->bitmap_aip,
+		  MAX_GPU_INSTANCE);
+
+	for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
+		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
+		if (!pdd) {
+			pr_debug("failed to get device by idx 0x%x\n", gpuidx);
+			continue;
+		}
+		adev = (struct amdgpu_device *)pdd->dev->kgd;
+
+		if (adev == bo_adev)
+			continue;
+
+		if (!amdgpu_xgmi_same_hive(adev, bo_adev)) {
+			best_loc = 0;
+			break;
+		}
+	}
+
+out:
+	pr_debug("xnack %d svms 0x%p [0x%lx 0x%lx] best loc 0x%x\n",
+		 p->xnack_enabled, &p->svms, prange->start, prange->last,
+		 best_loc);
+
+	return best_loc;
+}
+
+/* FIXME: This is a workaround for page locking bug when some pages are
+ * invalid during migration to VRAM
+ */
+void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm)
+{
+	struct hmm_range *hmm_range;
+	int r;
+
+	if (prange->validated_once)
+		return;
+
+	r = amdgpu_hmm_range_get_pages(&prange->notifier, mm, NULL,
+				       prange->start << PAGE_SHIFT,
+				       prange->npages, &hmm_range,
+				       false, true);
+	if (!r) {
+		amdgpu_hmm_range_get_pages_done(hmm_range);
+		prange->validated_once = true;
+	}
+}
+
+/* svm_range_trigger_migration - start page migration if prefetch loc changed
+ * @mm: current process mm_struct
+ * @prange: svm range structure
+ * @migrated: output, true if migration is triggered
+ *
+ * If range perfetch_loc is GPU, actual loc is cpu 0, then migrate the range
+ * from ram to vram.
+ * If range prefetch_loc is cpu 0, actual loc is GPU, then migrate the range
+ * from vram to ram.
+ *
+ * If GPU vm fault retry is not enabled, migration interact with MMU notifier
+ * and restore work:
+ * 1. migrate_vma_setup invalidate pages, MMU notifier callback svm_range_evict
+ *    stops all queues, schedule restore work
+ * 2. svm_range_restore_work wait for migration is done by
+ *    a. svm_range_validate_vram takes prange->migrate_mutex
+ *    b. svm_range_validate_ram HMM get pages wait for CPU fault handle returns
+ * 3. restore work update mappings of GPU, resume all queues.
+ *
+ * Context: Process context
+ *
+ * Return:
+ * 0 - OK, otherwise - error code of migration
+ */
+static int
+svm_range_trigger_migration(struct mm_struct *mm, struct svm_range *prange,
+			    bool *migrated)
+{
+	uint32_t best_loc;
+	int r = 0;
+
+	*migrated = false;
+	best_loc = svm_range_best_prefetch_location(prange);
+
+	if (best_loc == KFD_IOCTL_SVM_LOCATION_UNDEFINED ||
+	    best_loc == prange->actual_loc)
+		return 0;
+
+	/*
+	 * Prefetch to GPU without host access flag, set actual_loc to gpu, then
+	 * validate on gpu and map to gpus will be handled afterwards.
+	 */
+	if (best_loc && !prange->actual_loc &&
+	    !(prange->flags & KFD_IOCTL_SVM_FLAG_HOST_ACCESS)) {
+		prange->actual_loc = best_loc;
+		return 0;
+	}
+
+	if (!best_loc) {
+		r = svm_migrate_vram_to_ram(prange, mm);
+		*migrated = !r;
+		return r;
+	}
+
+	r = svm_migrate_to_vram(prange, best_loc, mm);
+	*migrated = !r;
+
+	return r;
+}
+
+int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence)
+{
+	if (!fence)
+		return -EINVAL;
+
+	if (dma_fence_is_signaled(&fence->base))
+		return 0;
+
+	if (fence->svm_bo) {
+		WRITE_ONCE(fence->svm_bo->evicting, 1);
+		schedule_work(&fence->svm_bo->eviction_work);
+	}
+
+	return 0;
+}
+
+static void svm_range_evict_svm_bo_worker(struct work_struct *work)
+{
+	struct svm_range_bo *svm_bo;
+	struct kfd_process *p;
+	struct mm_struct *mm;
+
+	svm_bo = container_of(work, struct svm_range_bo, eviction_work);
+	if (!svm_bo_ref_unless_zero(svm_bo))
+		return; /* svm_bo was freed while eviction was pending */
+
+	/* svm_range_bo_release destroys this worker thread. So during
+	 * the lifetime of this thread, kfd_process and mm will be valid.
+	 */
+	p = container_of(svm_bo->svms, struct kfd_process, svms);
+	mm = p->mm;
+	if (!mm)
+		return;
+
+	mmap_read_lock(mm);
+	spin_lock(&svm_bo->list_lock);
+	while (!list_empty(&svm_bo->range_list)) {
+		struct svm_range *prange =
+				list_first_entry(&svm_bo->range_list,
+						struct svm_range, svm_bo_list);
+		list_del_init(&prange->svm_bo_list);
+		spin_unlock(&svm_bo->list_lock);
+
+		pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms,
+			 prange->start, prange->last);
+
+		mutex_lock(&prange->migrate_mutex);
+		svm_migrate_vram_to_ram(prange, svm_bo->eviction_fence->mm);
+
+		mutex_lock(&prange->lock);
+		prange->svm_bo = NULL;
+		mutex_unlock(&prange->lock);
+
+		mutex_unlock(&prange->migrate_mutex);
+
+		spin_lock(&svm_bo->list_lock);
+	}
+	spin_unlock(&svm_bo->list_lock);
+	mmap_read_unlock(mm);
+
+	dma_fence_signal(&svm_bo->eviction_fence->base);
+	/* This is the last reference to svm_bo, after svm_range_vram_node_free
+	 * has been called in svm_migrate_vram_to_ram
+	 */
+	WARN_ONCE(kref_read(&svm_bo->kref) != 1, "This was not the last reference\n");
+	svm_range_bo_unref(svm_bo);
+}
+
+static int
+svm_range_set_attr(struct kfd_process *p, uint64_t start, uint64_t size,
+		   uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs)
+{
+	struct amdkfd_process_info *process_info = p->kgd_process_info;
+	struct mm_struct *mm = current->mm;
+	struct list_head update_list;
+	struct list_head insert_list;
+	struct list_head remove_list;
+	struct svm_range_list *svms;
+	struct svm_range *prange;
+	struct svm_range *next;
+	int r = 0;
+
+	pr_debug("pasid 0x%x svms 0x%p [0x%llx 0x%llx] pages 0x%llx\n",
+		 p->pasid, &p->svms, start, start + size - 1, size);
+
+	r = svm_range_check_attr(p, nattr, attrs);
+	if (r)
+		return r;
+
+	svms = &p->svms;
+
+	mutex_lock(&process_info->lock);
+
+	svm_range_list_lock_and_flush_work(svms, mm);
+
+	if (!svm_range_is_valid(mm, start, size)) {
+		pr_debug("invalid range\n");
+		r = -EFAULT;
+		mmap_write_unlock(mm);
+		goto out;
+	}
+
+	mutex_lock(&svms->lock);
+
+	/* Add new range and split existing ranges as needed */
+	r = svm_range_add(p, start, size, nattr, attrs, &update_list,
+			  &insert_list, &remove_list);
+	if (r) {
+		mutex_unlock(&svms->lock);
+		mmap_write_unlock(mm);
+		goto out;
+	}
+	/* Apply changes as a transaction */
+	list_for_each_entry_safe(prange, next, &insert_list, insert_list) {
+		svm_range_add_to_svms(prange);
+		svm_range_add_notifier_locked(mm, prange);
+	}
+	list_for_each_entry(prange, &update_list, update_list) {
+		svm_range_apply_attrs(p, prange, nattr, attrs);
+		/* TODO: unmap ranges from GPU that lost access */
+	}
+	list_for_each_entry_safe(prange, next, &remove_list,
+				remove_list) {
+		pr_debug("unlink old 0x%p prange 0x%p [0x%lx 0x%lx]\n",
+			 prange->svms, prange, prange->start,
+			 prange->last);
+		svm_range_unlink(prange);
+		svm_range_remove_notifier(prange);
+		svm_range_free(prange);
+	}
+
+	mmap_write_downgrade(mm);
+	/* Trigger migrations and revalidate and map to GPUs as needed. If
+	 * this fails we may be left with partially completed actions. There
+	 * is no clean way of rolling back to the previous state in such a
+	 * case because the rollback wouldn't be guaranteed to work either.
+	 */
+	list_for_each_entry(prange, &update_list, update_list) {
+		bool migrated;
+
+		mutex_lock(&prange->migrate_mutex);
+
+		r = svm_range_trigger_migration(mm, prange, &migrated);
+		if (r)
+			goto out_unlock_range;
+
+		if (migrated && !p->xnack_enabled) {
+			pr_debug("restore_work will update mappings of GPUs\n");
+			mutex_unlock(&prange->migrate_mutex);
+			continue;
+		}
+
+		r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,
+					       true, true);
+		if (r)
+			pr_debug("failed %d to map svm range\n", r);
+
+out_unlock_range:
+		mutex_unlock(&prange->migrate_mutex);
+		if (r)
+			break;
+	}
+
+	svm_range_debug_dump(svms);
+
+	mutex_unlock(&svms->lock);
+	mmap_read_unlock(mm);
+out:
+	mutex_unlock(&process_info->lock);
+
+	pr_debug("pasid 0x%x svms 0x%p [0x%llx 0x%llx] done, r=%d\n", p->pasid,
+		 &p->svms, start, start + size - 1, r);
+
+	return r;
+}
+
+static int
+svm_range_get_attr(struct kfd_process *p, uint64_t start, uint64_t size,
+		   uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs)
+{
+	DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE);
+	DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE);
+	bool get_preferred_loc = false;
+	bool get_prefetch_loc = false;
+	bool get_granularity = false;
+	bool get_accessible = false;
+	bool get_flags = false;
+	uint64_t last = start + size - 1UL;
+	struct mm_struct *mm = current->mm;
+	uint8_t granularity = 0xff;
+	struct interval_tree_node *node;
+	struct svm_range_list *svms;
+	struct svm_range *prange;
+	uint32_t prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
+	uint32_t location = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
+	uint32_t flags = 0xffffffff;
+	int gpuidx;
+	uint32_t i;
+
+	pr_debug("svms 0x%p [0x%llx 0x%llx] nattr 0x%x\n", &p->svms, start,
+		 start + size - 1, nattr);
+
+	mmap_read_lock(mm);
+	if (!svm_range_is_valid(mm, start, size)) {
+		pr_debug("invalid range\n");
+		mmap_read_unlock(mm);
+		return -EINVAL;
+	}
+	mmap_read_unlock(mm);
+
+	for (i = 0; i < nattr; i++) {
+		switch (attrs[i].type) {
+		case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
+			get_preferred_loc = true;
+			break;
+		case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC:
+			get_prefetch_loc = true;
+			break;
+		case KFD_IOCTL_SVM_ATTR_ACCESS:
+			get_accessible = true;
+			break;
+		case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
+			get_flags = true;
+			break;
+		case KFD_IOCTL_SVM_ATTR_GRANULARITY:
+			get_granularity = true;
+			break;
+		case KFD_IOCTL_SVM_ATTR_CLR_FLAGS:
+		case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE:
+		case KFD_IOCTL_SVM_ATTR_NO_ACCESS:
+			fallthrough;
+		default:
+			pr_debug("get invalid attr type 0x%x\n", attrs[i].type);
+			return -EINVAL;
+		}
+	}
+
+	svms = &p->svms;
+
+	mutex_lock(&svms->lock);
+
+	node = interval_tree_iter_first(&svms->objects, start, last);
+	if (!node) {
+		pr_debug("range attrs not found return default values\n");
+		svm_range_set_default_attributes(&location, &prefetch_loc,
+						 &granularity, &flags);
+		if (p->xnack_enabled)
+			bitmap_copy(bitmap_access, svms->bitmap_supported,
+				    MAX_GPU_INSTANCE);
+		else
+			bitmap_zero(bitmap_access, MAX_GPU_INSTANCE);
+		bitmap_zero(bitmap_aip, MAX_GPU_INSTANCE);
+		goto fill_values;
+	}
+	bitmap_copy(bitmap_access, svms->bitmap_supported, MAX_GPU_INSTANCE);
+	bitmap_copy(bitmap_aip, svms->bitmap_supported, MAX_GPU_INSTANCE);
+
+	while (node) {
+		struct interval_tree_node *next;
+
+		prange = container_of(node, struct svm_range, it_node);
+		next = interval_tree_iter_next(node, start, last);
+
+		if (get_preferred_loc) {
+			if (prange->preferred_loc ==
+					KFD_IOCTL_SVM_LOCATION_UNDEFINED ||
+			    (location != KFD_IOCTL_SVM_LOCATION_UNDEFINED &&
+			     location != prange->preferred_loc)) {
+				location = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
+				get_preferred_loc = false;
+			} else {
+				location = prange->preferred_loc;
+			}
+		}
+		if (get_prefetch_loc) {
+			if (prange->prefetch_loc ==
+					KFD_IOCTL_SVM_LOCATION_UNDEFINED ||
+			    (prefetch_loc != KFD_IOCTL_SVM_LOCATION_UNDEFINED &&
+			     prefetch_loc != prange->prefetch_loc)) {
+				prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
+				get_prefetch_loc = false;
+			} else {
+				prefetch_loc = prange->prefetch_loc;
+			}
+		}
+		if (get_accessible) {
+			bitmap_and(bitmap_access, bitmap_access,
+				   prange->bitmap_access, MAX_GPU_INSTANCE);
+			bitmap_and(bitmap_aip, bitmap_aip,
+				   prange->bitmap_aip, MAX_GPU_INSTANCE);
+		}
+		if (get_flags)
+			flags &= prange->flags;
+
+		if (get_granularity && prange->granularity < granularity)
+			granularity = prange->granularity;
+
+		node = next;
+	}
+fill_values:
+	mutex_unlock(&svms->lock);
+
+	for (i = 0; i < nattr; i++) {
+		switch (attrs[i].type) {
+		case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
+			attrs[i].value = location;
+			break;
+		case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC:
+			attrs[i].value = prefetch_loc;
+			break;
+		case KFD_IOCTL_SVM_ATTR_ACCESS:
+			gpuidx = kfd_process_gpuidx_from_gpuid(p,
+							       attrs[i].value);
+			if (gpuidx < 0) {
+				pr_debug("invalid gpuid %x\n", attrs[i].value);
+				return -EINVAL;
+			}
+			if (test_bit(gpuidx, bitmap_access))
+				attrs[i].type = KFD_IOCTL_SVM_ATTR_ACCESS;
+			else if (test_bit(gpuidx, bitmap_aip))
+				attrs[i].type =
+					KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE;
+			else
+				attrs[i].type = KFD_IOCTL_SVM_ATTR_NO_ACCESS;
+			break;
+		case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
+			attrs[i].value = flags;
+			break;
+		case KFD_IOCTL_SVM_ATTR_GRANULARITY:
+			attrs[i].value = (uint32_t)granularity;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+int
+svm_ioctl(struct kfd_process *p, enum kfd_ioctl_svm_op op, uint64_t start,
+	  uint64_t size, uint32_t nattrs, struct kfd_ioctl_svm_attribute *attrs)
+{
+	int r;
+
+	start >>= PAGE_SHIFT;
+	size >>= PAGE_SHIFT;
+
+	switch (op) {
+	case KFD_IOCTL_SVM_OP_SET_ATTR:
+		r = svm_range_set_attr(p, start, size, nattrs, attrs);
+		break;
+	case KFD_IOCTL_SVM_OP_GET_ATTR:
+		r = svm_range_get_attr(p, start, size, nattrs, attrs);
+		break;
+	default:
+		r = EINVAL;
+		break;
+	}
+
+	return r;
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
new file mode 100644
index 000000000000..0c0fc399395e
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2020-2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef KFD_SVM_H_
+#define KFD_SVM_H_
+
+#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
+
+#include <linux/rwsem.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/sched/mm.h>
+#include <linux/hmm.h>
+#include "amdgpu.h"
+#include "kfd_priv.h"
+
+struct svm_range_bo {
+	struct amdgpu_bo		*bo;
+	struct kref			kref;
+	struct list_head		range_list; /* all svm ranges shared this bo */
+	spinlock_t			list_lock;
+	struct amdgpu_amdkfd_fence	*eviction_fence;
+	struct work_struct		eviction_work;
+	struct svm_range_list		*svms;
+	uint32_t			evicting;
+};
+
+enum svm_work_list_ops {
+	SVM_OP_NULL,
+	SVM_OP_UNMAP_RANGE,
+	SVM_OP_UPDATE_RANGE_NOTIFIER,
+	SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP,
+	SVM_OP_ADD_RANGE,
+	SVM_OP_ADD_RANGE_AND_MAP
+};
+
+struct svm_work_list_item {
+	enum svm_work_list_ops op;
+	struct mm_struct *mm;
+};
+
+/**
+ * struct svm_range - shared virtual memory range
+ *
+ * @svms:       list of svm ranges, structure defined in kfd_process
+ * @migrate_mutex: to serialize range migration, validation and mapping update
+ * @start:      range start address in pages
+ * @last:       range last address in pages
+ * @it_node:    node [start, last] stored in interval tree, start, last are page
+ *              aligned, page size is (last - start + 1)
+ * @list:       link list node, used to scan all ranges of svms
+ * @update_list:link list node used to add to update_list
+ * @remove_list:link list node used to add to remove list
+ * @insert_list:link list node used to add to insert list
+ * @mapping:    bo_va mapping structure to create and update GPU page table
+ * @npages:     number of pages
+ * @dma_addr:   dma mapping address on each GPU for system memory physical page
+ * @ttm_res:    vram ttm resource map
+ * @offset:     range start offset within mm_nodes
+ * @svm_bo:     struct to manage splited amdgpu_bo
+ * @svm_bo_list:link list node, to scan all ranges which share same svm_bo
+ * @lock:       protect prange start, last, child_list, svm_bo_list
+ * @saved_flags:save/restore current PF_MEMALLOC flags
+ * @flags:      flags defined as KFD_IOCTL_SVM_FLAG_*
+ * @perferred_loc: perferred location, 0 for CPU, or GPU id
+ * @perfetch_loc: last prefetch location, 0 for CPU, or GPU id
+ * @actual_loc: the actual location, 0 for CPU, or GPU id
+ * @granularity:migration granularity, log2 num pages
+ * @invalid:    not 0 means cpu page table is invalidated
+ * @validate_timestamp: system timestamp when range is validated
+ * @notifier:   register mmu interval notifier
+ * @work_item:  deferred work item information
+ * @deferred_list: list header used to add range to deferred list
+ * @child_list: list header for split ranges which are not added to svms yet
+ * @bitmap_access: index bitmap of GPUs which can access the range
+ * @bitmap_aip: index bitmap of GPUs which can access the range in place
+ *
+ * Data structure for virtual memory range shared by CPU and GPUs, it can be
+ * allocated from system memory ram or device vram, and migrate from ram to vram
+ * or from vram to ram.
+ */
+struct svm_range {
+	struct svm_range_list		*svms;
+	struct mutex			migrate_mutex;
+	unsigned long			start;
+	unsigned long			last;
+	struct interval_tree_node	it_node;
+	struct list_head		list;
+	struct list_head		update_list;
+	struct list_head		remove_list;
+	struct list_head		insert_list;
+	struct amdgpu_bo_va_mapping	mapping;
+	uint64_t			npages;
+	dma_addr_t			*dma_addr[MAX_GPU_INSTANCE];
+	struct ttm_resource		*ttm_res;
+	uint64_t			offset;
+	struct svm_range_bo		*svm_bo;
+	struct list_head		svm_bo_list;
+	struct mutex                    lock;
+	unsigned int                    saved_flags;
+	uint32_t			flags;
+	uint32_t			preferred_loc;
+	uint32_t			prefetch_loc;
+	uint32_t			actual_loc;
+	uint8_t				granularity;
+	atomic_t			invalid;
+	uint64_t			validate_timestamp;
+	struct mmu_interval_notifier	notifier;
+	struct svm_work_list_item	work_item;
+	struct list_head		deferred_list;
+	struct list_head		child_list;
+	DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE);
+	DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE);
+	bool				validated_once;
+};
+
+static inline void svm_range_lock(struct svm_range *prange)
+{
+	mutex_lock(&prange->lock);
+	prange->saved_flags = memalloc_noreclaim_save();
+
+}
+static inline void svm_range_unlock(struct svm_range *prange)
+{
+	memalloc_noreclaim_restore(prange->saved_flags);
+	mutex_unlock(&prange->lock);
+}
+
+int svm_range_list_init(struct kfd_process *p);
+void svm_range_list_fini(struct kfd_process *p);
+int svm_ioctl(struct kfd_process *p, enum kfd_ioctl_svm_op op, uint64_t start,
+	      uint64_t size, uint32_t nattrs,
+	      struct kfd_ioctl_svm_attribute *attrs);
+struct svm_range *svm_range_from_addr(struct svm_range_list *svms,
+				      unsigned long addr,
+				      struct svm_range **parent);
+struct amdgpu_device *svm_range_get_adev_by_id(struct svm_range *prange,
+					       uint32_t id);
+int svm_range_vram_node_new(struct amdgpu_device *adev,
+			    struct svm_range *prange, bool clear);
+void svm_range_vram_node_free(struct svm_range *prange);
+int svm_range_split_by_granularity(struct kfd_process *p, struct mm_struct *mm,
+			       unsigned long addr, struct svm_range *parent,
+			       struct svm_range *prange);
+int svm_range_restore_pages(struct amdgpu_device *adev,
+			    unsigned int pasid, uint64_t addr);
+int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence);
+void svm_range_add_list_work(struct svm_range_list *svms,
+			     struct svm_range *prange, struct mm_struct *mm,
+			     enum svm_work_list_ops op);
+void schedule_deferred_list_work(struct svm_range_list *svms);
+void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr,
+			 unsigned long offset, unsigned long npages);
+void svm_range_free_dma_mappings(struct svm_range *prange);
+void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm);
+
+/* SVM API and HMM page migration work together, device memory type
+ * is initialized to not 0 when page migration register device memory.
+ */
+#define KFD_IS_SVM_API_SUPPORTED(dev) ((dev)->pgmap.type != 0)
+
+#else
+
+struct kfd_process;
+
+static inline int svm_range_list_init(struct kfd_process *p)
+{
+	return 0;
+}
+static inline void svm_range_list_fini(struct kfd_process *p)
+{
+	/* empty */
+}
+
+static inline int svm_range_restore_pages(struct amdgpu_device *adev,
+					  unsigned int pasid, uint64_t addr)
+{
+	return -EFAULT;
+}
+
+static inline int svm_range_schedule_evict_svm_bo(
+		struct amdgpu_amdkfd_fence *fence)
+{
+	WARN_ONCE(1, "SVM eviction fence triggered, but SVM is disabled");
+	return -EINVAL;
+}
+
+#define KFD_IS_SVM_API_SUPPORTED(dev) false
+
+#endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */
+
+#endif /* KFD_SVM_H_ */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index cdef608db4f4..b1ce072aa20b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -36,6 +36,7 @@
 #include "kfd_topology.h"
 #include "kfd_device_queue_manager.h"
 #include "kfd_iommu.h"
+#include "kfd_svm.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_ras.h"
 
@@ -1192,40 +1193,83 @@ static void kfd_fill_mem_clk_max_info(struct kfd_topology_device *dev)
 		mem->mem_clk_max = local_mem_info.mem_clk_max;
 }
 
-static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
+static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev,
+					struct kfd_topology_device *target_gpu_dev,
+					struct kfd_iolink_properties *link)
 {
-	struct kfd_iolink_properties *link, *cpu_link;
-	struct kfd_topology_device *cpu_dev;
-	uint32_t cap;
-	uint32_t cpu_flag = CRAT_IOLINK_FLAGS_ENABLED;
-	uint32_t flag = CRAT_IOLINK_FLAGS_ENABLED;
-
-	if (!dev || !dev->gpu)
+	/* xgmi always supports atomics between links. */
+	if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI)
 		return;
 
-	pcie_capability_read_dword(dev->gpu->pdev,
-			PCI_EXP_DEVCAP2, &cap);
+	/* check pcie support to set cpu(dev) flags for target_gpu_dev link. */
+	if (target_gpu_dev) {
+		uint32_t cap;
 
-	if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
-		     PCI_EXP_DEVCAP2_ATOMIC_COMP64)))
-		cpu_flag |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
-			CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+		pcie_capability_read_dword(target_gpu_dev->gpu->pdev,
+				PCI_EXP_DEVCAP2, &cap);
+
+		if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
+			     PCI_EXP_DEVCAP2_ATOMIC_COMP64)))
+			link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
+				CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+	/* set gpu (dev) flags. */
+	} else {
+		if (!dev->gpu->pci_atomic_requested ||
+				dev->gpu->device_info->asic_family ==
+							CHIP_HAWAII)
+			link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
+				CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+	}
+}
 
-	if (!dev->gpu->pci_atomic_requested ||
-	    dev->gpu->device_info->asic_family == CHIP_HAWAII)
-		flag |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
-			CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,
+		struct kfd_iolink_properties *outbound_link,
+		struct kfd_iolink_properties *inbound_link)
+{
+	/* CPU -> GPU with PCIe */
+	if (!to_dev->gpu &&
+	    inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
+		inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
+
+	if (to_dev->gpu) {
+		/* GPU <-> GPU with PCIe and
+		 * Vega20 with XGMI
+		 */
+		if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS ||
+		    (inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
+		    to_dev->gpu->device_info->asic_family == CHIP_VEGA20)) {
+			outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
+			inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
+		}
+	}
+}
+
+static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
+{
+	struct kfd_iolink_properties *link, *inbound_link;
+	struct kfd_topology_device *peer_dev;
+
+	if (!dev || !dev->gpu)
+		return;
 
 	/* GPU only creates direct links so apply flags setting to all */
 	list_for_each_entry(link, &dev->io_link_props, list) {
-		link->flags = flag;
-		cpu_dev = kfd_topology_device_by_proximity_domain(
+		link->flags = CRAT_IOLINK_FLAGS_ENABLED;
+		kfd_set_iolink_no_atomics(dev, NULL, link);
+		peer_dev = kfd_topology_device_by_proximity_domain(
 				link->node_to);
-		if (cpu_dev) {
-			list_for_each_entry(cpu_link,
-					    &cpu_dev->io_link_props, list)
-				if (cpu_link->node_to == link->node_from)
-					cpu_link->flags = cpu_flag;
+
+		if (!peer_dev)
+			continue;
+
+		list_for_each_entry(inbound_link, &peer_dev->io_link_props,
+									list) {
+			if (inbound_link->node_to != link->node_from)
+				continue;
+
+			inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
+			kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
+			kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
 		}
 	}
 }
@@ -1378,6 +1422,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
@@ -1410,15 +1456,18 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	adev = (struct amdgpu_device *)(dev->gpu->kgd);
 	/* kfd only concerns sram ecc on GFX and HBM ecc on UMC */
 	dev->node_props.capability |=
-		((adev->ras_features & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
+		((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
 		HSA_CAP_SRAM_EDCSUPPORTED : 0;
-	dev->node_props.capability |= ((adev->ras_features & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
+	dev->node_props.capability |= ((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
 		HSA_CAP_MEM_EDCSUPPORTED : 0;
 
 	if (adev->asic_type != CHIP_VEGA10)
-		dev->node_props.capability |= (adev->ras_features != 0) ?
+		dev->node_props.capability |= (adev->ras_enabled != 0) ?
 			HSA_CAP_RASEVENTNOTIFY : 0;
 
+	if (KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev))
+		dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED;
+
 	kfd_debug_print_topology();
 
 	if (!res)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
index b8b68087bd7a..8b48c6692007 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
@@ -53,8 +53,9 @@
 #define HSA_CAP_ASIC_REVISION_MASK		0x03c00000
 #define HSA_CAP_ASIC_REVISION_SHIFT		22
 #define HSA_CAP_SRAM_EDCSUPPORTED		0x04000000
-
-#define HSA_CAP_RESERVED			0xf80f8000
+#define HSA_CAP_SVMAPI_SUPPORTED		0x08000000
+#define HSA_CAP_FLAGS_COHERENTHOSTACCESS	0x10000000
+#define HSA_CAP_RESERVED			0xe00f8000
 
 struct kfd_node_properties {
 	uint64_t hive_id;
@@ -98,9 +99,9 @@ struct kfd_node_properties {
 #define HSA_MEM_HEAP_TYPE_GPU_LDS	4
 #define HSA_MEM_HEAP_TYPE_GPU_SCRATCH	5
 
-#define HSA_MEM_FLAGS_HOT_PLUGGABLE	0x00000001
-#define HSA_MEM_FLAGS_NON_VOLATILE	0x00000002
-#define HSA_MEM_FLAGS_RESERVED		0xfffffffc
+#define HSA_MEM_FLAGS_HOT_PLUGGABLE		0x00000001
+#define HSA_MEM_FLAGS_NON_VOLATILE		0x00000002
+#define HSA_MEM_FLAGS_RESERVED			0xfffffffc
 
 struct kfd_mem_properties {
 	struct list_head	list;
diff --git a/drivers/gpu/drm/amd/amdkfd/soc15_int.h b/drivers/gpu/drm/amd/amdkfd/soc15_int.h
index 0bc0b25cb410..daf3c44547d3 100644
--- a/drivers/gpu/drm/amd/amdkfd/soc15_int.h
+++ b/drivers/gpu/drm/amd/amdkfd/soc15_int.h
@@ -30,6 +30,7 @@
 #define SOC15_INTSRC_SQ_INTERRUPT_MSG	239
 #define SOC15_INTSRC_VMC_FAULT		0
 #define SOC15_INTSRC_SDMA_TRAP		224
+#define SOC15_INTSRC_SDMA_ECC		220
 
 
 #define SOC15_CLIENT_ID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) & 0xff)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
index 9a3b7bf8ab0b..91fb72c96545 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
@@ -28,7 +28,7 @@
 AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o amdgpu_dm_color.o
 
 ifneq ($(CONFIG_DRM_AMD_DC),)
-AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o
+AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o amdgpu_dm_psr.o
 endif
 
 ifdef CONFIG_DRM_AMD_DC_HDCP
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 652cc1a0e450..b5b5ccf0ed71 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -28,6 +28,7 @@
 
 #include "dm_services_types.h"
 #include "dc.h"
+#include "dc_link_dp.h"
 #include "dc/inc/core_types.h"
 #include "dal_asic_id.h"
 #include "dmub/dmub_srv.h"
@@ -35,6 +36,7 @@
 #include "dc/inc/hw/abm.h"
 #include "dc/dc_dmub_srv.h"
 #include "dc/dc_edid_parser.h"
+#include "dc/dc_stat.h"
 #include "amdgpu_dm_trace.h"
 
 #include "vid.h"
@@ -56,9 +58,11 @@
 #if defined(CONFIG_DEBUG_FS)
 #include "amdgpu_dm_debugfs.h"
 #endif
+#include "amdgpu_dm_psr.h"
 
 #include "ivsrcid/ivsrcid_vislands30.h"
 
+#include "i2caux_interface.h"
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/types.h>
@@ -104,6 +108,10 @@ MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
+#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
+#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 
 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -204,12 +212,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 static void handle_cursor_update(struct drm_plane *plane,
 				 struct drm_plane_state *old_plane_state);
 
-static void amdgpu_dm_set_psr_caps(struct dc_link *link);
-static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
-static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
-static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
-static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
-
 static const struct drm_format_info *
 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
 
@@ -310,10 +312,8 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev,
 	struct drm_crtc *crtc;
 	struct amdgpu_crtc *amdgpu_crtc;
 
-	if (otg_inst == -1) {
-		WARN_ON(1);
+	if (WARN_ON(otg_inst == -1))
 		return adev->mode_info.crtcs[0];
-	}
 
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		amdgpu_crtc = to_amdgpu_crtc(crtc);
@@ -392,8 +392,7 @@ static void dm_pflip_high_irq(void *interrupt_params)
 	e = amdgpu_crtc->event;
 	amdgpu_crtc->event = NULL;
 
-	if (!e)
-		WARN_ON(1);
+	WARN_ON(!e);
 
 	vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
 
@@ -596,14 +595,14 @@ static void dm_crtc_high_irq(void *interrupt_params)
 }
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 /**
  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
  * DCN generation ASICs
- * @interrupt params - interrupt parameters
+ * @interrupt_params: interrupt parameters
  *
  * Used to set crc window/read out crc value at vertical line 0 position
  */
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 {
 	struct common_irq_params *irq_params = interrupt_params;
@@ -618,6 +617,58 @@ static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 	amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 }
 #endif
+
+/**
+ * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
+ * @interrupt_params: used for determining the Outbox instance
+ *
+ * Handles the Outbox Interrupt
+ * event handler.
+ */
+#define DMUB_TRACE_MAX_READ 64
+static void dm_dmub_outbox1_low_irq(void *interrupt_params)
+{
+	struct dmub_notification notify;
+	struct common_irq_params *irq_params = interrupt_params;
+	struct amdgpu_device *adev = irq_params->adev;
+	struct amdgpu_display_manager *dm = &adev->dm;
+	struct dmcub_trace_buf_entry entry = { 0 };
+	uint32_t count = 0;
+
+	if (dc_enable_dmub_notifications(adev->dm.dc)) {
+		if (irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
+			do {
+				dc_stat_get_dmub_notification(adev->dm.dc, &notify);
+			} while (notify.pending_notification);
+
+			if (adev->dm.dmub_notify)
+				memcpy(adev->dm.dmub_notify, &notify, sizeof(struct dmub_notification));
+			if (notify.type == DMUB_NOTIFICATION_AUX_REPLY)
+				complete(&adev->dm.dmub_aux_transfer_done);
+			// TODO : HPD Implementation
+
+		} else {
+			DRM_ERROR("DM: Failed to receive correct outbox IRQ !");
+		}
+	}
+
+
+	do {
+		if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
+			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
+							entry.param0, entry.param1);
+
+			DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
+				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
+		} else
+			break;
+
+		count++;
+
+	} while (count <= DMUB_TRACE_MAX_READ);
+
+	ASSERT(count <= DMUB_TRACE_MAX_READ);
+}
 #endif
 
 static int dm_set_clockgating_state(void *handle,
@@ -939,32 +990,6 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
 }
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-#define DMUB_TRACE_MAX_READ 64
-static void dm_dmub_trace_high_irq(void *interrupt_params)
-{
-	struct common_irq_params *irq_params = interrupt_params;
-	struct amdgpu_device *adev = irq_params->adev;
-	struct amdgpu_display_manager *dm = &adev->dm;
-	struct dmcub_trace_buf_entry entry = { 0 };
-	uint32_t count = 0;
-
-	do {
-		if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
-			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
-							entry.param0, entry.param1);
-
-			DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
-				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
-		} else
-			break;
-
-		count++;
-
-	} while (count <= DMUB_TRACE_MAX_READ);
-
-	ASSERT(count <= DMUB_TRACE_MAX_READ);
-}
-
 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
 {
 	uint64_t pt_base;
@@ -1118,11 +1143,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 		if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
 			init_data.flags.disable_dmcu = true;
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		init_data.flags.gpu_vm_support = true;
 		break;
-#endif
 	default:
 		break;
 	}
@@ -1221,6 +1245,16 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 	adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
 #endif
+	if (dc_enable_dmub_notifications(adev->dm.dc)) {
+		init_completion(&adev->dm.dmub_aux_transfer_done);
+		adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
+		if (!adev->dm.dmub_notify) {
+			DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
+			goto error;
+		}
+		amdgpu_dm_outbox_init(adev);
+	}
+
 	if (amdgpu_dm_initialize_drm_device(adev)) {
 		DRM_ERROR(
 		"amdgpu: failed to initialize sw for display support.\n");
@@ -1252,6 +1286,15 @@ error:
 	return -EINVAL;
 }
 
+static int amdgpu_dm_early_fini(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	amdgpu_dm_audio_fini(adev);
+
+	return 0;
+}
+
 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 {
 	int i;
@@ -1260,8 +1303,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
 		drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
 	}
 
-	amdgpu_dm_audio_fini(adev);
-
 	amdgpu_dm_destroy_drm_device(&adev->dm);
 
 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
@@ -1289,9 +1330,11 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
 	}
 #endif
 
-	if (adev->dm.dc->ctx->dmub_srv) {
-		dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
-		adev->dm.dc->ctx->dmub_srv = NULL;
+	dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
+
+	if (dc_enable_dmub_notifications(adev->dm.dc)) {
+		kfree(adev->dm.dmub_notify);
+		adev->dm.dmub_notify = NULL;
 	}
 
 	if (adev->dm.dmub_bo)
@@ -1358,7 +1401,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		return 0;
 	case CHIP_NAVI12:
 		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1473,6 +1518,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
 		dmub_asic = DMUB_ASIC_DCN302;
 		fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
 		break;
+	case CHIP_BEIGE_GOBY:
+		dmub_asic = DMUB_ASIC_DCN303;
+		fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
+		break;
+	case CHIP_YELLOW_CARP:
+		dmub_asic = DMUB_ASIC_DCN31;
+		fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
+		break;
 
 	default:
 		/* ASIC doesn't support DMUB. */
@@ -1659,7 +1712,6 @@ static int dm_late_init(void *handle)
 	unsigned int linear_lut[16];
 	int i;
 	struct dmcu *dmcu = NULL;
-	bool ret = true;
 
 	dmcu = adev->dm.dc->res_pool->dmcu;
 
@@ -1676,18 +1728,23 @@ static int dm_late_init(void *handle)
 	 * 0xFFFF x 0.01 = 0x28F
 	 */
 	params.min_abm_backlight = 0x28F;
-
 	/* In the case where abm is implemented on dmcub,
-	 * dmcu object will be null.
-	 * ABM 2.4 and up are implemented on dmcub.
-	 */
-	if (dmcu)
-		ret = dmcu_load_iram(dmcu, params);
-	else if (adev->dm.dc->ctx->dmub_srv)
-		ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);
+	* dmcu object will be null.
+	* ABM 2.4 and up are implemented on dmcub.
+	*/
+	if (dmcu) {
+		if (!dmcu_load_iram(dmcu, params))
+			return -EINVAL;
+	} else if (adev->dm.dc->ctx->dmub_srv) {
+		struct dc_link *edp_links[MAX_NUM_EDP];
+		int edp_num;
 
-	if (!ret)
-		return -EINVAL;
+		get_edp_links(adev->dm.dc, edp_links, &edp_num);
+		for (i = 0; i < edp_num; i++) {
+			if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
+				return -EINVAL;
+		}
+	}
 
 	return detect_mst_link_for_all_connectors(adev_to_drm(adev));
 }
@@ -1945,9 +2002,6 @@ static int dm_suspend(void *handle)
 		return ret;
 	}
 
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-	amdgpu_dm_crtc_secure_display_suspend(adev);
-#endif
 	WARN_ON(adev->dm.cached_state);
 	adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
 
@@ -2166,6 +2220,15 @@ static int dm_resume(void *handle)
 					= 0xffffffff;
 			}
 		}
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		/*
+		 * Resource allocation happens for link encoders for newer ASIC in
+		 * dc_validate_global_state, so we need to revalidate it.
+		 *
+		 * This shouldn't fail (it passed once before), so warn if it does.
+		 */
+		WARN_ON(dc_validate_global_state(dm->dc, dc_state, false) != DC_OK);
+#endif
 
 		WARN_ON(!dc_commit_state(dm->dc, dc_state));
 
@@ -2271,10 +2334,6 @@ static int dm_resume(void *handle)
 
 	dm->cached_state = NULL;
 
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-	amdgpu_dm_crtc_secure_display_resume(adev);
-#endif
-
 	amdgpu_dm_irq_resume_late(adev);
 
 	amdgpu_dm_smu_write_watermarks_table(adev);
@@ -2298,6 +2357,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
 	.late_init = dm_late_init,
 	.sw_init = dm_sw_init,
 	.sw_fini = dm_sw_fini,
+	.early_fini = amdgpu_dm_early_fini,
 	.hw_init = dm_hw_init,
 	.hw_fini = dm_hw_fini,
 	.suspend = dm_suspend,
@@ -2696,6 +2756,7 @@ static void handle_hpd_rx_irq(void *param)
 	enum dc_connection_type new_connection_type = dc_connection_none;
 	struct amdgpu_device *adev = drm_to_adev(dev);
 	union hpd_irq_data hpd_irq_data;
+	bool lock_flag = 0;
 
 	memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
 
@@ -2708,8 +2769,7 @@ static void handle_hpd_rx_irq(void *param)
 	 * conflict, after implement i2c helper, this mutex should be
 	 * retired.
 	 */
-	if (dc_link->type != dc_connection_mst_branch)
-		mutex_lock(&aconnector->hpd_lock);
+	mutex_lock(&aconnector->hpd_lock);
 
 	read_hpd_rx_irq_data(dc_link, &hpd_irq_data);
 
@@ -2726,13 +2786,28 @@ static void handle_hpd_rx_irq(void *param)
 		}
 	}
 
-	mutex_lock(&adev->dm.dc_lock);
+	/*
+	 * TODO: We need the lock to avoid touching DC state while it's being
+	 * modified during automated compliance testing, or when link loss
+	 * happens. While this should be split into subhandlers and proper
+	 * interfaces to avoid having to conditionally lock like this in the
+	 * outer layer, we need this workaround temporarily to allow MST
+	 * lightup in some scenarios to avoid timeout.
+	 */
+	if (!amdgpu_in_reset(adev) &&
+	    (hpd_rx_irq_check_link_loss_status(dc_link, &hpd_irq_data) ||
+	     hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST)) {
+		mutex_lock(&adev->dm.dc_lock);
+		lock_flag = 1;
+	}
+
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 	result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL);
 #else
 	result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL);
 #endif
-	mutex_unlock(&adev->dm.dc_lock);
+	if (!amdgpu_in_reset(adev) && lock_flag)
+		mutex_unlock(&adev->dm.dc_lock);
 
 out:
 	if (result && !is_mst_root_connector) {
@@ -2776,10 +2851,10 @@ out:
 	}
 #endif
 
-	if (dc_link->type != dc_connection_mst_branch) {
+	if (dc_link->type != dc_connection_mst_branch)
 		drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
-		mutex_unlock(&aconnector->hpd_lock);
-	}
+
+	mutex_unlock(&aconnector->hpd_lock);
 }
 
 static void register_hpd_handlers(struct amdgpu_device *adev)
@@ -3151,38 +3226,51 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
 
 	}
 
-	if (dc->ctx->dmub_srv) {
-		i = DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT;
-		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->dmub_trace_irq);
+	/* HPD */
+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
+			&adev->hpd_irq);
+	if (r) {
+		DRM_ERROR("Failed to add hpd irq id!\n");
+		return r;
+	}
 
-		if (r) {
-			DRM_ERROR("Failed to add dmub trace irq id!\n");
-			return r;
-		}
+	register_hpd_handlers(adev);
 
-		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+	return 0;
+}
+/* Register Outbox IRQ sources and initialize IRQ callbacks */
+static int register_outbox_irq_handlers(struct amdgpu_device *adev)
+{
+	struct dc *dc = adev->dm.dc;
+	struct common_irq_params *c_irq_params;
+	struct dc_interrupt_params int_params = {0};
+	int r, i;
+
+	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
+	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
+
+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
+			&adev->dmub_outbox_irq);
+	if (r) {
+		DRM_ERROR("Failed to add outbox irq id!\n");
+		return r;
+	}
+
+	if (dc->ctx->dmub_srv) {
+		i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
+		int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
 		int_params.irq_source =
-			dc_interrupt_to_irq_source(dc, i, 0);
+		dc_interrupt_to_irq_source(dc, i, 0);
 
-		c_irq_params = &adev->dm.dmub_trace_params[0];
+		c_irq_params = &adev->dm.dmub_outbox_params[0];
 
 		c_irq_params->adev = adev;
 		c_irq_params->irq_src = int_params.irq_source;
 
 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-				dm_dmub_trace_high_irq, c_irq_params);
-	}
-
-	/* HPD */
-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
-			&adev->hpd_irq);
-	if (r) {
-		DRM_ERROR("Failed to add hpd irq id!\n");
-		return r;
+				dm_dmub_outbox1_low_irq, c_irq_params);
 	}
 
-	register_hpd_handlers(adev);
-
 	return 0;
 }
 #endif
@@ -3342,7 +3430,7 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
 	if (dm->backlight_caps.caps_valid)
 		return;
 
-	amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
+	amdgpu_acpi_get_backlight_caps(&caps);
 	if (caps.caps_valid) {
 		dm->backlight_caps.caps_valid = true;
 		if (caps.aux_support)
@@ -3410,56 +3498,88 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap
 				 max - min);
 }
 
-static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
+static int amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
+					 u32 user_brightness)
 {
-	struct amdgpu_display_manager *dm = bl_get_data(bd);
 	struct amdgpu_dm_backlight_caps caps;
-	struct dc_link *link = NULL;
-	u32 brightness;
+	struct dc_link *link[AMDGPU_DM_MAX_NUM_EDP];
+	u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
 	bool rc;
+	int i;
 
 	amdgpu_dm_update_backlight_caps(dm);
 	caps = dm->backlight_caps;
 
-	link = (struct dc_link *)dm->backlight_link;
+	for (i = 0; i < dm->num_of_edps; i++) {
+		dm->brightness[i] = user_brightness;
+		brightness[i] = convert_brightness_from_user(&caps, dm->brightness[i]);
+		link[i] = (struct dc_link *)dm->backlight_link[i];
+	}
 
-	brightness = convert_brightness_from_user(&caps, bd->props.brightness);
-	// Change brightness based on AUX property
-	if (caps.aux_support)
-		rc = dc_link_set_backlight_level_nits(link, true, brightness,
-						      AUX_BL_DEFAULT_TRANSITION_TIME_MS);
-	else
-		rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0);
+	/* Change brightness based on AUX property */
+	if (caps.aux_support) {
+		for (i = 0; i < dm->num_of_edps; i++) {
+			rc = dc_link_set_backlight_level_nits(link[i], true, brightness[i],
+				AUX_BL_DEFAULT_TRANSITION_TIME_MS);
+			if (!rc) {
+				DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", i);
+				break;
+			}
+		}
+	} else {
+		for (i = 0; i < dm->num_of_edps; i++) {
+			rc = dc_link_set_backlight_level(dm->backlight_link[i], brightness[i], 0);
+			if (!rc) {
+				DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", i);
+				break;
+			}
+		}
+	}
 
 	return rc ? 0 : 1;
 }
 
-static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
+static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
 {
 	struct amdgpu_display_manager *dm = bl_get_data(bd);
+
+	amdgpu_dm_backlight_set_level(dm, bd->props.brightness);
+
+	return 0;
+}
+
+static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm)
+{
 	struct amdgpu_dm_backlight_caps caps;
 
 	amdgpu_dm_update_backlight_caps(dm);
 	caps = dm->backlight_caps;
 
 	if (caps.aux_support) {
-		struct dc_link *link = (struct dc_link *)dm->backlight_link;
+		struct dc_link *link = (struct dc_link *)dm->backlight_link[0];
 		u32 avg, peak;
 		bool rc;
 
 		rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
 		if (!rc)
-			return bd->props.brightness;
+			return dm->brightness[0];
 		return convert_brightness_to_user(&caps, avg);
 	} else {
-		int ret = dc_link_get_backlight_level(dm->backlight_link);
+		int ret = dc_link_get_backlight_level(dm->backlight_link[0]);
 
 		if (ret == DC_ERROR_UNEXPECTED)
-			return bd->props.brightness;
+			return dm->brightness[0];
 		return convert_brightness_to_user(&caps, ret);
 	}
 }
 
+static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
+{
+	struct amdgpu_display_manager *dm = bl_get_data(bd);
+
+	return amdgpu_dm_backlight_get_level(dm);
+}
+
 static const struct backlight_ops amdgpu_dm_backlight_ops = {
 	.options = BL_CORE_SUSPENDRESUME,
 	.get_brightness = amdgpu_dm_backlight_get_brightness,
@@ -3471,8 +3591,11 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
 {
 	char bl_name[16];
 	struct backlight_properties props = { 0 };
+	int i;
 
 	amdgpu_dm_update_backlight_caps(dm);
+	for (i = 0; i < dm->num_of_edps; i++)
+		dm->brightness[i] = AMDGPU_MAX_BL_LEVEL;
 
 	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
 	props.brightness = AMDGPU_MAX_BL_LEVEL;
@@ -3549,10 +3672,13 @@ static void register_backlight_device(struct amdgpu_display_manager *dm,
 		 * DM initialization because not having a backlight control
 		 * is better then a black screen.
 		 */
-		amdgpu_dm_register_backlight_device(dm);
+		if (!dm->backlight_dev)
+			amdgpu_dm_register_backlight_device(dm);
 
-		if (dm->backlight_dev)
-			dm->backlight_link = link;
+		if (dm->backlight_dev) {
+			dm->backlight_link[dm->num_of_edps] = link;
+			dm->num_of_edps++;
+		}
 	}
 #endif
 }
@@ -3643,6 +3769,23 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 			goto fail;
 		}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	/* Use Outbox interrupt */
+	switch (adev->asic_type) {
+	case CHIP_SIENNA_CICHLID:
+	case CHIP_NAVY_FLOUNDER:
+	case CHIP_YELLOW_CARP:
+	case CHIP_RENOIR:
+		if (register_outbox_irq_handlers(dm->adev)) {
+			DRM_ERROR("DM: Failed to initialize IRQ\n");
+			goto fail;
+		}
+		break;
+	default:
+		DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", adev->asic_type);
+	}
+#endif
+
 	/* loops over all connectors on the board */
 	for (i = 0; i < link_cnt; i++) {
 		struct dc_link *link = NULL;
@@ -3734,7 +3877,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		if (dcn10_register_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
 			goto fail;
@@ -3756,7 +3901,6 @@ fail:
 
 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
 {
-	drm_mode_config_cleanup(dm->ddev);
 	drm_atomic_private_obj_fini(&dm->atomic_obj);
 	return;
 }
@@ -3907,12 +4051,22 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
+	case CHIP_YELLOW_CARP:
+		adev->mode_info.num_crtc = 4;
+		adev->mode_info.num_hpd = 4;
+		adev->mode_info.num_dig = 4;
+		break;
 	case CHIP_NAVI14:
 	case CHIP_DIMGREY_CAVEFISH:
 		adev->mode_info.num_crtc = 5;
 		adev->mode_info.num_hpd = 5;
 		adev->mode_info.num_dig = 5;
 		break;
+	case CHIP_BEIGE_GOBY:
+		adev->mode_info.num_crtc = 2;
+		adev->mode_info.num_hpd = 2;
+		adev->mode_info.num_dig = 2;
+		break;
 #endif
 	default:
 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
@@ -4138,6 +4292,8 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
 	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
 	    adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
+	    adev->asic_type == CHIP_BEIGE_GOBY ||
+	    adev->asic_type == CHIP_YELLOW_CARP ||
 	    adev->asic_type == CHIP_VANGOGH)
 		tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
 }
@@ -4557,6 +4713,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
 		break;
 	case AMDGPU_FAMILY_NV:
 	case AMDGPU_FAMILY_VGH:
+	case AMDGPU_FAMILY_YC:
 		if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 			add_gfx10_3_modifiers(adev, mods, &size, &capacity);
 		else
@@ -4828,6 +4985,14 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
 	case DRM_FORMAT_ABGR16161616F:
 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
 		break;
+	case DRM_FORMAT_XRGB16161616:
+	case DRM_FORMAT_ARGB16161616:
+		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
+		break;
+	case DRM_FORMAT_XBGR16161616:
+	case DRM_FORMAT_ABGR16161616:
+		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
+		break;
 	default:
 		DRM_ERROR(
 			"Unsupported screen format %p4cc\n",
@@ -5404,6 +5569,93 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
 	}
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
+							struct dc_sink *sink, struct dc_stream_state *stream,
+							struct dsc_dec_dpcd_caps *dsc_caps)
+{
+	stream->timing.flags.DSC = 0;
+
+	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
+		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
+				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
+				      dsc_caps);
+	}
+}
+
+static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
+										struct dc_sink *sink, struct dc_stream_state *stream,
+										struct dsc_dec_dpcd_caps *dsc_caps)
+{
+	struct drm_connector *drm_connector = &aconnector->base;
+	uint32_t link_bandwidth_kbps;
+
+	link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+							dc_link_get_link_cap(aconnector->dc_link));
+	/* Set DSC policy according to dsc_clock_en */
+	dc_dsc_policy_set_enable_dsc_when_not_needed(
+		aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
+
+	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
+
+		if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+						dsc_caps,
+						aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
+						0,
+						link_bandwidth_kbps,
+						&stream->timing,
+						&stream->timing.dsc_cfg)) {
+			stream->timing.flags.DSC = 1;
+			DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
+		}
+	}
+
+	/* Overwrite the stream flag if DSC is enabled through debugfs */
+	if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
+		stream->timing.flags.DSC = 1;
+
+	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
+		stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
+
+	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
+		stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
+
+	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
+		stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
+}
+#endif
+
+/**
+ * DOC: FreeSync Video
+ *
+ * When a userspace application wants to play a video, the content follows a
+ * standard format definition that usually specifies the FPS for that format.
+ * The below list illustrates some video format and the expected FPS,
+ * respectively:
+ *
+ * - TV/NTSC (23.976 FPS)
+ * - Cinema (24 FPS)
+ * - TV/PAL (25 FPS)
+ * - TV/NTSC (29.97 FPS)
+ * - TV/NTSC (30 FPS)
+ * - Cinema HFR (48 FPS)
+ * - TV/PAL (50 FPS)
+ * - Commonly used (60 FPS)
+ * - Multiples of 24 (48,72,96 FPS)
+ *
+ * The list of standards video format is not huge and can be added to the
+ * connector modeset list beforehand. With that, userspace can leverage
+ * FreeSync to extends the front porch in order to attain the target refresh
+ * rate. Such a switch will happen seamlessly, without screen blanking or
+ * reprogramming of the output in any other way. If the userspace requests a
+ * modesetting change compatible with FreeSync modes that only differ in the
+ * refresh rate, DC will skip the full update and avoid blink during the
+ * transition. For example, the video player can change the modesetting from
+ * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
+ * causing any display blink. This same concept can be applied to a mode
+ * setting change.
+ */
 static struct drm_display_mode *
 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
 			  bool use_probed_modes)
@@ -5506,7 +5758,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 	int preferred_refresh = 0;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	struct dsc_dec_dpcd_caps dsc_caps;
-	uint32_t link_bandwidth_kbps;
 #endif
 	struct dc_sink *sink = NULL;
 
@@ -5596,45 +5847,12 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 			stream, &mode, &aconnector->base, con_state, old_stream,
 			requested_bpc);
 
-	stream->timing.flags.DSC = 0;
-
-	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
-				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
-				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
-				      &dsc_caps);
-		link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
-							     dc_link_get_link_cap(aconnector->dc_link));
-
-		if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) {
-			/* Set DSC policy according to dsc_clock_en */
-			dc_dsc_policy_set_enable_dsc_when_not_needed(
-				aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
-
-			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
-						  &dsc_caps,
-						  aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
-						  0,
-						  link_bandwidth_kbps,
-						  &stream->timing,
-						  &stream->timing.dsc_cfg))
-				stream->timing.flags.DSC = 1;
-			/* Overwrite the stream flag if DSC is enabled through debugfs */
-			if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
-				stream->timing.flags.DSC = 1;
-
-			if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
-				stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
-
-			if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
-				stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
-
-			if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
-				stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
-		}
+	/* SST DSC determination policy */
+	update_dsc_caps(aconnector, sink, stream, &dsc_caps);
+	if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
+		apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
 #endif
-	}
 
 	update_stream_scaling_settings(&mode, dm_state, stream);
 
@@ -5662,6 +5880,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 				stream->use_vsc_sdp_for_colorimetry = true;
 		}
 		mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
+		aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
+
 	}
 finish:
 	dc_sink_release(sink);
@@ -6308,25 +6528,6 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state,
 	return 0;
 }
 
-static bool
-is_hdr_metadata_different(const struct drm_connector_state *old_state,
-			  const struct drm_connector_state *new_state)
-{
-	struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
-	struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
-
-	if (old_blob != new_blob) {
-		if (old_blob && new_blob &&
-		    old_blob->length == new_blob->length)
-			return memcmp(old_blob->data, new_blob->data,
-				      old_blob->length);
-
-		return true;
-	}
-
-	return false;
-}
-
 static int
 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
 				 struct drm_atomic_state *state)
@@ -6344,7 +6545,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
 	if (!crtc)
 		return 0;
 
-	if (is_hdr_metadata_different(old_con_state, new_con_state)) {
+	if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
 		struct dc_info_packet hdr_infopacket;
 
 		ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
@@ -6452,9 +6653,8 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
 
 	dm_update_crtc_active_planes(crtc, crtc_state);
 
-	if (unlikely(!dm_crtc_state->stream &&
-		     modeset_required(crtc_state, NULL, dm_crtc_state->stream))) {
-		WARN_ON(1);
+	if (WARN_ON(unlikely(!dm_crtc_state->stream &&
+		     modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
 		return ret;
 	}
 
@@ -6579,13 +6779,13 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
 {
 	struct dc_stream_state *stream = NULL;
 	struct drm_connector *connector;
-	struct drm_connector_state *new_con_state, *old_con_state;
+	struct drm_connector_state *new_con_state;
 	struct amdgpu_dm_connector *aconnector;
 	struct dm_connector_state *dm_conn_state;
 	int i, j, clock, bpp;
 	int vcpi, pbn_div, pbn = 0;
 
-	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
+	for_each_new_connector_in_state(state, connector, new_con_state, i) {
 
 		aconnector = to_amdgpu_dm_connector(connector);
 
@@ -6953,6 +7153,10 @@ static const uint32_t rgb_formats[] = {
 	DRM_FORMAT_XBGR2101010,
 	DRM_FORMAT_ARGB2101010,
 	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_XRGB16161616,
+	DRM_FORMAT_XBGR16161616,
+	DRM_FORMAT_ARGB16161616,
+	DRM_FORMAT_ABGR16161616,
 	DRM_FORMAT_XBGR8888,
 	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_RGB565,
@@ -7531,9 +7735,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 	    connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
 	    connector_type == DRM_MODE_CONNECTOR_eDP) {
-		drm_object_attach_property(
-			&aconnector->base.base,
-			dm->ddev->mode_config.hdr_output_metadata_property, 0);
+		drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
 
 		if (!aconnector->mst_port)
 			drm_connector_attach_vrr_capable_property(&aconnector->base);
@@ -8185,15 +8387,14 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
 {
 	struct drm_plane *plane;
-	struct drm_plane_state *old_plane_state, *new_plane_state;
+	struct drm_plane_state *old_plane_state;
 	int i;
 
 	/*
 	 * TODO: Make this per-stream so we don't issue redundant updates for
 	 * commits with multiple streams.
 	 */
-	for_each_oldnew_plane_in_state(state, plane, old_plane_state,
-				       new_plane_state, i)
+	for_each_old_plane_in_state(state, plane, old_plane_state, i)
 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
 			handle_cursor_update(plane, old_plane_state);
 }
@@ -8297,9 +8498,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		 * deadlock during GPU reset when this fence will not signal
 		 * but we hold reservation lock for the BO.
 		 */
-		r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
-							false,
-							msecs_to_jiffies(5000));
+		r = dma_resv_wait_timeout(abo->tbo.base.resv, true, false,
+					  msecs_to_jiffies(5000));
 		if (unlikely(r <= 0))
 			DRM_ERROR("Waiting for fences timed out!");
 
@@ -8495,7 +8695,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
 				acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
 				!acrtc_state->stream->link->psr_settings.psr_allow_active) {
-			amdgpu_dm_psr_enable(acrtc_state->stream);
+			struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
+					acrtc_state->stream->dm_stream_context;
+
+			if (aconn->psr_skip_count > 0)
+				aconn->psr_skip_count--;
+			else
+				amdgpu_dm_psr_enable(acrtc_state->stream);
 		}
 
 		mutex_unlock(&dm->dc_lock);
@@ -8838,7 +9044,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 			      dm_old_crtc_state->abm_level;
 
 		hdr_changed =
-			is_hdr_metadata_different(old_con_state, new_con_state);
+			!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
 
 		if (!scaling_changed && !abm_changed && !hdr_changed)
 			continue;
@@ -8864,7 +9070,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 		}
 
 		status = dc_stream_get_status(dm_new_crtc_state->stream);
-		WARN_ON(!status);
+
+		if (WARN_ON(!status))
+			continue;
+
 		WARN_ON(!status->plane_count);
 
 		/*
@@ -8914,6 +9123,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 #ifdef CONFIG_DEBUG_FS
 		bool configure_crc = false;
 		enum amdgpu_dm_pipe_crc_source cur_crc_src;
+#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
+		struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk;
+#endif
+		spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
+		cur_crc_src = acrtc->dm_irq_params.crc_src;
+		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 #endif
 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 
@@ -8930,21 +9145,26 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 			 * settings for the stream.
 			 */
 			dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-			spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
-			cur_crc_src = acrtc->dm_irq_params.crc_src;
-			spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 
 			if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
 				configure_crc = true;
 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
-				if (amdgpu_dm_crc_window_is_activated(crtc))
-					configure_crc = false;
+				if (amdgpu_dm_crc_window_is_activated(crtc)) {
+					spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
+					acrtc->dm_irq_params.crc_window.update_win = true;
+					acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2;
+					spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
+					crc_rd_wrk->crtc = crtc;
+					spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
+					spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
+				}
 #endif
 			}
 
 			if (configure_crc)
-				amdgpu_dm_crtc_configure_crc_source(
-					crtc, dm_new_crtc_state, cur_crc_src);
+				if (amdgpu_dm_crtc_configure_crc_source(
+					crtc, dm_new_crtc_state, cur_crc_src))
+					DRM_DEBUG_DRIVER("Failed to configure crc source");
 #endif
 		}
 	}
@@ -8965,6 +9185,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 	/* Update audio instances for each connector. */
 	amdgpu_dm_commit_audio(dev, state);
 
+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||		\
+	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
+	/* restore the backlight level */
+	if (dm->backlight_dev)
+		amdgpu_dm_backlight_set_level(dm, dm->brightness[0]);
+#endif
 	/*
 	 * send vblank event on all events not handled in flip and
 	 * mark consumed event for drm_atomic_helper_commit_hw_done
@@ -9464,7 +9690,8 @@ skip_modeset:
 	BUG_ON(dm_new_crtc_state->stream == NULL);
 
 	/* Scaling or underscan settings */
-	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
+	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
+				drm_atomic_crtc_needs_modeset(new_crtc_state))
 		update_stream_scaling_settings(
 			&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
 
@@ -9890,11 +10117,11 @@ static int validate_overlay(struct drm_atomic_state *state)
 {
 	int i;
 	struct drm_plane *plane;
-	struct drm_plane_state *old_plane_state, *new_plane_state;
+	struct drm_plane_state *new_plane_state;
 	struct drm_plane_state *primary_state, *cursor_state, *overlay_state = NULL;
 
 	/* Check if primary plane is contained inside overlay */
-	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
+	for_each_new_plane_in_state_reverse(state, plane, new_plane_state, i) {
 		if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
 			if (drm_atomic_plane_disabling(plane->state, new_plane_state))
 				return 0;
@@ -10031,6 +10258,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 			dm_old_crtc_state->dsc_force_changed == false)
 			continue;
 
+		ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
+		if (ret)
+			goto fail;
+
 		if (!new_crtc_state->enable)
 			continue;
 
@@ -10511,136 +10742,6 @@ update:
 						       freesync_capable);
 }
 
-static void amdgpu_dm_set_psr_caps(struct dc_link *link)
-{
-	uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
-
-	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
-		return;
-	if (link->type == dc_connection_none)
-		return;
-	if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
-					dpcd_data, sizeof(dpcd_data))) {
-		link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
-
-		if (dpcd_data[0] == 0) {
-			link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
-			link->psr_settings.psr_feature_enabled = false;
-		} else {
-			link->psr_settings.psr_version = DC_PSR_VERSION_1;
-			link->psr_settings.psr_feature_enabled = true;
-		}
-
-		DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
-	}
-}
-
-/*
- * amdgpu_dm_link_setup_psr() - configure psr link
- * @stream: stream state
- *
- * Return: true if success
- */
-static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
-{
-	struct dc_link *link = NULL;
-	struct psr_config psr_config = {0};
-	struct psr_context psr_context = {0};
-	bool ret = false;
-
-	if (stream == NULL)
-		return false;
-
-	link = stream->link;
-
-	psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
-
-	if (psr_config.psr_version > 0) {
-		psr_config.psr_exit_link_training_required = 0x1;
-		psr_config.psr_frame_capture_indication_req = 0;
-		psr_config.psr_rfb_setup_time = 0x37;
-		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
-		psr_config.allow_smu_optimizations = 0x0;
-
-		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
-
-	}
-	DRM_DEBUG_DRIVER("PSR link: %d\n",	link->psr_settings.psr_feature_enabled);
-
-	return ret;
-}
-
-/*
- * amdgpu_dm_psr_enable() - enable psr f/w
- * @stream: stream state
- *
- * Return: true if success
- */
-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
-{
-	struct dc_link *link = stream->link;
-	unsigned int vsync_rate_hz = 0;
-	struct dc_static_screen_params params = {0};
-	/* Calculate number of static frames before generating interrupt to
-	 * enter PSR.
-	 */
-	// Init fail safe of 2 frames static
-	unsigned int num_frames_static = 2;
-
-	DRM_DEBUG_DRIVER("Enabling psr...\n");
-
-	vsync_rate_hz = div64_u64(div64_u64((
-			stream->timing.pix_clk_100hz * 100),
-			stream->timing.v_total),
-			stream->timing.h_total);
-
-	/* Round up
-	 * Calculate number of frames such that at least 30 ms of time has
-	 * passed.
-	 */
-	if (vsync_rate_hz != 0) {
-		unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
-		num_frames_static = (30000 / frame_time_microsec) + 1;
-	}
-
-	params.triggers.cursor_update = true;
-	params.triggers.overlay_update = true;
-	params.triggers.surface_update = true;
-	params.num_frames = num_frames_static;
-
-	dc_stream_set_static_screen_params(link->ctx->dc,
-					   &stream, 1,
-					   &params);
-
-	return dc_link_set_psr_allow_active(link, true, false, false);
-}
-
-/*
- * amdgpu_dm_psr_disable() - disable psr f/w
- * @stream:  stream state
- *
- * Return: true if success
- */
-static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
-{
-
-	DRM_DEBUG_DRIVER("Disabling psr...\n");
-
-	return dc_link_set_psr_allow_active(stream->link, false, true, false);
-}
-
-/*
- * amdgpu_dm_psr_disable() - disable psr f/w
- * if psr is enabled on any stream
- *
- * Return: true if success
- */
-static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
-{
-	DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
-	return dc_set_psr_allow_active(dm->dc, false);
-}
-
 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
 {
 	struct amdgpu_device *adev = drm_to_adev(dev);
@@ -10697,3 +10798,30 @@ uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
 
 	return value;
 }
+
+int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex,
+				struct aux_payload *payload, enum aux_return_code_type *operation_result)
+{
+	struct amdgpu_device *adev = ctx->driver_context;
+	int ret = 0;
+
+	dc_process_dmub_aux_transfer_async(ctx->dc, linkIndex, payload);
+	ret = wait_for_completion_interruptible_timeout(&adev->dm.dmub_aux_transfer_done, 10*HZ);
+	if (ret == 0) {
+		*operation_result = AUX_RET_ERROR_TIMEOUT;
+		return -1;
+	}
+	*operation_result = (enum aux_return_code_type)adev->dm.dmub_notify->result;
+
+	if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) {
+		(*payload->reply) = adev->dm.dmub_notify->aux_reply.command;
+
+		// For read case, Copy data to payload
+		if (!payload->write && adev->dm.dmub_notify->aux_reply.length &&
+		(*payload->reply == AUX_TRANSACTION_REPLY_AUX_ACK))
+			memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data,
+			adev->dm.dmub_notify->aux_reply.length);
+	}
+
+	return adev->dm.dmub_notify->aux_reply.length;
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index b2f2ccfc20bb..9522d4ca299e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -46,6 +46,7 @@
 
 #define AMDGPU_DM_MAX_CRTC 6
 
+#define AMDGPU_DM_MAX_NUM_EDP 2
 /*
 #include "include/amdgpu_dal_power_if.h"
 #include "amdgpu_dm_irq.h"
@@ -54,6 +55,8 @@
 #include "irq_types.h"
 #include "signal_types.h"
 #include "amdgpu_dm_crc.h"
+struct aux_payload;
+enum aux_return_code_type;
 
 /* Forward declarations */
 struct amdgpu_device;
@@ -62,6 +65,7 @@ struct dc;
 struct amdgpu_bo;
 struct dmub_srv;
 struct dc_plane_state;
+struct dmub_notification;
 
 struct common_irq_params {
 	struct amdgpu_device *adev;
@@ -135,6 +139,10 @@ struct amdgpu_dm_backlight_caps {
 
 /**
  * struct dal_allocation - Tracks mapped FB memory for SMU communication
+ * @list: list of dal allocations
+ * @bo: GPU buffer object
+ * @cpu_ptr: CPU virtual address of the GPU buffer object
+ * @gpu_addr: GPU virtual address of the GPU buffer object
  */
 struct dal_allocation {
 	struct list_head list;
@@ -164,6 +172,7 @@ struct dal_allocation {
  * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
  * @force_timing_sync: set via debugfs. When set, indicates that all connected
  *		       displays will be forced to synchronize.
+ * @dmcub_trace_event_en: enable dmcub trace events
  */
 struct amdgpu_display_manager {
 
@@ -178,6 +187,8 @@ struct amdgpu_display_manager {
 	 */
 	struct dmub_srv *dmub_srv;
 
+	struct dmub_notification *dmub_notify;
+
 	/**
 	 * @dmub_fb_info:
 	 *
@@ -349,11 +360,17 @@ struct amdgpu_display_manager {
 	struct common_irq_params
 	dmub_trace_params[1];
 
+	struct common_irq_params
+	dmub_outbox_params[1];
+
 	spinlock_t irq_handler_list_table_lock;
 
 	struct backlight_device *backlight_dev;
 
-	const struct dc_link *backlight_link;
+	const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
+
+	uint8_t num_of_edps;
+
 	struct amdgpu_dm_backlight_caps backlight_caps;
 
 	struct mod_freesync *freesync_module;
@@ -418,6 +435,14 @@ struct amdgpu_display_manager {
 	 * DAL fb memory allocation list, for communication with SMU.
 	 */
 	struct list_head da_list;
+	struct completion dmub_aux_transfer_done;
+
+	/**
+	 * @brightness:
+	 *
+	 * cached backlight values.
+	 */
+	u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
 };
 
 enum dsc_clock_force_state {
@@ -431,6 +456,7 @@ struct dsc_preferred_settings {
 	uint32_t dsc_num_slices_v;
 	uint32_t dsc_num_slices_h;
 	uint32_t dsc_bits_per_pixel;
+	bool dsc_force_disable_passthrough;
 };
 
 struct amdgpu_dm_connector {
@@ -483,6 +509,8 @@ struct amdgpu_dm_connector {
 	struct dsc_preferred_settings dsc_settings;
 	/* Cached display modes */
 	struct drm_display_mode freesync_vid_base;
+
+	int psr_skip_count;
 };
 
 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
@@ -591,6 +619,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
 
 void amdgpu_dm_init_color_mod(void);
+int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
 				      struct dc_plane_state *dc_plane_state);
@@ -600,4 +629,6 @@ void amdgpu_dm_update_connector_after_detect(
 
 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
 
+int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex,
+					struct aux_payload *payload, enum aux_return_code_type *operation_result);
 #endif /* __AMDGPU_DM_H__ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 157fe4efbb59..a022e5bb30a5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -285,6 +285,37 @@ static int __set_input_tf(struct dc_transfer_func *func,
 }
 
 /**
+ * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of
+ * the expected size.
+ * Returns 0 on success.
+ */
+int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
+{
+	const struct drm_color_lut *lut = NULL;
+	uint32_t size = 0;
+
+	lut = __extract_blob_lut(crtc_state->degamma_lut, &size);
+	if (lut && size != MAX_COLOR_LUT_ENTRIES) {
+		DRM_DEBUG_DRIVER(
+			"Invalid Degamma LUT size. Should be %u but got %u.\n",
+			MAX_COLOR_LUT_ENTRIES, size);
+		return -EINVAL;
+	}
+
+	lut = __extract_blob_lut(crtc_state->gamma_lut, &size);
+	if (lut && size != MAX_COLOR_LUT_ENTRIES &&
+	    size != MAX_COLOR_LEGACY_LUT_ENTRIES) {
+		DRM_DEBUG_DRIVER(
+			"Invalid Gamma LUT size. Should be %u (or %u for legacy) but got %u.\n",
+			MAX_COLOR_LUT_ENTRIES, MAX_COLOR_LEGACY_LUT_ENTRIES,
+			size);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
  * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream.
  * @crtc: amdgpu_dm crtc state
  *
@@ -317,14 +348,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 	bool is_legacy;
 	int r;
 
-	degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, &degamma_size);
-	if (degamma_lut && degamma_size != MAX_COLOR_LUT_ENTRIES)
-		return -EINVAL;
+	r = amdgpu_dm_verify_lut_sizes(&crtc->base);
+	if (r)
+		return r;
 
+	degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, &degamma_size);
 	regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, &regamma_size);
-	if (regamma_lut && regamma_size != MAX_COLOR_LUT_ENTRIES &&
-	    regamma_size != MAX_COLOR_LEGACY_LUT_ENTRIES)
-		return -EINVAL;
 
 	has_degamma =
 		degamma_lut && !__is_lut_linear(degamma_lut, degamma_size);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 5cd788b20c21..cce062adc439 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -176,7 +176,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 
 	/* Configuration will be deferred to stream enable. */
 	if (!stream_state)
-		return 0;
+		return -EINVAL;
 
 	mutex_lock(&adev->dm.dc_lock);
 
@@ -525,67 +525,6 @@ cleanup:
 	spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
 }
 
-void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev)
-{
-	struct drm_crtc *crtc;
-	enum amdgpu_dm_pipe_crc_source cur_crc_src;
-	struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
-	struct crc_window_parm cur_crc_window;
-	struct amdgpu_crtc *acrtc = NULL;
-
-	drm_for_each_crtc(crtc, &adev->ddev) {
-		acrtc = to_amdgpu_crtc(crtc);
-
-		spin_lock_irq(&adev_to_drm(adev)->event_lock);
-		cur_crc_src = acrtc->dm_irq_params.crc_src;
-		cur_crc_window = acrtc->dm_irq_params.crc_window;
-		spin_unlock_irq(&adev_to_drm(adev)->event_lock);
-
-		if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
-			amdgpu_dm_crtc_set_crc_source(crtc,
-				pipe_crc_sources[cur_crc_src]);
-			spin_lock_irq(&adev_to_drm(adev)->event_lock);
-			acrtc->dm_irq_params.crc_window = cur_crc_window;
-			if (acrtc->dm_irq_params.crc_window.activated) {
-				acrtc->dm_irq_params.crc_window.update_win = true;
-				acrtc->dm_irq_params.crc_window.skip_frame_cnt = 1;
-				spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
-				crc_rd_wrk->crtc = crtc;
-				spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
-			}
-			spin_unlock_irq(&adev_to_drm(adev)->event_lock);
-		}
-	}
-}
-
-void amdgpu_dm_crtc_secure_display_suspend(struct amdgpu_device *adev)
-{
-	struct drm_crtc *crtc;
-	struct crc_window_parm cur_crc_window;
-	enum amdgpu_dm_pipe_crc_source cur_crc_src;
-	struct amdgpu_crtc *acrtc = NULL;
-
-	drm_for_each_crtc(crtc, &adev->ddev) {
-		acrtc = to_amdgpu_crtc(crtc);
-
-		spin_lock_irq(&adev_to_drm(adev)->event_lock);
-		cur_crc_src = acrtc->dm_irq_params.crc_src;
-		cur_crc_window = acrtc->dm_irq_params.crc_window;
-		cur_crc_window.update_win = false;
-		spin_unlock_irq(&adev_to_drm(adev)->event_lock);
-
-		if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
-			amdgpu_dm_crtc_set_crc_source(crtc, NULL);
-			spin_lock_irq(&adev_to_drm(adev)->event_lock);
-			/* For resume to set back crc source*/
-			acrtc->dm_irq_params.crc_src = cur_crc_src;
-			acrtc->dm_irq_params.crc_window = cur_crc_window;
-			spin_unlock_irq(&adev_to_drm(adev)->event_lock);
-		}
-	}
-
-}
-
 struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void)
 {
 	struct crc_rd_work *crc_rd_wrk = NULL;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
index 737e701fb0f0..f07850db60a6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
@@ -91,14 +91,10 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
 struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void);
-void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev);
-void amdgpu_dm_crtc_secure_display_suspend(struct amdgpu_device *adev);
 #else
 #define amdgpu_dm_crc_window_is_activated(x)
 #define amdgpu_dm_crtc_handle_crc_window_irq(x)
 #define amdgpu_dm_crtc_secure_display_create_work()
-#define amdgpu_dm_crtc_secure_display_resume(x)
-#define amdgpu_dm_crtc_secure_display_suspend(x)
 #endif
 
 #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 1b6b15708b96..f1145086a468 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -887,6 +887,47 @@ unlock:
 	return res;
 }
 
+/*
+ * Example usage:
+ * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
+ *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
+ * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
+ *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
+ */
+static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
+				 size_t size, loff_t *pos)
+{
+	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+	char *wr_buf = NULL;
+	uint32_t wr_buf_size = 42;
+	int max_param_num = 1;
+	long param;
+	uint8_t param_nums = 0;
+
+	if (size == 0)
+		return -EINVAL;
+
+	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
+
+	if (!wr_buf) {
+		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
+		return -ENOSPC;
+	}
+
+	if (parse_write_buffer_into_params(wr_buf, size,
+					   &param, buf,
+					   max_param_num,
+					   &param_nums)) {
+		kfree(wr_buf);
+		return -EINVAL;
+	}
+
+	aconnector->dsc_settings.dsc_force_disable_passthrough = param;
+
+	kfree(wr_buf);
+	return 0;
+}
+
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 /*
  * Returns the HDCP capability of the Display (1.4 for now).
@@ -925,6 +966,22 @@ static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 	return 0;
 }
 #endif
+
+/*
+ * Returns whether the connected display is internal and not hotpluggable.
+ * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
+ */
+static int internal_display_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+	struct dc_link *link = aconnector->dc_link;
+
+	seq_printf(m, "Internal: %u\n", link->is_internal_display);
+
+	return 0;
+}
+
 /* function description
  *
  * generic SDP message access for testing
@@ -2361,6 +2418,44 @@ unlock:
 	return size;
 }
 
+/*
+ * Backlight at this moment.  Read only.
+ * As written to display, taking ABM and backlight lut into account.
+ * Ranges from 0x0 to 0x10000 (= 100% PWM)
+ *
+ * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
+ */
+static int current_backlight_show(struct seq_file *m, void *unused)
+{
+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
+	struct dc_link *link = aconnector->dc_link;
+	unsigned int backlight;
+
+	backlight = dc_link_get_backlight_level(link);
+	seq_printf(m, "0x%x\n", backlight);
+
+	return 0;
+}
+
+/*
+ * Backlight value that is being approached.  Read only.
+ * As written to display, taking ABM and backlight lut into account.
+ * Ranges from 0x0 to 0x10000 (= 100% PWM)
+ *
+ * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
+ */
+static int target_backlight_show(struct seq_file *m, void *unused)
+{
+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
+	struct dc_link *link = aconnector->dc_link;
+	unsigned int backlight;
+
+	backlight = dc_link_get_target_backlight_pwm(link);
+	seq_printf(m, "0x%x\n", backlight);
+
+	return 0;
+}
+
 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
@@ -2369,6 +2464,7 @@ DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
 #endif
+DEFINE_SHOW_ATTRIBUTE(internal_display);
 
 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
 	.owner = THIS_MODULE,
@@ -2480,6 +2576,12 @@ static const struct file_operations dp_max_bpc_debugfs_fops = {
 	.llseek = default_llseek
 };
 
+static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
+	.owner = THIS_MODULE,
+	.write = dp_dsc_passthrough_set,
+	.llseek = default_llseek
+};
+
 static const struct {
 	char *name;
 	const struct file_operations *fops;
@@ -2504,7 +2606,8 @@ static const struct {
 		{"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
 		{"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
 		{"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
-		{"max_bpc", &dp_max_bpc_debugfs_fops}
+		{"max_bpc", &dp_max_bpc_debugfs_fops},
+		{"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
 };
 
 #ifdef CONFIG_DRM_AMD_DC_HDCP
@@ -2594,13 +2697,17 @@ DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_g
 
 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
 
+DEFINE_SHOW_ATTRIBUTE(current_backlight);
+DEFINE_SHOW_ATTRIBUTE(target_backlight);
+
 static const struct {
 	char *name;
 	const struct file_operations *fops;
 } connector_debugfs_entries[] = {
 		{"force_yuv420_output", &force_yuv420_output_fops},
 		{"output_bpc", &output_bpc_fops},
-		{"trigger_hotplug", &trigger_hotplug_debugfs_fops}
+		{"trigger_hotplug", &trigger_hotplug_debugfs_fops},
+		{"internal_display", &internal_display_fops}
 };
 
 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
@@ -2616,8 +2723,13 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
 					    dp_debugfs_entries[i].fops);
 		}
 	}
-	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
+	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
 		debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
+		debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
+				    &current_backlight_fops);
+		debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
+				    &target_backlight_fops);
+	}
 
 	for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
 		debugfs_create_file(connector_debugfs_entries[i].name,
@@ -2920,38 +3032,6 @@ static ssize_t dtn_log_write(
 	return size;
 }
 
-/*
- * Backlight at this moment.  Read only.
- * As written to display, taking ABM and backlight lut into account.
- * Ranges from 0x0 to 0x10000 (= 100% PWM)
- */
-static int current_backlight_show(struct seq_file *m, void *unused)
-{
-	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
-	struct amdgpu_display_manager *dm = &adev->dm;
-
-	unsigned int backlight = dc_link_get_backlight_level(dm->backlight_link);
-
-	seq_printf(m, "0x%x\n", backlight);
-	return 0;
-}
-
-/*
- * Backlight value that is being approached.  Read only.
- * As written to display, taking ABM and backlight lut into account.
- * Ranges from 0x0 to 0x10000 (= 100% PWM)
- */
-static int target_backlight_show(struct seq_file *m, void *unused)
-{
-	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
-	struct amdgpu_display_manager *dm = &adev->dm;
-
-	unsigned int backlight = dc_link_get_target_backlight_pwm(dm->backlight_link);
-
-	seq_printf(m, "0x%x\n", backlight);
-	return 0;
-}
-
 static int mst_topo_show(struct seq_file *m, void *unused)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
@@ -3134,8 +3214,6 @@ static int visual_confirm_get(void *data, u64 *val)
 	return 0;
 }
 
-DEFINE_SHOW_ATTRIBUTE(current_backlight);
-DEFINE_SHOW_ATTRIBUTE(target_backlight);
 DEFINE_SHOW_ATTRIBUTE(mst_topo);
 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
 			 visual_confirm_set, "%llu\n");
@@ -3215,10 +3293,6 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
 	struct drm_minor *minor = adev_to_drm(adev)->primary;
 	struct dentry *root = minor->debugfs_root;
 
-	debugfs_create_file("amdgpu_current_backlight_pwm", 0444,
-			    root, adev, &current_backlight_fops);
-	debugfs_create_file("amdgpu_target_backlight_pwm", 0444,
-			    root, adev, &target_backlight_fops);
 	debugfs_create_file("amdgpu_mst_topology", 0444, root,
 			    adev, &mst_topo_fops);
 	debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 666796a0067c..e63c6885c757 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -222,10 +222,23 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,
 			 struct amdgpu_dm_connector *aconnector)
 {
 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+	struct drm_connector_state *conn_state = aconnector->base.state;
 
 	mutex_lock(&hdcp_w->mutex);
 	hdcp_w->aconnector = aconnector;
 
+	/* the removal of display will invoke auth reset -> hdcp destroy and
+	 * we'd expect the Content Protection (CP) property changed back to
+	 * DESIRED if at the time ENABLED. CP property change should occur
+	 * before the element removed from linked list.
+	 */
+	if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
+		conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+
+		DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n",
+			 aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms);
+	}
+
 	mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
 
 	process_output(hdcp_w);
@@ -454,6 +467,11 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	display->dig_fe = config->dig_fe;
 	link->dig_be = config->dig_be;
 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
+	display->stream_enc_idx = config->stream_enc_idx;
+	link->link_enc_idx = config->link_enc_idx;
+	link->phy_idx = config->phy_idx;
+	link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link,
+			aconnector->dc_sink->sink_signal) ? 1 : 0;
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 	link->dp.assr_enabled = config->assr_enabled;
 	link->dp.mst_enabled = config->mst_enabled;
@@ -462,7 +480,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->adjust.hdcp1.disable = 0;
 	conn_state = aconnector->base.state;
 
-	pr_debug("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
+	DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
 			(!!aconnector->base.state) ? aconnector->base.state->content_protection : -1,
 			(!!aconnector->base.state) ? aconnector->base.state->hdcp_content_type : -1);
 
@@ -637,6 +655,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct
 		INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
 
 		hdcp_work[i].hdcp.config.psp.handle = &adev->psp;
+		if (dc->ctx->dce_version == DCN_VERSION_3_1) {
+			hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
+			hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false;
+		}
 		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
 		hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
 		hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index e8b325a828c1..6fee12c91ef5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -544,8 +544,10 @@ bool dm_helpers_dp_write_dsc_enable(
 		ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1);
 	}
 
-	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
-		return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
+		ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
+		DC_LOG_DC("Send DSC %s to sst display\n", enable_dsc ? "enable" : "disable");
+	}
 
 	return (ret > 0);
 }
@@ -640,12 +642,25 @@ enum dc_edid_status dm_helpers_read_local_edid(
 
 	return edid_status;
 }
-
+int dm_helper_dmub_aux_transfer_sync(
+		struct dc_context *ctx,
+		const struct dc_link *link,
+		struct aux_payload *payload,
+		enum aux_return_code_type *operation_result)
+{
+	return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, operation_result);
+}
 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 {
 	/* TODO: something */
 }
 
+void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
+{
+	// TODO:
+	//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
+}
+
 void *dm_helpers_allocate_gpu_mem(
 		struct dc_context *ctx,
 		enum dc_gpu_mem_alloc_type type,
@@ -698,12 +713,12 @@ void dm_helpers_free_gpu_mem(
 	}
 }
 
-bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable)
+bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
 {
 	enum dc_irq_source irq_source;
 	bool ret;
 
-	irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX0;
+	irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
 
 	ret = dc_interrupt_set(ctx->dc, irq_source, enable);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index b3ed7e777720..40f617bbb86f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -769,6 +769,18 @@ static int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev,
 		__func__);
 }
 
+static int amdgpu_dm_set_dmub_outbox_irq_state(struct amdgpu_device *adev,
+					struct amdgpu_irq_src *source,
+					unsigned int crtc_id,
+					enum amdgpu_interrupt_state state)
+{
+	enum dc_irq_source irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
+	bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
+
+	dc_interrupt_set(adev->dm.dc, irq_source, st);
+	return 0;
+}
+
 static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev,
 					   struct amdgpu_irq_src *source,
 					   unsigned int crtc_id,
@@ -805,6 +817,11 @@ static const struct amdgpu_irq_src_funcs dm_vline0_irq_funcs = {
 	.process = amdgpu_dm_irq_handler,
 };
 
+static const struct amdgpu_irq_src_funcs dm_dmub_outbox_irq_funcs = {
+	.set = amdgpu_dm_set_dmub_outbox_irq_state,
+	.process = amdgpu_dm_irq_handler,
+};
+
 static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = {
 	.set = amdgpu_dm_set_vupdate_irq_state,
 	.process = amdgpu_dm_irq_handler,
@@ -827,13 +844,15 @@ static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
 
 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
 {
-
 	adev->crtc_irq.num_types = adev->mode_info.num_crtc;
 	adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
 
 	adev->vline0_irq.num_types = adev->mode_info.num_crtc;
 	adev->vline0_irq.funcs = &dm_vline0_irq_funcs;
 
+	adev->dmub_outbox_irq.num_types = 1;
+	adev->dmub_outbox_irq.funcs = &dm_dmub_outbox_irq_funcs;
+
 	adev->vupdate_irq.num_types = adev->mode_info.num_crtc;
 	adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;
 
@@ -846,6 +865,12 @@ void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
 	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
 	adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
 }
+void amdgpu_dm_outbox_init(struct amdgpu_device *adev)
+{
+	dc_interrupt_set(adev->dm.dc,
+		DC_IRQ_SOURCE_DMCUB_OUTBOX,
+		true);
+}
 
 /**
  * amdgpu_dm_hpd_init - hpd setup callback.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h
index 82f8e761beca..2349238a626b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h
@@ -82,6 +82,7 @@ void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
 
 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
 
+void amdgpu_dm_outbox_init(struct amdgpu_device *adev);
 void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9b221db526dc..5568d4e518e6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -160,6 +160,8 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto
 	struct dc_sink *dc_sink = aconnector->dc_sink;
 	struct drm_dp_mst_port *port = aconnector->port;
 	u8 dsc_caps[16] = { 0 };
+	u8 dsc_branch_dec_caps_raw[3] = { 0 };	// DSC branch decoder caps 0xA0 ~ 0xA2
+	u8 *dsc_branch_dec_caps = NULL;
 
 	aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 #if defined(CONFIG_HP_HOOK_WORKAROUND)
@@ -182,9 +184,13 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto
 	if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 		return false;
 
+	if (drm_dp_dpcd_read(aconnector->dsc_aux,
+			DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
+		dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
+
 	if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
-				   dsc_caps, NULL,
-				   &dc_sink->dsc_caps.dsc_dec_caps))
+				  dsc_caps, dsc_branch_dec_caps,
+				  &dc_sink->dsc_caps.dsc_dec_caps))
 		return false;
 
 	return true;
@@ -278,6 +284,9 @@ dm_dp_mst_detect(struct drm_connector *connector,
 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 	struct amdgpu_dm_connector *master = aconnector->mst_port;
 
+	if (drm_connector_is_unregistered(connector))
+		return connector_status_disconnected;
+
 	return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 				      aconnector->port);
 }
@@ -434,10 +443,13 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 				       struct amdgpu_dm_connector *aconnector,
 				       int link_index)
 {
+	struct dc_link_settings max_link_enc_cap = {0};
+
 	aconnector->dm_dp_aux.aux.name =
 		kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
 			  link_index);
 	aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
+	aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
 	aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 
 	drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
@@ -447,6 +459,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 	if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 		return;
 
+	dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
 	aconnector->mst_mgr.cbs = &dm_mst_cbs;
 	drm_dp_mst_topology_mgr_init(
 		&aconnector->mst_mgr,
@@ -454,6 +467,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 		&aconnector->dm_dp_aux.aux,
 		16,
 		4,
+		max_link_enc_cap.lane_count,
+		drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate),
 		aconnector->connector_id);
 
 	drm_connector_attach_dp_subconnector_property(&aconnector->base);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
new file mode 100644
index 000000000000..70a554f1e725
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "amdgpu_dm_psr.h"
+#include "dc.h"
+#include "dm_helpers.h"
+
+/*
+ * amdgpu_dm_set_psr_caps() - set link psr capabilities
+ * @link: link
+ *
+ */
+void amdgpu_dm_set_psr_caps(struct dc_link *link)
+{
+	uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
+
+	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
+		return;
+	if (link->type == dc_connection_none)
+		return;
+	if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
+					dpcd_data, sizeof(dpcd_data))) {
+		link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
+
+		if (dpcd_data[0] == 0) {
+			link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
+			link->psr_settings.psr_feature_enabled = false;
+		} else {
+			link->psr_settings.psr_version = DC_PSR_VERSION_1;
+			link->psr_settings.psr_feature_enabled = true;
+		}
+
+		DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
+	}
+}
+
+/*
+ * amdgpu_dm_link_setup_psr() - configure psr link
+ * @stream: stream state
+ *
+ * Return: true if success
+ */
+bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
+{
+	struct dc_link *link = NULL;
+	struct psr_config psr_config = {0};
+	struct psr_context psr_context = {0};
+	bool ret = false;
+
+	if (stream == NULL)
+		return false;
+
+	link = stream->link;
+
+	psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
+
+	if (psr_config.psr_version > 0) {
+		psr_config.psr_exit_link_training_required = 0x1;
+		psr_config.psr_frame_capture_indication_req = 0;
+		psr_config.psr_rfb_setup_time = 0x37;
+		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
+		psr_config.allow_smu_optimizations = 0x0;
+
+		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
+
+	}
+	DRM_DEBUG_DRIVER("PSR link: %d\n",	link->psr_settings.psr_feature_enabled);
+
+	return ret;
+}
+
+/*
+ * amdgpu_dm_psr_enable() - enable psr f/w
+ * @stream: stream state
+ *
+ * Return: true if success
+ */
+bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
+{
+	struct dc_link *link = stream->link;
+	unsigned int vsync_rate_hz = 0;
+	struct dc_static_screen_params params = {0};
+	/* Calculate number of static frames before generating interrupt to
+	 * enter PSR.
+	 */
+	// Init fail safe of 2 frames static
+	unsigned int num_frames_static = 2;
+
+	DRM_DEBUG_DRIVER("Enabling psr...\n");
+
+	vsync_rate_hz = div64_u64(div64_u64((
+			stream->timing.pix_clk_100hz * 100),
+			stream->timing.v_total),
+			stream->timing.h_total);
+
+	/* Round up
+	 * Calculate number of frames such that at least 30 ms of time has
+	 * passed.
+	 */
+	if (vsync_rate_hz != 0) {
+		unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
+		num_frames_static = (30000 / frame_time_microsec) + 1;
+	}
+
+	params.triggers.cursor_update = true;
+	params.triggers.overlay_update = true;
+	params.triggers.surface_update = true;
+	params.num_frames = num_frames_static;
+
+	dc_stream_set_static_screen_params(link->ctx->dc,
+					   &stream, 1,
+					   &params);
+
+	return dc_link_set_psr_allow_active(link, true, false, false);
+}
+
+/*
+ * amdgpu_dm_psr_disable() - disable psr f/w
+ * @stream:  stream state
+ *
+ * Return: true if success
+ */
+bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
+{
+
+	DRM_DEBUG_DRIVER("Disabling psr...\n");
+
+	return dc_link_set_psr_allow_active(stream->link, false, true, false);
+}
+
+/*
+ * amdgpu_dm_psr_disable() - disable psr f/w
+ * if psr is enabled on any stream
+ *
+ * Return: true if success
+ */
+bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
+{
+	DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
+	return dc_set_psr_allow_active(dm->dc, false);
+}
+
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
new file mode 100644
index 000000000000..6806b3c9c84b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef AMDGPU_DM_AMDGPU_DM_PSR_H_
+#define AMDGPU_DM_AMDGPU_DM_PSR_H_
+
+#include "amdgpu.h"
+
+/* the number of pageflips before enabling psr */
+#define AMDGPU_DM_PSR_ENTRY_DELAY 5
+
+void amdgpu_dm_set_psr_caps(struct dc_link *link);
+bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
+bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
+bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
+bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
+
+#endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index f33847299bca..943fcb164876 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -33,6 +33,8 @@ DC_LIBS += dcn21
 DC_LIBS += dcn30
 DC_LIBS += dcn301
 DC_LIBS += dcn302
+DC_LIBS += dcn303
+DC_LIBS += dcn31
 endif
 
 DC_LIBS += dce120
@@ -54,9 +56,9 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI
 
 include $(AMD_DC)
 
-DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
+DISPLAY_CORE = dc.o  dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
 dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
-dc_link_enc_cfg.o
+dc_link_enc_cfg.o dc_link_dpcd.o
 
 ifdef CONFIG_DRM_AMD_DC_DCN
 DISPLAY_CORE += dc_vm_helper.o
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index c67d21a5ee52..9b8ea6e9a2b9 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -979,7 +979,7 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
 	struct spread_spectrum_info *info);
 
 /**
- * get_ss_info_from_table
+ * get_ss_info_from_tbl
  * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
  * SS_Info table from the VBIOS
  * There can not be more than 1 entry for  ASIC_InternalSS_Info Ver 2.1 or
@@ -1548,7 +1548,7 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
 	uint32_t id);
 
 /**
- * BiosParserObject::GetNumberofSpreadSpectrumEntry
+ * bios_parser_get_ss_entry_number
  * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from
  * the VBIOS that match the SSid (to be converted from signal)
  *
@@ -1725,7 +1725,7 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
 	return 0;
 }
 /**
- * get_ss_entry_number_from_internal_ss_info_table_V3_1
+ * get_ss_entry_number_from_internal_ss_info_tbl_V3_1
  * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of
  * the VBIOS that matches id
  *
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index d79f4fe06c47..6dbde74c1e06 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -577,6 +577,11 @@ static struct device_id device_type_from_device_id(uint16_t device_id)
 		result_device_id.enum_id = 1;
 		break;
 
+	case ATOM_DISPLAY_LCD2_SUPPORT:
+		result_device_id.device_type = DEVICE_TYPE_LCD;
+		result_device_id.enum_id = 2;
+		break;
+
 	case ATOM_DISPLAY_DFP1_SUPPORT:
 		result_device_id.device_type = DEVICE_TYPE_DFP;
 		result_device_id.enum_id = 1;
@@ -836,8 +841,10 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
 			return get_ss_info_v4_1(bp, signal, index, ss_info);
 		case 2:
 		case 3:
+		case 4:
 			return get_ss_info_v4_2(bp, signal, index, ss_info);
 		default:
+			ASSERT(0);
 			break;
 		}
 		break;
@@ -2131,7 +2138,7 @@ static enum bp_result get_integrated_info_v2_1(
 		info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
 	info->edp1_info.edp_panel_bpc =
 		info_v2_1->edp1_info.edp_panel_bpc;
-	info->edp1_info.edp_bootup_bl_level =
+	info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
 
 	info->edp2_info.edp_backlight_pwm_hz =
 	le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
@@ -2153,6 +2160,106 @@ static enum bp_result get_integrated_info_v2_1(
 	return BP_RESULT_OK;
 }
 
+static enum bp_result get_integrated_info_v2_2(
+	struct bios_parser *bp,
+	struct integrated_info *info)
+{
+	struct atom_integrated_system_info_v2_2 *info_v2_2;
+	uint32_t i;
+
+	info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
+					DATA_TABLES(integratedsysteminfo));
+
+	if (info_v2_2 == NULL)
+		return BP_RESULT_BADBIOSTABLE;
+
+	info->gpu_cap_info =
+	le32_to_cpu(info_v2_2->gpucapinfo);
+	/*
+	* system_config: Bit[0] = 0 : PCIE power gating disabled
+	*                       = 1 : PCIE power gating enabled
+	*                Bit[1] = 0 : DDR-PLL shut down disabled
+	*                       = 1 : DDR-PLL shut down enabled
+	*                Bit[2] = 0 : DDR-PLL power down disabled
+	*                       = 1 : DDR-PLL power down enabled
+	*/
+	info->system_config = le32_to_cpu(info_v2_2->system_config);
+	info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
+	info->memory_type = info_v2_2->memorytype;
+	info->ma_channel_number = info_v2_2->umachannelnumber;
+	info->dp_ss_control =
+		le16_to_cpu(info_v2_2->reserved1);
+
+	for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
+		info->ext_disp_conn_info.gu_id[i] =
+				info_v2_2->extdispconninfo.guid[i];
+	}
+
+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
+		info->ext_disp_conn_info.path[i].device_connector_id =
+		object_id_from_bios_object_id(
+		le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
+
+		info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
+		object_id_from_bios_object_id(
+			le16_to_cpu(
+			info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
+
+		info->ext_disp_conn_info.path[i].device_tag =
+			le16_to_cpu(
+				info_v2_2->extdispconninfo.path[i].device_tag);
+		info->ext_disp_conn_info.path[i].device_acpi_enum =
+		le16_to_cpu(
+			info_v2_2->extdispconninfo.path[i].device_acpi_enum);
+		info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
+			info_v2_2->extdispconninfo.path[i].auxddclut_index;
+		info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
+			info_v2_2->extdispconninfo.path[i].hpdlut_index;
+		info->ext_disp_conn_info.path[i].channel_mapping.raw =
+			info_v2_2->extdispconninfo.path[i].channelmapping;
+		info->ext_disp_conn_info.path[i].caps =
+				le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
+	}
+
+	info->ext_disp_conn_info.checksum =
+		info_v2_2->extdispconninfo.checksum;
+
+	info->edp1_info.edp_backlight_pwm_hz =
+	le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
+	info->edp1_info.edp_ss_percentage =
+	le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
+	info->edp1_info.edp_ss_rate_10hz =
+	le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
+	info->edp1_info.edp_pwr_on_off_delay =
+		info_v2_2->edp1_info.edp_pwr_on_off_delay;
+	info->edp1_info.edp_pwr_on_vary_bl_to_blon =
+		info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
+	info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
+		info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
+	info->edp1_info.edp_panel_bpc =
+		info_v2_2->edp1_info.edp_panel_bpc;
+	info->edp1_info.edp_bootup_bl_level =
+
+	info->edp2_info.edp_backlight_pwm_hz =
+	le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
+	info->edp2_info.edp_ss_percentage =
+	le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
+	info->edp2_info.edp_ss_rate_10hz =
+	le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
+	info->edp2_info.edp_pwr_on_off_delay =
+		info_v2_2->edp2_info.edp_pwr_on_off_delay;
+	info->edp2_info.edp_pwr_on_vary_bl_to_blon =
+		info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
+	info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
+		info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
+	info->edp2_info.edp_panel_bpc =
+		info_v2_2->edp2_info.edp_panel_bpc;
+	info->edp2_info.edp_bootup_bl_level =
+		info_v2_2->edp2_info.edp_bootup_bl_level;
+
+	return BP_RESULT_OK;
+}
+
 /*
  * construct_integrated_info
  *
@@ -2200,6 +2307,9 @@ static enum bp_result construct_integrated_info(
 			case 1:
 				result = get_integrated_info_v2_1(bp, info);
 				break;
+			case 2:
+				result = get_integrated_info_v2_2(bp, info);
+				break;
 			default:
 				return result;
 			}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index 53d7513b5083..adc710fe4a45 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -82,9 +82,6 @@ void bios_set_scratch_critical_state(
 uint32_t bios_get_vga_enabled_displays(
 	struct dc_bios *bios)
 {
-	uint32_t active_disp = 1;
-
-	active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF;
-	return active_disp;
+	return REG_READ(BIOS_SCRATCH_3) & 0XFFFF;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 5b77251e0590..e317a3615147 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -114,7 +114,7 @@ bool dal_cmd_table_helper_controller_id_to_atom(
 }
 
 /**
- * translate_transmitter_bp_to_atom - Translate the Transmitter to the
+ * dal_cmd_table_helper_transmitter_bp_to_atom - Translate the Transmitter to the
  *                                    corresponding ATOM BIOS value
  * @t: transmitter
  * returns: output digitalTransmitter
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 455ee2be15a3..cb3fd44cb1ed 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -73,6 +73,8 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 	case DCN_VERSION_3_0:
 	case DCN_VERSION_3_01:
 	case DCN_VERSION_3_02:
+	case DCN_VERSION_3_03:
+	case DCN_VERSION_3_1:
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
 		return true;
 #endif
@@ -128,7 +130,7 @@ bool dal_cmd_table_helper_controller_id_to_atom2(
 }
 
 /**
- * translate_transmitter_bp_to_atom2 - Translate the Transmitter to the
+ * dal_cmd_table_helper_transmitter_bp_to_atom2 - Translate the Transmitter to the
  *                                     corresponding ATOM BIOS value
  *  @t: transmitter
  *  returns: digitalTransmitter
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 1244fcb0f446..ff5bb152ef49 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -2863,6 +2863,7 @@ static void populate_initial_data(
 			data->bytes_per_pixel[num_displays + 4] = 4;
 			break;
 		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 			data->bytes_per_pixel[num_displays + 4] = 8;
 			break;
@@ -2966,6 +2967,7 @@ static void populate_initial_data(
 				data->bytes_per_pixel[num_displays + 4] = 4;
 				break;
 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 				data->bytes_per_pixel[num_displays + 4] = 8;
 				break;
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index d4df4da5b81a..0e18df1283b6 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -236,6 +236,7 @@ static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format for
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 		return dcn_bw_rgb_sub_32;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 		return dcn_bw_rgb_sub_64;
@@ -375,6 +376,7 @@ static void pipe_ctx_to_e2e_pipe_params (
 		input->src.viewport_height_c   = input->src.viewport_height / 2;
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 		input->src.source_format = dm_444_64;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index ff96bee57bfc..7fa0b007a7ea 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -135,4 +135,13 @@ endif
 AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)
+
+###############################################################################
+# DCN31
+###############################################################################
+CLK_MGR_DCN31 = dcn31_smu.o dcn31_clk_mgr.o
+
+AMD_DAL_CLK_MGR_DCN31 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn31/,$(CLK_MGR_DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31)
 endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 7d6c68c5dea9..bb31541f8072 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -41,6 +41,7 @@
 #include "dcn21/rn_clk_mgr.h"
 #include "dcn30/dcn30_clk_mgr.h"
 #include "dcn301/vg_clk_mgr.h"
+#include "dcn31/dcn31_clk_mgr.h"
 
 
 int clk_mgr_helper_get_active_display_cnt(
@@ -90,15 +91,20 @@ void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_m
 	struct dc_link *edp_links[MAX_NUM_EDP];
 	struct dc_link *edp_link = NULL;
 	int edp_num;
+	unsigned int panel_inst;
 
 	get_edp_links(dc, edp_links, &edp_num);
 	if (dc->hwss.exit_optimized_pwr_state)
 		dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
 
 	if (edp_num) {
-		edp_link = edp_links[0];
-		clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
-		dc_link_set_psr_allow_active(edp_link, false, false, false);
+		for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
+			edp_link = edp_links[panel_inst];
+			if (!edp_link->psr_settings.psr_feature_enabled)
+				continue;
+			clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
+			dc_link_set_psr_allow_active(edp_link, false, false, false);
+		}
 	}
 
 }
@@ -108,12 +114,17 @@ void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
 	struct dc_link *edp_links[MAX_NUM_EDP];
 	struct dc_link *edp_link = NULL;
 	int edp_num;
+	unsigned int panel_inst;
 
 	get_edp_links(dc, edp_links, &edp_num);
 	if (edp_num) {
-		edp_link = edp_links[0];
-		dc_link_set_psr_allow_active(edp_link,
-				clk_mgr->psr_allow_active_cache, false, false);
+		for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
+			edp_link = edp_links[panel_inst];
+			if (!edp_link->psr_settings.psr_feature_enabled)
+				continue;
+			dc_link_set_psr_allow_active(edp_link,
+					clk_mgr->psr_allow_active_cache, false, false);
+		}
 	}
 
 	if (dc->hwss.optimize_pwr_state)
@@ -241,6 +252,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 			return &clk_mgr->base;
 		}
+		if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {
+			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+			return &clk_mgr->base;
+		}
 		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 		return &clk_mgr->base;
 	}
@@ -256,7 +271,24 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 			return &clk_mgr->base.base;
 		}
 		break;
+	case FAMILY_YELLOW_CARP: {
+		struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
+
+		if (clk_mgr == NULL) {
+			BREAK_TO_DEBUGGER();
+			return NULL;
+		}
+		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) {
+			/* TODO: to add DCN31 clk_mgr support, once CLK IP header files are available,
+			 * for now use DCN3.0 clk mgr.
+			 */
+			dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+			return &clk_mgr->base.base;
+		}
+		return &clk_mgr->base.base;
+	}
 #endif
+
 	default:
 		ASSERT(0); /* Unknown Asic */
 		break;
@@ -278,6 +310,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 		if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
 			dcn3_clk_mgr_destroy(clk_mgr);
 		}
+		if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
+			dcn3_clk_mgr_destroy(clk_mgr);
+		}
 		break;
 
 	case FAMILY_VGH:
@@ -285,6 +320,11 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 			vg_clk_mgr_destroy(clk_mgr);
 		break;
 
+	case FAMILY_YELLOW_CARP:
+		if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev))
+			dcn31_clk_mgr_destroy(clk_mgr);
+		break;
+
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 372d53b5a34d..6e0c5c664fdc 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -123,7 +123,7 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 	}
 }
 
-void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
+void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)
 {
 	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
@@ -132,6 +132,68 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
 
 	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
 	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+	uint32_t current_dispclk_wdivider;
+	uint32_t i;
+
+	REG_GET(DENTIST_DISPCLK_CNTL,
+			DENTIST_DISPCLK_WDIVIDER, &current_dispclk_wdivider);
+
+	/* When changing divider to or from 127, some extra programming is required to prevent corruption */
+	if (current_dispclk_wdivider == 127 && dispclk_wdivider != 127) {
+		for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+			uint32_t fifo_level;
+			struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
+			struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
+			int32_t N;
+			int32_t j;
+
+			if (!pipe_ctx->stream)
+				continue;
+			/* Virtual encoders don't have this function */
+			if (!stream_enc->funcs->get_fifo_cal_average_level)
+				continue;
+			fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
+					stream_enc);
+			N = fifo_level / 4;
+			dccg->funcs->set_fifo_errdet_ovr_en(
+					dccg,
+					true);
+			for (j = 0; j < N - 4; j++)
+				dccg->funcs->otg_drop_pixel(
+						dccg,
+						pipe_ctx->stream_res.tg->inst);
+			dccg->funcs->set_fifo_errdet_ovr_en(
+					dccg,
+					false);
+		}
+	} else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) {
+		REG_UPDATE(DENTIST_DISPCLK_CNTL,
+				DENTIST_DISPCLK_WDIVIDER, 126);
+		REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 100);
+		for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+			struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
+			struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
+			uint32_t fifo_level;
+			int32_t N;
+			int32_t j;
+
+			if (!pipe_ctx->stream)
+				continue;
+			/* Virtual encoders don't have this function */
+			if (!stream_enc->funcs->get_fifo_cal_average_level)
+				continue;
+			fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
+					stream_enc);
+			N = fifo_level / 4;
+			dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
+			for (j = 0; j < 12 - N; j++)
+				dccg->funcs->otg_add_pixel(dccg,
+						pipe_ctx->stream_res.tg->inst);
+			dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
+		}
+	}
 
 	REG_UPDATE(DENTIST_DISPCLK_CNTL,
 			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
@@ -251,11 +313,11 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
 		if (dpp_clock_lowered) {
 			// if clock is being lowered, increase DTO before lowering refclk
 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
-			dcn20_update_clocks_update_dentist(clk_mgr);
+			dcn20_update_clocks_update_dentist(clk_mgr, context);
 		} else {
 			// if clock is being raised, increase refclk before lowering DTO
 			if (update_dppclk || update_dispclk)
-				dcn20_update_clocks_update_dentist(clk_mgr);
+				dcn20_update_clocks_update_dentist(clk_mgr, context);
 			// always update dtos unless clock is lowered and not safe to lower
 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 		}
@@ -324,6 +386,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
 	// Both fclk and ref_dppclk run on the same scemi clock.
 	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
 
+	/* TODO: set dtbclk in correct place */
+	clk_mgr->clks.dtbclk_en = false;
 	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
index 0b9c045b0c8e..d254d0b6fba1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
@@ -50,7 +50,8 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr,
 			enum dc_clock_type clock_type,
 			struct dc_clock_config *clock_cfg);
 
-void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr);
+void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,
+					struct dc_state *context);
 
 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index a06e86853bb9..c6f494f0dcea 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -106,10 +106,10 @@ static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
 		int dpp_inst, dppclk_khz, prev_dppclk_khz;
 
-		/* Loop index will match dpp->inst if resource exists,
-		 * and we want to avoid dependency on dpp object
+		/* Loop index may not match dpp->inst if some pipes disabled,
+		 * so select correct inst from res_pool
 		 */
-		dpp_inst = i;
+		dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;
 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 
 		prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
@@ -128,7 +128,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 	struct dc *dc = clk_mgr_base->ctx->dc;
-	int display_count, i;
+	int display_count;
 	bool update_dppclk = false;
 	bool update_dispclk = false;
 	bool dpp_clock_lowered = false;
@@ -210,14 +210,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 				clk_mgr_base->clks.dppclk_khz,
 				safe_to_lower);
 
-		for (i = 0; i < context->stream_count; i++) {
-			if (context->streams[i]->signal == SIGNAL_TYPE_EDP &&
-				context->streams[i]->apply_seamless_boot_optimization) {
-				dc_wait_for_vblank(dc, context->streams[i]);
-				break;
-			}
-		}
-
 		clk_mgr_base->clks.actual_dppclk_khz =
 				rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 
@@ -842,6 +834,7 @@ static struct wm_table lpddr4_wm_table_rn = {
 		},
 	}
 };
+
 static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 {
 	int i;
@@ -854,6 +847,7 @@ static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsi
 	ASSERT(0);
 	return 0;
 }
+
 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 {
 	int i;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 652fa89fae5f..513676a6f52b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -334,11 +334,11 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
 		if (dpp_clock_lowered) {
 			/* if clock is being lowered, increase DTO before lowering refclk */
 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
-			dcn20_update_clocks_update_dentist(clk_mgr);
+			dcn20_update_clocks_update_dentist(clk_mgr, context);
 		} else {
 			/* if clock is being raised, increase refclk before lowering DTO */
 			if (update_dppclk || update_dispclk)
-				dcn20_update_clocks_update_dentist(clk_mgr);
+				dcn20_update_clocks_update_dentist(clk_mgr, context);
 			/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
 			 * that we do not lower dto when it is not safe to lower. We do not need to
 			 * compare the current and new dppclk before calling this function.*/
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
new file mode 100644
index 000000000000..7b7d884d58be
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -0,0 +1,673 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+
+// For dce12_get_dp_ref_freq_khz
+#include "dce100/dce_clk_mgr.h"
+
+// For dcn20_update_clocks_update_dpp_dto
+#include "dcn20/dcn20_clk_mgr.h"
+
+
+
+#include "dcn31_clk_mgr.h"
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn31_smu.h"
+#include "dm_helpers.h"
+
+/* TODO: remove this include once we ported over remaining clk mgr functions*/
+#include "dcn30/dcn30_clk_mgr.h"
+
+#include "dc_dmub_srv.h"
+
+#define TO_CLK_MGR_DCN31(clk_mgr)\
+	container_of(clk_mgr, struct clk_mgr_dcn31, base)
+
+int dcn31_get_active_display_cnt_wa(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	int i, display_count;
+	bool tmds_present = false;
+
+	display_count = 0;
+	for (i = 0; i < context->stream_count; i++) {
+		const struct dc_stream_state *stream = context->streams[i];
+
+		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+			tmds_present = true;
+	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		const struct dc_link *link = dc->links[i];
+
+		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
+		if (link->link_enc->funcs->is_dig_enabled &&
+				link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			display_count++;
+	}
+
+	/* WA for hang on HDMI after display off back back on*/
+	if (display_count == 0 && tmds_present)
+		display_count = 1;
+
+	return display_count;
+}
+
+static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
+{
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+		if (pipe->top_pipe || pipe->prev_odm_pipe)
+			continue;
+		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
+			if (disable)
+				pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
+			else
+				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+		}
+	}
+}
+
+static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
+			struct dc_state *context,
+			bool safe_to_lower)
+{
+	union dmub_rb_cmd cmd;
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	int display_count;
+	bool update_dppclk = false;
+	bool update_dispclk = false;
+	bool dpp_clock_lowered = false;
+
+	if (dc->work_arounds.skip_clock_update)
+		return;
+
+	/*
+	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
+	 * also if safe to lower is false, we just go in the higher state
+	 */
+	if (safe_to_lower) {
+		if (new_clocks->z9_support == DCN_Z9_SUPPORT_ALLOW &&
+				new_clocks->z9_support != clk_mgr_base->clks.z9_support) {
+			dcn31_smu_set_Z9_support(clk_mgr, true);
+			clk_mgr_base->clks.z9_support = new_clocks->z9_support;
+		}
+
+		if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
+			dcn31_smu_set_dtbclk(clk_mgr, false);
+			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
+		}
+		/* check that we're not already in lower */
+		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+			display_count = dcn31_get_active_display_cnt_wa(dc, context);
+			/* if we can go lower, go lower */
+			if (display_count == 0) {
+				union display_idle_optimization_u idle_info = { 0 };
+				idle_info.idle_info.df_request_disabled = 1;
+				idle_info.idle_info.phy_ref_clk_off = 1;
+				dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+				/* update power state */
+				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+			}
+		}
+	} else {
+		if (new_clocks->z9_support == DCN_Z9_SUPPORT_DISALLOW &&
+				new_clocks->z9_support != clk_mgr_base->clks.z9_support) {
+			dcn31_smu_set_Z9_support(clk_mgr, false);
+			clk_mgr_base->clks.z9_support = new_clocks->z9_support;
+		}
+
+		if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
+			dcn31_smu_set_dtbclk(clk_mgr, true);
+			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
+		}
+
+		/* check that we're not already in D0 */
+		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
+			union display_idle_optimization_u idle_info = { 0 };
+			dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+			/* update power state */
+			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
+		}
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
+		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
+		dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
+	}
+
+	if (should_set_clock(safe_to_lower,
+			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
+		dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
+	}
+
+	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
+	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+		if (new_clocks->dppclk_khz < 100000)
+			new_clocks->dppclk_khz = 100000;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
+		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
+			dpp_clock_lowered = true;
+		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
+		update_dppclk = true;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+		dcn31_disable_otg_wa(clk_mgr_base, true);
+
+		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+		dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+		dcn31_disable_otg_wa(clk_mgr_base, false);
+
+		update_dispclk = true;
+	}
+
+	/* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/
+	if (dpp_clock_lowered) {
+		// increase per DPP DTO before lowering global dppclk
+		dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+	} else {
+		// increase global DPPCLK before lowering per DPP DTO
+		if (update_dppclk || update_dispclk)
+			dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+	}
+
+	// notify DMCUB of latest clocks
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
+	cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
+	cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
+	cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
+		clk_mgr_base->clks.dcfclk_deep_sleep_khz;
+	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
+	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
+
+	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+}
+
+static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
+{
+	return 0;
+}
+
+static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	dcn31_smu_enable_pme_wa(clk_mgr);
+}
+
+static void dcn31_init_clocks(struct clk_mgr *clk_mgr)
+{
+	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
+	// Assumption is that boot state always supports pstate
+	clk_mgr->clks.p_state_change_support = true;
+	clk_mgr->clks.prev_p_state_change_support = true;
+	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+	clk_mgr->clks.z9_support = DCN_Z9_SUPPORT_UNKNOWN;
+}
+
+static bool dcn31_are_clock_states_equal(struct dc_clocks *a,
+		struct dc_clocks *b)
+{
+	if (a->dispclk_khz != b->dispclk_khz)
+		return false;
+	else if (a->dppclk_khz != b->dppclk_khz)
+		return false;
+	else if (a->dcfclk_khz != b->dcfclk_khz)
+		return false;
+	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
+		return false;
+	else if (a->z9_support != b->z9_support)
+		return false;
+	else if (a->dtbclk_en != b->dtbclk_en)
+		return false;
+
+	return true;
+}
+
+static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
+{
+	return;
+}
+
+static struct clk_bw_params dcn31_bw_params = {
+	.vram_type = Ddr4MemType,
+	.num_channels = 1,
+	.clk_table = {
+		.num_entries = 4,
+	},
+
+};
+
+static struct wm_table ddr4_wm_table = {
+	.entries = {
+		{
+			.wm_inst = WM_A,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 6.09,
+			.sr_enter_plus_exit_time_us = 7.14,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_B,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_C,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_D,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+	}
+};
+
+static struct wm_table lpddr5_wm_table = {
+	.entries = {
+		{
+			.wm_inst = WM_A,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 5.32,
+			.sr_enter_plus_exit_time_us = 6.38,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_B,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.82,
+			.sr_enter_plus_exit_time_us = 11.196,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_C,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.89,
+			.sr_enter_plus_exit_time_us = 11.24,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_D,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.748,
+			.sr_enter_plus_exit_time_us = 11.102,
+			.valid = true,
+		},
+	}
+};
+
+static DpmClocks_t dummy_clocks;
+
+static struct dcn31_watermarks dummy_wms = { 0 };
+
+static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
+{
+	int i, num_valid_sets;
+
+	num_valid_sets = 0;
+
+	for (i = 0; i < WM_SET_COUNT; i++) {
+		/* skip empty entries, the smu array has no holes*/
+		if (!bw_params->wm_table.entries[i].valid)
+			continue;
+
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+		/* We will not select WM based on fclk, so leave it as unconstrained */
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+		if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
+			if (i == 0)
+				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
+			else {
+				/* add 1 to make it non-overlapping with next lvl */
+				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
+						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+			}
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
+					bw_params->clk_table.entries[i].dcfclk_mhz;
+
+		} else {
+			/* unconstrained for memory retraining */
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+			/* Modify previous watermark range to cover up to max */
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+		}
+		num_valid_sets++;
+	}
+
+	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
+
+	/* modify the min and max to make sure we cover the whole range*/
+	table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
+	table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
+	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
+	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+
+	/* This is for writeback only, does not matter currently as no writeback support*/
+	table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
+	table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
+	table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
+	table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
+	table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
+}
+
+static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
+	struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
+
+	if (!clk_mgr->smu_ver)
+		return;
+
+	if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
+
+	dcn31_smu_set_dram_addr_high(clk_mgr,
+			clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
+	dcn31_smu_set_dram_addr_low(clk_mgr,
+			clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
+	dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
+}
+
+static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
+		struct dcn31_smu_dpm_clks *smu_dpm_clks)
+{
+	DpmClocks_t *table = smu_dpm_clks->dpm_clks;
+
+	if (!clk_mgr->smu_ver)
+		return;
+
+	if (!table || smu_dpm_clks->mc_address.quad_part == 0)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	dcn31_smu_set_dram_addr_high(clk_mgr,
+			smu_dpm_clks->mc_address.high_part);
+	dcn31_smu_set_dram_addr_low(clk_mgr,
+			smu_dpm_clks->mc_address.low_part);
+	dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
+}
+
+static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
+{
+	uint32_t max = 0;
+	int i;
+
+	for (i = 0; i < num_clocks; ++i) {
+		if (clocks[i] > max)
+			max = clocks[i];
+	}
+
+	return max;
+}
+
+static unsigned int find_clk_for_voltage(
+		const DpmClocks_t *clock_table,
+		const uint32_t clocks[],
+		unsigned int voltage)
+{
+	int i;
+
+	for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
+		if (clock_table->SocVoltage[i] == voltage)
+			return clocks[i];
+	}
+
+	ASSERT(0);
+	return 0;
+}
+
+void dcn31_clk_mgr_helper_populate_bw_params(
+		struct clk_mgr_internal *clk_mgr,
+		struct integrated_info *bios_info,
+		const DpmClocks_t *clock_table)
+{
+	int i, j;
+	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
+	uint32_t max_dispclk = 0, max_dppclk = 0;
+
+	j = -1;
+
+	ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
+
+	/* Find lowest DPM, FCLK is filled in reverse order*/
+
+	for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
+		if (clock_table->DfPstateTable[i].FClk != 0) {
+			j = i;
+			break;
+		}
+	}
+
+	if (j == -1) {
+		/* clock table is all 0s, just use our own hardcode */
+		ASSERT(0);
+		return;
+	}
+
+	bw_params->clk_table.num_entries = j + 1;
+
+	/* dispclk and dppclk can be max at any voltage, same number of levels for both */
+	if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
+	    clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
+		max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
+		max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
+	} else {
+		ASSERT(0);
+	}
+
+	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
+		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
+		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
+		switch (clock_table->DfPstateTable[j].WckRatio) {
+		case WCK_RATIO_1_2:
+			bw_params->clk_table.entries[i].wck_ratio = 2;
+			break;
+		case WCK_RATIO_1_4:
+			bw_params->clk_table.entries[i].wck_ratio = 4;
+			break;
+		default:
+			bw_params->clk_table.entries[i].wck_ratio = 1;
+		}
+		bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
+		bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
+		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
+		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
+	}
+
+	bw_params->vram_type = bios_info->memory_type;
+	bw_params->num_channels = bios_info->ma_channel_number;
+
+	for (i = 0; i < WM_SET_COUNT; i++) {
+		bw_params->wm_table.entries[i].wm_inst = i;
+
+		if (i >= bw_params->clk_table.num_entries) {
+			bw_params->wm_table.entries[i].valid = false;
+			continue;
+		}
+
+		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
+		bw_params->wm_table.entries[i].valid = true;
+	}
+}
+
+static struct clk_mgr_funcs dcn31_funcs = {
+	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+	.update_clocks = dcn31_update_clocks,
+	.init_clocks = dcn31_init_clocks,
+	.enable_pme_wa = dcn31_enable_pme_wa,
+	.are_clock_states_equal = dcn31_are_clock_states_equal,
+	.notify_wm_ranges = dcn31_notify_wm_ranges
+};
+extern struct clk_mgr_funcs dcn3_fpga_funcs;
+
+void dcn31_clk_mgr_construct(
+		struct dc_context *ctx,
+		struct clk_mgr_dcn31 *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg)
+{
+	struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
+
+	clk_mgr->base.base.ctx = ctx;
+	clk_mgr->base.base.funcs = &dcn31_funcs;
+
+	clk_mgr->base.pp_smu = pp_smu;
+
+	clk_mgr->base.dccg = dccg;
+	clk_mgr->base.dfs_bypass_disp_clk = 0;
+
+	clk_mgr->base.dprefclk_ss_percentage = 0;
+	clk_mgr->base.dprefclk_ss_divider = 1000;
+	clk_mgr->base.ss_on_dprefclk = false;
+
+	clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
+				clk_mgr->base.base.ctx,
+				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				sizeof(struct dcn31_watermarks),
+				&clk_mgr->smu_wm_set.mc_address.quad_part);
+
+	if (clk_mgr->smu_wm_set.wm_set == 0) {
+		clk_mgr->smu_wm_set.wm_set = &dummy_wms;
+		clk_mgr->smu_wm_set.mc_address.quad_part = 0;
+	}
+	ASSERT(clk_mgr->smu_wm_set.wm_set);
+
+	smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
+				clk_mgr->base.base.ctx,
+				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				sizeof(DpmClocks_t),
+				&smu_dpm_clks.mc_address.quad_part);
+
+	if (smu_dpm_clks.dpm_clks == NULL) {
+		smu_dpm_clks.dpm_clks = &dummy_clocks;
+		smu_dpm_clks.mc_address.quad_part = 0;
+	}
+
+	ASSERT(smu_dpm_clks.dpm_clks);
+
+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+		clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
+	} else {
+		struct clk_log_info log_info = {0};
+
+		clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
+
+		if (clk_mgr->base.smu_ver)
+			clk_mgr->base.smu_present = true;
+
+		/* TODO: Check we get what we expect during bringup */
+		clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
+
+		if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
+			dcn31_bw_params.wm_table = lpddr5_wm_table;
+		} else {
+			dcn31_bw_params.wm_table = ddr4_wm_table;
+		}
+		/* Saved clocks configured at boot for debug purposes */
+		 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
+
+	}
+
+	clk_mgr->base.base.dprefclk_khz = 600000;
+	clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
+	dce_clock_read_ss_info(&clk_mgr->base);
+
+	clk_mgr->base.base.bw_params = &dcn31_bw_params;
+
+	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
+		dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
+
+		if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+			dcn31_clk_mgr_helper_populate_bw_params(
+					&clk_mgr->base,
+					ctx->dc_bios->integrated_info,
+					smu_dpm_clks.dpm_clks);
+		}
+	}
+
+	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
+		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				smu_dpm_clks.dpm_clks);
+}
+
+void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
+{
+	struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
+
+	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
+		dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				clk_mgr->smu_wm_set.wm_set);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h
new file mode 100644
index 000000000000..cc21cf75eafd
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN31_CLK_MGR_H__
+#define __DCN31_CLK_MGR_H__
+#include "clk_mgr_internal.h"
+
+//CLK1_CLK_PLL_REQ
+#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
+//CLK1_CLK0_DFS_CNTL
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT                                                               0x0
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK                                                                 0x0000007FL
+/*DPREF clock related*/
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+
+//CLK3_0_CLK3_CLK_PLL_REQ
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                           0xc
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK                                                             0x0000F000L
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+
+#define mmCLK0_CLK3_DFS_CNTL                            0x16C60
+#define mmCLK00_CLK0_CLK3_DFS_CNTL                      0x16C60
+#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E60
+#define mmCLK02_CLK0_CLK3_DFS_CNTL                      0x17060
+#define mmCLK03_CLK0_CLK3_DFS_CNTL                      0x17260
+
+#define mmCLK0_CLK_PLL_REQ                              0x16C10
+#define mmCLK00_CLK0_CLK_PLL_REQ                        0x16C10
+#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E10
+#define mmCLK02_CLK0_CLK_PLL_REQ                        0x17010
+#define mmCLK03_CLK0_CLK_PLL_REQ                        0x17210
+
+#define mmCLK1_CLK_PLL_REQ                              0x1B00D
+#define mmCLK10_CLK1_CLK_PLL_REQ                        0x1B00D
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+#define mmCLK12_CLK1_CLK_PLL_REQ                        0x1B40D
+#define mmCLK13_CLK1_CLK_PLL_REQ                        0x1B60D
+
+#define mmCLK2_CLK_PLL_REQ                              0x17E0D
+
+/*AMCLK*/
+#define mmCLK11_CLK1_CLK0_DFS_CNTL                      0x1B23F
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+#endif
+
+struct dcn31_watermarks;
+
+struct dcn31_smu_watermark_set {
+	struct dcn31_watermarks *wm_set;
+	union large_integer mc_address;
+};
+
+struct clk_mgr_dcn31 {
+	struct clk_mgr_internal base;
+	struct dcn31_smu_watermark_set smu_wm_set;
+};
+
+void dcn31_clk_mgr_construct(struct dc_context *ctx,
+		struct clk_mgr_dcn31 *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg);
+
+void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
+
+#endif //__DCN31_CLK_MGR_H__
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
new file mode 100644
index 000000000000..66db5e988bc1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include <linux/delay.h>
+#include "core_types.h"
+#include "clk_mgr_internal.h"
+#include "reg_helper.h"
+#include "dm_helpers.h"
+#include "dcn31_smu.h"
+
+#include "yellow_carp_offset.h"
+#include "mp/mp_13_0_1_offset.h"
+#include "mp/mp_13_0_1_sh_mask.h"
+
+#define REG(reg_name) \
+	(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
+
+#define FN(reg_name, field) \
+	FD(reg_name##__##field)
+
+#define VBIOSSMC_MSG_TestMessage                  0x1
+#define VBIOSSMC_MSG_GetSmuVersion                0x2
+#define VBIOSSMC_MSG_PowerUpGfx                   0x3
+#define VBIOSSMC_MSG_SetDispclkFreq               0x4
+#define VBIOSSMC_MSG_SetDprefclkFreq              0x5   //Not used. DPRef is constant
+#define VBIOSSMC_MSG_SetDppclkFreq                0x6
+#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq       0x7
+#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk        0x8
+#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq       0x9	//Keep it in case VMIN dees not support phy clk
+#define VBIOSSMC_MSG_GetFclkFrequency             0xA
+#define VBIOSSMC_MSG_SetDisplayCount              0xB   //Not used anymore
+#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC   //Not used anymore
+#define VBIOSSMC_MSG_UpdatePmeRestore             0xD
+#define VBIOSSMC_MSG_SetVbiosDramAddrHigh         0xE   //Used for WM table txfr
+#define VBIOSSMC_MSG_SetVbiosDramAddrLow          0xF
+#define VBIOSSMC_MSG_TransferTableSmu2Dram        0x10
+#define VBIOSSMC_MSG_TransferTableDram2Smu        0x11
+#define VBIOSSMC_MSG_SetDisplayIdleOptimizations  0x12
+#define VBIOSSMC_MSG_GetDprefclkFreq              0x13
+#define VBIOSSMC_MSG_GetDtbclkFreq                0x14
+#define VBIOSSMC_MSG_AllowZstatesEntry            0x15
+#define VBIOSSMC_MSG_DisallowZstatesEntry     	  0x16
+#define VBIOSSMC_MSG_SetDtbClk                    0x17
+#define VBIOSSMC_Message_Count                    0x18
+
+#define VBIOSSMC_Status_BUSY                      0x0
+#define VBIOSSMC_Result_OK                        0x1
+#define VBIOSSMC_Result_Failed                    0xFF
+#define VBIOSSMC_Result_UnknownCmd                0xFE
+#define VBIOSSMC_Result_CmdRejectedPrereq         0xFD
+#define VBIOSSMC_Result_CmdRejectedBusy           0xFC
+
+/*
+ * Function to be used instead of REG_WAIT macro because the wait ends when
+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h
+ * won't work with REG_WAIT.
+ */
+static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
+{
+	uint32_t res_val = VBIOSSMC_Status_BUSY;
+
+	do {
+		res_val = REG_READ(MP1_SMN_C2PMSG_91);
+		if (res_val != VBIOSSMC_Status_BUSY)
+			break;
+
+		if (delay_us >= 1000)
+			msleep(delay_us/1000);
+		else if (delay_us > 0)
+			udelay(delay_us);
+	} while (max_retries--);
+
+	return res_val;
+}
+
+int dcn31_smu_send_msg_with_param(
+		struct clk_mgr_internal *clk_mgr,
+		unsigned int msg_id, unsigned int param)
+{
+	uint32_t result;
+
+	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
+	ASSERT(result == VBIOSSMC_Result_OK);
+
+	if (result == VBIOSSMC_Status_BUSY) {
+		return -1;
+	}
+
+	/* First clear response register */
+	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
+
+	/* Set the parameter register for the SMU message, unit is Mhz */
+	REG_WRITE(MP1_SMN_C2PMSG_83, param);
+
+	/* Trigger the message transaction by writing the message ID */
+	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
+
+	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
+
+	if (IS_SMU_TIMEOUT(result)) {
+		ASSERT(0);
+		dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
+	}
+
+	return REG_READ(MP1_SMN_C2PMSG_83);
+}
+
+int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
+{
+	return dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_GetSmuVersion,
+			0);
+}
+
+
+int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+{
+	int actual_dispclk_set_mhz = -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_dispclk_khz;
+
+	/*  Unit of SMU msg parameter is Mhz */
+	actual_dispclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDispclkFreq,
+			(requested_dispclk_khz + 999) / 1000);
+
+	return actual_dispclk_set_mhz * 1000;
+}
+
+int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
+{
+	int actual_dprefclk_set_mhz = -1;
+
+	if (!clk_mgr->smu_present)
+		return clk_mgr->base.dprefclk_khz;
+
+	actual_dprefclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDprefclkFreq,
+			(clk_mgr->base.dprefclk_khz + 999) / 1000);
+
+	/* TODO: add code for programing DP DTO, currently this is down by command table */
+
+	return actual_dprefclk_set_mhz * 1000;
+}
+
+int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
+{
+	int actual_dcfclk_set_mhz = -1;
+
+	if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
+		return -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_dcfclk_khz;
+
+	actual_dcfclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+			(requested_dcfclk_khz + 999) / 1000);
+
+	return actual_dcfclk_set_mhz * 1000;
+}
+
+int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
+{
+	int actual_min_ds_dcfclk_mhz = -1;
+
+	if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
+		return -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_min_ds_dcfclk_khz;
+
+	actual_min_ds_dcfclk_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
+			(requested_min_ds_dcfclk_khz + 999) / 1000);
+
+	return actual_min_ds_dcfclk_mhz * 1000;
+}
+
+int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
+{
+	int actual_dppclk_set_mhz = -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_dpp_khz;
+
+	actual_dppclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDppclkFreq,
+			(requested_dpp_khz + 999) / 1000);
+
+	return actual_dppclk_set_mhz * 1000;
+}
+
+void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
+{
+	if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
+		return;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	//TODO: Work with smu team to define optimization options.
+	dcn31_smu_send_msg_with_param(
+		clk_mgr,
+		VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+		idle_info);
+}
+
+void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+	union display_idle_optimization_u idle_info = { 0 };
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (enable) {
+		idle_info.idle_info.df_request_disabled = 1;
+		idle_info.idle_info.phy_ref_clk_off = 1;
+	}
+
+	dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+			idle_info.data);
+}
+
+void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_UpdatePmeRestore,
+			0);
+}
+
+void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
+}
+
+void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
+}
+
+void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
+}
+
+void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
+}
+
+void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support)
+{
+	//TODO: Work with smu team to define optimization options.
+	unsigned int msg_id;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (support)
+		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
+	else
+		msg_id = VBIOSSMC_MSG_DisallowZstatesEntry;
+
+	dcn31_smu_send_msg_with_param(
+		clk_mgr,
+		msg_id,
+		0);
+
+}
+
+/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
+void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDtbClk,
+			enable);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h
new file mode 100644
index 000000000000..cd0b7e1e685f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DAL_DC_31_SMU_H_
+#define DAL_DC_31_SMU_H_
+
+#ifndef PMFW_DRIVER_IF_H
+#define PMFW_DRIVER_IF_H
+#define PMFW_DRIVER_IF_VERSION 4
+
+typedef struct {
+  int32_t value;
+  uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+  DSPCLK_DCFCLK = 0,
+  DSPCLK_DISPCLK,
+  DSPCLK_PIXCLK,
+  DSPCLK_PHYCLK,
+  DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+  uint16_t Freq; // in MHz
+  uint16_t Vid;  // min voltage in SVI3 VID
+} DisplayClockTable_t;
+
+typedef struct {
+  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MinMclk;
+  uint16_t MaxMclk;
+
+  uint8_t  WmSetting;
+  uint8_t  WmType;  // Used for normal pstate change or memory retraining
+  uint8_t  Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+  WM_SOCCLK = 0,
+  WM_DCFCLK,
+  WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+  uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+  CUSTOM_DPM_SETTING_GFXCLK,
+  CUSTOM_DPM_SETTING_CCLK,
+  CUSTOM_DPM_SETTING_FCLK_CCX,
+  CUSTOM_DPM_SETTING_FCLK_GFX,
+  CUSTOM_DPM_SETTING_FCLK_STALLS,
+  CUSTOM_DPM_SETTING_LCLK,
+  CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+  uint8_t             ActiveHystLimit;
+  uint8_t             IdleHystLimit;
+  uint8_t             FPS;
+  uint8_t             MinActiveFreqType;
+  FloatInIntFormat_t  MinActiveFreq;
+  FloatInIntFormat_t  PD_Data_limit;
+  FloatInIntFormat_t  PD_Data_time_constant;
+  FloatInIntFormat_t  PD_Data_error_coeff;
+  FloatInIntFormat_t  PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_DCFCLK_DPM_LEVELS   8
+#define NUM_DISPCLK_DPM_LEVELS  8
+#define NUM_DPPCLK_DPM_LEVELS   8
+#define NUM_SOCCLK_DPM_LEVELS   8
+#define NUM_VCN_DPM_LEVELS      8
+#define NUM_SOC_VOLTAGE_LEVELS  8
+#define NUM_DF_PSTATE_LEVELS    4
+
+typedef enum{
+  WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
+  WCK_RATIO_1_2,
+  WCK_RATIO_1_4,
+  WCK_RATIO_MAX
+} WCK_RATIO_e;
+
+typedef struct {
+  uint32_t FClk;
+  uint32_t MemClk;
+  uint32_t Voltage;
+  uint8_t  WckRatio;
+  uint8_t  Spare[3];
+} DfPstateTable_t;
+
+//Freq in MHz
+//Voltage in milli volts with 2 fractional bits
+typedef struct {
+  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+  uint32_t VClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t DClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+  DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
+
+  uint8_t  NumDcfClkLevelsEnabled;
+  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
+  uint8_t  NumSocClkLevelsEnabled;
+  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
+  uint8_t  NumDfPstatesEnabled;
+  uint8_t  spare[3];
+
+  uint32_t MinGfxClk;
+  uint32_t MaxGfxClk;
+} DpmClocks_t;
+
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL            0
+#define THROTTLER_STATUS_BIT_FPPT           1
+#define THROTTLER_STATUS_BIT_SPPT           2
+#define THROTTLER_STATUS_BIT_SPPT_APU       3
+#define THROTTLER_STATUS_BIT_THM_CORE       4
+#define THROTTLER_STATUS_BIT_THM_GFX        5
+#define THROTTLER_STATUS_BIT_THM_SOC        6
+#define THROTTLER_STATUS_BIT_TDC_VDD        7
+#define THROTTLER_STATUS_BIT_TDC_SOC        8
+#define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
+#define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
+#define THROTTLER_STATUS_BIT_EDC_CPU       11
+#define THROTTLER_STATUS_BIT_EDC_GFX       12
+
+typedef struct {
+  uint16_t GfxclkFrequency;             //[MHz]
+  uint16_t SocclkFrequency;             //[MHz]
+  uint16_t VclkFrequency;               //[MHz]
+  uint16_t DclkFrequency;               //[MHz]
+  uint16_t MemclkFrequency;             //[MHz]
+  uint16_t spare;
+
+  uint16_t GfxActivity;                 //[centi]
+  uint16_t UvdActivity;                 //[centi]
+
+  uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
+
+  //3rd party tools in Windows need this info in the case of APUs
+  uint16_t CoreFrequency[8];            //[MHz]
+  uint16_t CorePower[8];                //[mW]
+  uint16_t CoreTemperature[8];          //[centi-Celsius]
+  uint16_t L3Frequency;                 //[MHz]
+  uint16_t L3Temperature;               //[centi-Celsius]
+
+  uint16_t GfxTemperature;              //[centi-Celsius]
+  uint16_t SocTemperature;              //[centi-Celsius]
+  uint16_t ThrottlerStatus;
+
+  uint16_t CurrentSocketPower;          //[mW]
+  uint16_t StapmOriginalLimit;          //[W]
+  uint16_t StapmCurrentLimit;           //[W]
+  uint16_t ApuPower;                    //[W]
+  uint16_t dGpuPower;                   //[W]
+
+  uint16_t VddTdcValue;                 //[mA]
+  uint16_t SocTdcValue;                 //[mA]
+  uint16_t VddEdcValue;                 //[mA]
+  uint16_t SocEdcValue;                 //[mA]
+
+  uint16_t InfrastructureCpuMaxFreq;    //[MHz]
+  uint16_t InfrastructureGfxMaxFreq;    //[MHz]
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT          2
+#define WORKLOAD_PPLIB_VR_BIT             3
+#define WORKLOAD_PPLIB_COMPUTE_BIT        4
+#define WORKLOAD_PPLIB_CUSTOM_BIT         5
+#define WORKLOAD_PPLIB_COUNT              6
+
+#define TABLE_BIOS_IF            0 // Called by BIOS
+#define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM         2 // Called by Driver
+#define TABLE_SPARE1             3
+#define TABLE_DPMCLOCKS          4 // Called by Driver
+#define TABLE_MOMENTARY_PM       5 // Called by Tools
+#define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS        7 // Called by Driver
+#define TABLE_COUNT              8
+
+#endif
+
+struct dcn31_watermarks {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+  uint32_t MmHubPadding[7]; // SMU internal use
+};
+
+struct dcn31_smu_dpm_clks {
+	DpmClocks_t *dpm_clks;
+	union large_integer mc_address;
+};
+
+/* TODO: taken from vgh, may not be correct */
+struct display_idle_optimization {
+	unsigned int df_request_disabled : 1;
+	unsigned int phy_ref_clk_off     : 1;
+	unsigned int s0i2_rdy            : 1;
+	unsigned int reserved            : 29;
+};
+
+union display_idle_optimization_u {
+	struct display_idle_optimization idle_info;
+	uint32_t data;
+};
+
+int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
+int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
+int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
+int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
+int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
+int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
+void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
+void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
+void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
+void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
+void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
+void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
+void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+
+void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support);
+void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
+
+#endif /* DAL_DC_31_SMU_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4713f09bcbf1..605e297b7a59 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -59,7 +59,6 @@
 #include "dc_link_ddc.h"
 #include "dm_helpers.h"
 #include "mem_input.h"
-#include "hubp.h"
 
 #include "dc_link_dp.h"
 #include "dc_dmub_srv.h"
@@ -304,7 +303,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 		struct dc_stream_state *stream,
 		struct dc_crtc_timing_adjust *adjust)
 {
-	int i = 0;
+	int i;
 	bool ret = false;
 
 	stream->adjust.v_total_max = adjust->v_total_max;
@@ -326,13 +325,55 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 	return ret;
 }
 
+/**
+ *****************************************************************************
+ *  Function: dc_stream_get_last_vrr_vtotal
+ *
+ *  @brief
+ *     Looks up the pipe context of dc_stream_state and gets the
+ *     last VTOTAL used by DRR (Dynamic Refresh Rate)
+ *
+ *  @param [in] dc: dc reference
+ *  @param [in] stream: Initial dc stream state
+ *  @param [in] adjust: Updated parameters for vertical_total_min and
+ *  vertical_total_max
+ *****************************************************************************
+ */
+bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
+		struct dc_stream_state *stream,
+		uint32_t *refresh_rate)
+{
+	bool status = false;
+
+	int i = 0;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+		if (pipe->stream == stream && pipe->stream_res.tg) {
+			/* Only execute if a function pointer has been defined for
+			 * the DC version in question
+			 */
+			if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
+				pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
+
+				status = true;
+
+				break;
+			}
+		}
+	}
+
+	return status;
+}
+
 bool dc_stream_get_crtc_position(struct dc *dc,
 		struct dc_stream_state **streams, int num_streams,
 		unsigned int *v_pos, unsigned int *nom_v_pos)
 {
 	/* TODO: Support multiple streams */
 	const struct dc_stream_state *stream = streams[0];
-	int i = 0;
+	int i;
 	bool ret = false;
 	struct crtc_position position;
 
@@ -539,7 +580,7 @@ void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 		enum dc_dynamic_expansion option)
 {
 	/* OPP FMT dyn expansion updates*/
-	int i = 0;
+	int i;
 	struct pipe_ctx *pipe_ctx;
 
 	for (i = 0; i < MAX_PIPES; i++) {
@@ -597,7 +638,7 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream,
 
 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 {
-	int i = 0;
+	int i;
 	bool ret = false;
 	struct pipe_ctx *pipes;
 
@@ -614,7 +655,7 @@ bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stre
 
 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 {
-	int i = 0;
+	int i;
 	bool ret = false;
 	struct pipe_ctx *pipes;
 
@@ -640,8 +681,7 @@ void dc_stream_set_static_screen_params(struct dc *dc,
 		int num_streams,
 		const struct dc_static_screen_params *params)
 {
-	int i = 0;
-	int j = 0;
+	int i, j;
 	struct pipe_ctx *pipes_affected[MAX_PIPES];
 	int num_pipes_affected = 0;
 
@@ -896,7 +936,7 @@ static void disable_all_writeback_pipes_for_stream(
 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
 					  struct dc_stream_state *stream, bool lock)
 {
-	int i = 0;
+	int i;
 
 	/* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 	if (dc->hwss.interdependent_update_lock)
@@ -1156,7 +1196,7 @@ static void enable_timing_multisync(
 		struct dc *dc,
 		struct dc_state *ctx)
 {
-	int i = 0, multisync_count = 0;
+	int i, multisync_count = 0;
 	int pipe_count = dc->res_pool->pipe_count;
 	struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 
@@ -1484,6 +1524,13 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
 	return stream_mask;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+void dc_z10_restore(struct dc *dc)
+{
+	if (dc->hwss.z10_restore)
+		dc->hwss.z10_restore(dc);
+}
+#endif
 /*
  * Applies given context to HW and copy it into current context.
  * It's up to the user to release the src context afterwards.
@@ -1497,6 +1544,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+	dc_z10_restore(dc);
 	dc_allow_idle_optimizations(dc, false);
 #endif
 
@@ -1919,8 +1967,13 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
 	if (u->plane_info->dcc.enable != u->surface->dcc.enable
 			|| u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
 			|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
+		/* During DCC on/off, stutter period is calculated before
+		 * DCC has fully transitioned. This results in incorrect
+		 * stutter period calculation. Triggering a full update will
+		 * recalculate stutter period.
+		 */
 		update_flags->bits.dcc_change = 1;
-		elevate_update_type(&update_type, UPDATE_TYPE_MED);
+		elevate_update_type(&update_type, UPDATE_TYPE_FULL);
 	}
 
 	if (resource_pixel_format_to_bpp(u->plane_info->format) !=
@@ -2571,6 +2624,10 @@ static void commit_planes_for_stream(struct dc *dc,
 	int i, j;
 	struct pipe_ctx *top_pipe_to_program = NULL;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	dc_z10_restore(dc);
+#endif
+
 	if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
 		/* Optimize seamless boot flag keeps clocks and watermarks high until
 		 * first flip. After first flip, optimization is required to lower
@@ -2664,7 +2721,6 @@ static void commit_planes_for_stream(struct dc *dc,
 			dc->hwss.interdependent_update_lock(dc, context, false);
 		else
 			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
-
 		dc->hwss.post_unlock_program_front_end(dc, context);
 		return;
 	}
@@ -2765,6 +2821,7 @@ static void commit_planes_for_stream(struct dc *dc,
 							plane_state->flip_immediate);
 				}
 			}
+
 		/* Perform requested Updates */
 		for (i = 0; i < surface_count; i++) {
 			struct dc_plane_state *plane_state = srf_updates[i].surface;
@@ -2787,6 +2844,7 @@ static void commit_planes_for_stream(struct dc *dc,
 					dc->hwss.update_plane_addr(dc, pipe_ctx);
 			}
 		}
+
 	}
 
 	if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
@@ -3025,6 +3083,9 @@ void dc_set_power_state(
 	case DC_ACPI_CM_POWER_STATE_D0:
 		dc_resource_state_construct(dc, dc->current_state);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		dc_z10_restore(dc);
+#endif
 		if (dc->ctx->dmub_srv)
 			dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
 
@@ -3219,19 +3280,6 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
 	}
 }
 
-void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream)
-{
-	int i;
-
-	for (i = 0; i < dc->res_pool->pipe_count; i++)
-		if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
-			struct timing_generator *tg =
-				dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
-			tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
-			break;
-		}
-}
-
 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
 {
 	info->displayClock				= (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
@@ -3270,10 +3318,13 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
 			continue;
 
 		if (link->psr_settings.psr_feature_enabled) {
-			if (enable && !link->psr_settings.psr_allow_active)
-				return dc_link_set_psr_allow_active(link, true, false, false);
-			else if (!enable && link->psr_settings.psr_allow_active)
-				return dc_link_set_psr_allow_active(link, false, true, false);
+			if (enable && !link->psr_settings.psr_allow_active) {
+				if (!dc_link_set_psr_allow_active(link, true, false, false))
+					return false;
+			} else if (!enable && link->psr_settings.psr_allow_active) {
+				if (!dc_link_set_psr_allow_active(link, false, true, false))
+					return false;
+			}
 		}
 	}
 
@@ -3287,7 +3338,7 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
 	if (dc->debug.disable_idle_power_optimizations)
 		return;
 
-	if (dc->clk_mgr->funcs->is_smu_present)
+	if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
 		if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
 			return;
 
@@ -3348,18 +3399,10 @@ void dc_hardware_release(struct dc *dc)
 #endif
 
 /**
- *****************************************************************************
- *  Function: dc_enable_dmub_notifications
+ * dc_enable_dmub_notifications - Returns whether dmub notification can be enabled
+ * @dc: dc structure
  *
- *  @brief
- *		Returns whether dmub notification can be enabled
- *
- *  @param
- *		[in] dc: dc structure
- *
- *	@return
- *		True to enable dmub notifications, False otherwise
- *****************************************************************************
+ * Returns: True to enable dmub notifications, False otherwise
  */
 bool dc_enable_dmub_notifications(struct dc *dc)
 {
@@ -3368,21 +3411,13 @@ bool dc_enable_dmub_notifications(struct dc *dc)
 }
 
 /**
- *****************************************************************************
- *  Function: dc_process_dmub_aux_transfer_async
+ * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
+ *                                      Sets port index appropriately for legacy DDC
+ * @dc: dc structure
+ * @link_index: link index
+ * @payload: aux payload
  *
- *  @brief
- *		Submits aux command to dmub via inbox message
- *		Sets port index appropriately for legacy DDC
- *
- *  @param
- *		[in] dc: dc structure
- *		[in] link_index: link index
- *		[in] payload: aux payload
- *
- *	@return
- *		True if successful, False if failure
- *****************************************************************************
+ * Returns: True if successful, False if failure
  */
 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
 				uint32_t link_index,
@@ -3441,16 +3476,8 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
 }
 
 /**
- *****************************************************************************
- *  Function: dc_disable_accelerated_mode
- *
- *  @brief
- *		disable accelerated mode
- *
- *  @param
- *		[in] dc: dc structure
- *
- *****************************************************************************
+ * dc_disable_accelerated_mode - disable accelerated mode
+ * @dc: dc structure
  */
 void dc_disable_accelerated_mode(struct dc *dc)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2a9080400bdd..9039fb134db5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -291,3 +291,136 @@ bool hwss_wait_for_blank_complete(
 
 	return true;
 }
+
+void get_mpctree_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	const struct tg_color pipe_colors[6] = {
+			{MAX_TG_COLOR_VALUE, 0, 0}, /* red */
+			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */
+			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
+			{0, MAX_TG_COLOR_VALUE, 0}, /* green */
+			{0, 0, MAX_TG_COLOR_VALUE}, /* blue */
+			{MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */
+	};
+
+	struct pipe_ctx *top_pipe = pipe_ctx;
+
+	while (top_pipe->top_pipe)
+		top_pipe = top_pipe->top_pipe;
+
+	*color = pipe_colors[top_pipe->pipe_idx];
+}
+
+void get_surface_visual_confirm_color(
+		const struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	uint32_t color_value = MAX_TG_COLOR_VALUE;
+
+	switch (pipe_ctx->plane_res.scl_data.format) {
+	case PIXEL_FORMAT_ARGB8888:
+		/* set border color to red */
+		color->color_r_cr = color_value;
+		if (pipe_ctx->plane_state->layer_index > 0) {
+			/* set border color to pink */
+			color->color_b_cb = color_value;
+			color->color_g_y = color_value * 0.5;
+		}
+		break;
+
+	case PIXEL_FORMAT_ARGB2101010:
+		/* set border color to blue */
+		color->color_b_cb = color_value;
+		if (pipe_ctx->plane_state->layer_index > 0) {
+			/* set border color to cyan */
+			color->color_g_y = color_value;
+		}
+		break;
+	case PIXEL_FORMAT_420BPP8:
+		/* set border color to green */
+		color->color_g_y = color_value;
+		break;
+	case PIXEL_FORMAT_420BPP10:
+		/* set border color to yellow */
+		color->color_g_y = color_value;
+		color->color_r_cr = color_value;
+		break;
+	case PIXEL_FORMAT_FP16:
+		/* set border color to white */
+		color->color_r_cr = color_value;
+		color->color_b_cb = color_value;
+		color->color_g_y = color_value;
+		if (pipe_ctx->plane_state->layer_index > 0) {
+			/* set border color to orange */
+			color->color_g_y = 0.22 * color_value;
+			color->color_b_cb = 0;
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void get_hdr_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	uint32_t color_value = MAX_TG_COLOR_VALUE;
+
+	/* Determine the overscan color based on the top-most (desktop) plane's context */
+	struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
+
+	while (top_pipe_ctx->top_pipe != NULL)
+		top_pipe_ctx = top_pipe_ctx->top_pipe;
+
+	switch (top_pipe_ctx->plane_res.scl_data.format) {
+	case PIXEL_FORMAT_ARGB2101010:
+		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
+			/* HDR10, ARGB2101010 - set border color to red */
+			color->color_r_cr = color_value;
+		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
+			/* FreeSync 2 ARGB2101010 - set border color to pink */
+			color->color_r_cr = color_value;
+			color->color_b_cb = color_value;
+		}
+		break;
+	case PIXEL_FORMAT_FP16:
+		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
+			/* HDR10, FP16 - set border color to blue */
+			color->color_b_cb = color_value;
+		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
+			/* FreeSync 2 HDR - set border color to green */
+			color->color_g_y = color_value;
+		}
+		break;
+	default:
+		/* SDR - set border color to Gray */
+		color->color_r_cr = color_value/2;
+		color->color_b_cb = color_value/2;
+		color->color_g_y = color_value/2;
+		break;
+	}
+}
+
+void get_surface_tile_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	uint32_t color_value = MAX_TG_COLOR_VALUE;
+	/* Determine the overscan color based on the bottom-most plane's context */
+	struct pipe_ctx *bottom_pipe_ctx  = pipe_ctx;
+
+	while (bottom_pipe_ctx->bottom_pipe != NULL)
+		bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
+
+	switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
+	case DC_SW_LINEAR:
+		/* LINEAR Surface - set border color to red */
+		color->color_r_cr = color_value;
+		break;
+	default:
+		break;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c1f5474c205a..6132b645bfd1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -48,6 +48,8 @@
 #include "dce/dmub_psr.h"
 #include "dmub/dmub_srv.h"
 #include "inc/hw/panel_cntl.h"
+#include "inc/link_enc_cfg.h"
+#include "inc/link_dpcd.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -58,20 +60,6 @@
 #define RETIMER_REDRIVER_INFO(...) \
 	DC_LOG_RETIMER_REDRIVER(  \
 		__VA_ARGS__)
-/*******************************************************************************
- * Private structures
- ******************************************************************************/
-
-enum {
-	PEAK_FACTOR_X1000 = 1006,
-	/*
-	 * Some receivers fail to train on first try and are good
-	 * on subsequent tries. 2 retries should be plenty. If we
-	 * don't have a successful training then we don't expect to
-	 * ever get one.
-	 */
-	LINK_TRAINING_MAX_VERIFY_RETRY = 2
-};
 
 /*******************************************************************************
  * Private functions
@@ -247,6 +235,16 @@ bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
+	/* Link may not have physical HPD pin. */
+	if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
+		if (link->hpd_status)
+			*type = dc_connection_single;
+		else
+			*type = dc_connection_none;
+
+		return true;
+	}
+
 	/* todo: may need to lock gpio access */
 	hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 			       link->ctx->gpio_service);
@@ -432,8 +430,18 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
 static enum signal_type link_detect_sink(struct dc_link *link,
 					 enum dc_detect_reason reason)
 {
-	enum signal_type result = get_basic_signal_type(link->link_enc->id,
-							link->link_id);
+	enum signal_type result;
+	struct graphics_object_id enc_id;
+
+	if (link->is_dig_mapping_flexible)
+		enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
+	else
+		enc_id = link->link_enc->id;
+	result = get_basic_signal_type(enc_id, link->link_id);
+
+	/* Use basic signal type for link without physical connector. */
+	if (link->ep_type != DISPLAY_ENDPOINT_PHY)
+		return result;
 
 	/* Internal digital encoder will detect only dongles
 	 * that require digital signal
@@ -697,11 +705,9 @@ static void read_current_link_settings_on_detect(struct dc_link *link)
 
 static bool detect_dp(struct dc_link *link,
 		      struct display_sink_capability *sink_caps,
-		      bool *converter_disable_audio,
-		      struct audio_support *audio_support,
 		      enum dc_detect_reason reason)
 {
-	bool boot = false;
+	struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 
 	sink_caps->signal = link_detect_sink(link, reason);
 	sink_caps->transaction_type =
@@ -724,59 +730,12 @@ static bool detect_dp(struct dc_link *link,
 			 * of this function). */
 			query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 #endif
-			/*
-			 * This call will initiate MST topology discovery. Which
-			 * will detect MST ports and add new DRM connector DRM
-			 * framework. Then read EDID via remote i2c over aux. In
-			 * the end, will notify DRM detect result and save EDID
-			 * into DRM framework.
-			 *
-			 * .detect is called by .fill_modes.
-			 * .fill_modes is called by user mode ioctl
-			 * DRM_IOCTL_MODE_GETCONNECTOR.
-			 *
-			 * .get_modes is called by .fill_modes.
-			 *
-			 * call .get_modes, AMDGPU DM implementation will create
-			 * new dc_sink and add to dc_link. For long HPD plug
-			 * in/out, MST has its own handle.
-			 *
-			 * Therefore, just after dc_create, link->sink is not
-			 * created for MST until user mode app calls
-			 * DRM_IOCTL_MODE_GETCONNECTOR.
-			 *
-			 * Need check ->sink usages in case ->sink = NULL
-			 * TODO: s3 resume check
-			 */
-			if (reason == DETECT_REASON_BOOT)
-				boot = true;
-
-			dm_helpers_dp_update_branch_info(link->ctx, link);
-
-			if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
-							     link, boot)) {
-				/* MST not supported */
-				link->type = dc_connection_single;
-				sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-			}
 		}
 
 		if (link->type != dc_connection_mst_branch &&
-		    is_dp_active_dongle(link)) {
-			/* DP active dongles */
-			link->type = dc_connection_active_dongle;
-			if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
-				/*
-				 * active dongle unplug processing for short irq
-				 */
-				link_disconnect_sink(link);
-				return true;
-			}
-
-			if (link->dpcd_caps.dongle_type !=
-			    DISPLAY_DONGLE_DP_HDMI_CONVERTER)
-				*converter_disable_audio = true;
-		}
+				is_dp_branch_device(link))
+			/* DP SST branch */
+			link->type = dc_connection_sst_branch;
 	} else {
 		/* DP passive dongles */
 		sink_caps->signal = dp_passive_dongle_detection(link->ddc,
@@ -862,7 +821,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
 {
 	struct dc_sink_init_data sink_init_data = { 0 };
 	struct display_sink_capability sink_caps = { 0 };
-	uint8_t i;
+	uint32_t i;
 	bool converter_disable_audio = false;
 	struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 	bool same_edid = false;
@@ -871,7 +830,6 @@ static bool dc_link_detect_helper(struct dc_link *link,
 	struct dc_sink *sink = NULL;
 	struct dc_sink *prev_sink = NULL;
 	struct dpcd_caps prev_dpcd_caps;
-	bool same_dpcd = true;
 	enum dc_connection_type new_connection_type = dc_connection_none;
 	enum dc_connection_type pre_connection_type = dc_connection_none;
 	bool perform_dp_seamless_boot = false;
@@ -882,9 +840,10 @@ static bool dc_link_detect_helper(struct dc_link *link,
 	if (dc_is_virtual_signal(link->connector_signal))
 		return false;
 
-	if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
-	     link->connector_signal == SIGNAL_TYPE_EDP) &&
-	    link->local_sink) {
+	if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
+		link->connector_signal == SIGNAL_TYPE_EDP) &&
+		(!link->dc->config.allow_edp_hotplug_detection)) &&
+		link->local_sink) {
 		// need to re-write OUI and brightness in resume case
 		if (link->connector_signal == SIGNAL_TYPE_EDP) {
 			dpcd_set_source_specific_data(link);
@@ -954,41 +913,19 @@ static bool dc_link_detect_helper(struct dc_link *link,
 
 		case SIGNAL_TYPE_DISPLAY_PORT: {
 			/* wa HPD high coming too early*/
-			if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
+			if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
+			    link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 				/* if alt mode times out, return false */
 				if (!wait_for_entering_dp_alt_mode(link))
 					return false;
 			}
 
-			if (!detect_dp(link, &sink_caps,
-				       &converter_disable_audio,
-				       aud_support, reason)) {
+			if (!detect_dp(link, &sink_caps, reason)) {
 				if (prev_sink)
 					dc_sink_release(prev_sink);
 				return false;
 			}
 
-			// Check if dpcp block is the same
-			if (prev_sink) {
-				if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
-					   sizeof(struct dpcd_caps)))
-					same_dpcd = false;
-			}
-			/* Active dongle downstream unplug*/
-			if (link->type == dc_connection_active_dongle &&
-			    link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
-				if (prev_sink)
-					/* Downstream unplug */
-					dc_sink_release(prev_sink);
-				return true;
-			}
-
-			// link switch from MST to non-MST stop topology manager
-			if (pre_connection_type == dc_connection_mst_branch &&
-				link->type != dc_connection_mst_branch) {
-				dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
-			}
-
 			if (link->type == dc_connection_mst_branch) {
 				LINK_INFO("link=%d, mst branch is now Connected\n",
 					  link->link_index);
@@ -999,15 +936,69 @@ static bool dc_link_detect_helper(struct dc_link *link,
 				 */
 				dp_verify_mst_link_cap(link);
 
+				/*
+				 * This call will initiate MST topology discovery. Which
+				 * will detect MST ports and add new DRM connector DRM
+				 * framework. Then read EDID via remote i2c over aux. In
+				 * the end, will notify DRM detect result and save EDID
+				 * into DRM framework.
+				 *
+				 * .detect is called by .fill_modes.
+				 * .fill_modes is called by user mode ioctl
+				 * DRM_IOCTL_MODE_GETCONNECTOR.
+				 *
+				 * .get_modes is called by .fill_modes.
+				 *
+				 * call .get_modes, AMDGPU DM implementation will create
+				 * new dc_sink and add to dc_link. For long HPD plug
+				 * in/out, MST has its own handle.
+				 *
+				 * Therefore, just after dc_create, link->sink is not
+				 * created for MST until user mode app calls
+				 * DRM_IOCTL_MODE_GETCONNECTOR.
+				 *
+				 * Need check ->sink usages in case ->sink = NULL
+				 * TODO: s3 resume check
+				 */
+
+				dm_helpers_dp_update_branch_info(link->ctx, link);
+				if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
+						link, reason == DETECT_REASON_BOOT)) {
+					if (prev_sink)
+						dc_sink_release(prev_sink);
+					return false;
+				} else {
+					link->type = dc_connection_sst_branch;
+					sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
+				}
+			}
+
+			/* Active SST downstream branch device unplug*/
+			if (link->type == dc_connection_sst_branch &&
+			    link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 				if (prev_sink)
+					/* Downstream unplug */
 					dc_sink_release(prev_sink);
-				return false;
+				return true;
 			}
 
+			/* disable audio for non DP to HDMI active sst converter */
+			if (link->type == dc_connection_sst_branch &&
+					is_dp_active_dongle(link) &&
+					(link->dpcd_caps.dongle_type !=
+							DISPLAY_DONGLE_DP_HDMI_CONVERTER))
+				converter_disable_audio = true;
+
+			// link switch from MST to non-MST stop topology manager
+			if (pre_connection_type == dc_connection_mst_branch &&
+					link->type != dc_connection_mst_branch)
+				dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
+
+
 			// For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 			if (reason == DETECT_REASON_BOOT &&
-			    !dc_ctx->dc->config.power_down_display_on_boot &&
-			    link->link_status.link_active)
+					!dc_ctx->dc->config.power_down_display_on_boot &&
+					link->link_status.link_active)
 				perform_dp_seamless_boot = true;
 
 			if (perform_dp_seamless_boot) {
@@ -1076,24 +1067,6 @@ static bool dc_link_detect_helper(struct dc_link *link,
 			    dc_is_dvi_signal(link->connector_signal)) {
 				if (prev_sink)
 					dc_sink_release(prev_sink);
-				link_disconnect_sink(link);
-
-				return false;
-			}
-			/*
-			 * Abort detection for DP connectors if we have
-			 * no EDID and connector is active converter
-			 * as there are no display downstream
-			 *
-			 */
-			if (dc_is_dp_sst_signal(link->connector_signal) &&
-				(link->dpcd_caps.dongle_type ==
-						DISPLAY_DONGLE_DP_VGA_CONVERTER ||
-				link->dpcd_caps.dongle_type ==
-						DISPLAY_DONGLE_DP_DVI_CONVERTER)) {
-				if (prev_sink)
-					dc_sink_release(prev_sink);
-				link_disconnect_sink(link);
 
 				return false;
 			}
@@ -1208,11 +1181,11 @@ static bool dc_link_detect_helper(struct dc_link *link,
 		link->dongle_max_pix_clk = 0;
 	}
 
-	LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
+	LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
 		  link->link_index, sink,
 		  (sink_caps.signal ==
 		   SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
-		  prev_sink, same_dpcd, same_edid);
+		  prev_sink, same_edid);
 
 	if (prev_sink)
 		dc_sink_release(prev_sink);
@@ -1224,14 +1197,25 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 {
 	const struct dc *dc = link->dc;
 	bool ret;
+	bool can_apply_seamless_boot = false;
+	int i;
+
+	for (i = 0; i < dc->current_state->stream_count; i++) {
+		if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
+			can_apply_seamless_boot = true;
+			break;
+		}
+	}
 
 	/* get out of low power state */
-	clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
+	if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
+		clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 
 	ret = dc_link_detect_helper(link, reason);
 
 	/* Go back to power optimized state */
-	clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
+	if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
+		clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 
 	return ret;
 }
@@ -1485,7 +1469,8 @@ static bool dc_link_construct(struct dc_link *link,
 		link->connector_signal = SIGNAL_TYPE_EDP;
 
 		if (link->hpd_gpio) {
-			link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
+			if (!link->dc->config.allow_edp_hotplug_detection)
+				link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
 			link->irq_source_hpd_rx =
 					dal_irq_get_rx_source(link->hpd_gpio);
 		}
@@ -1734,6 +1719,8 @@ static enum dc_status enable_link_dp(struct dc_state *state,
 	bool apply_seamless_boot_optimization = false;
 	uint32_t bl_oled_enable_delay = 50; // in ms
 	const uint32_t post_oui_delay = 30; // 30ms
+	/* Reduce link bandwidth between failed link training attempts. */
+	bool do_fallback = false;
 
 	// check for seamless boot
 	for (i = 0; i < state->stream_count; i++) {
@@ -1772,7 +1759,8 @@ static enum dc_status enable_link_dp(struct dc_state *state,
 					       skip_video_pattern,
 					       LINK_TRAINING_ATTEMPTS,
 					       pipe_ctx,
-					       pipe_ctx->stream->signal)) {
+					       pipe_ctx->stream->signal,
+					       do_fallback)) {
 		link->cur_link_settings = link_settings;
 		status = DC_OK;
 	} else {
@@ -2664,16 +2652,24 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
 	struct dc  *dc = link->ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 	struct dmub_psr *psr = dc->res_pool->psr;
+	unsigned int panel_inst;
 
 	if (psr == NULL && force_static)
 		return false;
 
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return false;
+
 	link->psr_settings.psr_allow_active = allow_active;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	if (!allow_active)
+		dc_z10_restore(dc);
+#endif
 
 	if (psr != NULL && link->psr_settings.psr_feature_enabled) {
 		if (force_static && psr->funcs->psr_force_static)
-			psr->funcs->psr_force_static(psr);
-		psr->funcs->psr_enable(psr, allow_active, wait);
+			psr->funcs->psr_force_static(psr, panel_inst);
+		psr->funcs->psr_enable(psr, allow_active, wait, panel_inst);
 	} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
 		dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
 	else
@@ -2687,9 +2683,13 @@ bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
 	struct dc  *dc = link->ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 	struct dmub_psr *psr = dc->res_pool->psr;
+	unsigned int panel_inst;
+
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return false;
 
 	if (psr != NULL && link->psr_settings.psr_feature_enabled)
-		psr->funcs->psr_get_state(psr, state);
+		psr->funcs->psr_get_state(psr, state, panel_inst);
 	else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
 		dmcu->funcs->get_psr_state(dmcu, state);
 
@@ -2739,6 +2739,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 	struct dmcu *dmcu;
 	struct dmub_psr *psr;
 	int i;
+	unsigned int panel_inst;
 	/* updateSinkPsrDpcdConfig*/
 	union dpcd_psr_configuration psr_configuration;
 
@@ -2754,6 +2755,9 @@ bool dc_link_setup_psr(struct dc_link *link,
 	if (!dmcu && !psr)
 		return false;
 
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return false;
+
 
 	memset(&psr_configuration, 0, sizeof(psr_configuration));
 
@@ -2838,8 +2842,16 @@ bool dc_link_setup_psr(struct dc_link *link,
 	psr_context->psr_level.u32all = 0;
 
 	/*skip power down the single pipe since it blocks the cstate*/
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
+		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
+		if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
+			psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
+	}
+#else
 	if (link->ctx->asic_id.chip_family >= FAMILY_RV)
 		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
+#endif
 
 	/* SMU will perform additional powerdown sequence.
 	 * For unsupported ASICs, set psr_level flag to skip PSR
@@ -2860,7 +2872,8 @@ bool dc_link_setup_psr(struct dc_link *link,
 	psr_context->frame_delay = 0;
 
 	if (psr)
-		link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
+		link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
+			link, psr_context, panel_inst);
 	else
 		link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
 
@@ -2878,10 +2891,14 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
 {
 	struct dc  *dc = link->ctx->dc;
 	struct dmub_psr *psr = dc->res_pool->psr;
+	unsigned int panel_inst;
+
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return;
 
-	// PSR residency measurements only supported on DMCUB
+	/* PSR residency measurements only supported on DMCUB */
 	if (psr != NULL && link->psr_settings.psr_feature_enabled)
-		psr->funcs->psr_get_residency(psr, residency);
+		psr->funcs->psr_get_residency(psr, residency, panel_inst);
 	else
 		*residency = 0;
 }
@@ -3171,8 +3188,14 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
 				dp_get_panel_mode(pipe_ctx->stream->link);
 
 		config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
+		/*stream_enc_inst*/
 		config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
 		config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
+		config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+		config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+#endif
 		config.dpms_off = dpms_off;
 		config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
 		config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
@@ -3493,9 +3516,11 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
 	uint32_t kbps;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-	if (timing->flags.DSC) {
-		return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel);
-	}
+	if (timing->flags.DSC)
+		return dc_dsc_stream_bandwidth_in_kbps(timing,
+				timing->dsc_cfg.bits_per_pixel,
+				timing->dsc_cfg.num_slices_h,
+				timing->dsc_cfg.is_dp);
 #endif
 
 	switch (timing->display_color_depth) {
@@ -3557,19 +3582,6 @@ void dc_link_set_drive_settings(struct dc *dc,
 	dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
 }
 
-void dc_link_perform_link_training(struct dc *dc,
-				   struct dc_link_settings *link_setting,
-				   bool skip_video_pattern)
-{
-	int i;
-
-	for (i = 0; i < dc->link_count; i++)
-		dc_link_dp_perform_link_training(
-			dc->links[i],
-			link_setting,
-			skip_video_pattern);
-}
-
 void dc_link_set_preferred_link_settings(struct dc *dc,
 					 struct dc_link_settings *link_setting,
 					 struct dc_link *link)
@@ -3720,8 +3732,22 @@ void dc_link_overwrite_extended_receiver_cap(
 
 bool dc_link_is_fec_supported(const struct dc_link *link)
 {
+	struct link_encoder *link_enc = NULL;
+
+	/* Links supporting dynamically assigned link encoder will be assigned next
+	 * available encoder if one not already assigned.
+	 */
+	if (link->is_dig_mapping_flexible &&
+			link->dc->res_pool->funcs->link_encs_assign) {
+		link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+		if (link_enc == NULL)
+			link_enc = link_enc_cfg_get_next_avail_link_enc(link->dc, link->dc->current_state);
+	} else
+		link_enc = link->link_enc;
+	ASSERT(link_enc);
+
 	return (dc_is_dp_signal(link->connector_signal) &&
-			link->link_enc->features.fec_supported &&
+			link_enc->features.fec_supported &&
 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
 			!IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 64414c51312d..ba6b56f20269 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -658,7 +658,10 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
 		struct aux_payload *payload,
 		enum aux_return_code_type *operation_result)
 {
-	return dce_aux_transfer_raw(ddc, payload, operation_result);
+	if (dc_enable_dmub_notifications(ddc->ctx->dc))
+		return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
+	else
+		return dce_aux_transfer_raw(ddc, payload, operation_result);
 }
 
 /* dc_link_aux_transfer_with_retries() - Attempt to submit an
@@ -682,6 +685,10 @@ bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
 	bool result = false;
 	struct ddc *ddc_pin = ddc->ddc_pin;
 
+	/* Do not try to access nonexistent DDC pin. */
+	if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
+		return true;
+
 	if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {
 		ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
 		result = true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 3ff3d9e90983..b8832bdde2bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -14,6 +14,7 @@
 #include "dpcd_defs.h"
 #include "dc_dmub_srv.h"
 #include "dce/dmub_hw_lock_mgr.h"
+#include "inc/link_enc_cfg.h"
 
 /*Travis*/
 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
@@ -24,7 +25,7 @@ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
 	link->ctx->logger
 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
 
-#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
+#include "link_dpcd.h"
 
 	/* maximum pre emphasis level allowed for each voltage swing level*/
 	static const enum dc_pre_emphasis
@@ -38,14 +39,6 @@ enum {
 	POST_LT_ADJ_REQ_TIMEOUT = 200
 };
 
-enum {
-	LINK_TRAINING_MAX_RETRY_COUNT = 5,
-	/* to avoid infinite loop where-in the receiver
-	 * switches between different VS
-	 */
-	LINK_TRAINING_MAX_CR_RETRY = 100
-};
-
 static bool decide_fallback_link_setting(
 		struct dc_link_settings initial_link_settings,
 		struct dc_link_settings *current_link_setting,
@@ -96,7 +89,7 @@ static uint32_t get_eq_training_aux_rd_interval(
 	return wait_in_micro_secs;
 }
 
-static void wait_for_training_aux_rd_interval(
+void dp_wait_for_training_aux_rd_interval(
 	struct dc_link *link,
 	uint32_t wait_in_micro_secs)
 {
@@ -107,10 +100,50 @@ static void wait_for_training_aux_rd_interval(
 		wait_in_micro_secs);
 }
 
+enum dpcd_training_patterns
+	dc_dp_training_pattern_to_dpcd_training_pattern(
+	struct dc_link *link,
+	enum dc_dp_training_pattern pattern)
+{
+	enum dpcd_training_patterns dpcd_tr_pattern =
+	DPCD_TRAINING_PATTERN_VIDEOIDLE;
+
+	switch (pattern) {
+	case DP_TRAINING_PATTERN_SEQUENCE_1:
+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
+		break;
+	case DP_TRAINING_PATTERN_SEQUENCE_2:
+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
+		break;
+	case DP_TRAINING_PATTERN_SEQUENCE_3:
+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
+		break;
+	case DP_TRAINING_PATTERN_SEQUENCE_4:
+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
+		break;
+	case DP_TRAINING_PATTERN_VIDEOIDLE:
+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
+		break;
+	default:
+		ASSERT(0);
+		DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
+			__func__, pattern);
+		break;
+	}
+
+	return dpcd_tr_pattern;
+}
+
 static void dpcd_set_training_pattern(
 	struct dc_link *link,
-	union dpcd_training_pattern dpcd_pattern)
+	enum dc_dp_training_pattern training_pattern)
 {
+	union dpcd_training_pattern dpcd_pattern = { {0} };
+
+	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
+			dc_dp_training_pattern_to_dpcd_training_pattern(
+					link, training_pattern);
+
 	core_link_write_dpcd(
 		link,
 		DP_TRAINING_PATTERN_SET,
@@ -132,10 +165,22 @@ static enum dc_dp_training_pattern decide_cr_training_pattern(
 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 		const struct dc_link_settings *link_settings)
 {
+	struct link_encoder *link_enc;
 	enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
-	struct encoder_feature_support *features = &link->link_enc->features;
+	struct encoder_feature_support *features;
 	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 
+	/* Access link encoder capability based on whether it is statically
+	 * or dynamically assigned to a link.
+	 */
+	if (link->is_dig_mapping_flexible &&
+			link->dc->res_pool->funcs->link_encs_assign)
+		link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+	else
+		link_enc = link->link_enc;
+	ASSERT(link_enc);
+	features = &link_enc->features;
+
 	if (features->flags.bits.IS_TPS3_CAPABLE)
 		highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 
@@ -153,11 +198,12 @@ static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *li
 	return DP_TRAINING_PATTERN_SEQUENCE_2;
 }
 
-static void dpcd_set_link_settings(
+enum dc_status dpcd_set_link_settings(
 	struct dc_link *link,
 	const struct link_training_settings *lt_settings)
 {
 	uint8_t rate;
+	enum dc_status status;
 
 	union down_spread_ctrl downspread = { {0} };
 	union lane_count_set lane_count_set = { {0} };
@@ -172,15 +218,16 @@ static void dpcd_set_link_settings(
 	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 
 
-	if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
+	if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
+			lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 		lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 				link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 	}
 
-	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
+	status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 		&downspread.raw, sizeof(downspread));
 
-	core_link_write_dpcd(link, DP_LANE_COUNT_SET,
+	status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 		&lane_count_set.raw, 1);
 
 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
@@ -196,12 +243,12 @@ static void dpcd_set_link_settings(
 			core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 					supported_link_rates, sizeof(supported_link_rates));
 		}
-		core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
-		core_link_write_dpcd(link, DP_LINK_RATE_SET,
+		status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
+		status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
 				&lt_settings->link_settings.link_rate_set, 1);
 	} else {
 		rate = (uint8_t) (lt_settings->link_settings.link_rate);
-		core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
+		status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 	}
 
 	if (rate) {
@@ -225,40 +272,11 @@ static void dpcd_set_link_settings(
 			DP_DOWNSPREAD_CTRL,
 			lt_settings->link_settings.link_spread);
 	}
-}
 
-static enum dpcd_training_patterns
-	dc_dp_training_pattern_to_dpcd_training_pattern(
-	struct dc_link *link,
-	enum dc_dp_training_pattern pattern)
-{
-	enum dpcd_training_patterns dpcd_tr_pattern =
-	DPCD_TRAINING_PATTERN_VIDEOIDLE;
-
-	switch (pattern) {
-	case DP_TRAINING_PATTERN_SEQUENCE_1:
-		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
-		break;
-	case DP_TRAINING_PATTERN_SEQUENCE_2:
-		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
-		break;
-	case DP_TRAINING_PATTERN_SEQUENCE_3:
-		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
-		break;
-	case DP_TRAINING_PATTERN_SEQUENCE_4:
-		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
-		break;
-	default:
-		ASSERT(0);
-		DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
-			__func__, pattern);
-		break;
-	}
-
-	return dpcd_tr_pattern;
+	return status;
 }
 
-static uint8_t dc_dp_initialize_scrambling_data_symbols(
+uint8_t dc_dp_initialize_scrambling_data_symbols(
 	struct dc_link *link,
 	enum dc_dp_training_pattern pattern)
 {
@@ -407,7 +425,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
 	link->cur_lane_setting = lt_settings->lane_settings[0];
 }
 
-static bool is_cr_done(enum dc_lane_count ln_count,
+bool dp_is_cr_done(enum dc_lane_count ln_count,
 	union lane_status *dpcd_lane_status)
 {
 	uint32_t lane;
@@ -419,24 +437,34 @@ static bool is_cr_done(enum dc_lane_count ln_count,
 	return true;
 }
 
-static bool is_ch_eq_done(enum dc_lane_count ln_count,
-	union lane_status *dpcd_lane_status,
-	union lane_align_status_updated *lane_status_updated)
+bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
+		union lane_status *dpcd_lane_status)
 {
+	bool done = true;
 	uint32_t lane;
-	if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
-		return false;
-	else {
-		for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
-			if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
-				!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
-				return false;
-		}
-	}
-	return true;
+	for (lane = 0; lane < (uint32_t)(ln_count); lane++)
+		if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
+			done = false;
+	return done;
 }
 
-static void update_drive_settings(
+bool dp_is_symbol_locked(enum dc_lane_count ln_count,
+		union lane_status *dpcd_lane_status)
+{
+	bool locked = true;
+	uint32_t lane;
+	for (lane = 0; lane < (uint32_t)(ln_count); lane++)
+		if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
+			locked = false;
+	return locked;
+}
+
+bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
+{
+	return align_status.bits.INTERLANE_ALIGN_DONE == 1;
+}
+
+void dp_update_drive_settings(
 		struct link_training_settings *dest,
 		struct link_training_settings src)
 {
@@ -580,7 +608,7 @@ static void find_max_drive_settings(
 
 }
 
-static void get_lane_status_and_drive_settings(
+enum dc_status dp_get_lane_status_and_drive_settings(
 	struct dc_link *link,
 	const struct link_training_settings *link_training_setting,
 	union lane_status *ln_status,
@@ -595,6 +623,7 @@ static void get_lane_status_and_drive_settings(
 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 	struct link_training_settings request_settings = { {0} };
 	uint32_t lane;
+	enum dc_status status;
 
 	memset(req_settings, '\0', sizeof(struct link_training_settings));
 
@@ -605,7 +634,7 @@ static void get_lane_status_and_drive_settings(
 		lane_adjust_offset = 3;
 	}
 
-	core_link_read_dpcd(
+	status = core_link_read_dpcd(
 		link,
 		lane01_status_address,
 		(uint8_t *)(dpcd_buf),
@@ -693,9 +722,10 @@ static void get_lane_status_and_drive_settings(
 	 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 	 */
 
+	return status;
 }
 
-static void dpcd_set_lane_settings(
+enum dc_status dpcd_set_lane_settings(
 	struct dc_link *link,
 	const struct link_training_settings *link_training_setting,
 	uint32_t offset)
@@ -703,6 +733,7 @@ static void dpcd_set_lane_settings(
 	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 	uint32_t lane;
 	unsigned int lane0_set_address;
+	enum dc_status status;
 
 	lane0_set_address = DP_TRAINING_LANE0_SET;
 
@@ -730,7 +761,7 @@ static void dpcd_set_lane_settings(
 			PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 	}
 
-	core_link_write_dpcd(link,
+	status = core_link_write_dpcd(link,
 		lane0_set_address,
 		(uint8_t *)(dpcd_lane),
 		link_training_setting->link_settings.lane_count);
@@ -776,9 +807,10 @@ static void dpcd_set_lane_settings(
 	}
 	link->cur_lane_setting = link_training_setting->lane_settings[0];
 
+	return status;
 }
 
-static bool is_max_vs_reached(
+bool dp_is_max_vs_reached(
 	const struct link_training_settings *lt_settings)
 {
 	uint32_t lane;
@@ -820,25 +852,24 @@ static bool perform_post_lt_adj_req_sequence(
 			union lane_align_status_updated
 				dpcd_lane_status_updated;
 
-			get_lane_status_and_drive_settings(
-			link,
-			lt_settings,
-			dpcd_lane_status,
-			&dpcd_lane_status_updated,
-			&req_settings,
-			DPRX);
+			dp_get_lane_status_and_drive_settings(
+				link,
+				lt_settings,
+				dpcd_lane_status,
+				&dpcd_lane_status_updated,
+				&req_settings,
+				DPRX);
 
 			if (dpcd_lane_status_updated.bits.
 					POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 				return true;
 
-			if (!is_cr_done(lane_count, dpcd_lane_status))
+			if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 				return false;
 
-			if (!is_ch_eq_done(
-				lane_count,
-				dpcd_lane_status,
-				&dpcd_lane_status_updated))
+			if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
+					!dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
+					!dp_is_interlane_aligned(dpcd_lane_status_updated))
 				return false;
 
 			for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
@@ -856,7 +887,7 @@ static bool perform_post_lt_adj_req_sequence(
 			}
 
 			if (req_drv_setting_changed) {
-				update_drive_settings(
+				dp_update_drive_settings(
 					lt_settings, req_settings);
 
 				dc_link_dp_set_drive_settings(link,
@@ -884,7 +915,7 @@ static bool perform_post_lt_adj_req_sequence(
 }
 
 /* Only used for channel equalization */
-static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
+uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 {
 	unsigned int aux_rd_interval_us = 400;
 
@@ -908,7 +939,7 @@ static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_inte
 	return aux_rd_interval_us;
 }
 
-static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
+enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
 					union lane_status *dpcd_lane_status)
 {
 	enum link_training_result result = LINK_TRAINING_SUCCESS;
@@ -969,17 +1000,17 @@ static enum link_training_result perform_channel_equalization_sequence(
 
 		if (is_repeater(link, offset))
 			wait_time_microsec =
-					translate_training_aux_read_interval(
+					dp_translate_training_aux_read_interval(
 						link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 
-		wait_for_training_aux_rd_interval(
+		dp_wait_for_training_aux_rd_interval(
 				link,
 				wait_time_microsec);
 
 		/* 4. Read lane status and requested
 		 * drive settings as set by the sink*/
 
-		get_lane_status_and_drive_settings(
+		dp_get_lane_status_and_drive_settings(
 			link,
 			lt_settings,
 			dpcd_lane_status,
@@ -988,23 +1019,22 @@ static enum link_training_result perform_channel_equalization_sequence(
 			offset);
 
 		/* 5. check CR done*/
-		if (!is_cr_done(lane_count, dpcd_lane_status))
+		if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 			return LINK_TRAINING_EQ_FAIL_CR;
 
 		/* 6. check CHEQ done*/
-		if (is_ch_eq_done(lane_count,
-			dpcd_lane_status,
-			&dpcd_lane_status_updated))
+		if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
+				dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
+				dp_is_interlane_aligned(dpcd_lane_status_updated))
 			return LINK_TRAINING_SUCCESS;
 
 		/* 7. update VS/PE/PC2 in lt_settings*/
-		update_drive_settings(lt_settings, req_settings);
+		dp_update_drive_settings(lt_settings, req_settings);
 	}
 
 	return LINK_TRAINING_EQ_FAIL_EQ;
 
 }
-#define TRAINING_AUX_RD_INTERVAL 100 //us
 
 static void start_clock_recovery_pattern_early(struct dc_link *link,
 		struct link_training_settings *lt_settings,
@@ -1075,14 +1105,14 @@ static enum link_training_result perform_clock_recovery_sequence(
 		if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
 			wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
 
-		wait_for_training_aux_rd_interval(
+		dp_wait_for_training_aux_rd_interval(
 				link,
 				wait_time_microsec);
 
 		/* 4. Read lane status and requested drive
 		* settings as set by the sink
 		*/
-		get_lane_status_and_drive_settings(
+		dp_get_lane_status_and_drive_settings(
 				link,
 				lt_settings,
 				dpcd_lane_status,
@@ -1091,11 +1121,11 @@ static enum link_training_result perform_clock_recovery_sequence(
 				offset);
 
 		/* 5. check CR done*/
-		if (is_cr_done(lane_count, dpcd_lane_status))
+		if (dp_is_cr_done(lane_count, dpcd_lane_status))
 			return LINK_TRAINING_SUCCESS;
 
 		/* 6. max VS reached*/
-		if (is_max_vs_reached(lt_settings))
+		if (dp_is_max_vs_reached(lt_settings))
 			break;
 
 		/* 7. same lane settings*/
@@ -1110,7 +1140,7 @@ static enum link_training_result perform_clock_recovery_sequence(
 			retries_cr = 0;
 
 		/* 8. update VS/PE/PC2 in lt_settings*/
-		update_drive_settings(lt_settings, req_settings);
+		dp_update_drive_settings(lt_settings, req_settings);
 
 		retry_count++;
 	}
@@ -1123,10 +1153,10 @@ static enum link_training_result perform_clock_recovery_sequence(
 
 	}
 
-	return get_cr_failure(lane_count, dpcd_lane_status);
+	return dp_get_cr_failure(lane_count, dpcd_lane_status);
 }
 
-static inline enum link_training_result perform_link_training_int(
+static inline enum link_training_result dp_transition_to_video_idle(
 	struct dc_link *link,
 	struct link_training_settings *lt_settings,
 	enum link_training_result status)
@@ -1142,8 +1172,16 @@ static inline enum link_training_result perform_link_training_int(
 	 * TPS4 must be used instead of POST_LT_ADJ_REQ.
 	 */
 	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
-			lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
+			lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
+		/* delay 5ms after Main Link output idle pattern and then check
+		 * DPCD 0202h.
+		 */
+		if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
+			msleep(5);
+			status = dp_check_link_loss_status(link, lt_settings);
+		}
 		return status;
+	}
 
 	if (status == LINK_TRAINING_SUCCESS &&
 		perform_post_lt_adj_req_sequence(link, lt_settings) == false)
@@ -1162,7 +1200,7 @@ static inline enum link_training_result perform_link_training_int(
 	return status;
 }
 
-static enum link_training_result check_link_loss_status(
+enum link_training_result dp_check_link_loss_status(
 	struct dc_link *link,
 	const struct link_training_settings *link_training_setting)
 {
@@ -1200,7 +1238,7 @@ static enum link_training_result check_link_loss_status(
 	return status;
 }
 
-static void initialize_training_settings(
+static inline void decide_8b_10b_training_settings(
 	 struct dc_link *link,
 	const struct dc_link_settings *link_setting,
 	const struct dc_link_training_overrides *overrides,
@@ -1244,6 +1282,8 @@ static void initialize_training_settings(
 	else
 		lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
 
+	lt_settings->lttpr_mode = link->lttpr_mode;
+
 	/* Initialize lane settings overrides */
 	if (overrides->voltage_swing != NULL)
 		lt_settings->voltage_swing = overrides->voltage_swing;
@@ -1294,9 +1334,25 @@ static void initialize_training_settings(
 		lt_settings->enhanced_framing = *overrides->enhanced_framing;
 	else
 		lt_settings->enhanced_framing = 1;
+
+	if (link->preferred_training_settings.fec_enable != NULL)
+		lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
+	else
+		lt_settings->should_set_fec_ready = true;
 }
 
-static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
+void dp_decide_training_settings(
+		struct dc_link *link,
+		const struct dc_link_settings *link_settings,
+		const struct dc_link_training_overrides *overrides,
+		struct link_training_settings *lt_settings)
+{
+	if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
+		decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
+}
+
+
+uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
 {
 	switch (lttpr_repeater_count) {
 	case 0x80: // 1 lttpr repeater
@@ -1321,17 +1377,20 @@ static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
 	return 0; // invalid value
 }
 
-static void configure_lttpr_mode_transparent(struct dc_link *link)
+enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
 {
 	uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
 
-	core_link_write_dpcd(link,
+	DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
+	return core_link_write_dpcd(link,
 			DP_PHY_REPEATER_MODE,
 			(uint8_t *)&repeater_mode,
 			sizeof(repeater_mode));
 }
 
-static void configure_lttpr_mode_non_transparent(struct dc_link *link)
+enum dc_status configure_lttpr_mode_non_transparent(
+		struct dc_link *link,
+		const struct link_training_settings *lt_settings)
 {
 	/* aux timeout is already set to extended */
 	/* RESET/SET lttpr mode to enable non transparent mode */
@@ -1341,11 +1400,16 @@ static void configure_lttpr_mode_non_transparent(struct dc_link *link)
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 	uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
 
-	DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
-	result = core_link_write_dpcd(link,
-			DP_PHY_REPEATER_MODE,
-			(uint8_t *)&repeater_mode,
-			sizeof(repeater_mode));
+	enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
+
+	if (encoding == DP_8b_10b_ENCODING) {
+		DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
+		result = core_link_write_dpcd(link,
+				DP_PHY_REPEATER_MODE,
+				(uint8_t *)&repeater_mode,
+				sizeof(repeater_mode));
+
+	}
 
 	if (result == DC_OK) {
 		link->dpcd_caps.lttpr_caps.mode = repeater_mode;
@@ -1365,18 +1429,22 @@ static void configure_lttpr_mode_non_transparent(struct dc_link *link)
 			link->dpcd_caps.lttpr_caps.mode = repeater_mode;
 		}
 
-		repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
-		for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
-			aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
-						((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
-			core_link_read_dpcd(
-				link,
-				aux_interval_address,
-				(uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
-				sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
-			link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
+		if (encoding == DP_8b_10b_ENCODING) {
+			repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+			for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
+				aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
+							((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
+				core_link_read_dpcd(
+					link,
+					aux_interval_address,
+					(uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
+					sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
+				link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
+			}
 		}
 	}
+
+	return result;
 }
 
 static void repeater_training_done(struct dc_link *link, uint32_t offset)
@@ -1510,7 +1578,7 @@ bool dc_link_dp_perform_link_training_skip_aux(
 {
 	struct link_training_settings lt_settings;
 
-	initialize_training_settings(
+	dp_decide_training_settings(
 			link,
 			link_setting,
 			&link->preferred_training_settings,
@@ -1525,7 +1593,7 @@ bool dc_link_dp_perform_link_training_skip_aux(
 	dp_set_hw_lane_settings(link, &lt_settings, DPRX);
 
 	/* wait receiver to lock-on*/
-	wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
+	dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
 
 	/* 2. Perform_channel_equalization_sequence. */
 
@@ -1536,7 +1604,7 @@ bool dc_link_dp_perform_link_training_skip_aux(
 	dp_set_hw_lane_settings(link, &lt_settings, DPRX);
 
 	/* wait receiver to lock-on. */
-	wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
+	dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
 
 	/* 3. Perform_link_training_int. */
 
@@ -1548,60 +1616,78 @@ bool dc_link_dp_perform_link_training_skip_aux(
 	return true;
 }
 
-enum link_training_result dc_link_dp_perform_link_training(
-	struct dc_link *link,
-	const struct dc_link_settings *link_setting,
-	bool skip_video_pattern)
+enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
 {
-	enum link_training_result status = LINK_TRAINING_SUCCESS;
-	struct link_training_settings lt_settings;
-	union dpcd_training_pattern dpcd_pattern = { { 0 } };
+	enum dc_status status = DC_OK;
 
-	bool fec_enable;
-	uint8_t repeater_cnt;
-	uint8_t repeater_id;
+	if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
+		status = configure_lttpr_mode_non_transparent(link, lt_settings);
+	else
+		status = configure_lttpr_mode_transparent(link);
+
+	return status;
+}
+
+static void dpcd_exit_training_mode(struct dc_link *link)
+{
+
+	/* clear training pattern set */
+	dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
+}
 
-	initialize_training_settings(
+enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
+		struct link_training_settings *lt_settings)
+{
+	enum dp_link_encoding encoding =
+			dp_get_link_encoding_format(
+					&lt_settings->link_settings);
+	enum dc_status status;
+
+	status = core_link_write_dpcd(
 			link,
-			link_setting,
-			&link->preferred_training_settings,
-			&lt_settings);
+			DP_MAIN_LINK_CHANNEL_CODING_SET,
+			(uint8_t *) &encoding,
+			1);
+	DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
+					__func__,
+					DP_MAIN_LINK_CHANNEL_CODING_SET,
+					encoding);
 
-	/* Configure lttpr mode */
-	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
-		configure_lttpr_mode_non_transparent(link);
-	else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
-		configure_lttpr_mode_transparent(link);
+	return status;
+}
 
-	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
-		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
+static enum link_training_result dp_perform_8b_10b_link_training(
+		struct dc_link *link,
+		struct link_training_settings *lt_settings)
+{
+	enum link_training_result status = LINK_TRAINING_SUCCESS;
 
-	/* 1. set link rate, lane count and spread. */
-	dpcd_set_link_settings(link, &lt_settings);
+	uint8_t repeater_cnt;
+	uint8_t repeater_id;
+	uint8_t lane = 0;
 
-	if (link->preferred_training_settings.fec_enable != NULL)
-		fec_enable = *link->preferred_training_settings.fec_enable;
-	else
-		fec_enable = true;
+	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
+		start_clock_recovery_pattern_early(link, lt_settings, DPRX);
 
-	dp_set_fec_ready(link, fec_enable);
+	/* 1. set link rate, lane count and spread. */
+	dpcd_set_link_settings(link, lt_settings);
 
 	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
 
 		/* 2. perform link training (set link training done
 		 *  to false is done as well)
 		 */
-		repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+		repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
 
 		for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
 				repeater_id--) {
-			status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
+			status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
 
 			if (status != LINK_TRAINING_SUCCESS)
 				break;
 
 			status = perform_channel_equalization_sequence(link,
-					&lt_settings,
+					lt_settings,
 					repeater_id);
 
 			if (status != LINK_TRAINING_SUCCESS)
@@ -1609,77 +1695,69 @@ enum link_training_result dc_link_dp_perform_link_training(
 
 			repeater_training_done(link, repeater_id);
 		}
+
+		for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
+			lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
 	}
 
 	if (status == LINK_TRAINING_SUCCESS) {
-		status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
+		status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
 	if (status == LINK_TRAINING_SUCCESS) {
 		status = perform_channel_equalization_sequence(link,
-					&lt_settings,
+					lt_settings,
 					DPRX);
 		}
 	}
 
-	/* 3. set training not in progress*/
-	dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
-	dpcd_set_training_pattern(link, dpcd_pattern);
-	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
-		status = perform_link_training_int(link,
-				&lt_settings,
-				status);
-	}
-
-	/* delay 5ms after Main Link output idle pattern and then check
-	 * DPCD 0202h.
-	 */
-	if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
-		msleep(5);
-		status = check_link_loss_status(link, &lt_settings);
-	}
-
-	/* 6. print status message*/
-	print_status_message(link, &lt_settings, status);
-
-	if (status != LINK_TRAINING_SUCCESS)
-		link->ctx->dc->debug_data.ltFailCount++;
-
 	return status;
 }
 
-static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
+enum link_training_result dc_link_dp_perform_link_training(
+	struct dc_link *link,
+	const struct dc_link_settings *link_settings,
+	bool skip_video_pattern)
 {
-	struct dc_link *link = stream->link;
-	enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
-#ifdef CONFIG_DRM_AMD_DC_HDCP
-	struct cp_psp *cp_psp = &stream->ctx->cp_psp;
-#endif
+	enum link_training_result status = LINK_TRAINING_SUCCESS;
+	struct link_training_settings lt_settings;
+	enum dp_link_encoding encoding =
+			dp_get_link_encoding_format(link_settings);
 
-	/* ASSR must be supported on the panel */
-	if (panel_mode == DP_PANEL_MODE_DEFAULT)
-		return panel_mode;
+	/* decide training settings */
+	dp_decide_training_settings(
+			link,
+			link_settings,
+			&link->preferred_training_settings,
+			&lt_settings);
 
-	/* eDP or internal DP only */
-	if (link->connector_signal != SIGNAL_TYPE_EDP &&
-		!(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
-		 link->is_internal_display))
-		return DP_PANEL_MODE_DEFAULT;
+	/* reset previous training states */
+	dpcd_exit_training_mode(link);
 
-#ifdef CONFIG_DRM_AMD_DC_HDCP
-	if (cp_psp && cp_psp->funcs.enable_assr) {
-		if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
-			/* since eDP implies ASSR on, change panel
-			 * mode to disable ASSR
-			 */
-			panel_mode = DP_PANEL_MODE_DEFAULT;
-		}
-	} else
-		panel_mode = DP_PANEL_MODE_DEFAULT;
+	/* configure link prior to entering training mode */
+	dpcd_configure_lttpr_mode(link, &lt_settings);
+	dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
+	dpcd_configure_channel_coding(link, &lt_settings);
 
-#else
-	/* turn off ASSR if the implementation is not compiled in */
-	panel_mode = DP_PANEL_MODE_DEFAULT;
-#endif
-	return panel_mode;
+	/* enter training mode:
+	 * Per DP specs starting from here, DPTX device shall not issue
+	 * Non-LT AUX transactions inside training mode.
+	 */
+	if (encoding == DP_8b_10b_ENCODING)
+		status = dp_perform_8b_10b_link_training(link, &lt_settings);
+	else
+		ASSERT(0);
+
+	/* exit training mode and switch to video idle */
+	dpcd_exit_training_mode(link);
+	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
+		status = dp_transition_to_video_idle(link,
+				&lt_settings,
+				status);
+
+	/* dump debug data */
+	print_status_message(link, &lt_settings, status);
+	if (status != LINK_TRAINING_SUCCESS)
+		link->ctx->dc->debug_data.ltFailCount++;
+	return status;
 }
 
 bool perform_link_training_with_retries(
@@ -1687,18 +1765,31 @@ bool perform_link_training_with_retries(
 	bool skip_video_pattern,
 	int attempts,
 	struct pipe_ctx *pipe_ctx,
-	enum signal_type signal)
+	enum signal_type signal,
+	bool do_fallback)
 {
-	uint8_t j;
+	int j;
 	uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
 	struct dc_stream_state *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->link;
-	enum dp_panel_mode panel_mode;
+	enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
+	struct link_encoder *link_enc;
+	enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
+	struct dc_link_settings current_setting = *link_setting;
+
+	/* Dynamically assigned link encoders associated with stream rather than
+	 * link.
+	 */
+	if (link->dc->res_pool->funcs->link_encs_assign)
+		link_enc = stream->link_enc;
+	else
+		link_enc = link->link_enc;
+	ASSERT(link_enc);
 
 	/* We need to do this before the link training to ensure the idle pattern in SST
 	 * mode will be sent right after the link training
 	 */
-	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+	link_enc->funcs->connect_dig_be_to_fe(link_enc,
 							pipe_ctx->stream_res.stream_enc->id, true);
 
 	for (j = 0; j < attempts; ++j) {
@@ -1710,7 +1801,7 @@ bool perform_link_training_with_retries(
 			link,
 			signal,
 			pipe_ctx->clock_source->id,
-			link_setting);
+			&current_setting);
 
 		if (stream->sink_patches.dppowerup_delay > 0) {
 			int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
@@ -1718,21 +1809,31 @@ bool perform_link_training_with_retries(
 			msleep(delay_dp_power_up_in_ms);
 		}
 
-		panel_mode = try_enable_assr(stream);
+#ifdef CONFIG_DRM_AMD_DC_HDCP
+		if (panel_mode == DP_PANEL_MODE_EDP) {
+			struct cp_psp *cp_psp = &stream->ctx->cp_psp;
+
+			if (cp_psp && cp_psp->funcs.enable_assr) {
+				if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
+					/* since eDP implies ASSR on, change panel
+					 * mode to disable ASSR
+					 */
+					panel_mode = DP_PANEL_MODE_DEFAULT;
+				}
+			} else
+				panel_mode = DP_PANEL_MODE_DEFAULT;
+		}
+#endif
+
 		dp_set_panel_mode(link, panel_mode);
-		DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
-			 link->link_index,
-			 panel_mode != DP_PANEL_MODE_DEFAULT);
 
 		if (link->aux_access_disabled) {
-			dc_link_dp_perform_link_training_skip_aux(link, link_setting);
+			dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
 			return true;
 		} else {
-			enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
-
 				status = dc_link_dp_perform_link_training(
 										link,
-										link_setting,
+										&current_setting,
 										skip_video_pattern);
 			if (status == LINK_TRAINING_SUCCESS)
 				return true;
@@ -1740,7 +1841,7 @@ bool perform_link_training_with_retries(
 
 		/* latest link training still fail, skip delay and keep PHY on
 		 */
-		if (j == (attempts - 1))
+		if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
 			break;
 
 		DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
@@ -1748,6 +1849,19 @@ bool perform_link_training_with_retries(
 
 		dp_disable_link_phy(link, signal);
 
+		/* Abort link training if failure due to sink being unplugged. */
+		if (status == LINK_TRAINING_ABORT)
+			break;
+		else if (do_fallback) {
+			decide_fallback_link_setting(*link_setting, &current_setting, status);
+			/* Fail link training if reduced link bandwidth no longer meets
+			 * stream requirements.
+			 */
+			if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
+					dc_link_bandwidth_kbps(link, &current_setting))
+				break;
+		}
+
 		msleep(delay_between_attempts);
 
 		delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
@@ -1784,6 +1898,8 @@ static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
 		link->type = dc_connection_single;
 		link->local_sink = link->remote_sinks[0];
 		link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
+		dc_sink_retain(link->local_sink);
+		dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 	} else if (mst_enable == true &&
 			link->type == dc_connection_single &&
 			link->remote_sinks[0] != NULL) {
@@ -1823,7 +1939,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
 	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
 	bool fec_enable = false;
 
-	initialize_training_settings(
+	dp_decide_training_settings(
 		link,
 		link_settings,
 		lt_overrides,
@@ -1893,6 +2009,24 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
 	return true;
 }
 
+bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
+{
+	if (!max_link_enc_cap) {
+		DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
+		return false;
+	}
+
+	if (link->link_enc->funcs->get_max_link_cap) {
+		link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
+		return true;
+	}
+
+	DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
+	max_link_enc_cap->lane_count = 1;
+	max_link_enc_cap->link_rate = 6;
+	return false;
+}
+
 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
 {
 	struct dc_link_settings max_link_cap = {0};
@@ -1976,7 +2110,7 @@ enum dc_status read_hpd_rx_irq_data(
 	return retval;
 }
 
-static bool hpd_rx_irq_check_link_loss_status(
+bool hpd_rx_irq_check_link_loss_status(
 	struct dc_link *link,
 	union hpd_irq_data *hpd_irq_dpcd_data)
 {
@@ -2173,7 +2307,7 @@ bool dp_verify_link_cap_with_retries(
 	struct dc_link_settings *known_limit_link_setting,
 	int attempts)
 {
-	uint8_t i = 0;
+	int i = 0;
 	bool success = false;
 
 	for (i = 0; i < attempts; i++) {
@@ -2411,6 +2545,12 @@ bool dp_validate_mode_timing(
 
 	const struct dc_link_settings *link_setting;
 
+	/* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
+	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
+			!link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
+			dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
+		return false;
+
 	/*always DP fail safe mode*/
 	if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
 		timing->h_addressable == (uint32_t) 640 &&
@@ -2495,7 +2635,11 @@ bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *lin
 	struct dc_link_settings current_link_setting;
 	uint32_t link_bw;
 
-	if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
+	/*
+	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
+	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
+	 */
+	if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
 			link->dpcd_caps.edp_supported_link_rates_count == 0) {
 		*link_setting = link->verified_link_cap;
 		return true;
@@ -2593,13 +2737,11 @@ static bool allow_hpd_rx_irq(const struct dc_link *link)
 	/*
 	 * Don't handle RX IRQ unless one of following is met:
 	 * 1) The link is established (cur_link_settings != unknown)
-	 * 2) We kicked off MST detection
-	 * 3) We know we're dealing with an active dongle
+	 * 2) We know we're dealing with a branch device, SST or MST
 	 */
 
 	if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
-		(link->type == dc_connection_mst_branch) ||
-		is_dp_active_dongle(link))
+		is_dp_branch_device(link))
 		return true;
 
 	return false;
@@ -2697,9 +2839,10 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	union phy_test_pattern dpcd_test_pattern;
 	union lane_adjust dpcd_lane_adjustment[2];
 	unsigned char dpcd_post_cursor_2_adjustment = 0;
-	unsigned char test_80_bit_pattern[
+	unsigned char test_pattern_buffer[
 			(DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
 			DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
+	unsigned int test_pattern_size = 0;
 	enum dp_test_pattern test_pattern;
 	struct dc_link_training_settings link_settings;
 	union lane_adjust dpcd_lane_adjust;
@@ -2769,12 +2912,15 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	break;
 	}
 
-	if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
+	if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
+		test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
+				DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
 		core_link_read_dpcd(
 				link,
 				DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
-				test_80_bit_pattern,
-				sizeof(test_80_bit_pattern));
+				test_pattern_buffer,
+				test_pattern_size);
+	}
 
 	/* prepare link training settings */
 	link_settings.link = link->cur_link_settings;
@@ -2812,9 +2958,8 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 		test_pattern,
 		DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
 		&link_training_settings,
-		test_80_bit_pattern,
-		(DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
-		DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
+		test_pattern_buffer,
+		test_pattern_size);
 }
 
 static void dp_test_send_link_test_pattern(struct dc_link *link)
@@ -2899,6 +3044,22 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
 		break;
 	}
 
+	switch (dpcd_test_params.bits.CLR_FORMAT) {
+	case 0:
+		pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
+		break;
+	case 1:
+		pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
+		break;
+	case 2:
+		pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
+		break;
+	default:
+		pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
+		break;
+	}
+
+
 	if (requestColorDepth != COLOR_DEPTH_UNDEFINED
 			&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
 		DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
@@ -2906,9 +3067,10 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
 				pipe_ctx->stream->timing.display_color_depth,
 				requestColorDepth);
 		pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
-		dp_update_dsc_config(pipe_ctx);
 	}
 
+	dp_update_dsc_config(pipe_ctx);
+
 	dc_link_dp_set_test_pattern(
 			link,
 			test_pattern,
@@ -3164,7 +3326,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
 			*out_link_loss = true;
 	}
 
-	if (link->type == dc_connection_active_dongle &&
+	if (link->type == dc_connection_sst_branch &&
 		hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
 			!= link->dpcd_sink_count)
 		status = true;
@@ -3215,6 +3377,12 @@ bool is_mst_supported(struct dc_link *link)
 
 bool is_dp_active_dongle(const struct dc_link *link)
 {
+	return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
+				(link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
+}
+
+bool is_dp_branch_device(const struct dc_link *link)
+{
 	return link->dpcd_caps.is_branch_dev;
 }
 
@@ -3432,79 +3600,16 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
 	return true;
 }
 
-static bool retrieve_link_cap(struct dc_link *link)
+bool dp_retrieve_lttpr_cap(struct dc_link *link)
 {
-	/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
-	 * which means size 16 will be good for both of those DPCD register block reads
-	 */
-	uint8_t dpcd_data[16];
 	uint8_t lttpr_dpcd_data[6];
-
-	/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
-	 */
-	uint8_t dpcd_dprx_data = '\0';
-	uint8_t dpcd_power_state = '\0';
-
-	struct dp_device_vendor_id sink_id;
-	union down_stream_port_count down_strm_port_count;
-	union edp_configuration_cap edp_config_cap;
-	union dp_downstream_port_present ds_port = { 0 };
-	enum dc_status status = DC_ERROR_UNEXPECTED;
-	uint32_t read_dpcd_retry_cnt = 3;
-	int i;
-	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
-	bool is_lttpr_present = false;
-	const uint32_t post_oui_delay = 30; // 30ms
 	bool vbios_lttpr_enable = false;
 	bool vbios_lttpr_interop = false;
 	struct dc_bios *bios = link->dc->ctx->dc_bios;
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	bool is_lttpr_present = false;
 
-	memset(dpcd_data, '\0', sizeof(dpcd_data));
 	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
-	memset(&down_strm_port_count,
-		'\0', sizeof(union down_stream_port_count));
-	memset(&edp_config_cap, '\0',
-		sizeof(union edp_configuration_cap));
-
-	/* if extended timeout is supported in hardware,
-	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
-	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
-	 */
-	dc_link_aux_try_to_configure_timeout(link->ddc,
-			LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
-
-	status = core_link_read_dpcd(link, DP_SET_POWER,
-				&dpcd_power_state, sizeof(dpcd_power_state));
-
-	/* Delay 1 ms if AUX CH is in power down state. Based on spec
-	 * section 2.3.1.2, if AUX CH may be powered down due to
-	 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
-	 * signal and may need up to 1 ms before being able to reply.
-	 */
-	if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
-		udelay(1000);
-
-	dpcd_set_source_specific_data(link);
-	/* Sink may need to configure internals based on vendor, so allow some
-	 * time before proceeding with possibly vendor specific transactions
-	 */
-	msleep(post_oui_delay);
-
-	for (i = 0; i < read_dpcd_retry_cnt; i++) {
-		status = core_link_read_dpcd(
-				link,
-				DP_DPCD_REV,
-				dpcd_data,
-				sizeof(dpcd_data));
-		if (status == DC_OK)
-			break;
-	}
-
-	if (status != DC_OK) {
-		dm_error("%s: Read dpcd data failed.\n", __func__);
-		return false;
-	}
-
 	/* Query BIOS to determine if LTTPR functionality is forced on by system */
 	if (bios->funcs->get_lttpr_caps) {
 		enum bp_result bp_query_result;
@@ -3550,6 +3655,10 @@ static bool retrieve_link_cap(struct dc_link *link)
 				DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
 				lttpr_dpcd_data,
 				sizeof(lttpr_dpcd_data));
+		if (status != DC_OK) {
+			dm_error("%s: Read LTTPR caps data failed.\n", __func__);
+			return false;
+		}
 
 		link->dpcd_caps.lttpr_caps.revision.raw =
 				lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
@@ -3575,20 +3684,92 @@ static bool retrieve_link_cap(struct dc_link *link)
 				lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
 								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 
-		is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
+		/* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
+		is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
 				link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
 				link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
 				link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
-		if (is_lttpr_present)
+		if (is_lttpr_present) {
 			CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
-		else
+			configure_lttpr_mode_transparent(link);
+		} else
 			link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 	}
+	return is_lttpr_present;
+}
+
+static bool retrieve_link_cap(struct dc_link *link)
+{
+	/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
+	 * which means size 16 will be good for both of those DPCD register block reads
+	 */
+	uint8_t dpcd_data[16];
+	/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
+	 */
+	uint8_t dpcd_dprx_data = '\0';
+	uint8_t dpcd_power_state = '\0';
+
+	struct dp_device_vendor_id sink_id;
+	union down_stream_port_count down_strm_port_count;
+	union edp_configuration_cap edp_config_cap;
+	union dp_downstream_port_present ds_port = { 0 };
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	uint32_t read_dpcd_retry_cnt = 3;
+	int i;
+	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+	const uint32_t post_oui_delay = 30; // 30ms
+	bool is_lttpr_present = false;
+
+	memset(dpcd_data, '\0', sizeof(dpcd_data));
+	memset(&down_strm_port_count,
+		'\0', sizeof(union down_stream_port_count));
+	memset(&edp_config_cap, '\0',
+		sizeof(union edp_configuration_cap));
+
+	/* if extended timeout is supported in hardware,
+	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
+	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
+	 */
+	dc_link_aux_try_to_configure_timeout(link->ddc,
+			LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
+
+	is_lttpr_present = dp_retrieve_lttpr_cap(link);
+
+	status = core_link_read_dpcd(link, DP_SET_POWER,
+			&dpcd_power_state, sizeof(dpcd_power_state));
+
+	/* Delay 1 ms if AUX CH is in power down state. Based on spec
+	 * section 2.3.1.2, if AUX CH may be powered down due to
+	 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
+	 * signal and may need up to 1 ms before being able to reply.
+	 */
+	if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
+		udelay(1000);
+
+	dpcd_set_source_specific_data(link);
+	/* Sink may need to configure internals based on vendor, so allow some
+	 * time before proceeding with possibly vendor specific transactions
+	 */
+	msleep(post_oui_delay);
+
+	for (i = 0; i < read_dpcd_retry_cnt; i++) {
+		status = core_link_read_dpcd(
+				link,
+				DP_DPCD_REV,
+				dpcd_data,
+				sizeof(dpcd_data));
+		if (status == DC_OK)
+			break;
+	}
+
+	if (status != DC_OK) {
+		dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
+		return false;
+	}
 
 	if (!is_lttpr_present)
 		dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
 
-
 	{
 		union training_aux_rd_interval aux_rd_interval;
 
@@ -3892,7 +4073,11 @@ void detect_edp_sink_caps(struct dc_link *link)
 	link->dpcd_caps.edp_supported_link_rates_count = 0;
 	memset(supported_link_rates, 0, sizeof(supported_link_rates));
 
-	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
+	/*
+	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
+	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
+	 */
+	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
 			(link->dc->debug.optimize_edp_link_rate ||
 			link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
 		// Read DPCD 00010h - 0001Fh 16 bytes at one shot
@@ -4472,50 +4657,74 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
 	return DP_PANEL_MODE_DEFAULT;
 }
 
-void dp_set_fec_ready(struct dc_link *link, bool ready)
+enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
 {
 	/* FEC has to be "set ready" before the link training.
 	 * The policy is to always train with FEC
 	 * if the sink supports it and leave it enabled on link.
 	 * If FEC is not supported, disable it.
 	 */
-	struct link_encoder *link_enc = link->link_enc;
+	struct link_encoder *link_enc = NULL;
+	enum dc_status status = DC_OK;
 	uint8_t fec_config = 0;
 
+	/* Access link encoder based on whether it is statically
+	 * or dynamically assigned to a link.
+	 */
+	if (link->is_dig_mapping_flexible &&
+			link->dc->res_pool->funcs->link_encs_assign)
+		link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+	else
+		link_enc = link->link_enc;
+	ASSERT(link_enc);
+
 	if (!dc_link_should_enable_fec(link))
-		return;
+		return status;
 
 	if (link_enc->funcs->fec_set_ready &&
 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
 		if (ready) {
 			fec_config = 1;
-			if (core_link_write_dpcd(link,
+			status = core_link_write_dpcd(link,
 					DP_FEC_CONFIGURATION,
 					&fec_config,
-					sizeof(fec_config)) == DC_OK) {
+					sizeof(fec_config));
+			if (status == DC_OK) {
 				link_enc->funcs->fec_set_ready(link_enc, true);
 				link->fec_state = dc_link_fec_ready;
 			} else {
-				link->link_enc->funcs->fec_set_ready(link->link_enc, false);
+				link_enc->funcs->fec_set_ready(link->link_enc, false);
 				link->fec_state = dc_link_fec_not_ready;
 				dm_error("dpcd write failed to set fec_ready");
 			}
 		} else if (link->fec_state == dc_link_fec_ready) {
 			fec_config = 0;
-			core_link_write_dpcd(link,
+			status = core_link_write_dpcd(link,
 					DP_FEC_CONFIGURATION,
 					&fec_config,
 					sizeof(fec_config));
-			link->link_enc->funcs->fec_set_ready(
-					link->link_enc, false);
+			link_enc->funcs->fec_set_ready(link_enc, false);
 			link->fec_state = dc_link_fec_not_ready;
 		}
 	}
+
+	return status;
 }
 
 void dp_set_fec_enable(struct dc_link *link, bool enable)
 {
-	struct link_encoder *link_enc = link->link_enc;
+	struct link_encoder *link_enc = NULL;
+
+	/* Access link encoder based on whether it is statically
+	 * or dynamically assigned to a link.
+	 */
+	if (link->is_dig_mapping_flexible &&
+			link->dc->res_pool->funcs->link_encs_assign)
+		link_enc = link_enc_cfg_get_link_enc_used_by_link(
+				link->dc->current_state, link);
+	else
+		link_enc = link->link_enc;
+	ASSERT(link_enc);
 
 	if (!dc_link_should_enable_fec(link))
 		return;
@@ -4766,4 +4975,11 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin
 	return false;
 }
 
+enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
+{
+	if ((link_settings->link_rate >= LINK_RATE_LOW) &&
+			(link_settings->link_rate <= LINK_RATE_HIGH3))
+		return DP_8b_10b_ENCODING;
+	return DP_UNKNOWN_ENCODING;
+}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
new file mode 100644
index 000000000000..fe234760a0f5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
@@ -0,0 +1,218 @@
+#include <inc/core_status.h>
+#include <dc_link.h>
+#include <inc/link_hwss.h>
+#include <inc/link_dpcd.h>
+#include "drm/drm_dp_helper.h"
+#include <dc_dp_types.h>
+#include "dm_helpers.h"
+
+#define END_ADDRESS(start, size) (start + size - 1)
+#define ADDRESS_RANGE_SIZE(start, end) (end - start + 1)
+struct dpcd_address_range {
+	uint32_t start;
+	uint32_t end;
+};
+
+static enum dc_status internal_link_read_dpcd(
+	struct dc_link *link,
+	uint32_t address,
+	uint8_t *data,
+	uint32_t size)
+{
+	if (!link->aux_access_disabled &&
+			!dm_helpers_dp_read_dpcd(link->ctx,
+			link, address, data, size)) {
+		return DC_ERROR_UNEXPECTED;
+	}
+
+	return DC_OK;
+}
+
+static enum dc_status internal_link_write_dpcd(
+	struct dc_link *link,
+	uint32_t address,
+	const uint8_t *data,
+	uint32_t size)
+{
+	if (!link->aux_access_disabled &&
+			!dm_helpers_dp_write_dpcd(link->ctx,
+			link, address, data, size)) {
+		return DC_ERROR_UNEXPECTED;
+	}
+
+	return DC_OK;
+}
+
+/*
+ * Partition the entire DPCD address space
+ * XXX: This partitioning must cover the entire DPCD address space,
+ * and must contain no gaps or overlapping address ranges.
+ */
+static const struct dpcd_address_range mandatory_dpcd_partitions[] = {
+	{ 0, DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1) - 1},
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8) - 1 },
+	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
+	/*
+	 * The FEC registers are contiguous
+	 */
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
+	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR8), DP_LTTPR_MAX_ADD },
+	/* all remaining DPCD addresses */
+	{ DP_LTTPR_MAX_ADD + 1, DP_DPCD_MAX_ADD } };
+
+static inline bool do_addresses_intersect_with_range(
+		const struct dpcd_address_range *range,
+		const uint32_t start_address,
+		const uint32_t end_address)
+{
+	return start_address <= range->end && end_address >= range->start;
+}
+
+static uint32_t dpcd_get_next_partition_size(const uint32_t address, const uint32_t size)
+{
+	const uint32_t end_address = END_ADDRESS(address, size);
+	uint32_t partition_iterator = 0;
+
+	/*
+	 * find current partition
+	 * this loop spins forever if partition map above is not surjective
+	 */
+	while (!do_addresses_intersect_with_range(&mandatory_dpcd_partitions[partition_iterator],
+				address, end_address))
+		partition_iterator++;
+	if (end_address < mandatory_dpcd_partitions[partition_iterator].end)
+		return size;
+	return ADDRESS_RANGE_SIZE(address, mandatory_dpcd_partitions[partition_iterator].end);
+}
+
+/*
+ * Ranges of DPCD addresses that must be read in a single transaction
+ * XXX: Do not allow any two address ranges in this array to overlap
+ */
+static const struct dpcd_address_range mandatory_dpcd_blocks[] = {
+	{ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT }};
+
+/*
+ * extend addresses to read all mandatory blocks together
+ */
+static void dpcd_extend_address_range(
+		const uint32_t in_address,
+		uint8_t * const in_data,
+		const uint32_t in_size,
+		uint32_t *out_address,
+		uint8_t **out_data,
+		uint32_t *out_size)
+{
+	const uint32_t end_address = END_ADDRESS(in_address, in_size);
+	const struct dpcd_address_range *addr_range;
+	struct dpcd_address_range new_addr_range;
+	uint32_t i;
+
+	new_addr_range.start = in_address;
+	new_addr_range.end = end_address;
+	for (i = 0; i < ARRAY_SIZE(mandatory_dpcd_blocks); i++) {
+		addr_range = &mandatory_dpcd_blocks[i];
+		if (addr_range->start <= in_address && addr_range->end >= in_address)
+			new_addr_range.start = addr_range->start;
+
+		if (addr_range->start <= end_address && addr_range->end >= end_address)
+			new_addr_range.end = addr_range->end;
+	}
+	*out_address = in_address;
+	*out_size = in_size;
+	*out_data = in_data;
+	if (new_addr_range.start != in_address || new_addr_range.end != end_address) {
+		*out_address = new_addr_range.start;
+		*out_size = ADDRESS_RANGE_SIZE(new_addr_range.start, new_addr_range.end);
+		*out_data = kzalloc(*out_size * sizeof(**out_data), GFP_KERNEL);
+	}
+}
+
+/*
+ * Reduce the AUX reply down to the values the caller requested
+ */
+static void dpcd_reduce_address_range(
+		const uint32_t extended_address,
+		uint8_t * const extended_data,
+		const uint32_t extended_size,
+		const uint32_t reduced_address,
+		uint8_t * const reduced_data,
+		const uint32_t reduced_size)
+{
+	const uint32_t reduced_end_address = END_ADDRESS(reduced_address, reduced_size);
+	const uint32_t extended_end_address = END_ADDRESS(extended_address, extended_size);
+	const uint32_t offset = reduced_address - extended_address;
+
+	if (extended_end_address == reduced_end_address && extended_address == reduced_address)
+		return; /* extended and reduced address ranges point to the same data */
+
+	memcpy(&extended_data[offset], reduced_data, reduced_size);
+	kfree(extended_data);
+}
+
+enum dc_status core_link_read_dpcd(
+	struct dc_link *link,
+	uint32_t address,
+	uint8_t *data,
+	uint32_t size)
+{
+	uint32_t extended_address;
+	uint32_t partitioned_address;
+	uint8_t *extended_data;
+	uint32_t extended_size;
+	/* size of the remaining partitioned address space */
+	uint32_t size_left_to_read;
+	enum dc_status status;
+	/* size of the next partition to be read from */
+	uint32_t partition_size;
+	uint32_t data_index = 0;
+
+	dpcd_extend_address_range(address, data, size, &extended_address, &extended_data, &extended_size);
+	partitioned_address = extended_address;
+	size_left_to_read = extended_size;
+	while (size_left_to_read) {
+		partition_size = dpcd_get_next_partition_size(partitioned_address, size_left_to_read);
+		status = internal_link_read_dpcd(link, partitioned_address, &extended_data[data_index], partition_size);
+		if (status != DC_OK)
+			break;
+		partitioned_address += partition_size;
+		data_index += partition_size;
+		size_left_to_read -= partition_size;
+	}
+	dpcd_reduce_address_range(extended_address, extended_data, extended_size, address, data, size);
+	return status;
+}
+
+enum dc_status core_link_write_dpcd(
+	struct dc_link *link,
+	uint32_t address,
+	const uint8_t *data,
+	uint32_t size)
+{
+	uint32_t partition_size;
+	uint32_t data_index = 0;
+	enum dc_status status;
+
+	while (size) {
+		partition_size = dpcd_get_next_partition_size(address, size);
+		status = internal_link_write_dpcd(link, address, &data[data_index], partition_size);
+		if (status != DC_OK)
+			break;
+		address += partition_size;
+		data_index += partition_size;
+		size -= partition_size;
+	}
+	return status;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 1361b87d86d7..1a89d565c92e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -112,8 +112,8 @@ static void update_link_enc_assignment(
 
 /* Return first available DIG link encoder. */
 static enum engine_id find_first_avail_link_enc(
-		struct dc_context *ctx,
-		struct dc_state *state)
+		const struct dc_context *ctx,
+		const struct dc_state *state)
 {
 	enum engine_id eng_id = ENGINE_ID_UNKNOWN;
 	int i;
@@ -270,7 +270,7 @@ struct dc_link *link_enc_cfg_get_link_using_link_enc(
 
 struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(
 		struct dc_state *state,
-		struct dc_link *link)
+		const struct dc_link *link)
 {
 	struct link_encoder *link_enc = NULL;
 	struct display_endpoint_id ep_id;
@@ -296,8 +296,20 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(
 
 	if (stream_idx != -1)
 		link_enc = state->streams[stream_idx]->link_enc;
-	else
-		dm_output_to_console("%s: No link encoder used by link(%d).\n", __func__, link->link_index);
+
+	return link_enc;
+}
+
+struct link_encoder *link_enc_cfg_get_next_avail_link_enc(
+	const struct dc *dc,
+	const struct dc_state *state)
+{
+	struct link_encoder *link_enc = NULL;
+	enum engine_id eng_id = ENGINE_ID_UNKNOWN;
+
+	eng_id = find_first_avail_link_enc(dc->ctx, state);
+	if (eng_id != ENGINE_ID_UNKNOWN)
+		link_enc = dc->res_pool->link_encoders[eng_id - ENGINE_ID_DIGA];
 
 	return link_enc;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index b426f878fb99..9c51cd09dcf1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -16,6 +16,7 @@
 #include "resource.h"
 #include "link_enc_cfg.h"
 #include "clk_mgr.h"
+#include "inc/link_dpcd.h"
 
 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
 {
@@ -47,36 +48,6 @@ static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset
 	return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);
 }
 
-enum dc_status core_link_read_dpcd(
-	struct dc_link *link,
-	uint32_t address,
-	uint8_t *data,
-	uint32_t size)
-{
-	if (!link->aux_access_disabled &&
-			!dm_helpers_dp_read_dpcd(link->ctx,
-			link, address, data, size)) {
-		return DC_ERROR_UNEXPECTED;
-	}
-
-	return DC_OK;
-}
-
-enum dc_status core_link_write_dpcd(
-	struct dc_link *link,
-	uint32_t address,
-	const uint8_t *data,
-	uint32_t size)
-{
-	if (!link->aux_access_disabled &&
-			!dm_helpers_dp_write_dpcd(link->ctx,
-			link, address, data, size)) {
-		return DC_ERROR_UNEXPECTED;
-	}
-
-	return DC_OK;
-}
-
 void dp_receiver_power_ctrl(struct dc_link *link, bool on)
 {
 	uint8_t state;
@@ -332,7 +303,16 @@ void dp_set_hw_test_pattern(
 	uint32_t custom_pattern_size)
 {
 	struct encoder_set_dp_phy_pattern_param pattern_param = {0};
-	struct link_encoder *encoder = link->link_enc;
+	struct link_encoder *encoder;
+
+	/* Access link encoder based on whether it is statically
+	 * or dynamically assigned to a link.
+	 */
+	if (link->is_dig_mapping_flexible &&
+			link->dc->res_pool->funcs->link_encs_assign)
+		encoder = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+	else
+		encoder = link->link_enc;
 
 	pattern_param.dp_phy_pattern = test_pattern;
 	pattern_param.custom_pattern = custom_pattern;
@@ -384,7 +364,8 @@ void dp_retrain_link_dp_test(struct dc_link *link,
 					skip_video_pattern,
 					LINK_TRAINING_ATTEMPTS,
 					&pipes[i],
-					SIGNAL_TYPE_DISPLAY_PORT);
+					SIGNAL_TYPE_DISPLAY_PORT,
+					false);
 
 			link->dc->hwss.enable_stream(&pipes[i]);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8cb937c046aa..a6a67244a322 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -57,6 +57,8 @@
 #include "dcn30/dcn30_resource.h"
 #include "dcn301/dcn301_resource.h"
 #include "dcn302/dcn302_resource.h"
+#include "dcn303/dcn303_resource.h"
+#include "dcn31/dcn31_resource.h"
 #endif
 
 #define DC_LOGGER_INIT(logger)
@@ -130,12 +132,20 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 			dc_version = DCN_VERSION_3_0;
 		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
 			dc_version = DCN_VERSION_3_02;
+		if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
+			dc_version = DCN_VERSION_3_03;
 		break;
 
 	case FAMILY_VGH:
 		dc_version = DCN_VERSION_3_01;
 		break;
+
+	case FAMILY_YELLOW_CARP:
+		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
+			dc_version = DCN_VERSION_3_1;
+		break;
 #endif
+
 	default:
 		dc_version = DCE_VERSION_UNKNOWN;
 		break;
@@ -216,6 +226,12 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 	case DCN_VERSION_3_02:
 		res_pool = dcn302_create_resource_pool(init_data, dc);
 		break;
+	case DCN_VERSION_3_03:
+		res_pool = dcn303_create_resource_pool(init_data, dc);
+		break;
+	case DCN_VERSION_3_1:
+		res_pool = dcn31_create_resource_pool(init_data, dc);
+		break;
 #endif
 	default:
 		break;
@@ -423,7 +439,7 @@ bool resource_are_vblanks_synchronizable(
 {
 	uint32_t base60_refresh_rates[] = {10, 20, 5};
 	uint8_t i;
-	uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]);
+	uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
 	uint64_t frame_time_diff;
 
 	if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
@@ -605,6 +621,7 @@ static enum pixel_format convert_pixel_format_to_dalsurface(
 		dal_pixel_format = PIXEL_FORMAT_420BPP10;
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 	default:
 		dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
 		break;
@@ -695,124 +712,23 @@ static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *spli
 	}
 }
 
-static void calculate_viewport(struct pipe_ctx *pipe_ctx)
+/*
+ * This is a preliminary vp size calculation to allow us to check taps support.
+ * The result is completely overridden afterwards.
+ */
+static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
 {
-	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-	const struct dc_stream_state *stream = pipe_ctx->stream;
 	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
-	struct rect surf_src = plane_state->src_rect;
-	struct rect clip, dest;
-	int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
-			|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
-	int split_count = 0;
-	int split_idx = 0;
-	bool orthogonal_rotation, flip_y_start, flip_x_start;
-
-	calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
-
-	if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
-		stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
-		split_count = 0;
-		split_idx = 0;
-	}
-
-	/* The actual clip is an intersection between stream
-	 * source and surface clip
-	 */
-	dest = plane_state->dst_rect;
-	clip.x = stream->src.x > plane_state->clip_rect.x ?
-			stream->src.x : plane_state->clip_rect.x;
-
-	clip.width = stream->src.x + stream->src.width <
-			plane_state->clip_rect.x + plane_state->clip_rect.width ?
-			stream->src.x + stream->src.width - clip.x :
-			plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
-
-	clip.y = stream->src.y > plane_state->clip_rect.y ?
-			stream->src.y : plane_state->clip_rect.y;
-
-	clip.height = stream->src.y + stream->src.height <
-			plane_state->clip_rect.y + plane_state->clip_rect.height ?
-			stream->src.y + stream->src.height - clip.y :
-			plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
 
-	/*
-	 * Need to calculate how scan origin is shifted in vp space
-	 * to correctly rotate clip and dst
-	 */
-	get_vp_scan_direction(
-			plane_state->rotation,
-			plane_state->horizontal_mirror,
-			&orthogonal_rotation,
-			&flip_y_start,
-			&flip_x_start);
-
-	if (orthogonal_rotation) {
-		swap(clip.x, clip.y);
-		swap(clip.width, clip.height);
-		swap(dest.x, dest.y);
-		swap(dest.width, dest.height);
-	}
-	if (flip_x_start) {
-		clip.x = dest.x + dest.width - clip.x - clip.width;
-		dest.x = 0;
-	}
-	if (flip_y_start) {
-		clip.y = dest.y + dest.height - clip.y - clip.height;
-		dest.y = 0;
-	}
-
-	/* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
-	 * num_pixels = clip.num_pix * scl_ratio
-	 */
-	data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
-	data->viewport.width = clip.width * surf_src.width / dest.width;
-
-	data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
-	data->viewport.height = clip.height * surf_src.height / dest.height;
-
-	/* Handle split */
-	if (split_count) {
-		/* extra pixels in the division remainder need to go to pipes after
-		 * the extra pixel index minus one(epimo) defined here as:
-		 */
-		int epimo = 0;
-
-		if (orthogonal_rotation) {
-			if (flip_y_start)
-				split_idx = split_count - split_idx;
-
-			epimo = split_count - data->viewport.height % (split_count + 1);
-
-			data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
-			if (split_idx > epimo)
-				data->viewport.y += split_idx - epimo - 1;
-			data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
-		} else {
-			if (flip_x_start)
-				split_idx = split_count - split_idx;
-
-			epimo = split_count - data->viewport.width % (split_count + 1);
-
-			data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
-			if (split_idx > epimo)
-				data->viewport.x += split_idx - epimo - 1;
-			data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
-		}
+	data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width));
+	data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height));
+	data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width));
+	data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height));
+	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
+			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
+		swap(data->viewport.width, data->viewport.height);
+		swap(data->viewport_c.width, data->viewport_c.height);
 	}
-
-	/* Round down, compensate in init */
-	data->viewport_c.x = data->viewport.x / vpc_div;
-	data->viewport_c.y = data->viewport.y / vpc_div;
-	data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
-	data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
-
-	/* Round up, assume original video size always even dimensions */
-	data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
-	data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
-
-	data->viewport_unadjusted = data->viewport;
-	data->viewport_c_unadjusted = data->viewport_c;
 }
 
 static void calculate_recout(struct pipe_ctx *pipe_ctx)
@@ -821,26 +737,21 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
 	const struct dc_stream_state *stream = pipe_ctx->stream;
 	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 	struct rect surf_clip = plane_state->clip_rect;
-	bool pri_split_tb = pipe_ctx->bottom_pipe &&
-			pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
-			stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
-	bool sec_split_tb = pipe_ctx->top_pipe &&
-			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
-			stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
-	int split_count = 0;
-	int split_idx = 0;
+	bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
+	int split_count, split_idx;
 
 	calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
+	if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
+		split_idx = 0;
 
 	/*
 	 * Only the leftmost ODM pipe should be offset by a nonzero distance
 	 */
-	if (!pipe_ctx->prev_odm_pipe) {
+	if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) {
 		data->recout.x = stream->dst.x;
 		if (stream->src.x < surf_clip.x)
 			data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
 						/ stream->src.width;
-
 	} else
 		data->recout.x = 0;
 
@@ -861,26 +772,36 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
 	if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
 		data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
 
-	/* Handle h & v split, handle rotation using viewport */
-	if (sec_split_tb) {
-		data->recout.y += data->recout.height / 2;
-		/* Floor primary pipe, ceil 2ndary pipe */
-		data->recout.height = (data->recout.height + 1) / 2;
-	} else if (pri_split_tb)
+	/* Handle h & v split */
+	if (split_tb) {
+		ASSERT(data->recout.height % 2 == 0);
 		data->recout.height /= 2;
-	else if (split_count) {
-		/* extra pixels in the division remainder need to go to pipes after
-		 * the extra pixel index minus one(epimo) defined here as:
-		 */
-		int epimo = split_count - data->recout.width % (split_count + 1);
-
-		/*no recout offset due to odm */
+	} else if (split_count) {
 		if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
+			/* extra pixels in the division remainder need to go to pipes after
+			 * the extra pixel index minus one(epimo) defined here as:
+			 */
+			int epimo = split_count - data->recout.width % (split_count + 1);
+
 			data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
 			if (split_idx > epimo)
 				data->recout.x += split_idx - epimo - 1;
+			ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0);
+			data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
+		} else {
+			/* odm */
+			if (split_idx == split_count) {
+				/* rightmost pipe is the remainder recout */
+				data->recout.width -= data->h_active * split_count - data->recout.x;
+
+				/* ODM combine cases with MPO we can get negative widths */
+				if (data->recout.width < 0)
+					data->recout.width = 0;
+
+				data->recout.x = 0;
+			} else
+				data->recout.width = data->h_active - data->recout.x;
 		}
-		data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
 	}
 }
 
@@ -934,9 +855,15 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
 			pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 }
 
-static inline void adjust_vp_and_init_for_seamless_clip(
+
+/*
+ * We completely calculate vp offset, size and inits here based entirely on scaling
+ * ratios and recout for pixel perfect pipe combine.
+ */
+static void calculate_init_and_vp(
 		bool flip_scan_dir,
-		int recout_skip,
+		int recout_offset_within_recout_full,
+		int recout_size,
 		int src_size,
 		int taps,
 		struct fixed31_32 ratio,
@@ -944,91 +871,87 @@ static inline void adjust_vp_and_init_for_seamless_clip(
 		int *vp_offset,
 		int *vp_size)
 {
-	if (!flip_scan_dir) {
-		/* Adjust for viewport end clip-off */
-		if ((*vp_offset + *vp_size) < src_size) {
-			int vp_clip = src_size - *vp_size - *vp_offset;
-			int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
+	struct fixed31_32 temp;
+	int int_part;
 
-			int_part = int_part > 0 ? int_part : 0;
-			*vp_size += int_part < vp_clip ? int_part : vp_clip;
-		}
-
-		/* Adjust for non-0 viewport offset */
-		if (*vp_offset) {
-			int int_part;
-
-			*init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
-			int_part = dc_fixpt_floor(*init) - *vp_offset;
-			if (int_part < taps) {
-				int int_adj = *vp_offset >= (taps - int_part) ?
-							(taps - int_part) : *vp_offset;
-				*vp_offset -= int_adj;
-				*vp_size += int_adj;
-				int_part += int_adj;
-			} else if (int_part > taps) {
-				*vp_offset += int_part - taps;
-				*vp_size -= int_part - taps;
-				int_part = taps;
-			}
-			init->value &= 0xffffffff;
-			*init = dc_fixpt_add_int(*init, int_part);
-		}
-	} else {
-		/* Adjust for non-0 viewport offset */
-		if (*vp_offset) {
-			int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
-
-			int_part = int_part > 0 ? int_part : 0;
-			*vp_size += int_part < *vp_offset ? int_part : *vp_offset;
-			*vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
-		}
-
-		/* Adjust for viewport end clip-off */
-		if ((*vp_offset + *vp_size) < src_size) {
-			int int_part;
-			int end_offset = src_size - *vp_offset - *vp_size;
-
-			/*
-			 * this is init if vp had no offset, keep in mind this is from the
-			 * right side of vp due to scan direction
-			 */
-			*init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
-			/*
-			 * this is the difference between first pixel of viewport available to read
-			 * and init position, takning into account scan direction
-			 */
-			int_part = dc_fixpt_floor(*init) - end_offset;
-			if (int_part < taps) {
-				int int_adj = end_offset >= (taps - int_part) ?
-							(taps - int_part) : end_offset;
-				*vp_size += int_adj;
-				int_part += int_adj;
-			} else if (int_part > taps) {
-				*vp_size += int_part - taps;
-				int_part = taps;
-			}
-			init->value &= 0xffffffff;
-			*init = dc_fixpt_add_int(*init, int_part);
-		}
+	/*
+	 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
+	 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
+	 * All following calculations are based on this logic.
+	 *
+	 * Init calculated according to formula:
+	 * 	init = (scaling_ratio + number_of_taps + 1) / 2
+	 * 	init_bot = init + scaling_ratio
+	 * 	to get pixel perfect combine add the fraction from calculating vp offset
+	 */
+	temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
+	*vp_offset = dc_fixpt_floor(temp);
+	temp.value &= 0xffffffff;
+	*init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
+			dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
+	/*
+	 * If viewport has non 0 offset and there are more taps than covered by init then
+	 * we should decrease the offset and increase init so we are never sampling
+	 * outside of viewport.
+	 */
+	int_part = dc_fixpt_floor(*init);
+	if (int_part < taps) {
+		int_part = taps - int_part;
+		if (int_part > *vp_offset)
+			int_part = *vp_offset;
+		*vp_offset -= int_part;
+		*init = dc_fixpt_add_int(*init, int_part);
 	}
+	/*
+	 * If taps are sampling outside of viewport at end of recout and there are more pixels
+	 * available in the surface we should increase the viewport size, regardless set vp to
+	 * only what is used.
+	 */
+	temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
+	*vp_size = dc_fixpt_floor(temp);
+	if (*vp_size + *vp_offset > src_size)
+		*vp_size = src_size - *vp_offset;
+
+	/* We did all the math assuming we are scanning same direction as display does,
+	 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
+	 * is flipped we simply need to calculate offset from the other side of plane.
+	 * Note that outside of viewport all scaling hardware works in recout space.
+	 */
+	if (flip_scan_dir)
+		*vp_offset = src_size - *vp_offset - *vp_size;
 }
 
-static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
+static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
 {
 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	const struct dc_stream_state *stream = pipe_ctx->stream;
-	struct pipe_ctx *odm_pipe = pipe_ctx;
 	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
-	struct rect src = pipe_ctx->plane_state->src_rect;
-	int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
+	struct rect src = plane_state->src_rect;
 	int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
-			|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
+				|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
+	int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y;
 	bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
-	int odm_idx = 0;
+
+	calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
+	/*
+	 * recout full is what the recout would have been if we didnt clip
+	 * the source plane at all. We only care about left(ro_lb) and top(ro_tb)
+	 * offsets of recout within recout full because those are the directions
+	 * we scan from and therefore the only ones that affect inits.
+	 */
+	recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
+			* stream->dst.width / stream->src.width;
+	recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
+			* stream->dst.height / stream->src.height;
+	if (pipe_ctx->prev_odm_pipe && split_idx)
+		ro_lb = data->h_active * split_idx - recout_full_x;
+	else
+		ro_lb = data->recout.x - recout_full_x;
+	ro_tb = data->recout.y - recout_full_y;
+	ASSERT(ro_lb >= 0 && ro_tb >= 0);
 
 	/*
-	 * Need to calculate the scan direction for viewport to make adjustments
+	 * Work in recout rotation since that requires less transformations
 	 */
 	get_vp_scan_direction(
 			plane_state->rotation,
@@ -1037,145 +960,62 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
 			&flip_vert_scan_dir,
 			&flip_horz_scan_dir);
 
-	/* Calculate src rect rotation adjusted to recout space */
-	surf_size_h = src.x + src.width;
-	surf_size_v = src.y + src.height;
-	if (flip_horz_scan_dir)
-		src.x = 0;
-	if (flip_vert_scan_dir)
-		src.y = 0;
 	if (orthogonal_rotation) {
-		swap(src.x, src.y);
 		swap(src.width, src.height);
+		swap(flip_vert_scan_dir, flip_horz_scan_dir);
 	}
 
-	/*modified recout_skip_h calculation due to odm having no recout offset*/
-	while (odm_pipe->prev_odm_pipe) {
-		odm_idx++;
-		odm_pipe = odm_pipe->prev_odm_pipe;
-	}
-	/*odm_pipe is the leftmost pipe in the ODM group*/
-	recout_skip_h = odm_idx * data->recout.width;
-
-	/* Recout matching initial vp offset = recout_offset - (stream dst offset +
-	 *			((surf dst offset - stream src offset) * 1/ stream scaling ratio)
-	 *			- (surf surf_src offset * 1/ full scl ratio))
-	 */
-	recout_skip_h += odm_pipe->plane_res.scl_data.recout.x
-				- (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
-					* stream->dst.width / stream->src.width -
-					src.x * plane_state->dst_rect.width / src.width
-					* stream->dst.width / stream->src.width);
-
-
-	recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
-					* stream->dst.height / stream->src.height -
-					src.y * plane_state->dst_rect.height / src.height
-					* stream->dst.height / stream->src.height);
-	if (orthogonal_rotation)
-		swap(recout_skip_h, recout_skip_v);
-	/*
-	 * Init calculated according to formula:
-	 * 	init = (scaling_ratio + number_of_taps + 1) / 2
-	 * 	init_bot = init + scaling_ratio
-	 * 	init_c = init + truncated_vp_c_offset(from calculate viewport)
-	 */
-	data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
-			dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
-
-	data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
-			dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
-
-	data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
-			dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
-
-	data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
-			dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
-
-	/*
-	 * Taps, inits and scaling ratios are in recout space need to rotate
-	 * to viewport rotation before adjustment
-	 */
-	adjust_vp_and_init_for_seamless_clip(
+	calculate_init_and_vp(
 			flip_horz_scan_dir,
-			recout_skip_h,
-			surf_size_h,
-			orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
-			orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
-			orthogonal_rotation ? &data->inits.v : &data->inits.h,
+			ro_lb,
+			data->recout.width,
+			src.width,
+			data->taps.h_taps,
+			data->ratios.horz,
+			&data->inits.h,
 			&data->viewport.x,
 			&data->viewport.width);
-	adjust_vp_and_init_for_seamless_clip(
+	calculate_init_and_vp(
 			flip_horz_scan_dir,
-			recout_skip_h,
-			surf_size_h / vpc_div,
-			orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
-			orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
-			orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
+			ro_lb,
+			data->recout.width,
+			src.width / vpc_div,
+			data->taps.h_taps_c,
+			data->ratios.horz_c,
+			&data->inits.h_c,
 			&data->viewport_c.x,
 			&data->viewport_c.width);
-	adjust_vp_and_init_for_seamless_clip(
+	calculate_init_and_vp(
 			flip_vert_scan_dir,
-			recout_skip_v,
-			surf_size_v,
-			orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
-			orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
-			orthogonal_rotation ? &data->inits.h : &data->inits.v,
+			ro_tb,
+			data->recout.height,
+			src.height,
+			data->taps.v_taps,
+			data->ratios.vert,
+			&data->inits.v,
 			&data->viewport.y,
 			&data->viewport.height);
-	adjust_vp_and_init_for_seamless_clip(
+	calculate_init_and_vp(
 			flip_vert_scan_dir,
-			recout_skip_v,
-			surf_size_v / vpc_div,
-			orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
-			orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
-			orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
+			ro_tb,
+			data->recout.height,
+			src.height / vpc_div,
+			data->taps.v_taps_c,
+			data->ratios.vert_c,
+			&data->inits.v_c,
 			&data->viewport_c.y,
 			&data->viewport_c.height);
-
-	/* Interlaced inits based on final vert inits */
-	data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
-	data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
-
-}
-
-/*
- * When handling 270 rotation in mixed SLS mode, we have
- * stream->timing.h_border_left that is non zero.  If we are doing
- * pipe-splitting, this h_border_left value gets added to recout.x and when it
- * calls calculate_inits_and_adj_vp() and
- * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
- * pipe to be incorrect.
- *
- * To fix this, instead of using stream->timing.h_border_left, we can use
- * stream->dst.x to represent the border instead.  So we will set h_border_left
- * to 0 and shift the appropriate amount in stream->dst.x.  We will then
- * perform all calculations in resource_build_scaling_params() based on this
- * and then restore the h_border_left and stream->dst.x to their original
- * values.
- *
- * shift_border_left_to_dst() will shift the amount of h_border_left to
- * stream->dst.x and set h_border_left to 0.  restore_border_left_from_dst()
- * will restore h_border_left and stream->dst.x back to their original values
- * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
- * original h_border_left value in its calculation.
- */
-static int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
-{
-	int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
-
-	if (store_h_border_left) {
-		pipe_ctx->stream->timing.h_border_left = 0;
-		pipe_ctx->stream->dst.x += store_h_border_left;
+	if (orthogonal_rotation) {
+		swap(data->viewport.x, data->viewport.y);
+		swap(data->viewport.width, data->viewport.height);
+		swap(data->viewport_c.x, data->viewport_c.y);
+		swap(data->viewport_c.width, data->viewport_c.height);
 	}
-	return store_h_border_left;
-}
-
-static void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
-					 int store_h_border_left)
-{
-	pipe_ctx->stream->dst.x -= store_h_border_left;
-	pipe_ctx->stream->timing.h_border_left = store_h_border_left;
+	data->viewport.x += src.x;
+	data->viewport.y += src.y;
+	ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
+	data->viewport_c.x += src.x / vpc_div;
+	data->viewport_c.y += src.y / vpc_div;
 }
 
 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
@@ -1183,48 +1023,52 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 	bool res = false;
-	int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
-	/* Important: scaling ratio calculation requires pixel format,
-	 * lb depth calculation requires recout and taps require scaling ratios.
-	 * Inits require viewport, taps, ratios and recout of split pipe
-	 */
+
 	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
 			pipe_ctx->plane_state->format);
 
-	calculate_scaling_ratios(pipe_ctx);
-
-	calculate_viewport(pipe_ctx);
-
-	if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
-		pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) {
-		if (store_h_border_left) {
-			restore_border_left_from_dst(pipe_ctx,
-				store_h_border_left);
-		}
-		return false;
-	}
-
-	calculate_recout(pipe_ctx);
-
-	/**
-	 * Setting line buffer pixel depth to 24bpp yields banding
-	 * on certain displays, such as the Sharp 4k
+	/* Timing borders are part of vactive that we are also supposed to skip in addition
+	 * to any stream dst offset. Since dm logic assumes dst is in addressable
+	 * space we need to add the the left and top borders to dst offsets temporarily.
+	 * TODO: fix in DM, stream dst is supposed to be in vactive
 	 */
-	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
-	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
-
-	pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
-	pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
+	pipe_ctx->stream->dst.x += timing->h_border_left;
+	pipe_ctx->stream->dst.y += timing->v_border_top;
 
+	/* Calculate H and V active size */
 	pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
-		store_h_border_left + timing->h_border_right;
+			timing->h_border_left + timing->h_border_right;
 	pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
 		timing->v_border_top + timing->v_border_bottom;
 	if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
 		pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
 
-	/* Taps calculations */
+	/* depends on h_active */
+	calculate_recout(pipe_ctx);
+	/* depends on pixel format */
+	calculate_scaling_ratios(pipe_ctx);
+	/* depends on scaling ratios and recout, does not calculate offset yet */
+	calculate_viewport_size(pipe_ctx);
+
+	/*
+	 * LB calculations depend on vp size, h/v_active and scaling ratios
+	 * Setting line buffer pixel depth to 24bpp yields banding
+	 * on certain displays, such as the Sharp 4k. 36bpp is needed
+	 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
+	 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
+	 * precision on at least DCN display engines. However, at least
+	 * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
+	 * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3
+	 * did not show such problems, so this seems to be the exception.
+	 */
+	if (plane_state->ctx->dce_version != DCE_VERSION_11_0)
+		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
+	else
+		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
+
+	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
+
 	if (pipe_ctx->plane_res.xfm != NULL)
 		res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
 				pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
@@ -1251,9 +1095,31 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 					&plane_state->scaling_quality);
 	}
 
+	/*
+	 * Depends on recout, scaling ratios, h_active and taps
+	 * May need to re-check lb size after this in some obscure scenario
+	 */
 	if (res)
-		/* May need to re-check lb size after this in some obscure scenario */
-		calculate_inits_and_adj_vp(pipe_ctx);
+		calculate_inits_and_viewports(pipe_ctx);
+
+	/*
+	 * Handle side by side and top bottom 3d recout offsets after vp calculation
+	 * since 3d is special and needs to calculate vp as if there is no recout offset
+	 * This may break with rotation, good thing we aren't mixing hw rotation and 3d
+	 */
+	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
+		ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
+			(pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
+				pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
+		if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
+			pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
+		else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
+			pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
+	}
+
+	if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
+			pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
+		res = false;
 
 	DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d  Recout: height:%d width:%d x:%d y:%d  HACTIVE:%d VACTIVE:%d\n"
 			"src_rect: height:%d width:%d x:%d y:%d  dst_rect: height:%d width:%d x:%d y:%d  clip_rect: height:%d width:%d x:%d y:%d\n",
@@ -1282,8 +1148,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 			plane_state->clip_rect.x,
 			plane_state->clip_rect.y);
 
-	if (store_h_border_left)
-		restore_border_left_from_dst(pipe_ctx, store_h_border_left);
+	pipe_ctx->stream->dst.x -= timing->h_border_left;
+	pipe_ctx->stream->dst.y -= timing->v_border_top;
 
 	return res;
 }
@@ -1706,12 +1572,6 @@ static bool is_timing_changed(struct dc_stream_state *cur_stream,
 	if (cur_stream == NULL)
 		return true;
 
-	/* If sink pointer changed, it means this is a hotplug, we should do
-	 * full hw setting.
-	 */
-	if (cur_stream->sink != new_stream->sink)
-		return true;
-
 	/* If output color space is changed, need to reprogram info frames */
 	if (cur_stream->output_color_space != new_stream->output_color_space)
 		return true;
@@ -2276,6 +2136,16 @@ enum dc_status dc_validate_global_state(
 
 	if (!new_ctx)
 		return DC_ERROR_UNEXPECTED;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+
+	/*
+	 * Update link encoder to stream assignment.
+	 * TODO: Split out reason allocation from validation.
+	 */
+	if (dc->res_pool->funcs->link_encs_assign)
+		dc->res_pool->funcs->link_encs_assign(
+			dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
+#endif
 
 	if (dc->res_pool->funcs->validate_global) {
 		result = dc->res_pool->funcs->validate_global(dc, new_ctx);
@@ -2679,6 +2549,7 @@ void dc_resource_state_destruct(struct dc_state *context)
 		dc_stream_release(context->streams[i]);
 		context->streams[i] = NULL;
 	}
+	context->stream_count = 0;
 }
 
 void dc_resource_state_copy_construct(
@@ -3045,6 +2916,7 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
 #endif
 		return 32;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 		return 64;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 25fa712a7847..45931ee14a6e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -294,6 +294,7 @@ bool dc_stream_set_cursor_attributes(
 	stream->cursor_attributes = *attributes;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+	dc_z10_restore(dc);
 	/* disable idle optimizations while updating cursor */
 	if (dc->idle_optimizations_allowed) {
 		dc_allow_idle_optimizations(dc, false);
@@ -355,6 +356,7 @@ bool dc_stream_set_cursor_position(
 	dc = stream->ctx->dc;
 	res_ctx = &dc->current_state->res_ctx;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+	dc_z10_restore(dc);
 
 	/* disable idle optimizations if enabling cursor */
 	if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 100d434f7a03..5101a4f8f69f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
 /* forward declaration */
 struct aux_payload;
 
-#define DC_VER "3.2.132"
+#define DC_VER "3.2.141"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
@@ -303,6 +303,7 @@ struct dc_config {
 	bool multi_mon_pp_mclk_switch;
 	bool disable_dmcu;
 	bool enable_4to1MPC;
+	bool allow_edp_hotplug_detection;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool clamp_min_dcfclk;
 #endif
@@ -318,6 +319,7 @@ enum visual_confirm {
 	VISUAL_CONFIRM_HDR = 2,
 	VISUAL_CONFIRM_MPCTREE = 4,
 	VISUAL_CONFIRM_PSR = 5,
+	VISUAL_CONFIRM_SWIZZLE = 9,
 };
 
 enum dcc_option {
@@ -350,6 +352,13 @@ enum dcn_pwr_state {
 	DCN_PWR_STATE_LOW_POWER = 3,
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+enum dcn_z9_support_state {
+	DCN_Z9_SUPPORT_UNKNOWN,
+	DCN_Z9_SUPPORT_ALLOW,
+	DCN_Z9_SUPPORT_DISALLOW,
+};
+#endif
 /*
  * For any clocks that may differ per pipe
  * only the max is stored in this structure
@@ -367,6 +376,10 @@ struct dc_clocks {
 	int phyclk_khz;
 	int dramclk_khz;
 	bool p_state_change_support;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	enum dcn_z9_support_state z9_support;
+	bool dtbclk_en;
+#endif
 	enum dcn_pwr_state pwr_state;
 	/*
 	 * Elements below are not compared for the purposes of
@@ -433,6 +446,7 @@ struct dc_bw_validation_profile {
 
 union mem_low_power_enable_options {
 	struct {
+		bool vga: 1;
 		bool i2c: 1;
 		bool dmcu: 1;
 		bool dscl: 1;
@@ -487,6 +501,9 @@ struct dc_debug_options {
 	bool disable_pplib_clock_request;
 	bool disable_clock_gate;
 	bool disable_mem_low_power;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	bool pstate_enabled;
+#endif
 	bool disable_dmcu;
 	bool disable_psr;
 	bool force_abm_enable;
@@ -505,6 +522,7 @@ struct dc_debug_options {
 	unsigned int force_odm_combine; //bit vector based on otg inst
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
+	bool disable_z9_mpc;
 #endif
 	unsigned int force_fclk_khz;
 	bool enable_tri_buf;
@@ -547,6 +565,10 @@ struct dc_debug_options {
 	bool force_enable_edp_fec;
 	/* FEC/PSR1 sequence enable delay in 100us */
 	uint8_t fec_enable_delay_in100us;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	bool disable_z10;
+	bool enable_sw_cntl_psr;
+#endif
 };
 
 struct dc_debug_data {
@@ -571,6 +593,9 @@ struct dc_phy_addr_space_config {
 		uint64_t page_table_start_addr;
 		uint64_t page_table_end_addr;
 		uint64_t page_table_base_addr;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		bool base_addr_is_mc_addr;
+#endif
 	} gart_config;
 
 	bool valid;
@@ -600,7 +625,6 @@ struct dc_bounding_box_overrides {
 	int min_dcfclk_mhz;
 };
 
-struct dc_state;
 struct resource_pool;
 struct dce_hwseq;
 struct gpu_info_soc_bounding_box_v1_0;
@@ -719,7 +743,6 @@ void dc_init_callbacks(struct dc *dc,
 void dc_deinit_callbacks(struct dc *dc);
 void dc_destroy(struct dc **dc);
 
-void dc_wait_for_vblank(struct dc *dc, struct dc_stream_state *stream);
 /*******************************************************************************
  * Surface Interfaces
  ******************************************************************************/
@@ -1071,8 +1094,6 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
  */
 bool dc_commit_state(struct dc *dc, struct dc_state *context);
 
-void dc_power_down_on_boot(struct dc *dc);
-
 struct dc_state *dc_create_state(struct dc *dc);
 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
 void dc_retain_state(struct dc_state *context);
@@ -1312,6 +1333,9 @@ void dc_hardware_release(struct dc *dc);
 #endif
 
 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+void dc_z10_restore(struct dc *dc);
+#endif
 
 bool dc_enable_dmub_notifications(struct dc *dc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 6b72af2b3f4c..360f3199ea6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -86,6 +86,7 @@ void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
 
 error:
 	DC_ERROR("Error queuing DMUB command: status=%d\n", status);
+	dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 }
 
 void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
@@ -95,8 +96,10 @@ void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
 	enum dmub_status status;
 
 	status = dmub_srv_cmd_execute(dmub);
-	if (status != DMUB_STATUS_OK)
+	if (status != DMUB_STATUS_OK) {
 		DC_ERROR("Error starting DMUB execution: status=%d\n", status);
+		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
+	}
 }
 
 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
@@ -106,8 +109,19 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
 	enum dmub_status status;
 
 	status = dmub_srv_wait_for_idle(dmub, 100000);
-	if (status != DMUB_STATUS_OK)
+	if (status != DMUB_STATUS_OK) {
 		DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
+		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
+	}
+}
+
+void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
+		union dmub_inbox0_data_register data)
+{
+	struct dmub_srv *dmub = dmub_srv->dmub;
+	if (dmub->hw_funcs.send_inbox0_cmd)
+		dmub->hw_funcs.send_inbox0_cmd(dmub, data);
+	// TODO: Add wait command -- poll register for ACK
 }
 
 bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd)
@@ -172,6 +186,28 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 		       stream_mask, timeout) == DMUB_STATUS_OK;
 }
 
+bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
+{
+	struct dmub_srv *dmub;
+	struct dc_context *dc_ctx;
+	union dmub_fw_boot_status boot_status;
+	enum dmub_status status;
+
+	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
+		return false;
+
+	dmub = dc_dmub_srv->dmub;
+	dc_ctx = dc_dmub_srv->ctx;
+
+	status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
+	if (status != DMUB_STATUS_OK) {
+		DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
+		return false;
+	}
+
+	return boot_status.bits.restore_required;
+}
+
 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
 {
 	struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
@@ -180,5 +216,96 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_bu
 
 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
 {
-	dm_helpers_dmub_outbox0_interrupt_control(dc->ctx, enable);
+	dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
+}
+
+bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
+{
+	if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
+		return false;
+	return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
+}
+
+void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
+{
+	struct dmub_diagnostic_data diag_data = {0};
+
+	if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
+		DC_LOG_ERROR("%s: invalid parameters.", __func__);
+		return;
+	}
+
+	if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
+		DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
+		return;
+	}
+
+	DC_LOG_DEBUG(
+		"DMCUB STATE\n"
+		"    dmcub_version      : %08x\n"
+		"    scratch  [0]       : %08x\n"
+		"    scratch  [1]       : %08x\n"
+		"    scratch  [2]       : %08x\n"
+		"    scratch  [3]       : %08x\n"
+		"    scratch  [4]       : %08x\n"
+		"    scratch  [5]       : %08x\n"
+		"    scratch  [6]       : %08x\n"
+		"    scratch  [7]       : %08x\n"
+		"    scratch  [8]       : %08x\n"
+		"    scratch  [9]       : %08x\n"
+		"    scratch [10]       : %08x\n"
+		"    scratch [11]       : %08x\n"
+		"    scratch [12]       : %08x\n"
+		"    scratch [13]       : %08x\n"
+		"    scratch [14]       : %08x\n"
+		"    scratch [15]       : %08x\n"
+		"    pc                 : %08x\n"
+		"    unk_fault_addr     : %08x\n"
+		"    inst_fault_addr    : %08x\n"
+		"    data_fault_addr    : %08x\n"
+		"    inbox1_rptr        : %08x\n"
+		"    inbox1_wptr        : %08x\n"
+		"    inbox1_size        : %08x\n"
+		"    inbox0_rptr        : %08x\n"
+		"    inbox0_wptr        : %08x\n"
+		"    inbox0_size        : %08x\n"
+		"    is_enabled         : %d\n"
+		"    is_soft_reset      : %d\n"
+		"    is_secure_reset    : %d\n"
+		"    is_traceport_en    : %d\n"
+		"    is_cw0_en          : %d\n"
+		"    is_cw6_en          : %d\n",
+		diag_data.dmcub_version,
+		diag_data.scratch[0],
+		diag_data.scratch[1],
+		diag_data.scratch[2],
+		diag_data.scratch[3],
+		diag_data.scratch[4],
+		diag_data.scratch[5],
+		diag_data.scratch[6],
+		diag_data.scratch[7],
+		diag_data.scratch[8],
+		diag_data.scratch[9],
+		diag_data.scratch[10],
+		diag_data.scratch[11],
+		diag_data.scratch[12],
+		diag_data.scratch[13],
+		diag_data.scratch[14],
+		diag_data.scratch[15],
+		diag_data.pc,
+		diag_data.undefined_address_fault_addr,
+		diag_data.inst_fetch_fault_addr,
+		diag_data.data_write_fault_addr,
+		diag_data.inbox1_rptr,
+		diag_data.inbox1_wptr,
+		diag_data.inbox1_size,
+		diag_data.inbox0_rptr,
+		diag_data.inbox0_wptr,
+		diag_data.inbox0_size,
+		diag_data.is_dmcub_enabled,
+		diag_data.is_dmcub_soft_reset,
+		diag_data.is_dmcub_secure_reset,
+		diag_data.is_traceport_en,
+		diag_data.is_cw0_enabled,
+		diag_data.is_cw6_enabled);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 338f776990db..3e35eee7188c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -62,8 +62,16 @@ bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub
 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 				    unsigned int stream_mask);
 
+bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);
+
 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);
 
 void dc_dmub_trace_event_control(struct dc *dc, bool enable);
 
+void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);
+
+bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *dmub_oca);
+
+void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);
+
 #endif /* _DMUB_DC_SRV_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index cc6fb838420e..1948cd9427d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -95,6 +95,12 @@ enum dc_dp_training_pattern {
 	DP_TRAINING_PATTERN_SEQUENCE_2,
 	DP_TRAINING_PATTERN_SEQUENCE_3,
 	DP_TRAINING_PATTERN_SEQUENCE_4,
+	DP_TRAINING_PATTERN_VIDEOIDLE,
+};
+
+enum dp_link_encoding {
+	DP_UNKNOWN_ENCODING = 0,
+	DP_8b_10b_ENCODING = 1,
 };
 
 struct dc_link_settings {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index c51d2d961b7a..16cc76ce3739 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -78,7 +78,8 @@ bool dc_dsc_compute_config(
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_config *dsc_cfg);
 
-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);
+uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
+		uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);
 
 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
 		uint32_t max_target_bpp_limit_override_x16,
@@ -88,6 +89,6 @@ void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
 
 void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);
 
-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);
+void dc_dsc_policy_set_disable_dsc_stream_overhead(bool disable);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index bcec019efa6f..52355fe6994c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -182,6 +182,8 @@ enum surface_pixel_format {
 	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
 	/*64 bpp */
 	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
+	/*swapped*/
+	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616,
 	/*float*/
 	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
 	/*swaped & float*/
@@ -739,6 +741,7 @@ struct dc_dsc_config {
 	uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
 	bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
 	int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
+	bool is_dp; /* indicate if DSC is applied based on DP's capability */
 };
 struct dc_crtc_timing {
 	uint32_t h_total;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 054bab45ee17..83845d006c54 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -36,12 +36,6 @@ enum dc_link_fec_state {
 	dc_link_fec_enabled
 };
 
-enum lttpr_mode {
-	LTTPR_MODE_NON_LTTPR,
-	LTTPR_MODE_TRANSPARENT,
-	LTTPR_MODE_NON_TRANSPARENT,
-};
-
 struct dc_link_status {
 	bool link_active;
 	struct dpcd_caps *dpcd_caps;
@@ -113,6 +107,7 @@ struct dc_link {
 	/* TODO: Rename. Flag an endpoint as having a programmable mapping to a
 	 * DIG encoder. */
 	bool is_dig_mapping_flexible;
+	bool hpd_status; /* HPD status of link without physical HPD pin. */
 
 	bool edp_sink_present;
 
@@ -221,6 +216,23 @@ static inline void get_edp_links(const struct dc *dc,
 	}
 }
 
+static inline bool dc_get_edp_link_panel_inst(const struct dc *dc,
+		const struct dc_link *link,
+		unsigned int *inst_out)
+{
+	struct dc_link *edp_links[MAX_NUM_EDP];
+	int edp_num;
+
+	if (link->connector_signal != SIGNAL_TYPE_EDP)
+		return false;
+	get_edp_links(dc, edp_links, &edp_num);
+	if ((edp_num > 1) && (link->link_index > edp_links[0]->link_index))
+		*inst_out = 1;
+	else
+		*inst_out = 0;
+	return true;
+}
+
 /* Set backlight level of an embedded panel (eDP, LVDS).
  * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
  * and 16 bit fractional, where 1.0 is max backlight value.
@@ -321,7 +333,7 @@ bool dc_link_dp_perform_link_training_skip_aux(
 
 enum link_training_result dc_link_dp_perform_link_training(
 	struct dc_link *link,
-	const struct dc_link_settings *link_setting,
+	const struct dc_link_settings *link_settings,
 	bool skip_video_pattern);
 
 bool dc_link_dp_sync_lt_begin(struct dc_link *link);
@@ -345,6 +357,8 @@ bool dc_link_dp_set_test_pattern(
 	const unsigned char *p_custom_pattern,
 	unsigned int cust_pattern_size);
 
+bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap);
+
 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
 
 bool dc_link_is_dp_sink_present(struct dc_link *link);
@@ -361,9 +375,6 @@ bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
 void dc_link_set_drive_settings(struct dc *dc,
 				struct link_training_settings *lt_settings,
 				const struct dc_link *link);
-void dc_link_perform_link_training(struct dc *dc,
-				   struct dc_link_settings *link_setting,
-				   bool skip_video_pattern);
 void dc_link_set_preferred_link_settings(struct dc *dc,
 					 struct dc_link_settings *link_setting,
 					 struct dc_link *link);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 13dae7238a58..b8ebc1f09538 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -179,6 +179,9 @@ struct dc_stream_state {
 
 	bool use_vsc_sdp_for_colorimetry;
 	bool ignore_msa_timing_param;
+
+	bool freesync_on_desktop;
+
 	bool converter_disable_audio;
 	uint8_t qs_bit;
 	uint8_t qy_bit;
@@ -462,6 +465,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 				struct dc_stream_state *stream,
 				struct dc_crtc_timing_adjust *adjust);
 
+bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
+		struct dc_stream_state *stream,
+		uint32_t *refresh_rate);
+
 bool dc_stream_get_crtc_position(struct dc *dc,
 				 struct dc_stream_state **stream,
 				 int num_streams,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 432754eaf10b..8016e22114ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -271,11 +271,6 @@ struct dc_edid_caps {
 	struct dc_panel_patch panel_patch;
 };
 
-struct view {
-	uint32_t width;
-	uint32_t height;
-};
-
 struct dc_mode_flags {
 	/* note: part of refresh rate flag*/
 	uint32_t INTERLACE :1;
@@ -404,7 +399,7 @@ enum dc_connection_type {
 	dc_connection_none,
 	dc_connection_single,
 	dc_connection_mst_branch,
-	dc_connection_active_dongle
+	dc_connection_sst_branch
 };
 
 struct dc_csc_adjustments {
@@ -909,6 +904,7 @@ struct dsc_dec_dpcd_caps {
 	uint32_t branch_overall_throughput_0_mps; /* In MPs */
 	uint32_t branch_overall_throughput_1_mps; /* In MPs */
 	uint32_t branch_max_line_width;
+	bool is_dp;
 };
 
 struct dc_golden_table {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 87d57e81de12..2fb88e54a4bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -595,8 +595,28 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
 	return res;
 }
 
+int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
+		struct aux_payload *payload,
+		enum aux_return_code_type *operation_result)
+{
+	struct ddc *ddc_pin = ddc->ddc_pin;
+
+	if (ddc_pin != NULL) {
+		struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+		/* XXX: Workaround to configure ddc channels for aux transactions */
+		if (!acquire(aux_engine, ddc_pin)) {
+			*operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
+			return -1;
+		}
+		release_engine(aux_engine);
+	}
+
+	return dm_helper_dmub_aux_transfer_sync(ddc->ctx, ddc->link, payload, operation_result);
+}
+
 #define AUX_MAX_RETRIES 7
-#define AUX_MAX_DEFER_RETRIES 7
+#define AUX_MIN_DEFER_RETRIES 7
+#define AUX_MAX_DEFER_TIMEOUT_MS 50
 #define AUX_MAX_I2C_DEFER_RETRIES 7
 #define AUX_MAX_INVALID_REPLY_RETRIES 2
 #define AUX_MAX_TIMEOUT_RETRIES 3
@@ -609,6 +629,10 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 	bool payload_reply = true;
 	enum aux_return_code_type operation_result;
 	bool retry_on_defer = false;
+	struct ddc *ddc_pin = ddc->ddc_pin;
+	struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+	uint32_t defer_time_in_ms = 0;
 
 	int aux_ack_retries = 0,
 		aux_defer_retries = 0,
@@ -641,19 +665,27 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 			break;
 
 			case AUX_TRANSACTION_REPLY_AUX_DEFER:
+				/* polling_timeout_period is in us */
+				defer_time_in_ms += aux110->polling_timeout_period / 1000;
+				++aux_defer_retries;
+				fallthrough;
 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
 				retry_on_defer = true;
 				fallthrough;
 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
-				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) {
+				if (aux_defer_retries >= AUX_MIN_DEFER_RETRIES
+						&& defer_time_in_ms >= AUX_MAX_DEFER_TIMEOUT_MS) {
 					goto fail;
 				} else {
 					if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
 						(*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
-						if (payload->defer_delay > 1)
+						if (payload->defer_delay > 1) {
 							msleep(payload->defer_delay);
-						else if (payload->defer_delay <= 1)
+							defer_time_in_ms += payload->defer_delay;
+						} else if (payload->defer_delay <= 1) {
 							udelay(payload->defer_delay * 1000);
+							defer_time_in_ms += payload->defer_delay;
+						}
 					}
 				}
 				break;
@@ -682,7 +714,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 			// Check whether a DEFER had occurred before the timeout.
 			// If so, treat timeout as a DEFER.
 			if (retry_on_defer) {
-				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES)
+				if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES)
 					goto fail;
 				else if (payload->defer_delay > 0)
 					msleep(payload->defer_delay);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index 566b1bddd8cc..e69f1899fbf0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -304,6 +304,9 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
 		struct aux_payload *cmd,
 		enum aux_return_code_type *operation_result);
 
+int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
+		struct aux_payload *payload,
+		enum aux_return_code_type *operation_result);
 bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 		struct aux_payload *cmd);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 7fe5a07e2233..3139285bd403 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -142,6 +142,15 @@
 		SRII(PIXEL_RATE_CNTL, OTG, 3),\
 		SRII(PIXEL_RATE_CNTL, OTG, 4)
 
+#define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \
+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+		SRII(PHASE, DP_DTO, 0),\
+		SRII(PHASE, DP_DTO, 1),\
+		SRII(MODULO, DP_DTO, 0),\
+		SRII(MODULO, DP_DTO, 1),\
+		SRII(PIXEL_RATE_CNTL, OTG, 0),\
+		SRII(PIXEL_RATE_CNTL, OTG, 1)
+
 #endif
 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
 	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index fe31abfa6c85..df6539e4c730 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -480,6 +480,35 @@
 	SR(AZALIA_AUDIO_DTO), \
 	SR(AZALIA_CONTROLLER_CLOCK_GATING)
 
+#define HWSEQ_DCN303_REG_LIST() \
+	HWSEQ_DCN_REG_LIST(), \
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \
+	HWSEQ_PHYPLL_REG_LIST_303(OTG), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+	SR(HPO_TOP_CLOCK_CONTROL)
+
 #define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
 	SRII(PIXEL_RATE_CNTL, blk, 0), \
 	SRII(PIXEL_RATE_CNTL, blk, 1),\
@@ -494,6 +523,14 @@
 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
 
+#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
+	SRII(PIXEL_RATE_CNTL, blk, 0), \
+	SRII(PIXEL_RATE_CNTL, blk, 1)
+
+#define HWSEQ_PHYPLL_REG_LIST_303(blk) \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
+
 struct dce_hwseq_registers {
 	uint32_t DCFE_CLOCK_CONTROL[6];
 	uint32_t DCFEV_CLOCK_CONTROL;
@@ -598,6 +635,7 @@ struct dce_hwseq_registers {
 	uint32_t HPO_TOP_CLOCK_CONTROL;
 	uint32_t ODM_MEM_PWR_CTRL3;
 	uint32_t DMU_MEM_PWR_CNTL;
+	uint32_t MMHUBBUB_MEM_PWR_CNTL;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -838,7 +876,8 @@ struct dce_hwseq_registers {
 	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
-	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh)
+	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 
 #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
@@ -934,6 +973,12 @@ struct dce_hwseq_registers {
 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
 
+#define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh)
+
 #define HWSEQ_REG_FIELD_LIST(type) \
 	type DCFE_CLOCK_ENABLE; \
 	type DCFEV_CLOCK_ENABLE; \
@@ -1049,7 +1094,8 @@ struct dce_hwseq_registers {
 	type AZALIA_AUDIO_DTO_MODULE; \
 	type ODM_MEM_UNASSIGNED_PWR_MODE; \
 	type ODM_MEM_VBLANK_PWR_MODE; \
-	type DMCU_ERAM_MEM_PWR_FORCE;
+	type DMCU_ERAM_MEM_PWR_FORCE; \
+	type VGA_MEM_PWR_FORCE;
 
 #define HWSEQ_DCN3_REG_FIELD_LIST(type) \
 	type HPO_HDMISTREAMCLK_GATE_DIS;
@@ -1060,11 +1106,18 @@ struct dce_hwseq_registers {
 	type PANEL_DIGON_OVRD;\
 	type PANEL_PWRSEQ_TARGET_STATE_R;
 
+#define HWSEQ_DCN31_REG_FIELD_LIST(type) \
+	type DOMAIN_POWER_FORCEON;\
+	type DOMAIN_POWER_GATE;\
+	type DOMAIN_PGFSM_PWR_STATUS;\
+	type HPO_HDMISTREAMCLK_G_GATE_DIS;
+
 struct dce_hwseq_shift {
 	HWSEQ_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
+	HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
 };
 
 struct dce_hwseq_mask {
@@ -1072,6 +1125,7 @@ struct dce_hwseq_mask {
 	HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
 	HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
 	HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
+	HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index a524f471e0d7..6d1b01c267b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -264,18 +264,25 @@ static void set_speed(
 	struct dce_i2c_hw *dce_i2c_hw,
 	uint32_t speed)
 {
-	uint32_t xtal_ref_div = 0;
+	uint32_t xtal_ref_div = 0, ref_base_div = 0;
 	uint32_t prescale = 0;
+	uint32_t i2c_ref_clock = 0;
 
 	if (speed == 0)
 		return;
 
-	REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
+	REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div,
+		XTAL_REF_DIV, &xtal_ref_div);
 
 	if (xtal_ref_div == 0)
 		xtal_ref_div = 2;
 
-	prescale = ((dce_i2c_hw->reference_frequency * 2) / xtal_ref_div) / speed;
+	if (ref_base_div == 0)
+		i2c_ref_clock = (dce_i2c_hw->reference_frequency * 2);
+	else
+		i2c_ref_clock = ref_base_div * 1000;
+
+	prescale = (i2c_ref_clock / xtal_ref_div) / speed;
 
 	if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
 		REG_UPDATE_N(SPEED, 3,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index 2309f2bb162c..3f45ecd189a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -139,6 +139,7 @@ enum {
 	I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
 	I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
 	I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
+	I2C_SF(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, mask_sh),\
 	I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh)
 
 #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
@@ -182,6 +183,7 @@ struct dce_i2c_shift {
 	uint8_t DC_I2C_INDEX;
 	uint8_t DC_I2C_INDEX_WRITE;
 	uint8_t XTAL_REF_DIV;
+	uint8_t MICROSECOND_TIME_BASE_DIV;
 	uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
 	uint8_t DC_I2C_REG_RW_CNTL_STATUS;
 	uint8_t I2C_LIGHT_SLEEP_FORCE;
@@ -225,6 +227,7 @@ struct dce_i2c_mask {
 	uint32_t DC_I2C_INDEX;
 	uint32_t DC_I2C_INDEX_WRITE;
 	uint32_t XTAL_REF_DIV;
+	uint32_t MICROSECOND_TIME_BASE_DIV;
 	uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
 	uint32_t DC_I2C_REG_RW_CNTL_STATUS;
 	uint32_t I2C_LIGHT_SLEEP_FORCE;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 79a6f261a0da..4cdd4dacb761 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -566,6 +566,7 @@ static void program_grph_pixel_format(
 			 *  should problem swap endian*/
 		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
 		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
+		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 ||
 		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 		/* ABGR formats */
 		red_xbar = 2;
@@ -606,6 +607,7 @@ static void program_grph_pixel_format(
 		fallthrough;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get float too? */
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 		grph_depth = 3;
 		grph_format = 0;
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 23db5c72f07e..f98400efdd9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -181,7 +181,6 @@ struct dce_mem_input_registers {
 	SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
-	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
 	SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
 	SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
 	SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
@@ -207,7 +206,6 @@ struct dce_mem_input_registers {
 	SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
-	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
 	SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
 	SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
 	SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
@@ -299,6 +297,7 @@ struct dce_mem_input_registers {
 	MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
 
 #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 151dc7bf6d23..d9fd4ec60588 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -794,7 +794,7 @@ static void program_bit_depth_reduction(
 	enum dcp_out_trunc_round_mode trunc_mode;
 	bool spatial_dither_enable;
 
-	ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
+	ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
 
 	spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
 	/* Default to 12 bit truncation without rounding */
@@ -854,7 +854,7 @@ static void dce60_program_bit_depth_reduction(
 	enum dcp_out_trunc_round_mode trunc_mode;
 	bool spatial_dither_enable;
 
-	ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
+	ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
 
 	spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
 	/* Default to 12 bit truncation without rounding */
@@ -1647,7 +1647,8 @@ void dce_transform_construct(
 	xfm_dce->lb_pixel_depth_supported =
 			LB_PIXEL_DEPTH_18BPP |
 			LB_PIXEL_DEPTH_24BPP |
-			LB_PIXEL_DEPTH_30BPP;
+			LB_PIXEL_DEPTH_30BPP |
+			LB_PIXEL_DEPTH_36BPP;
 
 	xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 	xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
@@ -1675,7 +1676,8 @@ void dce60_transform_construct(
 	xfm_dce->lb_pixel_depth_supported =
 			LB_PIXEL_DEPTH_18BPP |
 			LB_PIXEL_DEPTH_24BPP |
-			LB_PIXEL_DEPTH_30BPP;
+			LB_PIXEL_DEPTH_30BPP |
+			LB_PIXEL_DEPTH_36BPP;
 
 	xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 	xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index eb1698d54a48..54a1408c8015 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -56,11 +56,19 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
 {
 	union dmub_rb_cmd cmd;
 	uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;
+	uint32_t edp_id_count = dc->dc_edp_id_count;
+	int i;
+	uint8_t panel_mask = 0;
+
+	for (i = 0; i < edp_id_count; i++)
+		panel_mask |= 0x01 << i;
 
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;
 	cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;
 	cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = fractional_pwm;
+	cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
+	cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.panel_mask = panel_mask;
 	cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pwm_frac_data);
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
@@ -135,11 +143,24 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t level)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = abm->ctx;
+	struct dc_link *edp_links[MAX_NUM_EDP];
+	int i;
+	int edp_num;
+	uint8_t panel_mask = 0;
+
+	get_edp_links(dc->dc, edp_links, &edp_num);
+
+	for (i = 0; i < edp_num; i++) {
+		if (edp_links[i]->link_status.link_active)
+			panel_mask |= (0x01 << i);
+	}
 
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.abm_set_level.header.type = DMUB_CMD__ABM;
 	cmd.abm_set_level.header.sub_type = DMUB_CMD__ABM_SET_LEVEL;
 	cmd.abm_set_level.abm_set_level_data.level = level;
+	cmd.abm_set_level.abm_set_level_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
+	cmd.abm_set_level.abm_set_level_data.panel_mask = panel_mask;
 	cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_level_data);
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
@@ -151,10 +172,12 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t level)
 
 static bool dmub_abm_init_config(struct abm *abm,
 	const char *src,
-	unsigned int bytes)
+	unsigned int bytes,
+	unsigned int inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = abm->ctx;
+	uint8_t panel_mask = 0x01 << inst;
 
 	// TODO: Optimize by only reading back final 4 bytes
 	dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);
@@ -168,6 +191,9 @@ static bool dmub_abm_init_config(struct abm *abm,
 	cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG;
 	cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;
 	cmd.abm_init_config.abm_init_config_data.bytes = bytes;
+	cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
+	cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask;
+
 	cmd.abm_init_config.header.payload_bytes = sizeof(struct dmub_cmd_abm_init_config_data);
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index c97ee5abc0ef..9baf8ca0a920 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -52,6 +52,14 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,
 	dc_dmub_srv_wait_idle(dmub_srv);
 }
 
+void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
+		union dmub_inbox0_cmd_lock_hw hw_lock_cmd)
+{
+	union dmub_inbox0_data_register data = { 0 };
+	data.inbox0_cmd_lock_hw = hw_lock_cmd;
+	dc_dmub_srv_send_inbox0_cmd(dmub_srv, data);
+}
+
 bool should_use_dmub_lock(struct dc_link *link)
 {
 	return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
index bc5906347493..5a72b168fb4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
@@ -34,6 +34,9 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,
 				union dmub_hw_lock_flags *hw_locks,
 				struct dmub_hw_lock_inst_flags *inst_flags);
 
+void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
+		union dmub_inbox0_cmd_lock_hw hw_lock_cmd);
+
 bool should_use_dmub_lock(struct dc_link *link);
 
 #endif /*_DMUB_HW_LOCK_MGR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
index 295596d1f47f..faad8555ddbb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
@@ -27,19 +27,10 @@
 #include "dmub/inc/dmub_cmd.h"
 
 /**
- *****************************************************************************
- *  Function: dmub_enable_outbox_notification
- *
- *  @brief
- *		Sends inbox cmd to dmub to enable outbox1 messages with interrupt.
- *		Dmub sends outbox1 message and triggers outbox1 interrupt.
- *
- *  @param
- *		[in] dc: dc structure
- *
- *  @return
- *     None
- *****************************************************************************
+ *  dmub_enable_outbox_notification - Sends inbox cmd to dmub to enable outbox1
+ *                                    messages with interrupt. Dmub sends outbox1
+ *                                    message and triggers outbox1 interrupt.
+ * @dc: dc structure
  */
 void dmub_enable_outbox_notification(struct dc *dc)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 5e99553fcdd4..10d42ae0cffe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -77,7 +77,7 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
 /*
  * Get PSR state from firmware.
  */
-static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
+static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
 {
 	struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
 	uint32_t raw_state = 0;
@@ -86,7 +86,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
 
 	do {
 		// Send gpint command and wait for ack
-		status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30);
+		status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
 
 		if (status == DMUB_STATUS_OK) {
 			// GPINT was executed, get response
@@ -105,7 +105,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
 /*
  * Set PSR version.
  */
-static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream)
+static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
@@ -125,6 +125,8 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
 		break;
 	}
+	cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+	cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
 	cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
@@ -137,7 +139,7 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 /*
  * Enable/Disable PSR.
  */
-static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
+static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
@@ -147,6 +149,9 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.psr_enable.header.type = DMUB_CMD__PSR;
 
+	cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+	cmd.psr_enable.data.panel_inst = panel_inst;
+
 	if (enable)
 		cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
 	else
@@ -164,7 +169,7 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
 	 */
 	if (wait) {
 		for (retry_count = 0; retry_count <= 1000; retry_count++) {
-			dmub_psr_get_state(dmub, &state);
+			dmub_psr_get_state(dmub, &state, panel_inst);
 
 			if (enable) {
 				if (state != PSR_STATE0)
@@ -186,13 +191,13 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
 /*
  * Set PSR level.
  */
-static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
+static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	enum dc_psr_state state = PSR_STATE0;
 	struct dc_context *dc = dmub->ctx;
 
-	dmub_psr_get_state(dmub, &state);
+	dmub_psr_get_state(dmub, &state, panel_inst);
 
 	if (state == PSR_STATE0)
 		return;
@@ -202,7 +207,8 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
 	cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
 	cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
 	cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
-
+	cmd.psr_set_level.psr_set_level_data.cmd_version = PSR_VERSION_1;
+	cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 	dc_dmub_srv_cmd_execute(dc->dmub_srv);
 	dc_dmub_srv_wait_idle(dc->dmub_srv);
@@ -213,7 +219,8 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
  */
 static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 		struct dc_link *link,
-		struct psr_context *psr_context)
+		struct psr_context *psr_context,
+		uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
@@ -237,7 +244,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 		return false;
 
 	// First, set the psr version
-	if (!dmub_psr_set_version(dmub, pipe_ctx->stream))
+	if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
 		return false;
 
 	// Program DP DPHY fast training registers
@@ -286,6 +293,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
+	copy_settings_data->cmd_version =  PSR_VERSION_1;
+	copy_settings_data->panel_inst = panel_inst;
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 	dc_dmub_srv_cmd_execute(dc->dmub_srv);
@@ -297,12 +306,15 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 /*
  * Send command to PSR to force static ENTER and ignore all state changes until exit
  */
-static void dmub_psr_force_static(struct dmub_psr *dmub)
+static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
 
 	memset(&cmd, 0, sizeof(cmd));
+
+	cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
+	cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
 	cmd.psr_force_static.header.type = DMUB_CMD__PSR;
 	cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
 	cmd.psr_enable.header.payload_bytes = 0;
@@ -315,12 +327,13 @@ static void dmub_psr_force_static(struct dmub_psr *dmub)
 /*
  * Get PSR residency from firmware.
  */
-static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency)
+static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
 {
 	struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
+	uint16_t param = (uint16_t)(panel_inst << 8);
 
-	// Send gpint command and wait for ack
-	dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, 0, 30);
+	/* Send gpint command and wait for ack */
+	dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
 
 	dmub_srv_get_gpint_response(srv, residency);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index fe747c20a0d2..9675c269e649 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -35,12 +35,17 @@ struct dmub_psr {
 };
 
 struct dmub_psr_funcs {
-	bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context);
-	void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait);
-	void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state);
-	void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level);
-	void (*psr_force_static)(struct dmub_psr *dmub);
-	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency);
+	bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link,
+	struct psr_context *psr_context, uint8_t panel_inst);
+	void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait,
+	uint8_t panel_inst);
+	void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state,
+	uint8_t panel_inst);
+	void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level,
+	uint8_t panel_inst);
+	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
+	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
+	uint8_t panel_inst);
 };
 
 struct dmub_psr *dmub_psr_create(struct dc_context *ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5ddeee96bf23..2938caaa2299 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -32,7 +32,6 @@
 #include "core_status.h"
 #include "resource.h"
 #include "dm_helpers.h"
-#include "dce110_hw_sequencer.h"
 #include "dce110_timing_generator.h"
 #include "dce/dce_hwseq.h"
 #include "gpio_service_interface.h"
@@ -49,6 +48,9 @@
 #include "link_encoder.h"
 #include "link_hwss.h"
 #include "dc_link_dp.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+#include "dccg.h"
+#endif
 #include "clock_source.h"
 #include "clk_mgr.h"
 #include "abm.h"
@@ -63,6 +65,8 @@
 
 #include "atomfirmware.h"
 
+#include "dcn10/dcn10_hw_sequencer.h"
+
 #define GAMMA_HW_POINTS_NUM 256
 
 /*
@@ -264,6 +268,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 		prescale_params->scale = 0x2008;
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 		prescale_params->scale = 0x2000;
 		break;
@@ -1306,41 +1311,6 @@ static void build_audio_output(
 			pipe_ctx->pll_settings.ss_percentage;
 }
 
-static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
-{
-	uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
-
-	switch (pipe_ctx->plane_res.scl_data.format) {
-	case PIXEL_FORMAT_ARGB8888:
-		/* set boarder color to red */
-		color->color_r_cr = color_value;
-		break;
-
-	case PIXEL_FORMAT_ARGB2101010:
-		/* set boarder color to blue */
-		color->color_b_cb = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP8:
-		/* set boarder color to green */
-		color->color_g_y = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP10:
-		/* set boarder color to yellow */
-		color->color_g_y = color_value;
-		color->color_r_cr = color_value;
-		break;
-	case PIXEL_FORMAT_FP16:
-		/* set boarder color to white */
-		color->color_r_cr = color_value;
-		color->color_b_cb = color_value;
-		color->color_g_y = color_value;
-		break;
-	default:
-		break;
-	}
-}
-
 static void program_scaler(const struct dc *dc,
 		const struct pipe_ctx *pipe_ctx)
 {
@@ -2120,11 +2090,31 @@ static void dce110_setup_audio_dto(
 
 			build_audio_output(context, pipe_ctx, &audio_output);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+			/* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
+			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
+				/* disable audio DTBCLK DTO */
+				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
+					dc->res_pool->dccg, 0);
+
+				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
+						pipe_ctx->stream_res.audio,
+						pipe_ctx->stream->signal,
+						&audio_output.crtc_info,
+						&audio_output.pll_info);
+			} else
+				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
+					pipe_ctx->stream_res.audio,
+					pipe_ctx->stream->signal,
+					&audio_output.crtc_info,
+					&audio_output.pll_info);
+#else
 			pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 				pipe_ctx->stream_res.audio,
 				pipe_ctx->stream->signal,
 				&audio_output.crtc_info,
 				&audio_output.pll_info);
+#endif
 			break;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 8bbb499067f7..db7557a1c613 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -393,6 +393,7 @@ static void program_pixel_format(
 			grph_format = 1;
 			break;
 		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 			grph_depth = 3;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index d88a74559edd..27cbb5b42c7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -2231,6 +2231,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = {
 				dce110_timing_generator_enable_advanced_request,
 		.set_drr =
 				dce110_timing_generator_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control =
 			dce110_timing_generator_set_static_screen_control,
 		.set_test_pattern = dce110_timing_generator_set_test_pattern,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index 29438c6050db..45bca0db5e5e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -708,7 +708,8 @@ bool dce110_transform_v_construct(
 	xfm_dce->lb_pixel_depth_supported =
 			LB_PIXEL_DEPTH_18BPP |
 			LB_PIXEL_DEPTH_24BPP |
-			LB_PIXEL_DEPTH_30BPP;
+			LB_PIXEL_DEPTH_30BPP |
+			LB_PIXEL_DEPTH_36BPP;
 
 	xfm_dce->prescaler_on = true;
 	xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index b57c466124e7..4af0c70098c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -1190,6 +1190,7 @@ static const struct timing_generator_funcs dce120_tg_funcs = {
 		.tear_down_global_swap_lock = dce120_timing_generator_tear_down_global_swap_lock,
 		.enable_advanced_request = dce120_timing_generator_enable_advanced_request,
 		.set_drr = dce120_timing_generator_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control = dce120_timing_generator_set_static_screen_control,
 		.set_test_pattern = dce120_timing_generator_set_test_pattern,
 		.arm_vert_intr = dce120_arm_vert_intr,
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 397e7f94e1e8..b8fd43dc010b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -209,6 +209,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = {
 		.tear_down_global_swap_lock =
 				dce110_timing_generator_tear_down_global_swap_lock,
 		.set_drr = dce110_timing_generator_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control =
 			dce110_timing_generator_set_static_screen_control,
 		.set_test_pattern = dce110_timing_generator_set_test_pattern,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 7f8456b9988b..91fdfcd8a14e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -257,7 +257,8 @@ static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
 	if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
 		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
 		*fmt = PIXEL_FORMAT_FLOAT;
-	else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
+	else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ||
+		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616)
 		*fmt = PIXEL_FORMAT_FIXED16;
 	else
 		*fmt = PIXEL_FORMAT_FIXED;
@@ -368,7 +369,8 @@ void dpp1_cnv_setup (
 		select = INPUT_CSC_SELECT_ICSC;
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-		pixel_format = 22;
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
+		pixel_format = 26; /* ARGB16161616_UNORM */
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 		pixel_format = 24;
@@ -566,7 +568,8 @@ void dpp1_construct(
 	dpp->lb_pixel_depth_supported =
 		LB_PIXEL_DEPTH_18BPP |
 		LB_PIXEL_DEPTH_24BPP |
-		LB_PIXEL_DEPTH_30BPP;
+		LB_PIXEL_DEPTH_30BPP |
+		LB_PIXEL_DEPTH_36BPP;
 
 	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 9a1f40eb5c47..71b3a6949001 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1497,8 +1497,6 @@ void dpp1_cnv_setup (
 		enum dc_color_space input_color_space,
 		struct cnv_alpha_2bit_lut *alpha_2bit_lut);
 
-void dpp1_full_bypass(struct dpp *dpp_base);
-
 void dpp1_dppclk_control(
 		struct dpp *dpp_base,
 		bool dppclk_div,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index efa86d5c6847..673b93f4fea5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -496,10 +496,13 @@ static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *d
 	int vtaps_c = scl_data->taps.v_taps_c;
 	int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
 	int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
-	enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0;
 
-	if (dpp->base.ctx->dc->debug.use_max_lb)
-		return mem_cfg;
+	if (dpp->base.ctx->dc->debug.use_max_lb) {
+		if (scl_data->format == PIXEL_FORMAT_420BPP8
+				|| scl_data->format == PIXEL_FORMAT_420BPP10)
+			return LB_MEMORY_CONFIG_3;
+		return LB_MEMORY_CONFIG_0;
+	}
 
 	dpp->base.caps->dscl_calc_lb_num_partitions(
 			scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
@@ -628,8 +631,10 @@ static void dpp1_dscl_set_manual_ratio_init(
 		SCL_V_INIT_INT, init_int);
 
 	if (REG(SCL_VERT_FILTER_INIT_BOT)) {
-		init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
-		init_int = dc_fixpt_floor(data->inits.v_bot);
+		struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
+
+		init_frac = dc_fixpt_u0d19(bot) << 5;
+		init_int = dc_fixpt_floor(bot);
 		REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
 			SCL_V_INIT_FRAC_BOT, init_frac,
 			SCL_V_INIT_INT_BOT, init_int);
@@ -642,41 +647,60 @@ static void dpp1_dscl_set_manual_ratio_init(
 		SCL_V_INIT_INT_C, init_int);
 
 	if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
-		init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
-		init_int = dc_fixpt_floor(data->inits.v_c_bot);
+		struct fixed31_32 bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
+
+		init_frac = dc_fixpt_u0d19(bot) << 5;
+		init_int = dc_fixpt_floor(bot);
 		REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
 			SCL_V_INIT_FRAC_BOT_C, init_frac,
 			SCL_V_INIT_INT_BOT_C, init_int);
 	}
 }
 
-
-
-static void dpp1_dscl_set_recout(
-			struct dcn10_dpp *dpp, const struct rect *recout)
+/**
+ * dpp1_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area
+ *
+ * @dpp: DPP data struct
+ * @recount: Rectangle information
+ *
+ * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on
+ * the values specified in the recount parameter.
+ *
+ * Note: This function only have effect if AutoCal is disabled.
+ */
+static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,
+				 const struct rect *recout)
 {
 	int visual_confirm_on = 0;
 	if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
 		visual_confirm_on = 1;
 
 	REG_SET_2(RECOUT_START, 0,
-		/* First pixel of RECOUT */
-			 RECOUT_START_X, recout->x,
-		/* First line of RECOUT */
-			 RECOUT_START_Y, recout->y);
+		  /* First pixel of RECOUT in the active OTG area */
+		  RECOUT_START_X, recout->x,
+		  /* First line of RECOUT in the active OTG area */
+		  RECOUT_START_Y, recout->y);
 
 	REG_SET_2(RECOUT_SIZE, 0,
-		/* Number of RECOUT horizontal pixels */
-			 RECOUT_WIDTH, recout->width,
-		/* Number of RECOUT vertical lines */
-			 RECOUT_HEIGHT, recout->height
+		  /* Number of RECOUT horizontal pixels */
+		  RECOUT_WIDTH, recout->width,
+		  /* Number of RECOUT vertical lines */
+		  RECOUT_HEIGHT, recout->height
 			 - visual_confirm_on * 2 * (dpp->base.inst + 1));
 }
 
-/* Main function to program scaler and line buffer in manual scaling mode */
-void dpp1_dscl_set_scaler_manual_scale(
-	struct dpp *dpp_base,
-	const struct scaler_data *scl_data)
+/**
+ * dpp1_dscl_set_scaler_manual_scale - Manually program scaler and line buffer
+ *
+ * @dpp_base: High level DPP struct
+ * @scl_data: scalaer_data info
+ *
+ * This is the primary function to program scaler and line buffer in manual
+ * scaling mode. To execute the required operations for manual scale, we need
+ * to disable AutoCal first.
+ */
+void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base,
+				       const struct scaler_data *scl_data)
 {
 	enum lb_memory_config lb_config;
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 6f42d10dd772..f4f423d0b8c3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -785,6 +785,7 @@ static bool hubbub1_dcc_support_pixel_format(
 		*bytes_per_element = 4;
 		return true;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 		*bytes_per_element = 8;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 343a537172c7..8d7e92d5d3e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -139,6 +139,21 @@ struct dcn_hubbub_registers {
 	uint32_t DCHVM_CLK_CTRL;
 	uint32_t DCHVM_RIOMMU_CTRL0;
 	uint32_t DCHVM_RIOMMU_STAT0;
+	uint32_t DCHUBBUB_DET0_CTRL;
+	uint32_t DCHUBBUB_DET1_CTRL;
+	uint32_t DCHUBBUB_DET2_CTRL;
+	uint32_t DCHUBBUB_DET3_CTRL;
+	uint32_t DCHUBBUB_COMPBUF_CTRL;
+	uint32_t COMPBUF_RESERVED_SPACE;
+	uint32_t DCHUBBUB_DEBUG_CTRL_0;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;
 };
 
 /* set field name */
@@ -276,16 +291,42 @@ struct dcn_hubbub_registers {
 		type RIOMMU_ACTIVE; \
 		type HOSTVM_PREFETCH_DONE
 
+#define HUBBUB_RET_REG_FIELD_LIST(type) \
+		type DET_DEPTH;\
+		type DET0_SIZE;\
+		type DET1_SIZE;\
+		type DET2_SIZE;\
+		type DET3_SIZE;\
+		type DET0_SIZE_CURRENT;\
+		type DET1_SIZE_CURRENT;\
+		type DET2_SIZE_CURRENT;\
+		type DET3_SIZE_CURRENT;\
+		type COMPBUF_SIZE;\
+		type COMPBUF_SIZE_CURRENT;\
+		type COMPBUF_RESERVED_SPACE_64B;\
+		type COMPBUF_RESERVED_SPACE_ZS;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D
+
+
 struct dcn_hubbub_shift {
 	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
+	HUBBUB_RET_REG_FIELD_LIST(uint8_t);
 };
 
 struct dcn_hubbub_mask {
 	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
+	HUBBUB_RET_REG_FIELD_LIST(uint32_t);
 };
 
 struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 714c71a5fbde..04303fe9c659 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -245,6 +245,7 @@ void hubp1_program_pixel_format(
 	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 		red_bar = 2;
 		blue_bar = 3;
@@ -277,8 +278,9 @@ void hubp1_program_pixel_format(
 				SURFACE_PIXEL_FORMAT, 10);
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-				SURFACE_PIXEL_FORMAT, 22);
+				SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
@@ -1226,6 +1228,14 @@ void hubp1_cursor_set_position(
 	/* TODO Handle surface pixel formats other than 4:4:4 */
 }
 
+/**
+ * hubp1_clk_cntl - Disable or enable clocks for DCHUBP
+ *
+ * @hubp: hubp struct reference.
+ * @enable: Set true for enabling gate clock.
+ *
+ * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk.
+ */
 void hubp1_clk_cntl(struct hubp *hubp, bool enable)
 {
 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
@@ -1257,6 +1267,11 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset)
 	REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0);
 }
 
+/**
+ * hubp1_set_flip_int - Enable surface flip interrupt
+ *
+ * @hubp: hubp struct reference.
+ */
 void hubp1_set_flip_int(struct hubp *hubp)
 {
 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7c939c0a977b..c545eddabdcc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -54,6 +54,8 @@
 #include "dce/dmub_hw_lock_mgr.h"
 #include "dc_trace.h"
 #include "dce/dmub_outbox.h"
+#include "inc/dc_link_dp.h"
+#include "inc/link_dpcd.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -72,6 +74,9 @@
 
 #define GAMMA_HW_POINTS_NUM 256
 
+#define PGFSM_POWER_ON 0
+#define PGFSM_POWER_OFF 2
+
 void print_microsec(struct dc_context *dc_ctx,
 	struct dc_log_buffer_ctx *log_ctx,
 	uint32_t ref_cycle)
@@ -536,13 +541,22 @@ void dcn10_disable_vga(
 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 }
 
+/**
+ * dcn10_dpp_pg_control - DPP power gate control.
+ *
+ * @hws: dce_hwseq reference.
+ * @dpp_inst: DPP instance reference.
+ * @power_on: true if we want to enable power gate, false otherwise.
+ *
+ * Enable or disable power gate in the specific DPP instance.
+ */
 void dcn10_dpp_pg_control(
 		struct dce_hwseq *hws,
 		unsigned int dpp_inst,
 		bool power_on)
 {
 	uint32_t power_gate = power_on ? 0 : 1;
-	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t pwr_status = power_on ? PGFSM_POWER_ON : PGFSM_POWER_OFF;
 
 	if (hws->ctx->dc->debug.disable_dpp_power_gate)
 		return;
@@ -588,13 +602,22 @@ void dcn10_dpp_pg_control(
 	}
 }
 
+/**
+ * dcn10_hubp_pg_control - HUBP power gate control.
+ *
+ * @hws: dce_hwseq reference.
+ * @hubp_inst: DPP instance reference.
+ * @power_on: true if we want to enable power gate, false otherwise.
+ *
+ * Enable or disable power gate in the specific HUBP instance.
+ */
 void dcn10_hubp_pg_control(
 		struct dce_hwseq *hws,
 		unsigned int hubp_inst,
 		bool power_on)
 {
 	uint32_t power_gate = power_on ? 0 : 1;
-	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t pwr_status = power_on ? PGFSM_POWER_ON : PGFSM_POWER_OFF;
 
 	if (hws->ctx->dc->debug.disable_hubp_power_gate)
 		return;
@@ -1078,6 +1101,19 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 		hws->funcs.verify_allow_pstate_change_high(dc);
 }
 
+/**
+ * dcn10_plane_atomic_power_down - Power down plane components.
+ *
+ * @dc: dc struct reference. used for grab hwseq.
+ * @dpp: dpp struct reference.
+ * @hubp: hubp struct reference.
+ *
+ * Keep in mind that this operation requires a power gate configuration;
+ * however, requests for switch power gate are precisely controlled to avoid
+ * problems. For this reason, power gate request is usually disabled. This
+ * function first needs to enable the power gate request before disabling DPP
+ * and HUBP. Finally, it disables the power gate request again.
+ */
 void dcn10_plane_atomic_power_down(struct dc *dc,
 		struct dpp *dpp,
 		struct hubp *hubp)
@@ -1369,6 +1405,9 @@ void dcn10_init_hw(struct dc *dc)
 			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
 				continue;
 
+			/* DP 2.0 requires that LTTPR Caps be read first */
+			dp_retrieve_lttpr_cap(dc->links[i]);
+
 			/*
 			 * If any of the displays are lit up turn them off.
 			 * The reason is that some MST hubs cannot be turned off
@@ -2165,129 +2204,6 @@ void dcn10_enable_per_frame_crtc_position_reset(
 	DC_SYNC_INFO("Multi-display sync is complete\n");
 }
 
-/*static void print_rq_dlg_ttu(
-		struct dc *dc,
-		struct pipe_ctx *pipe_ctx)
-{
-	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
-			"\n============== DML TTU Output parameters [%d] ==============\n"
-			"qos_level_low_wm: %d, \n"
-			"qos_level_high_wm: %d, \n"
-			"min_ttu_vblank: %d, \n"
-			"qos_level_flip: %d, \n"
-			"refcyc_per_req_delivery_l: %d, \n"
-			"qos_level_fixed_l: %d, \n"
-			"qos_ramp_disable_l: %d, \n"
-			"refcyc_per_req_delivery_pre_l: %d, \n"
-			"refcyc_per_req_delivery_c: %d, \n"
-			"qos_level_fixed_c: %d, \n"
-			"qos_ramp_disable_c: %d, \n"
-			"refcyc_per_req_delivery_pre_c: %d\n"
-			"=============================================================\n",
-			pipe_ctx->pipe_idx,
-			pipe_ctx->ttu_regs.qos_level_low_wm,
-			pipe_ctx->ttu_regs.qos_level_high_wm,
-			pipe_ctx->ttu_regs.min_ttu_vblank,
-			pipe_ctx->ttu_regs.qos_level_flip,
-			pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
-			pipe_ctx->ttu_regs.qos_level_fixed_l,
-			pipe_ctx->ttu_regs.qos_ramp_disable_l,
-			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
-			pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
-			pipe_ctx->ttu_regs.qos_level_fixed_c,
-			pipe_ctx->ttu_regs.qos_ramp_disable_c,
-			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
-			);
-
-	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
-			"\n============== DML DLG Output parameters [%d] ==============\n"
-			"refcyc_h_blank_end: %d, \n"
-			"dlg_vblank_end: %d, \n"
-			"min_dst_y_next_start: %d, \n"
-			"refcyc_per_htotal: %d, \n"
-			"refcyc_x_after_scaler: %d, \n"
-			"dst_y_after_scaler: %d, \n"
-			"dst_y_prefetch: %d, \n"
-			"dst_y_per_vm_vblank: %d, \n"
-			"dst_y_per_row_vblank: %d, \n"
-			"ref_freq_to_pix_freq: %d, \n"
-			"vratio_prefetch: %d, \n"
-			"refcyc_per_pte_group_vblank_l: %d, \n"
-			"refcyc_per_meta_chunk_vblank_l: %d, \n"
-			"dst_y_per_pte_row_nom_l: %d, \n"
-			"refcyc_per_pte_group_nom_l: %d, \n",
-			pipe_ctx->pipe_idx,
-			pipe_ctx->dlg_regs.refcyc_h_blank_end,
-			pipe_ctx->dlg_regs.dlg_vblank_end,
-			pipe_ctx->dlg_regs.min_dst_y_next_start,
-			pipe_ctx->dlg_regs.refcyc_per_htotal,
-			pipe_ctx->dlg_regs.refcyc_x_after_scaler,
-			pipe_ctx->dlg_regs.dst_y_after_scaler,
-			pipe_ctx->dlg_regs.dst_y_prefetch,
-			pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
-			pipe_ctx->dlg_regs.dst_y_per_row_vblank,
-			pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
-			pipe_ctx->dlg_regs.vratio_prefetch,
-			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
-			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
-			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
-			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
-			);
-
-	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
-			"\ndst_y_per_meta_row_nom_l: %d, \n"
-			"refcyc_per_meta_chunk_nom_l: %d, \n"
-			"refcyc_per_line_delivery_pre_l: %d, \n"
-			"refcyc_per_line_delivery_l: %d, \n"
-			"vratio_prefetch_c: %d, \n"
-			"refcyc_per_pte_group_vblank_c: %d, \n"
-			"refcyc_per_meta_chunk_vblank_c: %d, \n"
-			"dst_y_per_pte_row_nom_c: %d, \n"
-			"refcyc_per_pte_group_nom_c: %d, \n"
-			"dst_y_per_meta_row_nom_c: %d, \n"
-			"refcyc_per_meta_chunk_nom_c: %d, \n"
-			"refcyc_per_line_delivery_pre_c: %d, \n"
-			"refcyc_per_line_delivery_c: %d \n"
-			"========================================================\n",
-			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
-			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
-			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
-			pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
-			pipe_ctx->dlg_regs.vratio_prefetch_c,
-			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
-			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
-			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
-			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
-			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
-			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
-			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
-			pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
-			);
-
-	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
-			"\n============== DML RQ Output parameters [%d] ==============\n"
-			"chunk_size: %d \n"
-			"min_chunk_size: %d \n"
-			"meta_chunk_size: %d \n"
-			"min_meta_chunk_size: %d \n"
-			"dpte_group_size: %d \n"
-			"mpte_group_size: %d \n"
-			"swath_height: %d \n"
-			"pte_row_height_linear: %d \n"
-			"========================================================\n",
-			pipe_ctx->pipe_idx,
-			pipe_ctx->rq_regs.rq_regs_l.chunk_size,
-			pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
-			pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
-			pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
-			pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
-			pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
-			pipe_ctx->rq_regs.rq_regs_l.swath_height,
-			pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
-			);
-}
-*/
-
 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
 		struct vm_system_aperture_param *apt,
 		struct dce_hwseq *hws)
@@ -2395,43 +2311,6 @@ static void dcn10_enable_plane(
 			pipe_ctx->stream_res.opp,
 			true);
 
-/* TODO: enable/disable in dm as per update type.
-	if (plane_state) {
-		DC_LOG_DC(dc->ctx->logger,
-				"Pipe:%d 0x%x: addr hi:0x%x, "
-				"addr low:0x%x, "
-				"src: %d, %d, %d,"
-				" %d; dst: %d, %d, %d, %d;\n",
-				pipe_ctx->pipe_idx,
-				plane_state,
-				plane_state->address.grph.addr.high_part,
-				plane_state->address.grph.addr.low_part,
-				plane_state->src_rect.x,
-				plane_state->src_rect.y,
-				plane_state->src_rect.width,
-				plane_state->src_rect.height,
-				plane_state->dst_rect.x,
-				plane_state->dst_rect.y,
-				plane_state->dst_rect.width,
-				plane_state->dst_rect.height);
-
-		DC_LOG_DC(dc->ctx->logger,
-				"Pipe %d: width, height, x, y         format:%d\n"
-				"viewport:%d, %d, %d, %d\n"
-				"recout:  %d, %d, %d, %d\n",
-				pipe_ctx->pipe_idx,
-				plane_state->format,
-				pipe_ctx->plane_res.scl_data.viewport.width,
-				pipe_ctx->plane_res.scl_data.viewport.height,
-				pipe_ctx->plane_res.scl_data.viewport.x,
-				pipe_ctx->plane_res.scl_data.viewport.y,
-				pipe_ctx->plane_res.scl_data.recout.width,
-				pipe_ctx->plane_res.scl_data.recout.height,
-				pipe_ctx->plane_res.scl_data.recout.x,
-				pipe_ctx->plane_res.scl_data.recout.y);
-		print_rq_dlg_ttu(dc, pipe_ctx);
-	}
-*/
 	if (dc->config.gpu_vm_support)
 		dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
 
@@ -2533,83 +2412,6 @@ void dcn10_program_output_csc(struct dc *dc,
 	}
 }
 
-void dcn10_get_surface_visual_confirm_color(
-		const struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
-{
-	uint32_t color_value = MAX_TG_COLOR_VALUE;
-
-	switch (pipe_ctx->plane_res.scl_data.format) {
-	case PIXEL_FORMAT_ARGB8888:
-		/* set border color to red */
-		color->color_r_cr = color_value;
-		break;
-
-	case PIXEL_FORMAT_ARGB2101010:
-		/* set border color to blue */
-		color->color_b_cb = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP8:
-		/* set border color to green */
-		color->color_g_y = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP10:
-		/* set border color to yellow */
-		color->color_g_y = color_value;
-		color->color_r_cr = color_value;
-		break;
-	case PIXEL_FORMAT_FP16:
-		/* set border color to white */
-		color->color_r_cr = color_value;
-		color->color_b_cb = color_value;
-		color->color_g_y = color_value;
-		break;
-	default:
-		break;
-	}
-}
-
-void dcn10_get_hdr_visual_confirm_color(
-		struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
-{
-	uint32_t color_value = MAX_TG_COLOR_VALUE;
-
-	// Determine the overscan color based on the top-most (desktop) plane's context
-	struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
-
-	while (top_pipe_ctx->top_pipe != NULL)
-		top_pipe_ctx = top_pipe_ctx->top_pipe;
-
-	switch (top_pipe_ctx->plane_res.scl_data.format) {
-	case PIXEL_FORMAT_ARGB2101010:
-		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
-			/* HDR10, ARGB2101010 - set border color to red */
-			color->color_r_cr = color_value;
-		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
-			/* FreeSync 2 ARGB2101010 - set border color to pink */
-			color->color_r_cr = color_value;
-			color->color_b_cb = color_value;
-		}
-		break;
-	case PIXEL_FORMAT_FP16:
-		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
-			/* HDR10, FP16 - set border color to blue */
-			color->color_b_cb = color_value;
-		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
-			/* FreeSync 2 HDR - set border color to green */
-			color->color_g_y = color_value;
-		}
-		break;
-	default:
-		/* SDR - set border color to Gray */
-		color->color_r_cr = color_value/2;
-		color->color_b_cb = color_value/2;
-		color->color_g_y = color_value/2;
-		break;
-	}
-}
-
 static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
 {
 	struct dc_bias_and_scale bns_params = {0};
@@ -2628,9 +2430,26 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state
 		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
 }
 
+void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
+{
+	struct mpc *mpc = dc->res_pool->mpc;
+
+	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
+		get_hdr_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
+		get_surface_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
+		get_surface_tile_visual_confirm_color(pipe_ctx, color);
+	else
+		color_space_to_black_color(
+				dc, pipe_ctx->stream->output_color_space, color);
+
+	if (mpc->funcs->set_bg_color)
+		mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+}
+
 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
-	struct dce_hwseq *hws = dc->hwseq;
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
 	struct mpcc_blnd_cfg blnd_cfg = {{0}};
 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
@@ -2639,18 +2458,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	struct mpc *mpc = dc->res_pool->mpc;
 	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
 
-	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
-		hws->funcs.get_hdr_visual_confirm_color(
-				pipe_ctx, &blnd_cfg.black_color);
-	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
-		hws->funcs.get_surface_visual_confirm_color(
-				pipe_ctx, &blnd_cfg.black_color);
-	} else {
-		color_space_to_black_color(
-				dc, pipe_ctx->stream->output_color_space,
-				&blnd_cfg.black_color);
-	}
-
 	if (per_pixel_alpha)
 		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
 	else
@@ -2685,6 +2492,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	/* If there is no full update, don't need to touch MPC tree*/
 	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
 		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
+		dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 		return;
 	}
 
@@ -2706,6 +2514,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 			NULL,
 			hubp->inst,
 			mpcc_id);
+	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
 
@@ -2719,7 +2528,7 @@ static void update_scaler(struct pipe_ctx *pipe_ctx)
 			pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
 
 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
-	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
+	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
 	/* scaler configuration */
 	pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
 			pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
@@ -2956,35 +2765,6 @@ void dcn10_program_pipe(
 {
 	struct dce_hwseq *hws = dc->hwseq;
 
-	if (pipe_ctx->plane_state->update_flags.bits.full_update)
-		dcn10_enable_plane(dc, pipe_ctx, context);
-
-	dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
-
-	hws->funcs.set_hdr_multiplier(pipe_ctx);
-
-	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
-			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
-			pipe_ctx->plane_state->update_flags.bits.gamma_change)
-		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
-
-	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
-	 * only do gamma programming for full update.
-	 * TODO: This can be further optimized/cleaned up
-	 * Always call this for now since it does memcmp inside before
-	 * doing heavy calculation and programming
-	 */
-	if (pipe_ctx->plane_state->update_flags.bits.full_update)
-		hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
-}
-
-static void dcn10_program_all_pipe_in_tree(
-		struct dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		struct dc_state *context)
-{
-	struct dce_hwseq *hws = dc->hwseq;
-
 	if (pipe_ctx->top_pipe == NULL) {
 		bool blank = !is_pipe_tree_visible(pipe_ctx);
 
@@ -3004,35 +2784,26 @@ static void dcn10_program_all_pipe_in_tree(
 		hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
 	}
 
-	if (pipe_ctx->plane_state != NULL)
-		hws->funcs.program_pipe(dc, pipe_ctx, context);
-
-	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
-		dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
-}
-
-static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
-		struct dc *dc,
-		struct dc_state *context,
-		const struct dc_stream_state *stream)
-{
-	int i;
+	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+		dcn10_enable_plane(dc, pipe_ctx, context);
 
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-		struct pipe_ctx *old_pipe_ctx =
-				&dc->current_state->res_ctx.pipe_ctx[i];
+	dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
 
-		if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
-			continue;
+	hws->funcs.set_hdr_multiplier(pipe_ctx);
 
-		if (pipe_ctx->stream != stream)
-			continue;
+	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
 
-		if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
-			return pipe_ctx;
-	}
-	return NULL;
+	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
+	 * only do gamma programming for full update.
+	 * TODO: This can be further optimized/cleaned up
+	 * Always call this for now since it does memcmp inside before
+	 * doing heavy calculation and programming
+	 */
+	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+		hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
 }
 
 void dcn10_wait_for_pending_cleared(struct dc *dc,
@@ -3067,91 +2838,6 @@ void dcn10_wait_for_pending_cleared(struct dc *dc,
 		}
 }
 
-void dcn10_apply_ctx_for_surface(
-		struct dc *dc,
-		const struct dc_stream_state *stream,
-		int num_planes,
-		struct dc_state *context)
-{
-	struct dce_hwseq *hws = dc->hwseq;
-	int i;
-	struct timing_generator *tg;
-	uint32_t underflow_check_delay_us;
-	bool interdependent_update = false;
-	struct pipe_ctx *top_pipe_to_program =
-			dcn10_find_top_pipe_for_stream(dc, context, stream);
-	DC_LOGGER_INIT(dc->ctx->logger);
-
-	// Clear pipe_ctx flag
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-		pipe_ctx->update_flags.raw = 0;
-	}
-
-	if (!top_pipe_to_program)
-		return;
-
-	tg = top_pipe_to_program->stream_res.tg;
-
-	interdependent_update = top_pipe_to_program->plane_state &&
-		top_pipe_to_program->plane_state->update_flags.bits.full_update;
-
-	underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
-
-	if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
-		ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
-
-	if (underflow_check_delay_us != 0xFFFFFFFF)
-		udelay(underflow_check_delay_us);
-
-	if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
-		ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
-
-	if (num_planes == 0) {
-		/* OTG blank before remove all front end */
-		hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true);
-	}
-
-	/* Disconnect unused mpcc */
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-		struct pipe_ctx *old_pipe_ctx =
-				&dc->current_state->res_ctx.pipe_ctx[i];
-
-		if ((!pipe_ctx->plane_state ||
-		     pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
-		    old_pipe_ctx->plane_state &&
-		    old_pipe_ctx->stream_res.tg == tg) {
-
-			hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx);
-			pipe_ctx->update_flags.bits.disable = 1;
-
-			DC_LOG_DC("Reset mpcc for pipe %d\n",
-					old_pipe_ctx->pipe_idx);
-		}
-	}
-
-	if (num_planes > 0)
-		dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
-
-	/* Program secondary blending tree and writeback pipes */
-	if ((stream->num_wb_info > 0) && (hws->funcs.program_all_writeback_pipes_in_tree))
-		hws->funcs.program_all_writeback_pipes_in_tree(dc, stream, context);
-	if (interdependent_update)
-		for (i = 0; i < dc->res_pool->pipe_count; i++) {
-			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-			/* Skip inactive pipes and ones already updated */
-			if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
-			    !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
-				continue;
-
-			pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
-				pipe_ctx->plane_res.hubp,
-				&pipe_ctx->dlg_regs,
-				&pipe_ctx->ttu_regs);
-		}
-}
-
 void dcn10_post_unlock_program_front_end(
 		struct dc *dc,
 		struct dc_state *context)
@@ -3559,10 +3245,17 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 	 * about the actual size being incorrect, that's a limitation of
 	 * the hardware.
 	 */
-	x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
-			pipe_ctx->plane_state->dst_rect.width;
-	y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
-			pipe_ctx->plane_state->dst_rect.height;
+	if (param.rotation == ROTATION_ANGLE_90 || param.rotation == ROTATION_ANGLE_270) {
+		x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height /
+				pipe_ctx->plane_state->dst_rect.width;
+		y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width /
+				pipe_ctx->plane_state->dst_rect.height;
+	} else {
+		x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
+				pipe_ctx->plane_state->dst_rect.width;
+		y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
+				pipe_ctx->plane_state->dst_rect.height;
+	}
 
 	/**
 	 * If the cursor's source viewport is clipped then we need to
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 37bec421fde8..9ae07c77fdc0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -80,11 +80,6 @@ void dcn10_lock_all_pipes(
 		struct dc *dc,
 		struct dc_state *context,
 		bool lock);
-void dcn10_apply_ctx_for_surface(
-		struct dc *dc,
-		const struct dc_stream_state *stream,
-		int num_planes,
-		struct dc_state *context);
 void dcn10_post_unlock_program_front_end(
 		struct dc *dc,
 		struct dc_state *context);
@@ -194,12 +189,6 @@ void dcn10_bios_golden_init(struct dc *dc);
 void dcn10_plane_atomic_power_down(struct dc *dc,
 		struct dpp *dpp,
 		struct hubp *hubp);
-void dcn10_get_surface_visual_confirm_color(
-		const struct pipe_ctx *pipe_ctx,
-		struct tg_color *color);
-void dcn10_get_hdr_visual_confirm_color(
-		struct pipe_ctx *pipe_ctx,
-		struct tg_color *color);
 bool dcn10_disconnect_pipes(
 		struct dc *dc,
 		struct dc_state *context);
@@ -211,4 +200,10 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 
 void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
 
+void dcn10_update_visual_confirm_color(
+		struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color,
+		int mpcc_id);
+
 #endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index d532c78ee764..34001a30d449 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -26,13 +26,15 @@
 #include "hw_sequencer_private.h"
 #include "dce110/dce110_hw_sequencer.h"
 #include "dcn10_hw_sequencer.h"
+#include "dcn20/dcn20_hwseq.h"
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
 	.program_gamut_remap = dcn10_program_gamut_remap,
 	.init_hw = dcn10_init_hw,
 	.power_down_on_boot = dcn10_power_down_on_boot,
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
-	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+	.apply_ctx_for_surface = NULL,
+	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
 	.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 	.update_plane_addr = dcn10_update_plane_addr,
@@ -80,6 +82,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,
 	.set_pipe = dce110_set_pipe,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn10_private_funcs = {
@@ -109,8 +112,6 @@ static const struct hwseq_private_funcs dcn10_private_funcs = {
 	.dpp_pg_control = dcn10_dpp_pg_control,
 	.hubp_pg_control = dcn10_hubp_pg_control,
 	.dsc_pg_control = NULL,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 3e1a582e4b88..d8b22618b79e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -160,6 +160,12 @@ struct dcn10_link_enc_registers {
 	uint32_t PHYA_LINK_CNTL2;
 	uint32_t PHYB_LINK_CNTL2;
 	uint32_t PHYC_LINK_CNTL2;
+	uint32_t DIO_LINKA_CNTL;
+	uint32_t DIO_LINKB_CNTL;
+	uint32_t DIO_LINKC_CNTL;
+	uint32_t DIO_LINKD_CNTL;
+	uint32_t DIO_LINKE_CNTL;
+	uint32_t DIO_LINKF_CNTL;
 };
 
 #define LE_SF(reg_name, field_name, post_fix)\
@@ -460,16 +466,23 @@ struct dcn10_link_enc_registers {
 	type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
 	type RDPCS_TX_CLK_EN
 
+#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
+	type ENC_TYPE_SEL;\
+	type HPO_DP_ENC_SEL;\
+	type HPO_HDMI_ENC_SEL
+
 struct dcn10_link_enc_shift {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 };
 
 struct dcn10_link_enc_mask {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 };
 
 struct dcn10_link_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index b096011acb49..11019c2c62cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -45,6 +45,8 @@ void mpc1_set_bg_color(struct mpc *mpc,
 	struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
 	uint32_t bg_r_cr, bg_g_y, bg_b_cb;
 
+	bottommost_mpcc->blnd_cfg.black_color = *bg_color;
+
 	/* find bottommost mpcc. */
 	while (bottommost_mpcc->mpcc_bot) {
 		bottommost_mpcc = bottommost_mpcc->mpcc_bot;
@@ -81,7 +83,6 @@ static void mpc1_update_blending(
 			MPCC_GLOBAL_ALPHA,		blnd_cfg->global_alpha,
 			MPCC_GLOBAL_GAIN,		blnd_cfg->global_gain);
 
-	mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
 	mpcc->blnd_cfg = *blnd_cfg;
 }
 
@@ -495,6 +496,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
 	.set_output_csc = NULL,
 	.set_output_gamma = NULL,
 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
+	.set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 677663cc7bff..3696faf12d86 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -968,6 +968,17 @@ void optc1_set_drr(
 	}
 }
 
+void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_SET(OTG_V_TOTAL_MAX, 0,
+		OTG_V_TOTAL_MAX, vtotal_max);
+
+	REG_SET(OTG_V_TOTAL_MIN, 0,
+		OTG_V_TOTAL_MIN, vtotal_min);
+}
+
 static void optc1_set_test_pattern(
 	struct timing_generator *optc,
 	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
@@ -1543,6 +1554,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.unlock = optc1_unlock,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.set_test_pattern = optc1_set_test_pattern,
 		.program_stereo = optc1_program_stereo,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index cabfe83fd634..29d6fbe0093a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -171,6 +171,7 @@ struct dcn_optc_registers {
 	uint32_t OPTC_DATA_FORMAT_CONTROL;
 	uint32_t OPTC_BYTES_PER_PIXEL;
 	uint32_t OPTC_WIDTH_CONTROL;
+	uint32_t OTG_DRR_CONTROL;
 	uint32_t OTG_BLANK_DATA_COLOR;
 	uint32_t OTG_BLANK_DATA_COLOR_EXT;
 	uint32_t OTG_DRR_TRIGGER_WINDOW;
@@ -517,7 +518,8 @@ struct dcn_optc_registers {
 	type OTG_CRC_DSC_MODE;\
 	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
 	type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
-	type OTG_CRC_DATA_FORMAT;
+	type OTG_CRC_DATA_FORMAT;\
+	type OTG_V_TOTAL_LAST_USED_BY_DRR;
 
 
 struct dcn_optc_shift {
@@ -666,6 +668,8 @@ void optc1_set_drr(
 	struct timing_generator *optc,
 	const struct drr_params *params);
 
+void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
+
 void optc1_set_static_screen_control(
 	struct timing_generator *optc,
 	uint32_t event_triggers,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index f962b905e79e..7daadb6a5233 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1266,8 +1266,6 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont
 
 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
 {
-	enum dc_status result = DC_OK;
-
 	enum surface_pixel_format surf_pix_format = plane_state->format;
 	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
 
@@ -1279,7 +1277,7 @@ static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *pla
 		swizzle = DC_SW_64KB_S;
 
 	plane_state->tiling_info.gfx9.swizzle = swizzle;
-	return result;
+	return DC_OK;
 }
 
 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 76b334644f9e..0d86df97878c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -52,6 +52,7 @@
 	SRI(AFMT_60958_1, DIG, id), \
 	SRI(AFMT_60958_2, DIG, id), \
 	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(DIG_FIFO_STATUS, DIG, id), \
 	SRI(HDMI_CONTROL, DIG, id), \
 	SRI(HDMI_DB_CONTROL, DIG, id), \
 	SRI(HDMI_GC, DIG, id), \
@@ -124,6 +125,7 @@ struct dcn10_stream_enc_registers {
 	uint32_t AFMT_60958_2;
 	uint32_t DIG_FE_CNTL;
 	uint32_t DIG_FE_CNTL2;
+	uint32_t DIG_FIFO_STATUS;
 	uint32_t DP_MSE_RATE_CNTL;
 	uint32_t DP_MSE_RATE_UPDATE;
 	uint32_t DP_PIXEL_FORMAT;
@@ -266,6 +268,17 @@ struct dcn10_stream_enc_registers {
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
@@ -488,6 +501,17 @@ struct dcn10_stream_enc_registers {
 	type DP_VID_N_MUL;\
 	type DP_VID_M_DOUBLE_VALUE_EN;\
 	type DIG_SOURCE_SELECT;\
+	type DIG_FIFO_LEVEL_ERROR;\
+	type DIG_FIFO_USE_OVERWRITE_LEVEL;\
+	type DIG_FIFO_OVERWRITE_LEVEL;\
+	type DIG_FIFO_ERROR_ACK;\
+	type DIG_FIFO_CAL_AVERAGE_LEVEL;\
+	type DIG_FIFO_MAXIMUM_LEVEL;\
+	type DIG_FIFO_MINIMUM_LEVEL;\
+	type DIG_FIFO_READ_CLOCK_SRC;\
+	type DIG_FIFO_CALIBRATED;\
+	type DIG_FIFO_FORCE_RECAL_AVERAGE;\
+	type DIG_FIFO_FORCE_RECOMP_MINMAX;\
 	type DIG_CLOCK_PATTERN
 
 #define SE_REG_FIELD_LIST_DCN2_0(type) \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index 8774406120fc..5999b2da3a01 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -96,6 +96,39 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
 	return;
 }
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+		bool en)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL,
+			DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0);
+}
+
+void dccg2_otg_add_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 0,
+			OTG_DROP_PIXEL[otg_inst], 0);
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 1);
+}
+
+void dccg2_otg_drop_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 0,
+			OTG_DROP_PIXEL[otg_inst], 0);
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_DROP_PIXEL[otg_inst], 1);
+}
+
 void dccg2_init(struct dccg *dccg)
 {
 }
@@ -103,6 +136,9 @@ void dccg2_init(struct dccg *dccg)
 static const struct dccg_funcs dccg2_funcs = {
 	.update_dpp_dto = dccg2_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index d407f33308b9..ede65100a050 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -34,12 +34,19 @@
 	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
-	SR(REFCLK_CNTL)
+	SR(REFCLK_CNTL),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SR(DISPCLK_FREQ_CHANGE_CNTL)
 
 #define DCCG_REG_LIST_DCN2() \
 	DCCG_COMMON_REG_LIST_DCN_BASE(),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
-	DCCG_SRII(DTO_PARAM, DPPCLK, 5)
+	DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
 
 #define DCCG_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -47,6 +54,9 @@
 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
 	.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
 
+#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
+	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
+
 #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
@@ -59,14 +69,49 @@
 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
 	DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
-	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
+	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
+
+
+
 
 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
 	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
-	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh)
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
+
+#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \
+	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
+
 
 #define DCCG_REG_FIELD_LIST(type) \
 	type DPPCLK0_DTO_PHASE;\
@@ -74,7 +119,18 @@
 	type DPPCLK_DTO_ENABLE[6];\
 	type DPPCLK_DTO_DB_EN[6];\
 	type REFCLK_CLOCK_EN;\
-	type REFCLK_SRC_SEL;
+	type REFCLK_SRC_SEL;\
+	type DISPCLK_STEP_DELAY;\
+	type DISPCLK_STEP_SIZE;\
+	type DISPCLK_FREQ_RAMP_DONE;\
+	type DISPCLK_MAX_ERRDET_CYCLES;\
+	type DCCG_FIFO_ERRDET_RESET;\
+	type DCCG_FIFO_ERRDET_STATE;\
+	type DCCG_FIFO_ERRDET_OVR_EN;\
+	type DISPCLK_CHG_FWD_CORR_DISABLE;\
+	type DISPCLK_FREQ_CHANGE_CNTL;\
+	type OTG_ADD_PIXEL[MAX_PIPES];\
+	type OTG_DROP_PIXEL[MAX_PIPES];
 
 #define DCCG3_REG_FIELD_LIST(type) \
 	type PHYASYMCLK_FORCE_EN;\
@@ -84,24 +140,71 @@
 	type PHYCSYMCLK_FORCE_EN;\
 	type PHYCSYMCLK_FORCE_SRC_SEL;
 
+#define DCCG31_REG_FIELD_LIST(type) \
+	type PHYDSYMCLK_FORCE_EN;\
+	type PHYDSYMCLK_FORCE_SRC_SEL;\
+	type PHYESYMCLK_FORCE_EN;\
+	type PHYESYMCLK_FORCE_SRC_SEL;\
+	type DPSTREAMCLK_PIPE0_EN;\
+	type DPSTREAMCLK_PIPE1_EN;\
+	type DPSTREAMCLK_PIPE2_EN;\
+	type DPSTREAMCLK_PIPE3_EN;\
+	type HDMISTREAMCLK0_SRC_SEL;\
+	type HDMISTREAMCLK0_DTO_FORCE_DIS;\
+	type SYMCLK32_SE0_SRC_SEL;\
+	type SYMCLK32_SE1_SRC_SEL;\
+	type SYMCLK32_SE2_SRC_SEL;\
+	type SYMCLK32_SE3_SRC_SEL;\
+	type SYMCLK32_SE0_EN;\
+	type SYMCLK32_SE1_EN;\
+	type SYMCLK32_SE2_EN;\
+	type SYMCLK32_SE3_EN;\
+	type SYMCLK32_LE0_SRC_SEL;\
+	type SYMCLK32_LE1_SRC_SEL;\
+	type SYMCLK32_LE0_EN;\
+	type SYMCLK32_LE1_EN;\
+	type DTBCLK_DTO_ENABLE[MAX_PIPES];\
+	type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
+	type PIPE_DTO_SRC_SEL[MAX_PIPES];\
+	type DTBCLK_DTO_DIV[MAX_PIPES];\
+	type DCCG_AUDIO_DTO_SEL;\
+	type DCCG_AUDIO_DTO0_SOURCE_SEL;\
+	type DENTIST_DISPCLK_CHG_MODE;
+
 struct dccg_shift {
 	DCCG_REG_FIELD_LIST(uint8_t)
 	DCCG3_REG_FIELD_LIST(uint8_t)
+	DCCG31_REG_FIELD_LIST(uint8_t)
 };
 
 struct dccg_mask {
 	DCCG_REG_FIELD_LIST(uint32_t)
 	DCCG3_REG_FIELD_LIST(uint32_t)
+	DCCG31_REG_FIELD_LIST(uint32_t)
 };
 
 struct dccg_registers {
 	uint32_t DPPCLK_DTO_CTRL;
 	uint32_t DPPCLK_DTO_PARAM[6];
 	uint32_t REFCLK_CNTL;
+	uint32_t DISPCLK_FREQ_CHANGE_CNTL;
+	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
 	uint32_t HDMICHARCLK_CLOCK_CNTL[6];
 	uint32_t PHYASYMCLK_CLOCK_CNTL;
 	uint32_t PHYBSYMCLK_CLOCK_CNTL;
 	uint32_t PHYCSYMCLK_CLOCK_CNTL;
+	uint32_t PHYDSYMCLK_CLOCK_CNTL;
+	uint32_t PHYESYMCLK_CLOCK_CNTL;
+	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
+	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
+	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
+	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;
+	uint32_t DCCG_AUDIO_DTO_SOURCE;
+	uint32_t DPSTREAMCLK_CNTL;
+	uint32_t HDMISTREAMCLK_CNTL;
+	uint32_t SYMCLK32_SE_CNTL;
+	uint32_t SYMCLK32_LE_CNTL;
+	uint32_t DENTIST_DISPCLK_CNTL;
 };
 
 struct dcn_dccg {
@@ -117,6 +220,14 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
 		unsigned int xtalin_freq_inKhz,
 		unsigned int *dccg_ref_freq_inKhz);
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+		bool en);
+void dccg2_otg_add_pixel(struct dccg *dccg,
+		uint32_t otg_inst);
+void dccg2_otg_drop_pixel(struct dccg *dccg,
+		uint32_t otg_inst);
+
+
 void dccg2_init(struct dccg *dccg);
 
 struct dccg *dccg2_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 4af96cc5d9d6..a9e420c7d75a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -166,7 +166,8 @@ static void dpp2_cnv_setup (
 		select = DCN2_ICSC_SELECT_ICSC_A;
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-		pixel_format = 22;
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
+		pixel_format = 26; /* ARGB16161616_UNORM */
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 		pixel_format = 24;
@@ -431,7 +432,8 @@ bool dpp2_construct(
 	dpp->lb_pixel_depth_supported =
 		LB_PIXEL_DEPTH_18BPP |
 		LB_PIXEL_DEPTH_24BPP |
-		LB_PIXEL_DEPTH_30BPP;
+		LB_PIXEL_DEPTH_30BPP |
+		LB_PIXEL_DEPTH_36BPP;
 
 	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
index 8dc3d1f73984..2feb051a2002 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
@@ -482,7 +482,7 @@ bool dpp20_program_blnd_lut(
 		next_mode = LUT_RAM_A;
 
 	dpp20_power_on_blnd_lut(dpp_base, true);
-	dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
+	dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
 
 	if (next_mode == LUT_RAM_A)
 		dpp20_program_blnd_luta_settings(dpp_base, params);
@@ -893,7 +893,7 @@ bool dpp20_program_shaper(
 	else
 		next_mode = LUT_RAM_A;
 
-	dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
+	dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
 
 	if (next_mode == LUT_RAM_A)
 		dpp20_program_shaper_luta_settings(dpp_base, params);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index 6d03d98fca22..91a9305d42e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -158,6 +158,7 @@ bool hubbub2_dcc_support_pixel_format(
 		*bytes_per_element = 4;
 		return true;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 		*bytes_per_element = 8;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index c478213ba7ad..10af257d90ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -83,6 +83,13 @@ struct dcn20_hubbub {
 	int num_vmid;
 	struct dcn20_vmid vmid[16];
 	unsigned int detile_buf_size;
+	unsigned int crb_size_segs;
+	unsigned int compbuf_size_segments;
+	unsigned int pixel_chunk_size;
+	unsigned int det0_size;
+	unsigned int det1_size;
+	unsigned int det2_size;
+	unsigned int det3_size;
 };
 
 void hubbub2_construct(struct dcn20_hubbub *hubbub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index a1318c31bcfa..7e54058715aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -431,6 +431,7 @@ void hubp2_program_pixel_format(
 	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 		red_bar = 2;
 		blue_bar = 3;
@@ -463,8 +464,9 @@ void hubp2_program_pixel_format(
 				SURFACE_PIXEL_FORMAT, 10);
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-				SURFACE_PIXEL_FORMAT, 22);
+				SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index f501c02c244b..eea2254b15e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -216,16 +216,22 @@
 	type ROW_TTU_MODE; \
 	type NUM_PKRS
 
+#define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+	type HUBP_UNBOUNDED_REQ_MODE;\
+	type CURSOR_REQ_MODE;\
+	type HUBP_SOFT_RESET
+
 struct dcn_hubp2_registers {
 	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
 };
 
 struct dcn_hubp2_shift {
-	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
+	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
 };
 
 struct dcn_hubp2_mask {
-	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
+	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
 };
 
 struct dcn20_hubp {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6a10daec15cc..5c2853654cca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -51,6 +51,7 @@
 #include "dccg.h"
 #include "dc_dmub_srv.h"
 #include "dce/dmub_hw_lock_mgr.h"
+#include "hw_sequencer.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -243,7 +244,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
 	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 
 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
-	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 }
 
 void dcn20_disable_vga(
@@ -1269,6 +1270,7 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx
 		new_pipe->update_flags.bits.gamut_remap = 1;
 		new_pipe->update_flags.bits.scaler = 1;
 		new_pipe->update_flags.bits.viewport = 1;
+		new_pipe->update_flags.bits.det_size = 1;
 		if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
 			new_pipe->update_flags.bits.odm = 1;
 			new_pipe->update_flags.bits.global_sync = 1;
@@ -1303,6 +1305,9 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx
 			new_pipe->update_flags.bits.global_sync = 1;
 	}
 
+	if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
+		new_pipe->update_flags.bits.det_size = 1;
+
 	/*
 	 * Detect opp / tg change, only set on change, not on enable
 	 * Assume mpcc inst = pipe index, if not this code needs to be updated
@@ -1418,6 +1423,9 @@ static void dcn20_update_dchubp_dpp(
 			&pipe_ctx->ttu_regs,
 			&pipe_ctx->rq_regs,
 			&pipe_ctx->pipe_dlg_param);
+
+		if (hubp->funcs->set_unbounded_requesting)
+			hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
 	}
 	if (pipe_ctx->update_flags.bits.hubp_interdependent)
 		hubp->funcs->hubp_setup_interdependent(
@@ -1473,7 +1481,7 @@ static void dcn20_update_dchubp_dpp(
 			plane_state->update_flags.bits.per_pixel_alpha_change ||
 			pipe_ctx->stream->update_flags.bits.scaling) {
 		pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
-		ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
+		ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
 		/* scaler configuration */
 		pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
@@ -1597,6 +1605,10 @@ static void dcn20_program_pipe(
 			dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
 	}
 
+	if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
+		dc->res_pool->hubbub->funcs->program_det_size(
+			dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
+
 	if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
 		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
 
@@ -1687,6 +1699,10 @@ void dcn20_program_front_end_for_ctx(
 	for (i = 0; i < dc->res_pool->pipe_count; i++)
 		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
 				|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
+			struct hubbub *hubbub = dc->res_pool->hubbub;
+
+			if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
+				hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
 			hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
 			DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
 		}
@@ -1700,7 +1716,11 @@ void dcn20_program_front_end_for_ctx(
 
 		if (pipe->plane_state && !pipe->top_pipe) {
 			while (pipe) {
-				dcn20_program_pipe(dc, pipe, context);
+				if (hws->funcs.program_pipe)
+					hws->funcs.program_pipe(dc, pipe, context);
+				else
+					dcn20_program_pipe(dc, pipe, context);
+
 				pipe = pipe->bottom_pipe;
 			}
 			/* Program secondary blending tree and writeback pipes */
@@ -1800,6 +1820,9 @@ void dcn20_prepare_bandwidth(
 					&context->bw_ctx.bw.dcn.watermarks,
 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
 					false);
+	/* decrease compbuf size */
+	if (hubbub->funcs->program_compbuf_size)
+		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false);
 }
 
 void dcn20_optimize_bandwidth(
@@ -1818,6 +1841,9 @@ void dcn20_optimize_bandwidth(
 			dc->clk_mgr,
 			context,
 			true);
+	/* increase compbuf size */
+	if (hubbub->funcs->program_compbuf_size)
+		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
 }
 
 bool dcn20_update_bandwidth(
@@ -2241,31 +2267,26 @@ void dcn20_reset_hw_ctx_wrap(
 	}
 }
 
-void dcn20_get_mpctree_visual_confirm_color(
-		struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
+void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
 {
-	const struct tg_color pipe_colors[6] = {
-			{MAX_TG_COLOR_VALUE, 0, 0}, // red
-			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, // orange
-			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, // yellow
-			{0, MAX_TG_COLOR_VALUE, 0}, // green
-			{0, 0, MAX_TG_COLOR_VALUE}, // blue
-			{MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
-	};
-
-	struct pipe_ctx *top_pipe = pipe_ctx;
-
-	while (top_pipe->top_pipe) {
-		top_pipe = top_pipe->top_pipe;
-	}
+	struct mpc *mpc = dc->res_pool->mpc;
 
-	*color = pipe_colors[top_pipe->pipe_idx];
+	// input to MPCC is always RGB, by default leave black_color at 0
+	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
+		get_hdr_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
+		get_surface_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
+		get_mpctree_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
+		get_surface_tile_visual_confirm_color(pipe_ctx, color);
+
+	if (mpc->funcs->set_bg_color)
+		mpc->funcs->set_bg_color(mpc, color, mpcc_id);
 }
 
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
-	struct dce_hwseq *hws = dc->hwseq;
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
 	struct mpcc_blnd_cfg blnd_cfg = { {0} };
 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
@@ -2274,15 +2295,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	struct mpc *mpc = dc->res_pool->mpc;
 	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
 
-	// input to MPCC is always RGB, by default leave black_color at 0
-	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
-		hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
-	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
-		hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
-	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
-		dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
-	}
-
 	if (per_pixel_alpha)
 		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
 	else
@@ -2320,6 +2332,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
 		!pipe_ctx->update_flags.bits.mpcc) {
 		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
+		dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 		return;
 	}
 
@@ -2341,6 +2354,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 			NULL,
 			hubp->inst,
 			mpcc_id);
+	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
 	hubp->opp_id = pipe_ctx->stream_res.opp->inst;
@@ -2535,6 +2549,9 @@ void dcn20_fpga_init_hw(struct dc *dc)
 
 		tg->funcs->tg_init(tg);
 	}
+
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 }
 #ifndef TRIM_FSFT
 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index c69f766a40ce..6bba191cd33e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -146,5 +146,10 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset);
 
+void dcn20_update_visual_confirm_color(struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color,
+		int mpcc_id);
+
 #endif /* __DC_HWSS_DCN20_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index b5bb613eed4d..5cfd4b0afea5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -96,6 +96,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
 #endif
 	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {
@@ -125,8 +126,6 @@ static const struct hwseq_private_funcs dcn20_private_funcs = {
 	.hubp_pg_control = dcn20_hubp_pg_control,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 6a99fdd55e8c..947eb0df3f12 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -67,7 +67,6 @@ void mpc2_update_blending(
 	REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
 	REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
 
-	mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
 	mpcc->blnd_cfg = *blnd_cfg;
 }
 
@@ -557,6 +556,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
 	.set_output_gamma = mpc2_set_output_gamma,
 	.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
+	.set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 3139d90017ee..7fa9fc656b0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -520,6 +520,14 @@ bool optc2_configure_crc(struct timing_generator *optc,
 	return optc1_configure_crc(optc, params);
 }
 
+
+void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
+}
+
 static struct timing_generator_funcs dcn20_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
 		.program_timing = optc1_program_timing,
@@ -553,6 +561,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
 		.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
@@ -591,4 +600,3 @@ void dcn20_timing_generator_init(struct optc *optc1)
 	optc1->min_h_sync_width = 4;//	Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
 	optc1->min_v_sync_width = 1;
 }
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index 3dee2ec2a1bb..be19a6885fbf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -42,7 +42,8 @@
 	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
 	SR(DWB_SOURCE_SELECT),\
-	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
+	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
+	SRI(OTG_DRR_CONTROL, OTG, inst)
 
 #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
 	TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
@@ -75,10 +76,14 @@
 	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
 	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
 	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
-	SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh)
+	SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
 void dcn20_timing_generator_init(struct optc *optc);
 
+void optc2_get_last_used_drr_vtotal(struct timing_generator *optc,
+		uint32_t *refresh_rate);
+
 bool optc2_enable_crtc(struct timing_generator *optc);
 
 void optc2_set_gsl(struct timing_generator *optc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 8357aa3c41d5..1b05a37b674d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1065,7 +1065,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.timing_trace = false,
 		.clock_trace = true,
 		.disable_pplib_clock_request = true,
-		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.vsr_support = true,
@@ -2289,12 +2289,14 @@ int dcn20_populate_dml_pipes_from_context(
 
 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
-			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y;
-			pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y;
-			pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width;
-			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width;
-			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height;
-			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height;
+			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
+			pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
+			pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
+			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
+			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
+			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
+			pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
+			pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
 			pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
 			pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
 			pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
@@ -2363,6 +2365,7 @@ int dcn20_populate_dml_pipes_from_context(
 				pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
 				break;
 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 				pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
@@ -2786,7 +2789,6 @@ int dcn20_validate_apply_pipe_split_flags(
 				split[i] = 0;
 			} else if (get_num_odm_splits(pipe)) {
 				/* ODM -> MPC transition */
-				ASSERT(0); /* NOT expected yet */
 				if (pipe->prev_odm_pipe) {
 					split[i] = 0;
 					merge[i] = true;
@@ -3067,6 +3069,16 @@ static void dcn20_calculate_wm(
 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 }
 
+static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+	}
+	return false;
+}
+
 void dcn20_calculate_dlg_params(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
@@ -3074,6 +3086,7 @@ void dcn20_calculate_dlg_params(
 		int vlevel)
 {
 	int i, pipe_idx;
+	int plane_count;
 
 	/* Writeback MCIF_WB arbitration parameters */
 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@@ -3089,6 +3102,20 @@ void dcn20_calculate_dlg_params(
 							!= dm_dram_clock_change_unsupported;
 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
 
+	context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ?
+			DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW;
+
+	plane_count = 0;
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (context->res_ctx.pipe_ctx[i].plane_state)
+			plane_count++;
+	}
+
+	if (plane_count == 0)
+		context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
+
+	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
+
 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
 
@@ -3099,6 +3126,9 @@ void dcn20_calculate_dlg_params(
 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+		context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
+		context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
+
 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
@@ -3112,6 +3142,9 @@ void dcn20_calculate_dlg_params(
 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
 
+	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
+						- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
+
 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
 
@@ -3667,7 +3700,7 @@ static bool dcn20_resource_construct(
 	int i;
 	struct dc_context *ctx = dc->ctx;
 	struct irq_service_init_data init_data;
-	struct ddc_service_init_data ddc_init_data;
+	struct ddc_service_init_data ddc_init_data = {0};
 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
 			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
 	struct _vcs_dpi_ip_params_st *loaded_ip =
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 4075ae111530..e6307397e0d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -552,6 +552,17 @@ void enc2_stream_encoder_dp_set_stream_attribute(
 		DP_SST_SDP_SPLITTING, enable_sdp_splitting);
 }
 
+uint32_t enc2_get_fifo_cal_average_level(
+		struct stream_encoder *enc)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+	uint32_t fifo_level;
+
+	REG_GET(DIG_FIFO_STATUS,
+			DIG_FIFO_CAL_AVERAGE_LEVEL, &fifo_level);
+	return fifo_level;
+}
+
 static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
 	.dp_set_odm_combine =
 		enc2_dp_set_odm_combine,
@@ -598,6 +609,7 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
 	.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
 	.set_dynamic_metadata = enc2_set_dynamic_metadata,
 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+	.get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
 };
 
 void dcn20_stream_encoder_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
index 9a881e639709..f3d1a0237bda 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
@@ -112,4 +112,7 @@ void enc2_set_dynamic_metadata(struct stream_encoder *enc,
 		uint32_t hubp_requestor_id,
 		enum dynamic_metadata_mode dmdata_mode);
 
+uint32_t enc2_get_fifo_cal_average_level(
+		struct stream_encoder *enc);
+
 #endif /* __DC_STREAM_ENCODER_DCN20_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
index 60cf3ff68cb0..33fc9aa8621b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
@@ -100,6 +100,9 @@ void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
 static const struct dccg_funcs dccg21_funcs = {
 	.update_dpp_dto = dccg21_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
index 8fccee5a3036..69cc192a7e71 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
@@ -218,7 +218,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
 	cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
 	cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;
 	cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_pwm_u16_16;
-	cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1;
+	cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
 	cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_cntl->inst);
 	cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 4f20a85ff396..54c11ba550ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
 	.is_abm_supported = dcn21_is_abm_supported,
 	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn21_private_funcs = {
 	.hubp_pg_control = dcn20_hubp_pg_control,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 8e3f1d0b4cc3..f3d98e3ba624 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -448,11 +448,11 @@ static const struct dccg_registers dccg_regs = {
 };
 
 static const struct dccg_shift dccg_shift = {
-		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
+		DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
 };
 
 static const struct dccg_mask dccg_mask = {
-		DCCG_MASK_SH_LIST_DCN2(_MASK)
+		DCCG_MASK_SH_LIST_DCN2_1(_MASK)
 };
 
 #define opp_regs(id)\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
index b822a13e40ce..d445dfefc047 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
@@ -46,6 +46,9 @@
 static const struct dccg_funcs dccg3_funcs = {
 	.update_dpp_dto = dccg2_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
index 029dda13a464..35a613bb08bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
@@ -38,10 +38,25 @@
 
 #define DCCG_REG_LIST_DCN30() \
 	DCCG_REG_LIST_DCN2(),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
 	SR(PHYASYMCLK_CLOCK_CNTL),\
 	SR(PHYBSYMCLK_CLOCK_CNTL),\
 	SR(PHYCSYMCLK_CLOCK_CNTL)
 
+#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
+	DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
+
 #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
 	DCCG_MASK_SH_LIST_DCN2(mask_sh),\
 	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
@@ -49,7 +64,7 @@
 	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
 	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
 	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
-	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
 
 struct dccg *dccg3_create(
 	struct dc_context *ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index 72bee637c1e4..8487516819ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -823,6 +823,8 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = {
 	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
 	.set_dynamic_metadata = enc2_set_dynamic_metadata,
 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+
+	.get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
 };
 
 void dcn30_dio_stream_encoder_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
index 0b1755f1dea8..e2c264ecb20f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
@@ -85,7 +85,9 @@
 	SRI(DP_MSE_RATE_UPDATE, DP, id), \
 	SRI(DP_PIXEL_FORMAT, DP, id), \
 	SRI(DP_SEC_CNTL, DP, id), \
+	SRI(DP_SEC_CNTL1, DP, id), \
 	SRI(DP_SEC_CNTL2, DP, id), \
+	SRI(DP_SEC_CNTL5, DP, id), \
 	SRI(DP_SEC_CNTL6, DP, id), \
 	SRI(DP_STEER_FIFO, DP, id), \
 	SRI(DP_VID_M, DP, id), \
@@ -104,6 +106,7 @@
 	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
 	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
 	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(DIG_FIFO_STATUS, DIG, id), \
 	SRI(DIG_CLOCK_PATTERN, DIG, id)
 
 
@@ -165,11 +168,24 @@
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\
 	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 434d3c46cad4..2140b75540cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -245,7 +245,8 @@ static void dpp3_cnv_setup (
 		select = INPUT_CSC_SELECT_ICSC;
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-		pixel_format = 22;
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
+		pixel_format = 26; /* ARGB16161616_UNORM */
 		break;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 		pixel_format = 24;
@@ -1442,7 +1443,8 @@ bool dpp3_construct(
 	dpp->lb_pixel_depth_supported =
 		LB_PIXEL_DEPTH_18BPP |
 		LB_PIXEL_DEPTH_24BPP |
-		LB_PIXEL_DEPTH_30BPP;
+		LB_PIXEL_DEPTH_30BPP |
+		LB_PIXEL_DEPTH_36BPP;
 
 	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index d53f8b39699b..c68e3a708a33 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -48,6 +48,8 @@
 #include "dc_dmub_srv.h"
 #include "link_hwss.h"
 #include "dpcd_defs.h"
+#include "inc/dc_link_dp.h"
+#include "inc/link_dpcd.h"
 
 
 
@@ -529,6 +531,8 @@ void dcn30_init_hw(struct dc *dc)
 		for (i = 0; i < dc->link_count; i++) {
 			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
 				continue;
+			/* DP 2.0 states that LTTPR regs must be read first */
+			dp_retrieve_lttpr_cap(dc->links[i]);
 
 			/* if any of the displays are lit up turn them off */
 			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
@@ -651,6 +655,9 @@ void dcn30_init_hw(struct dc *dc)
 	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
 				dc->res_pool->hubbub, false, false);
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
+
 }
 
 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
@@ -813,6 +820,15 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 						(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
 						denom) - 64LL;
 
+				/* In some cases the stutter period is really big (tiny modes) in these
+				 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
+				 *
+				 * We can check if stutter_period is more than 1/10th the frame time to
+				 * consider if we can actually meet the range of hysteresis timer
+				 */
+				if (stutter_period > 100000/refresh_hz)
+					return false;
+
 				/* scale should be increased until it fits into 6 bits */
 				while (tmr_delay & ~0x3F) {
 					tmr_scale++;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index bf7fa98b39eb..3a5b53dd2f6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -99,6 +99,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.set_pipe = dcn21_set_pipe,
 	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn30_private_funcs = {
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn30_private_funcs = {
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 910c17fd4278..a82319f4d081 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -874,7 +874,7 @@ bool mpc3_program_shaper(
 	else
 		next_mode = LUT_RAM_A;
 
-	mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, rmu_idx);
+	mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, rmu_idx);
 
 	if (next_mode == LUT_RAM_A)
 		mpc3_program_shaper_luta_settings(mpc, params, rmu_idx);
@@ -1431,7 +1431,7 @@ const struct mpc_funcs dcn30_mpc_funcs = {
 	.release_rmu = mpcc3_release_rmu,
 	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
-
+	.set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn30_mpc_construct(struct dcn30_mpc *mpc30,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
index d1fd0b9aa0f9..b7dc78624963 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
@@ -585,6 +585,181 @@
 	type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
 	type MPC_RMU_SHAPER_MODE_CURRENT
 
+#define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \
+	MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
+	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
+	SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
+	SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
+	SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
+	SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
+	SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
+	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
+	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
+	SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
+	SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
+	SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
+	SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
+	SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
+	SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
+	SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
+	/*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
+	SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\
+	SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\
+	/*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\
+	SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\
+	SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\
+	SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\
+	/*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\
+	SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\
+	SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\
+	SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\
+	SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\
+	SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\
+	SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\
+	/*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\
+	SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\
+	SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\
+	SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\
+	SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\
+	SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\
+	SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\
+	SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\
+	SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\
+	SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
+	SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\
+	/*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\
+	SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
+	SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
+	SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
+	SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
+	SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+	SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+	SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+	SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\
+	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
+	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
+	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
+	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\
+	SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
+
+#define MPC_REG_FIELD_LIST_DCN3_03(type) \
+	MPC_REG_FIELD_LIST_DCN2_0(type) \
+	type MPC_DWB0_MUX;\
+	type MPC_DWB0_MUX_STATUS;\
+	type MPC_OUT_RATE_CONTROL;\
+	type MPC_OUT_RATE_CONTROL_DISABLE;\
+	type MPC_OUT_FLOW_CONTROL_MODE;\
+	type MPC_OUT_FLOW_CONTROL_COUNT; \
+	type MPCC_GAMUT_REMAP_MODE; \
+	type MPCC_GAMUT_REMAP_MODE_CURRENT;\
+	type MPCC_GAMUT_REMAP_COEF_FORMAT; \
+	type MPCC_GAMUT_REMAP_C11_A; \
+	type MPCC_GAMUT_REMAP_C12_A; \
+	type MPC_RMU0_MUX; \
+	type MPC_RMU0_MUX_STATUS; \
+	type MPC_RMU0_MEM_PWR_FORCE;\
+	type MPC_RMU0_MEM_PWR_DIS;\
+	type MPC_RMU0_MEM_LOW_PWR_MODE;\
+	type MPC_RMU0_SHAPER_MEM_PWR_STATE;\
+	type MPC_RMU0_3DLUT_MEM_PWR_STATE;\
+	type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \
+	type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\
+	type MPCC_OGAM_RAMA_OFFSET_B;\
+	type MPCC_OGAM_RAMA_OFFSET_G;\
+	type MPCC_OGAM_RAMA_OFFSET_R;\
+	type MPCC_OGAM_SELECT; \
+	type MPCC_OGAM_PWL_DISABLE; \
+	type MPCC_OGAM_MODE_CURRENT; \
+	type MPCC_OGAM_SELECT_CURRENT; \
+	type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \
+	type MPCC_OGAM_LUT_READ_COLOR_SEL; \
+	type MPCC_OGAM_LUT_READ_DBG; \
+	type MPCC_OGAM_LUT_HOST_SEL; \
+	type MPCC_OGAM_LUT_CONFIG_MODE; \
+	type MPCC_OGAM_LUT_STATUS; \
+	type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\
+	type MPCC_OGAM_MEM_LOW_PWR_MODE;\
+	type MPCC_OGAM_MEM_PWR_STATE;\
+	type MPC_RMU_3DLUT_MODE; \
+	type MPC_RMU_3DLUT_SIZE; \
+	type MPC_RMU_3DLUT_MODE_CURRENT; \
+	type MPC_RMU_3DLUT_WRITE_EN_MASK;\
+	type MPC_RMU_3DLUT_RAM_SEL;\
+	type MPC_RMU_3DLUT_30BIT_EN;\
+	type MPC_RMU_3DLUT_CONFIG_STATUS;\
+	type MPC_RMU_3DLUT_READ_SEL;\
+	type MPC_RMU_3DLUT_INDEX;\
+	type MPC_RMU_3DLUT_DATA0;\
+	type MPC_RMU_3DLUT_DATA1;\
+	type MPC_RMU_3DLUT_DATA_30BIT;\
+	type MPC_RMU_SHAPER_LUT_MODE;\
+	type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\
+	type MPC_RMU_SHAPER_OFFSET_R;\
+	type MPC_RMU_SHAPER_OFFSET_G;\
+	type MPC_RMU_SHAPER_OFFSET_B;\
+	type MPC_RMU_SHAPER_SCALE_R;\
+	type MPC_RMU_SHAPER_SCALE_G;\
+	type MPC_RMU_SHAPER_SCALE_B;\
+	type MPC_RMU_SHAPER_LUT_INDEX;\
+	type MPC_RMU_SHAPER_LUT_DATA;\
+	type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\
+	type MPC_RMU_SHAPER_LUT_WRITE_SEL;\
+	type MPC_RMU_SHAPER_CONFIG_STATUS;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
+	type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
+	type MPC_RMU_SHAPER_MODE_CURRENT
 
 struct dcn30_mpc_registers {
 	MPC_REG_VARIABLE_LIST_DCN3_0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 8980c90b2277..f37e8254df21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -97,7 +97,7 @@ void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
 		MASTER_UPDATE_LOCK_DB_END_Y, 0);
 
 	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
-	REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 1);
+	REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
 }
 
 void optc3_lock(struct timing_generator *optc)
@@ -315,6 +315,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = {
 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
index 379616831636..736e63bc80c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
@@ -87,7 +87,8 @@
 	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
 	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
 	SR(GSL_SOURCE_SELECT),\
-	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
+	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+	SRI(OTG_DRR_CONTROL, OTG, inst)
 
 
 #define OPTC_COMMON_REG_LIST_DCN3_0(inst) \
@@ -233,7 +234,8 @@
 	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
 	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
 	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh)\
 	OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 5fcc2e64305d..596c97dce67e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -840,7 +840,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.timing_trace = false,
 	.clock_trace = true,
 	.disable_pplib_clock_request = true,
-	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 	.force_single_disp_pipe_split = false,
 	.disable_dcc = DCC_ENABLE,
 	.vsr_support = true,
@@ -1725,7 +1725,7 @@ static bool init_soc_bounding_box(struct dc *dc,
 	DC_LOGGER_INIT(dc->ctx->logger);
 
 	if (!is_soc_bounding_box_valid(dc)) {
-		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
 		return false;
 	}
 
@@ -2539,7 +2539,7 @@ static bool dcn30_resource_construct(
 	int i;
 	struct dc_context *ctx = dc->ctx;
 	struct irq_service_init_data init_data;
-	struct ddc_service_init_data ddc_init_data;
+	struct ddc_service_init_data ddc_init_data = {0};
 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
 	uint32_t num_pipes = 0;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
index 420da414929c..97e9be87afd9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
@@ -45,6 +45,9 @@
 static const struct dccg_funcs dccg301_funcs = {
 	.update_dpp_dto = dccg2_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
index 70b053d9ba40..e85b695f2351 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -101,6 +101,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
 	.optimize_pwr_state = dcn21_optimize_pwr_state,
 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn301_private_funcs = {
@@ -131,8 +132,6 @@ static const struct hwseq_private_funcs dcn301_private_funcs = {
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 472696f949ac..9776d1737818 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1498,7 +1498,7 @@ static bool init_soc_bounding_box(struct dc *dc,
 	DC_LOGGER_INIT(dc->ctx->logger);
 
 	if (!is_soc_bounding_box_valid(dc)) {
-		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
 		return false;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
index e8580cccbebf..0a6d58dd8f6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
@@ -86,17 +86,12 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool po
 				1, 1000);
 		break;
 	case 4: /* DPP4 */
-		/*
-		 * Do not power gate DPP4, should be left at HW default, power on permanently.
-		 * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
-		 * reset.
-		 * REG_UPDATE(DOMAIN9_PG_CONFIG,
-		 *		DOMAIN9_POWER_GATE, power_gate);
-		 *
-		 * REG_WAIT(DOMAIN9_PG_STATUS,
-		 *		DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
-		 *		1, 1000);
-		 */
+		REG_UPDATE(DOMAIN9_PG_CONFIG,
+				DOMAIN9_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN9_PG_STATUS,
+				DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
@@ -148,17 +143,12 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
 				1, 1000);
 		break;
 	case 4: /* DCHUBP4 */
-		/*
-		 * Do not power gate DCHUB4, should be left at HW default, power on permanently.
-		 * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
-		 * reset.
-		 * REG_UPDATE(DOMAIN8_PG_CONFIG,
-		 *		DOMAIN8_POWER_GATE, power_gate);
-		 *
-		 * REG_WAIT(DOMAIN8_PG_STATUS,
-		 *		DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
-		 *		1, 1000);
-		 */
+		REG_UPDATE(DOMAIN8_PG_CONFIG,
+				DOMAIN8_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN8_PG_STATUS,
+				DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index a33f0365329b..16a75ba0ca82 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
 
 		.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
 		.num_states = 1,
-		.sr_exit_time_us = 15.5,
-		.sr_enter_plus_exit_time_us = 20,
+		.sr_exit_time_us = 26.5,
+		.sr_enter_plus_exit_time_us = 31,
 		.urgent_latency_us = 4.0,
 		.urgent_latency_pixel_data_only_us = 4.0,
 		.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
@@ -211,7 +211,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.timing_trace = false,
 		.clock_trace = true,
 		.disable_pplib_clock_request = true,
-		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.vsr_support = true,
@@ -1094,7 +1094,7 @@ static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
 	DC_LOGGER_INIT(dc->ctx->logger);
 
 	if (!is_soc_bounding_box_valid(dc)) {
-		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
 		return false;
 	}
 
@@ -1102,6 +1102,26 @@ static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
 	loaded_ip->max_num_dpp = pool->pipe_count;
 	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
 	dcn20_patch_bounding_box(dc, loaded_bb);
+
+	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+		struct bp_soc_bb_info bb_info = { 0 };
+
+		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
+			    dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+			if (bb_info.dram_clock_change_latency_100ns > 0)
+				dcn3_02_soc.dram_clock_change_latency_us =
+					bb_info.dram_clock_change_latency_100ns * 10;
+
+			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+				dcn3_02_soc.sr_enter_plus_exit_time_us =
+					bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+			if (bb_info.dram_sr_exit_latency_100ns > 0)
+				dcn3_02_soc.sr_exit_time_us =
+					bb_info.dram_sr_exit_latency_100ns * 10;
+		}
+	}
+
 	return true;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/Makefile b/drivers/gpu/drm/amd/display/dc/dcn303/Makefile
new file mode 100644
index 000000000000..6f7a1f2b49f0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/Makefile
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (C) 2021 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  Authors: AMD
+#
+# Makefile for dcn303.
+
+DCN3_03 = dcn303_init.o dcn303_hwseq.o dcn303_resource.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o := -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o += -mhard-float
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn303/dcn303_resource.o += -msse2
+endif
+endif
+
+AMD_DAL_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/dcn303/,$(DCN3_03))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN3_03)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h
new file mode 100644
index 000000000000..a79c54bbc899
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef __DCN303_DCCG_H__
+#define __DCN303_DCCG_H__
+
+#include "dcn30/dcn30_dccg.h"
+
+
+#define DCCG_REG_LIST_DCN3_03() \
+	SR(DPPCLK_DTO_CTRL),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
+	SR(REFCLK_CNTL)
+
+#define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \
+		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
+		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
+		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
+		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
+		DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
+		DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
+		DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
+		DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
+
+#endif //__DCN303_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c
new file mode 100644
index 000000000000..b48b732aa647
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#include "dcn303_hwseq.h"
+
+#include "dce/dce_hwseq.h"
+
+#include "reg_helper.h"
+#include "dc.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+	hws->ctx
+#define REG(reg)\
+	hws->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hws->shifts->field_name, hws->masks->field_name
+
+
+void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)
+{
+	/*DCN303 removes PG registers*/
+}
+
+void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+{
+	/*DCN303 removes PG registers*/
+}
+
+void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)
+{
+	/*DCN303 removes PG registers*/
+}
+
+void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
+{
+	/*DCN303 removes PG registers*/
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.h
new file mode 100644
index 000000000000..8b69a3b76c11
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.h
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef __DC_HWSS_DCN303_H__
+#define __DC_HWSS_DCN303_H__
+
+#include "hw_sequencer_private.h"
+
+void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
+void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
+void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
+
+#endif /* __DC_HWSS_DCN303_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c
new file mode 100644
index 000000000000..aa5dbbade2bd
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#include "dcn303_hwseq.h"
+#include "dcn30/dcn30_init.h"
+#include "dc.h"
+
+void dcn303_hw_sequencer_construct(struct dc *dc)
+{
+	dcn30_hw_sequencer_construct(dc);
+
+	dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control;
+	dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control;
+	dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control;
+	dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h
new file mode 100644
index 000000000000..66b1e3604f07
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef __DC_DCN303_INIT_H__
+#define __DC_DCN303_INIT_H__
+
+struct dc;
+
+void dcn303_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_DCN303_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
new file mode 100644
index 000000000000..34b89464ae02
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -0,0 +1,1695 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#include "dcn303_init.h"
+#include "dcn303_resource.h"
+#include "dcn303_dccg.h"
+#include "irq/dcn303/irq_service_dcn303.h"
+
+#include "dcn30/dcn30_dio_link_encoder.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn30/dcn30_dpp.h"
+#include "dcn30/dcn30_dwb.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn30/dcn30_hubp.h"
+#include "dcn30/dcn30_mmhubbub.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn30/dcn30_optc.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn20/dcn20_dsc.h"
+#include "dcn20/dcn20_resource.h"
+
+#include "dcn10/dcn10_resource.h"
+
+#include "dc_link_ddc.h"
+
+#include "dce/dce_abm.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_hwseq.h"
+#include "dce/dce_i2c_hw.h"
+#include "dce/dce_panel_cntl.h"
+#include "dce/dmub_abm.h"
+#include "dce/dmub_psr.h"
+#include "clk_mgr.h"
+
+#include "hw_sequencer_private.h"
+#include "reg_helper.h"
+#include "resource.h"
+#include "vm_helper.h"
+
+#include "sienna_cichlid_ip_offset.h"
+#include "dcn/dcn_3_0_3_offset.h"
+#include "dcn/dcn_3_0_3_sh_mask.h"
+#include "dcn/dpcs_3_0_3_offset.h"
+#include "dcn/dpcs_3_0_3_sh_mask.h"
+#include "nbio/nbio_2_3_offset.h"
+
+#define DC_LOGGER_INIT(logger)
+
+struct _vcs_dpi_ip_params_st dcn3_03_ip = {
+		.use_min_dcfclk = 0,
+		.clamp_min_dcfclk = 0,
+		.odm_capable = 1,
+		.gpuvm_enable = 1,
+		.hostvm_enable = 0,
+		.gpuvm_max_page_table_levels = 4,
+		.hostvm_max_page_table_levels = 4,
+		.hostvm_cached_page_table_levels = 0,
+		.pte_group_size_bytes = 2048,
+		.num_dsc = 2,
+		.rob_buffer_size_kbytes = 184,
+		.det_buffer_size_kbytes = 184,
+		.dpte_buffer_size_in_pte_reqs_luma = 64,
+		.dpte_buffer_size_in_pte_reqs_chroma = 34,
+		.pde_proc_buffer_size_64k_reqs = 48,
+		.dpp_output_buffer_pixels = 2560,
+		.opp_output_buffer_lines = 1,
+		.pixel_chunk_size_kbytes = 8,
+		.pte_enable = 1,
+		.max_page_table_levels = 2,
+		.pte_chunk_size_kbytes = 2,  // ?
+		.meta_chunk_size_kbytes = 2,
+		.writeback_chunk_size_kbytes = 8,
+		.line_buffer_size_bits = 789504,
+		.is_line_buffer_bpp_fixed = 0,  // ?
+		.line_buffer_fixed_bpp = 0,     // ?
+		.dcc_supported = true,
+		.writeback_interface_buffer_size_kbytes = 90,
+		.writeback_line_buffer_buffer_size = 0,
+		.max_line_buffer_lines = 12,
+		.writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
+		.writeback_chroma_buffer_size_kbytes = 8,
+		.writeback_chroma_line_buffer_width_pixels = 4,
+		.writeback_max_hscl_ratio = 1,
+		.writeback_max_vscl_ratio = 1,
+		.writeback_min_hscl_ratio = 1,
+		.writeback_min_vscl_ratio = 1,
+		.writeback_max_hscl_taps = 1,
+		.writeback_max_vscl_taps = 1,
+		.writeback_line_buffer_luma_buffer_size = 0,
+		.writeback_line_buffer_chroma_buffer_size = 14643,
+		.cursor_buffer_size = 8,
+		.cursor_chunk_size = 2,
+		.max_num_otg = 2,
+		.max_num_dpp = 2,
+		.max_num_wb = 1,
+		.max_dchub_pscl_bw_pix_per_clk = 4,
+		.max_pscl_lb_bw_pix_per_clk = 2,
+		.max_lb_vscl_bw_pix_per_clk = 4,
+		.max_vscl_hscl_bw_pix_per_clk = 4,
+		.max_hscl_ratio = 6,
+		.max_vscl_ratio = 6,
+		.hscl_mults = 4,
+		.vscl_mults = 4,
+		.max_hscl_taps = 8,
+		.max_vscl_taps = 8,
+		.dispclk_ramp_margin_percent = 1,
+		.underscan_factor = 1.11,
+		.min_vblank_lines = 32,
+		.dppclk_delay_subtotal = 46,
+		.dynamic_metadata_vm_enabled = true,
+		.dppclk_delay_scl_lb_only = 16,
+		.dppclk_delay_scl = 50,
+		.dppclk_delay_cnvc_formatter = 27,
+		.dppclk_delay_cnvc_cursor = 6,
+		.dispclk_delay_subtotal = 119,
+		.dcfclk_cstate_latency = 5.2, // SRExitTime
+		.max_inter_dcn_tile_repeaters = 8,
+		.max_num_hdmi_frl_outputs = 1,
+		.odm_combine_4to1_supported = false,
+		.xfc_supported = false,
+		.xfc_fill_bw_overhead_percent = 10.0,
+		.xfc_fill_constant_bytes = 0,
+		.gfx7_compat_tiling_supported = 0,
+		.number_of_cursors = 1,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = {
+		.clock_limits = {
+				{
+						.state = 0,
+						.dispclk_mhz = 1217.0,
+						.dppclk_mhz = 1217.0,
+						.phyclk_mhz = 810.0,
+						.phyclk_d18_mhz = 667.0,
+						.dscclk_mhz = 405.6,
+				},
+		},
+
+		.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
+		.num_states = 1,
+		.sr_exit_time_us = 26.5,
+		.sr_enter_plus_exit_time_us = 31,
+		.urgent_latency_us = 4.0,
+		.urgent_latency_pixel_data_only_us = 4.0,
+		.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+		.urgent_latency_vm_data_only_us = 4.0,
+		.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+		.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+		.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+		.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
+		.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
+		.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
+		.max_avg_sdp_bw_use_normal_percent = 60.0,
+		.max_avg_dram_bw_use_normal_percent = 40.0,
+		.writeback_latency_us = 12.0,
+		.max_request_size_bytes = 256,
+		.fabric_datapath_to_dcn_data_return_bytes = 64,
+		.dcn_downspread_percent = 0.5,
+		.downspread_percent = 0.38,
+		.dram_page_open_time_ns = 50.0,
+		.dram_rw_turnaround_time_ns = 17.5,
+		.dram_return_buffer_per_channel_bytes = 8192,
+		.round_trip_ping_latency_dcfclk_cycles = 156,
+		.urgent_out_of_order_return_per_channel_bytes = 4096,
+		.channel_interleave_bytes = 256,
+		.num_banks = 8,
+		.gpuvm_min_page_size_bytes = 4096,
+		.hostvm_min_page_size_bytes = 4096,
+		.dram_clock_change_latency_us = 404,
+		.dummy_pstate_latency_us = 5,
+		.writeback_dram_clock_change_latency_us = 23.0,
+		.return_bus_width_bytes = 64,
+		.dispclk_dppclk_vco_speed_mhz = 3650,
+		.xfc_bus_transport_time_us = 20,      // ?
+		.xfc_xbuf_latency_tolerance_us = 4,  // ?
+		.use_urgent_burst_bw = 1,            // ?
+		.do_urgent_latency_adjustment = true,
+		.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
+		.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+		.disable_dmcu = true,
+		.force_abm_enable = false,
+		.timing_trace = false,
+		.clock_trace = true,
+		.disable_pplib_clock_request = true,
+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+		.force_single_disp_pipe_split = false,
+		.disable_dcc = DCC_ENABLE,
+		.vsr_support = true,
+		.performance_trace = false,
+		.max_downscale_src_width = 7680,/*upto 8K*/
+		.disable_pplib_wm_range = false,
+		.scl_reset_length10 = true,
+		.sanity_checks = false,
+		.underflow_assert_delay_us = 0xFFFFFFFF,
+		.dwb_fi_phase = -1, // -1 = disable,
+		.dmub_command_table = true,
+		.disable_idle_power_optimizations = false,
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+		.disable_dmcu = true,
+		.force_abm_enable = false,
+		.timing_trace = true,
+		.clock_trace = true,
+		.disable_dpp_power_gate = true,
+		.disable_hubp_power_gate = true,
+		.disable_clock_gate = true,
+		.disable_pplib_clock_request = true,
+		.disable_pplib_wm_range = true,
+		.disable_stutter = false,
+		.scl_reset_length10 = true,
+		.dwb_fi_phase = -1, // -1 = disable
+		.dmub_command_table = true,
+		.enable_tri_buf = true,
+		.disable_psr = true,
+};
+
+enum dcn303_clk_src_array_id {
+	DCN303_CLK_SRC_PLL0,
+	DCN303_CLK_SRC_PLL1,
+	DCN303_CLK_SRC_TOTAL
+};
+
+static const struct resource_caps res_cap_dcn303 = {
+		.num_timing_generator = 2,
+		.num_opp = 2,
+		.num_video_plane = 2,
+		.num_audio = 2,
+		.num_stream_encoder = 2,
+		.num_dwb = 1,
+		.num_ddc = 2,
+		.num_vmid = 16,
+		.num_mpc_3dlut = 1,
+		.num_dsc = 2,
+};
+
+static const struct dc_plane_cap plane_cap = {
+		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+		.blends_with_above = true,
+		.blends_with_below = true,
+		.per_pixel_alpha = true,
+		.pixel_format_support = {
+				.argb8888 = true,
+				.nv12 = true,
+				.fp16 = true,
+				.p010 = false,
+				.ayuv = false,
+		},
+		.max_upscale_factor = {
+				.argb8888 = 16000,
+				.nv12 = 16000,
+				.fp16 = 16000
+		},
+		.max_downscale_factor = {
+				.argb8888 = 600,
+				.nv12 = 600,
+				.fp16 = 600
+		},
+		16,
+		16
+};
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+		NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+		NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
+		mm ## reg_name
+
+/* DCN */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+		.field_name = reg_name ## __ ## field_name ## post_fix
+
+#define SRI(reg_name, block, id)\
+		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define SRII(reg_name, block, id)\
+		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+#define DCCG_SRII(reg_name, block, id)\
+		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+		mm ## reg_name ## _ ## block ## id
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## temp_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN30(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define vmid_regs(id)\
+		[id] = { DCN20_VMID_REG_LIST(id) }
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+		vmid_regs(0),
+		vmid_regs(1),
+		vmid_regs(2),
+		vmid_regs(3),
+		vmid_regs(4),
+		vmid_regs(5),
+		vmid_regs(6),
+		vmid_regs(7),
+		vmid_regs(8),
+		vmid_regs(9),
+		vmid_regs(10),
+		vmid_regs(11),
+		vmid_regs(12),
+		vmid_regs(13),
+		vmid_regs(14),
+		vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
+
+	if (!hubbub3)
+		return NULL;
+
+	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
+
+	for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub3->base;
+}
+
+#define vpg_regs(id)\
+		[id] = { VPG_DCN3_REG_LIST(id) }
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+		vpg_regs(0),
+		vpg_regs(1),
+		vpg_regs(2)
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+		DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+		DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
+
+	return &vpg3->base;
+}
+
+#define afmt_regs(id)\
+		[id] = { AFMT_DCN3_REG_LIST(id) }
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+		afmt_regs(0),
+		afmt_regs(1),
+		afmt_regs(2)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+		DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
+
+	return &afmt3->base;
+}
+
+#define audio_regs(id)\
+		[id] = { AUD_COMMON_REG_LIST(id) }
+
+static const struct dce_audio_registers audio_regs[] = {
+		audio_regs(0),
+		audio_regs(1),
+		audio_regs(2),
+		audio_regs(3),
+		audio_regs(4),
+		audio_regs(5),
+		audio_regs(6)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+#define stream_enc_regs(id)\
+		[id] = { SE_DCN3_REG_LIST(id) }
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+		stream_enc_regs(0),
+		stream_enc_regs(1)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGE) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn303_vpg_create(ctx, vpg_inst);
+	afmt = dcn303_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt)
+		return NULL;
+
+	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
+			&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+#define clk_src_regs(index, pllid)\
+		[index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+		clk_src_regs(0, A),
+		clk_src_regs(1, B)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
+		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN303_REG_LIST()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN303_MASK_SH_LIST(_MASK)
+};
+
+static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+
+#define hubp_regs(id)\
+		[id] = { HUBP_REG_LIST_DCN30(id) }
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1)
+};
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+#define dpp_regs(id)\
+		[id] = { DPP_REG_LIST_DCN30(id) }
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+		dpp_regs(0),
+		dpp_regs(1)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
+};
+
+static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp)
+		return NULL;
+
+	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp);
+	return NULL;
+}
+
+#define opp_regs(id)\
+		[id] = { OPP_REG_LIST_DCN30(id) }
+
+static const struct dcn20_opp_registers opp_regs[] = {
+		opp_regs(0),
+		opp_regs(1)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+		OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+		OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp->base;
+}
+
+#define optc_regs(id)\
+		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
+
+static const struct dcn_optc_registers optc_regs[] = {
+		optc_regs(0),
+		optc_regs(1)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
+{
+	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn30_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
+		MPC_RMU_REG_LIST_DCN3AG(0),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+		MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+		MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
+};
+
+static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
+
+	return &mpc30->base;
+}
+
+#define dsc_regsDCN20(id)\
+[id] = { DSC_REG_LIST_DCN20(id) }
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+		dsc_regsDCN20(0),
+		dsc_regsDCN20(1)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+	return &dsc->base;
+}
+
+#define dwbc_regs_dcn3(id)\
+[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+		dwbc_regs_dcn3(0)
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+		mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+#define aux_engine_regs(id)\
+[id] = {\
+		AUX_COMMON_REG_LIST0(id), \
+		.AUXN_IMPCAL = 0, \
+		.AUXP_IMPCAL = 0, \
+		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1)
+};
+
+static const struct dce110_aux_registers_shift aux_shift = {
+		DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+		DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2)
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
+};
+
+static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+#define link_regs(id, phyid)\
+		[id] = {\
+				LE_DCN3_REG_LIST(id), \
+				UNIPHY_DCN2_REG_LIST(phyid), \
+				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
+		}
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+		link_regs(0, A),
+		link_regs(1, B)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
+		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
+		DPCS_DCN2_MASK_SH_LIST(_MASK)
+};
+
+#define aux_regs(id)\
+		[id] = { DCN2_AUX_REG_LIST(id) }
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1)
+};
+
+#define hpd_regs(id)\
+		[id] = { HPD_REG_LIST(id) }
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1)
+};
+
+static struct link_encoder *dcn303_link_encoder_create(const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
+
+	return &enc20->enc10.base;
+}
+
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
+		{ DCN_PANEL_CNTL_REG_LIST() }
+};
+
+static const struct dce_panel_cntl_shift panel_cntl_shift = {
+		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_panel_cntl_mask panel_cntl_mask = {
+		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
+};
+
+static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
+
+	if (!panel_cntl)
+		return NULL;
+
+	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
+			&panel_cntl_shift, &panel_cntl_mask);
+
+	return &panel_cntl->base;
+}
+
+static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
+{
+	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
+			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+}
+
+static const struct resource_create_funcs res_create_funcs = {
+		.read_dce_straps = read_dce_straps,
+		.create_audio = dcn303_create_audio,
+		.create_stream_encoder = dcn303_stream_encoder_create,
+		.create_hwseq = dcn303_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+		.read_dce_straps = NULL,
+		.create_audio = NULL,
+		.create_stream_encoder = NULL,
+		.create_hwseq = dcn303_hwseq_create,
+};
+
+static bool is_soc_bounding_box_valid(struct dc *dc)
+{
+	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
+
+	if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
+		return true;
+
+	return false;
+}
+
+static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
+{
+	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
+	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+
+	if (!is_soc_bounding_box_valid(dc)) {
+		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+		return false;
+	}
+
+	loaded_ip->max_num_otg = pool->pipe_count;
+	loaded_ip->max_num_dpp = pool->pipe_count;
+	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
+	dcn20_patch_bounding_box(dc, loaded_bb);
+
+	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+		struct bp_soc_bb_info bb_info = { 0 };
+
+		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
+			    dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+			if (bb_info.dram_clock_change_latency_100ns > 0)
+				dcn3_03_soc.dram_clock_change_latency_us =
+					bb_info.dram_clock_change_latency_100ns * 10;
+
+			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+				dcn3_03_soc.sr_enter_plus_exit_time_us =
+					bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+			if (bb_info.dram_sr_exit_latency_100ns > 0)
+				dcn3_03_soc.sr_exit_time_us =
+					bb_info.dram_sr_exit_latency_100ns * 10;
+		}
+	}
+
+	return true;
+}
+
+static void dcn303_resource_destruct(struct resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->stream_enc_count; i++) {
+		if (pool->stream_enc[i] != NULL) {
+			if (pool->stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
+				pool->stream_enc[i]->vpg = NULL;
+			}
+			if (pool->stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
+				pool->stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
+			pool->stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_dsc; i++) {
+		if (pool->dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->dscs[i]);
+	}
+
+	if (pool->mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->mpc));
+		pool->mpc = NULL;
+	}
+
+	if (pool->hubbub != NULL) {
+		kfree(pool->hubbub);
+		pool->hubbub = NULL;
+	}
+
+	for (i = 0; i < pool->pipe_count; i++) {
+		if (pool->dpps[i] != NULL) {
+			kfree(TO_DCN20_DPP(pool->dpps[i]));
+			pool->dpps[i] = NULL;
+		}
+
+		if (pool->hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->hubps[i]));
+			pool->hubps[i] = NULL;
+		}
+
+		if (pool->irqs != NULL)
+			dal_irq_service_destroy(&pool->irqs);
+	}
+
+	for (i = 0; i < pool->res_cap->num_ddc; i++) {
+		if (pool->engines[i] != NULL)
+			dce110_engine_destroy(&pool->engines[i]);
+		if (pool->hw_i2cs[i] != NULL) {
+			kfree(pool->hw_i2cs[i]);
+			pool->hw_i2cs[i] = NULL;
+		}
+		if (pool->sw_i2cs[i] != NULL) {
+			kfree(pool->sw_i2cs[i]);
+			pool->sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_opp; i++) {
+		if (pool->opps[i] != NULL)
+			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
+	}
+
+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+		if (pool->timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
+			pool->timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_dwb; i++) {
+		if (pool->dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
+			pool->dwbc[i] = NULL;
+		}
+		if (pool->mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
+			pool->mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->audio_count; i++) {
+		if (pool->audios[i])
+			dce_aud_destroy(&pool->audios[i]);
+	}
+
+	for (i = 0; i < pool->clk_src_count; i++) {
+		if (pool->clock_sources[i] != NULL)
+			dcn20_clock_source_destroy(&pool->clock_sources[i]);
+	}
+
+	if (pool->dp_clock_source != NULL)
+		dcn20_clock_source_destroy(&pool->dp_clock_source);
+
+	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+		if (pool->mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->mpc_lut[i]);
+			pool->mpc_lut[i] = NULL;
+		}
+		if (pool->mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->mpc_shaper[i]);
+			pool->mpc_shaper[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->pipe_count; i++) {
+		if (pool->multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->multiple_abms[i]);
+	}
+
+	if (pool->psr != NULL)
+		dmub_psr_destroy(&pool->psr);
+
+	if (pool->dccg != NULL)
+		dcn_dccg_destroy(&pool->dccg);
+
+	if (pool->oem_device != NULL)
+		dal_ddc_service_destroy(&pool->oem_device);
+}
+
+static void dcn303_destroy_resource_pool(struct resource_pool **pool)
+{
+	dcn303_resource_destruct(*pool);
+	kfree(*pool);
+	*pool = NULL;
+}
+
+static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
+		unsigned int *optimal_dcfclk,
+		unsigned int *optimal_fclk)
+{
+	double bw_from_dram, bw_from_dram1, bw_from_dram2;
+
+	bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans *
+		dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100);
+	bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans *
+		dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100);
+
+	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
+
+	if (optimal_fclk)
+		*optimal_fclk = bw_from_dram /
+		(dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes *
+				(dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
+
+	if (optimal_dcfclk)
+		*optimal_dcfclk =  bw_from_dram /
+		(dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
+}
+
+void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	unsigned int i, j;
+	unsigned int num_states = 0;
+
+	unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
+	unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
+	unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
+	unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
+
+	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
+	unsigned int num_dcfclk_sta_targets = 4;
+	unsigned int num_uclk_states;
+
+
+	if (dc->ctx->dc_bios->vram_info.num_chans)
+		dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
+
+	if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
+		dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
+
+	dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+
+	if (bw_params->clk_table.entries[0].memclk_mhz) {
+		int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+
+		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
+			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
+				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
+				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
+			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
+				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
+			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
+				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
+		}
+		if (!max_dcfclk_mhz)
+			max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz;
+		if (!max_dispclk_mhz)
+			max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz;
+		if (!max_dppclk_mhz)
+			max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz;
+		if (!max_phyclk_mhz)
+			max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz;
+
+		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
+			num_dcfclk_sta_targets++;
+		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			for (i = 0; i < num_dcfclk_sta_targets; i++) {
+				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
+					dcfclk_sta_targets[i] = max_dcfclk_mhz;
+					break;
+				}
+			}
+			/* Update size of array since we "removed" duplicates */
+			num_dcfclk_sta_targets = i + 1;
+		}
+
+		num_uclk_states = bw_params->clk_table.num_entries;
+
+		/* Calculate optimal dcfclk for each uclk */
+		for (i = 0; i < num_uclk_states; i++) {
+			dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
+					&optimal_dcfclk_for_uclk[i], NULL);
+			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
+				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
+		}
+
+		/* Calculate optimal uclk for each dcfclk sta target */
+		for (i = 0; i < num_dcfclk_sta_targets; i++) {
+			for (j = 0; j < num_uclk_states; j++) {
+				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
+					optimal_uclk_for_dcfclk_sta_targets[i] =
+							bw_params->clk_table.entries[j].memclk_mhz * 16;
+					break;
+				}
+			}
+		}
+
+		i = 0;
+		j = 0;
+		/* create the final dcfclk and uclk table */
+		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
+			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+			} else {
+				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+					dram_speed_mts[num_states++] =
+							bw_params->clk_table.entries[j++].memclk_mhz * 16;
+				} else {
+					j = num_uclk_states;
+				}
+			}
+		}
+
+		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
+			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+		}
+
+		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
+				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+		}
+
+		dcn3_03_soc.num_states = num_states;
+		for (i = 0; i < dcn3_03_soc.num_states; i++) {
+			dcn3_03_soc.clock_limits[i].state = i;
+			dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
+			dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
+			dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
+			/* Fill all states with max values of all other clocks */
+			dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+			dcn3_03_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
+			dcn3_03_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
+			dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
+			/* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
+			/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
+			dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
+			dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz;
+			dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
+		}
+		/* re-init DML with updated bb */
+		dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
+		if (dc->current_state)
+			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
+	}
+}
+
+static struct resource_funcs dcn303_res_pool_funcs = {
+		.destroy = dcn303_destroy_resource_pool,
+		.link_enc_create = dcn303_link_encoder_create,
+		.panel_cntl_create = dcn303_panel_cntl_create,
+		.validate_bandwidth = dcn30_validate_bandwidth,
+		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
+		.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
+		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
+		.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
+		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
+		.update_bw_bounding_box = dcn303_update_bw_bounding_box,
+		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+};
+
+static struct dc_cap_funcs cap_funcs = {
+		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN3_03()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN3_03(_MASK)
+};
+
+#define abm_regs(id)\
+		[id] = { ABM_DCN301_REG_LIST(id) }
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1)
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static bool dcn303_resource_construct(
+		uint8_t num_virtual_links,
+		struct dc *dc,
+		struct resource_pool *pool)
+{
+	int i;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+	struct ddc_service_init_data ddc_init_data;
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->res_cap = &res_cap_dcn303;
+
+	pool->funcs = &dcn303_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->pipe_count = pool->res_cap->num_timing_generator;
+	pool->mpcc_count = pool->res_cap->num_timing_generator;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
+	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
+	dc->caps.dmdata_alloc_size = 2048;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	dc->caps.mall_size_per_mem_channel = 4;
+	/* total size = mall per channel * num channels * 1024 * 1024 */
+	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
+				   dc->ctx->dc_bios->vram_info.num_chans *
+				   1024 * 1024;
+	dc->caps.cursor_cache_size =
+		dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
+#endif
+	dc->caps.max_slave_planes = 1;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
+
+	dc->caps.color.dpp.hw_3d_lut = 1;
+	dc->caps.color.dpp.ogam_ram = 1;
+	// no OGAM ROM on DCN3
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else
+		dc->debug = debug_defaults_diags;
+
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->clock_sources[DCN303_CLK_SRC_PLL0] =
+			dcn303_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_COMBO_PHY_PLL0,
+					&clk_src_regs[0], false);
+	pool->clock_sources[DCN303_CLK_SRC_PLL1] =
+			dcn303_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_COMBO_PHY_PLL1,
+					&clk_src_regs[1], false);
+
+	pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->dp_clock_source =
+			dcn303_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_ID_DP_DTO,
+					&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->clk_src_count; i++) {
+		if (pool->clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* DCCG */
+	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* PP Lib and SMU interfaces */
+	init_soc_bounding_box(dc, pool);
+
+	/* DML */
+	dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
+
+	/* IRQ */
+	init_data.ctx = dc->ctx;
+	pool->irqs = dal_irq_service_dcn303_create(&init_data);
+	if (!pool->irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->hubbub = dcn303_hubbub_create(ctx);
+	if (pool->hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs and TGs */
+	for (i = 0; i < pool->pipe_count; i++) {
+		pool->hubps[i] = dcn303_hubp_create(ctx, i);
+		if (pool->hubps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		pool->dpps[i] = dcn303_dpp_create(ctx, i);
+		if (pool->dpps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_opp; i++) {
+		pool->opps[i] = dcn303_opp_create(ctx, i);
+		if (pool->opps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+		pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);
+		if (pool->timing_generators[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+	}
+	pool->timing_generator_count = i;
+
+	/* PSR */
+	pool->psr = dmub_psr_create(ctx);
+	if (pool->psr == NULL) {
+		dm_error("DC: failed to create psr!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* ABM */
+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
+		if (pool->multiple_abms[i] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* MPC and DSC */
+	pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
+	if (pool->mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	for (i = 0; i < pool->res_cap->num_dsc; i++) {
+		pool->dscs[i] = dcn303_dsc_create(ctx, i);
+		if (pool->dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB and MMHUBBUB */
+	if (!dcn303_dwbc_create(ctx, pool)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	if (!dcn303_mmhubbub_create(ctx, pool)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->res_cap->num_ddc; i++) {
+		pool->engines[i] = dcn303_aux_engine_create(ctx, i);
+		if (pool->engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);
+		if (pool->hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, pool,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+					&res_create_funcs : &res_create_maximus_funcs)))
+		goto create_fail;
+
+	/* HW Sequencer and Plane caps */
+	dcn303_hw_sequencer_construct(dc);
+
+	dc->caps.max_planes =  pool->pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
+		ddc_init_data.ctx = dc->ctx;
+		ddc_init_data.link = NULL;
+		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
+		ddc_init_data.id.enum_id = 0;
+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
+		pool->oem_device = dal_ddc_service_create(&ddc_init_data);
+	} else {
+		pool->oem_device = NULL;
+	}
+
+	return true;
+
+create_fail:
+
+	dcn303_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
+{
+	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
+		return pool;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h
new file mode 100644
index 000000000000..5b590c169763
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef _DCN303_RESOURCE_H_
+#define _DCN303_RESOURCE_H_
+
+#include "core_types.h"
+
+struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);
+
+void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
+
+#endif /* _DCN303_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/Makefile b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile
new file mode 100644
index 000000000000..5dcdc5a858fe
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile
@@ -0,0 +1,42 @@
+#
+# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn31.
+
+DCN31 = dcn31_resource.o dcn31_hubbub.o dcn31_hwseq.o dcn31_init.o dcn31_hubp.o \
+	dcn31_dccg.o dcn31_optc.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o := -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -mhard-float
+endif
+
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -msse2
+endif
+
+AMD_DAL_DCN31 = $(addprefix $(AMDDALPATH)/dc/dcn31/,$(DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN31)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
new file mode 100644
index 000000000000..696c9307715d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn31_dccg.h"
+
+#define TO_DCN_DCCG(dccg)\
+	container_of(dccg, struct dcn_dccg, base)
+
+#define REG(reg) \
+	(dccg_dcn->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
+
+#define CTX \
+	dccg_dcn->base.ctx
+#define DC_LOGGER \
+	dccg->ctx->logger
+
+void dccg31_set_physymclk(
+		struct dccg *dccg,
+		int phy_inst,
+		enum physymclk_clock_source clk_src,
+		bool force_enable)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */
+	switch (phy_inst) {
+	case 0:
+		if (force_enable)
+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
+					PHYASYMCLK_FORCE_EN, 1,
+					PHYASYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
+					PHYASYMCLK_FORCE_EN, 0,
+					PHYASYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 1:
+		if (force_enable)
+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
+					PHYBSYMCLK_FORCE_EN, 1,
+					PHYBSYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
+					PHYBSYMCLK_FORCE_EN, 0,
+					PHYBSYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 2:
+		if (force_enable)
+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
+					PHYCSYMCLK_FORCE_EN, 1,
+					PHYCSYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
+					PHYCSYMCLK_FORCE_EN, 0,
+					PHYCSYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 3:
+		if (force_enable)
+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
+					PHYDSYMCLK_FORCE_EN, 1,
+					PHYDSYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
+					PHYDSYMCLK_FORCE_EN, 0,
+					PHYDSYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 4:
+		if (force_enable)
+			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
+					PHYESYMCLK_FORCE_EN, 1,
+					PHYESYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
+					PHYESYMCLK_FORCE_EN, 0,
+					PHYESYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
+void dccg31_set_dtbclk_dto(
+		struct dccg *dccg,
+		int dtbclk_inst,
+		int req_dtbclk_khz,
+		int num_odm_segments,
+		const struct dc_crtc_timing *timing)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+	uint32_t dtbdto_div;
+
+	/* Mode	                DTBDTO Rate       DTBCLK_DTO<x>_DIV Register
+	 * ODM 4:1 combine      pixel rate/4      2
+	 * ODM 2:1 combine      pixel rate/2      4
+	 * non-DSC 4:2:0 mode   pixel rate/2      4
+	 * DSC native 4:2:0     pixel rate/2      4
+	 * DSC native 4:2:2     pixel rate/2      4
+	 * Other modes          pixel rate        8
+	 */
+	if (num_odm_segments == 4) {
+		dtbdto_div = 2;
+		req_dtbclk_khz = req_dtbclk_khz / 4;
+	} else if ((num_odm_segments == 2) ||
+			(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
+			(timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+					&& !timing->dsc_cfg.ycbcr422_simple)) {
+		dtbdto_div = 4;
+		req_dtbclk_khz = req_dtbclk_khz / 2;
+	} else
+		dtbdto_div = 8;
+
+	if (dccg->ref_dtbclk_khz && req_dtbclk_khz) {
+		uint32_t modulo, phase;
+
+		// phase / modulo = dtbclk / dtbclk ref
+		modulo = dccg->ref_dtbclk_khz * 1000;
+		phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1),
+			dccg->ref_dtbclk_khz);
+
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLK_DTO_DIV[dtbclk_inst], dtbdto_div);
+
+		REG_WRITE(DTBCLK_DTO_MODULO[dtbclk_inst], modulo);
+		REG_WRITE(DTBCLK_DTO_PHASE[dtbclk_inst], phase);
+
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLK_DTO_ENABLE[dtbclk_inst], 1);
+
+		REG_WAIT(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLKDTO_ENABLE_STATUS[dtbclk_inst], 1,
+				1, 100);
+
+		/* The recommended programming sequence to enable DTBCLK DTO to generate
+		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
+		 * be set only after DTO is enabled
+		 */
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				PIPE_DTO_SRC_SEL[dtbclk_inst], 1);
+
+		dccg->dtbclk_khz[dtbclk_inst] = req_dtbclk_khz;
+	} else {
+		REG_UPDATE_3(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLK_DTO_ENABLE[dtbclk_inst], 0,
+				PIPE_DTO_SRC_SEL[dtbclk_inst], 0,
+				DTBCLK_DTO_DIV[dtbclk_inst], dtbdto_div);
+
+		REG_WRITE(DTBCLK_DTO_MODULO[dtbclk_inst], 0);
+		REG_WRITE(DTBCLK_DTO_PHASE[dtbclk_inst], 0);
+
+		dccg->dtbclk_khz[dtbclk_inst] = 0;
+	}
+}
+
+void dccg31_set_audio_dtbclk_dto(
+		struct dccg *dccg,
+		uint32_t req_audio_dtbclk_khz)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (dccg->ref_dtbclk_khz && req_audio_dtbclk_khz) {
+		uint32_t modulo, phase;
+
+		// phase / modulo = dtbclk / dtbclk ref
+		modulo = dccg->ref_dtbclk_khz * 1000;
+		phase = div_u64((((unsigned long long)modulo * req_audio_dtbclk_khz) + dccg->ref_dtbclk_khz - 1),
+			dccg->ref_dtbclk_khz);
+
+
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
+
+		//REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
+		//		DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO, 1);
+
+		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
+				DCCG_AUDIO_DTO_SEL, 4);  //  04 - DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK
+
+		dccg->audio_dtbclk_khz = req_audio_dtbclk_khz;
+	} else {
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0);
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0);
+
+		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
+				DCCG_AUDIO_DTO_SEL, 3);  //  03 - DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO
+
+		dccg->audio_dtbclk_khz = 0;
+	}
+}
+
+static void dccg31_get_dccg_ref_freq(struct dccg *dccg,
+		unsigned int xtalin_freq_inKhz,
+		unsigned int *dccg_ref_freq_inKhz)
+{
+	/*
+	 * Assume refclk is sourced from xtalin
+	 * expect 24MHz
+	 */
+	*dccg_ref_freq_inKhz = xtalin_freq_inKhz;
+	return;
+}
+
+static void dccg31_set_dispclk_change_mode(
+	struct dccg *dccg,
+	enum dentist_dispclk_change_mode change_mode)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE,
+		   change_mode == DISPCLK_CHANGE_MODE_RAMPING ? 2 : 0);
+}
+
+void dccg31_init(struct dccg *dccg)
+{
+}
+
+static const struct dccg_funcs dccg31_funcs = {
+	.update_dpp_dto = dccg2_update_dpp_dto,
+	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
+	.dccg_init = dccg31_init,
+	.set_physymclk = dccg31_set_physymclk,
+	.set_dtbclk_dto = dccg31_set_dtbclk_dto,
+	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
+	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
+};
+
+struct dccg *dccg31_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask)
+{
+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+	struct dccg *base;
+
+	if (dccg_dcn == NULL) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	base = &dccg_dcn->base;
+	base->ctx = ctx;
+	base->funcs = &dccg31_funcs;
+
+	dccg_dcn->regs = regs;
+	dccg_dcn->dccg_shift = dccg_shift;
+	dccg_dcn->dccg_mask = dccg_mask;
+
+	return &dccg_dcn->base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
new file mode 100644
index 000000000000..706ad80ba873
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN31_DCCG_H__
+#define __DCN31_DCCG_H__
+
+#include "dcn30/dcn30_dccg.h"
+
+#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
+	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
+
+
+#define DCCG_REG_LIST_DCN31() \
+	SR(DPPCLK_DTO_CTRL),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
+	SR(PHYASYMCLK_CLOCK_CNTL),\
+	SR(PHYBSYMCLK_CLOCK_CNTL),\
+	SR(PHYCSYMCLK_CLOCK_CNTL),\
+	SR(PHYDSYMCLK_CLOCK_CNTL),\
+	SR(PHYESYMCLK_CLOCK_CNTL),\
+	SR(DPSTREAMCLK_CNTL),\
+	SR(SYMCLK32_SE_CNTL),\
+	SR(SYMCLK32_LE_CNTL),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
+	SR(DCCG_AUDIO_DTO_SOURCE),\
+	SR(DENTIST_DISPCLK_CNTL)
+
+
+#define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
+	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh)
+
+
+struct dccg *dccg31_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask);
+
+void dccg31_init(struct dccg *dccg);
+
+void dccg31_set_physymclk(
+		struct dccg *dccg,
+		int phy_inst,
+		enum physymclk_clock_source clk_src,
+		bool force_enable);
+
+void dccg31_set_audio_dtbclk_dto(
+		struct dccg *dccg,
+		uint32_t req_audio_dtbclk_khz);
+
+void dccg31_set_hdmistreamclk(
+		struct dccg *dccg,
+		enum hdmistreamclk_source src);
+
+#endif //__DCN31_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
new file mode 100644
index 000000000000..90127c1f9e35
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn31_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "gpio_service_interface.h"
+
+#include "link_enc_cfg.h"
+#include "dc_dmub_srv.h"
+
+#define CTX \
+	enc10->base.ctx
+#define DC_LOGGER \
+	enc10->base.ctx->logger
+
+#define REG(reg)\
+	(enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define IND_REG(index) \
+	(enc10->link_regs->index)
+
+#define AUX_REG(reg)\
+	(enc10->aux_regs->reg)
+
+#define AUX_REG_READ(reg_name) \
+		dm_read_reg(CTX, AUX_REG(reg_name))
+
+#define AUX_REG_WRITE(reg_name, val) \
+			dm_write_reg(CTX, AUX_REG(reg_name), val)
+
+void dcn31_link_encoder_set_dio_phy_mux(
+	struct link_encoder *enc,
+	enum encoder_type_select sel,
+	uint32_t hpo_inst)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+	switch (enc->transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKA_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKA_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKA_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_B:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKB_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKB_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKB_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_C:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKC_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKC_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKC_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_D:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKD_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKD_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKD_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_E:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKE_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKE_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKE_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_F:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKF_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKF_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKF_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	default:
+		/* Do nothing */
+		break;
+	}
+}
+
+void enc31_hw_init(struct link_encoder *enc)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+/*
+	00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
+	01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
+	02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
+	03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
+	04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
+	05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
+	06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
+	07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
+*/
+
+/*
+	AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
+	AUX_RX_START_WINDOW = 1 [6:4]
+	AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
+	AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
+	AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
+	AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
+	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
+	AUX_RX_DETECTION_THRESHOLD [30:28] = 1
+*/
+	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
+
+	AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
+
+	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
+	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
+	// 27MHz -> 0xd
+	// 100MHz -> 0x32
+	// 48MHz -> 0x18
+
+#ifdef CLEANUP_FIXME
+	/*from display_init*/
+	REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
+#endif
+
+	// Set TMDS_CTL0 to 1.  This is a legacy setting.
+	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
+
+	/*HW default is 5*/
+	REG_UPDATE(RDPCSTX_CNTL,
+			RDPCS_TX_FIFO_RD_START_DELAY, 4);
+
+	dcn10_aux_initialize(enc10);
+}
+
+static const struct link_encoder_funcs dcn31_link_enc_funcs = {
+	.read_state = link_enc2_read_state,
+	.validate_output_with_stream =
+			dcn30_link_encoder_validate_output_with_stream,
+	.hw_init = enc31_hw_init,
+	.setup = dcn10_link_encoder_setup,
+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+	.enable_dp_output = dcn31_link_encoder_enable_dp_output,
+	.enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
+	.disable_output = dcn31_link_encoder_disable_output,
+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+	.update_mst_stream_allocation_table =
+		dcn10_link_encoder_update_mst_stream_allocation_table,
+	.psr_program_dp_dphy_fast_training =
+			dcn10_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+	.enable_hpd = dcn10_link_encoder_enable_hpd,
+	.disable_hpd = dcn10_link_encoder_disable_hpd,
+	.is_dig_enabled = dcn10_is_dig_enabled,
+	.destroy = dcn10_link_encoder_destroy,
+	.fec_set_enable = enc2_fec_set_enable,
+	.fec_set_ready = enc2_fec_set_ready,
+	.fec_is_active = enc2_fec_is_active,
+	.get_dig_frontend = dcn10_get_dig_frontend,
+	.get_dig_mode = dcn10_get_dig_mode,
+	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
+	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
+};
+
+void dcn31_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask)
+{
+	struct bp_encoder_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+	enum bp_result result = BP_RESULT_OK;
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn31_link_enc_funcs;
+	enc10->base.ctx = init_data->ctx;
+	enc10->base.id = init_data->encoder;
+
+	enc10->base.hpd_source = init_data->hpd_source;
+	enc10->base.connector = init_data->connector;
+
+	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+	enc10->base.features = *enc_features;
+
+	enc10->base.transmitter = init_data->transmitter;
+
+	/* set the flag to indicate whether driver poll the I2C data pin
+	 * while doing the DP sink detect
+	 */
+
+/*	if (dal_adapter_service_is_feature_supported(as,
+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+		enc10->base.features.flags.bits.
+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DVI_SINGLE_LINK |
+		SIGNAL_TYPE_DVI_DUAL_LINK |
+		SIGNAL_TYPE_LVDS |
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP |
+		SIGNAL_TYPE_HDMI_TYPE_A;
+
+	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
+	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
+	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
+	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
+	 * Prefer DIG assignment is decided by board design.
+	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
+	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
+	 * By this, adding DIGG should not hurt DCE 8.0.
+	 * This will let DCE 8.1 share DCE 8.0 as much as possible
+	 */
+
+	enc10->link_regs = link_regs;
+	enc10->aux_regs = aux_regs;
+	enc10->hpd_regs = hpd_regs;
+	enc10->link_shift = link_shift;
+	enc10->link_mask = link_mask;
+
+	switch (enc10->base.transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		enc10->base.preferred_engine = ENGINE_ID_DIGA;
+	break;
+	case TRANSMITTER_UNIPHY_B:
+		enc10->base.preferred_engine = ENGINE_ID_DIGB;
+	break;
+	case TRANSMITTER_UNIPHY_C:
+		enc10->base.preferred_engine = ENGINE_ID_DIGC;
+	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc10->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc10->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	case TRANSMITTER_UNIPHY_F:
+		enc10->base.preferred_engine = ENGINE_ID_DIGF;
+	break;
+	default:
+		ASSERT_CRITICAL(false);
+		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+	}
+
+	/* default to one to mirror Windows behavior */
+	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
+						enc10->base.id, &bp_cap_info);
+
+	/* Override features with DCE-specific values */
+	if (result == BP_RESULT_OK) {
+		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+				bp_cap_info.DP_HBR2_EN;
+		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+		enc10->base.features.flags.bits.DP_IS_USB_C =
+				bp_cap_info.DP_IS_USB_C;
+	} else {
+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+				__func__,
+				result);
+	}
+	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+	}
+}
+
+void dcn31_link_encoder_construct_minimal(
+	struct dcn20_link_encoder *enc20,
+	struct dc_context *ctx,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	enum engine_id eng_id)
+{
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn31_link_enc_funcs;
+	enc10->base.ctx = ctx;
+	enc10->base.id.type = OBJECT_TYPE_ENCODER;
+	enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
+	enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
+	enc10->base.preferred_engine = eng_id;
+	enc10->base.features = *enc_features;
+	enc10->base.transmitter = TRANSMITTER_UNKNOWN;
+	enc10->link_regs = link_regs;
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP;
+}
+
+void dcn31_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source)
+{
+	/* Enable transmitter and encoder. */
+	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
+
+		dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
+
+	} else {
+
+		/** @todo Handle transmitter with programmable mapping to link encoder. */
+	}
+}
+
+void dcn31_link_encoder_enable_dp_mst_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source)
+{
+	/* Enable transmitter and encoder. */
+	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
+
+		dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
+
+	} else {
+
+		/** @todo Handle transmitter with programmable mapping to link encoder. */
+	}
+}
+
+void dcn31_link_encoder_disable_output(
+	struct link_encoder *enc,
+	enum signal_type signal)
+{
+	/* Disable transmitter and encoder. */
+	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
+
+		dcn10_link_encoder_disable_output(enc, signal);
+
+	} else {
+
+		/** @todo Handle transmitter with programmable mapping to link encoder. */
+	}
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
new file mode 100644
index 000000000000..32d146312838
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN31_H__
+#define __DC_LINK_ENCODER__DCN31_H__
+
+#include "dcn30/dcn30_dio_link_encoder.h"
+
+
+#define LE_DCN31_REG_LIST(id)\
+	LE_DCN3_REG_LIST(id),\
+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+	SR(DIO_LINKA_CNTL), \
+	SR(DIO_LINKB_CNTL), \
+	SR(DIO_LINKC_CNTL), \
+	SR(DIO_LINKD_CNTL), \
+	SR(DIO_LINKE_CNTL), \
+	SR(DIO_LINKF_CNTL)
+
+#define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \
+	LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
+	LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\
+	LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
+	LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
+	LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
+
+#define DPCS_DCN31_REG_LIST(id) \
+	SRI(TMDS_CTL_BITS, DIG, id), \
+	SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
+	SRI(RDPCSTX_CNTL, RDPCSTX, id), \
+	SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
+	SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
+	SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
+	SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
+	SR(RDPCSTX0_RDPCSTX_SCRATCH), \
+	SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
+	SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
+
+#define DPCS_DCN31_MASK_SH_LIST(mask_sh)\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh)
+
+void dcn31_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask);
+
+/*
+ * Create a minimal link encoder object with no dc_link object associated with it.
+ */
+void dcn31_link_encoder_construct_minimal(
+	struct dcn20_link_encoder *enc20,
+	struct dc_context *ctx,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	enum engine_id eng_id);
+
+void dcn31_link_encoder_set_dio_phy_mux(
+	struct link_encoder *enc,
+	enum encoder_type_select sel,
+	uint32_t hpo_inst);
+
+/*
+ * Enable DP transmitter and its encoder.
+ */
+void dcn31_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source);
+
+/*
+ * Enable DP transmitter and its encoder in MST mode.
+ */
+void dcn31_link_encoder_enable_dp_mst_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source);
+
+/*
+ * Disable transmitter and its encoder.
+ */
+void dcn31_link_encoder_disable_output(
+	struct link_encoder *enc,
+	enum signal_type signal);
+
+#endif /* __DC_LINK_ENCODER__DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
new file mode 100644
index 000000000000..bb9648488900
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -0,0 +1,956 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31_hubbub.h"
+#include "dm_services.h"
+#include "reg_helper.h"
+
+
+#define CTX \
+	hubbub2->base.ctx
+#define DC_LOGGER \
+	hubbub2->base.ctx->logger
+#define REG(reg)\
+	hubbub2->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubbub2->shifts->field_name, hubbub2->masks->field_name
+
+#ifdef NUM_VMID
+#undef NUM_VMID
+#endif
+#define NUM_VMID 16
+
+#define DCN31_CRB_SEGMENT_SIZE_KB 64
+
+static void dcn31_init_crb(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
+		&hubbub2->det0_size);
+
+	REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
+		&hubbub2->det1_size);
+
+	REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
+		&hubbub2->det2_size);
+
+	REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
+		&hubbub2->det3_size);
+
+	REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
+		&hubbub2->compbuf_size_segments);
+
+	REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
+			COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32,
+			COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128);
+	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F);
+}
+
+static void dcn31_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	unsigned int det_size_segments = (det_buffer_size_in_kbyte + DCN31_CRB_SEGMENT_SIZE_KB - 1) / DCN31_CRB_SEGMENT_SIZE_KB;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_UPDATE(DCHUBBUB_DET0_CTRL,
+					DET0_SIZE, det_size_segments);
+		hubbub2->det0_size = det_size_segments;
+		break;
+	case 1:
+		REG_UPDATE(DCHUBBUB_DET1_CTRL,
+					DET1_SIZE, det_size_segments);
+		hubbub2->det1_size = det_size_segments;
+		break;
+	case 2:
+		REG_UPDATE(DCHUBBUB_DET2_CTRL,
+					DET2_SIZE, det_size_segments);
+		hubbub2->det2_size = det_size_segments;
+		break;
+	case 3:
+		REG_UPDATE(DCHUBBUB_DET3_CTRL,
+					DET3_SIZE, det_size_segments);
+		hubbub2->det3_size = det_size_segments;
+		break;
+	default:
+		break;
+	}
+	/* Should never be hit, if it is we have an erroneous hw config*/
+	ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+			+ hubbub2->det3_size + hubbub2->compbuf_size_segments <= hubbub2->crb_size_segs);
+}
+
+static void dcn31_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	unsigned int compbuf_size_segments = (compbuf_size_kb + DCN31_CRB_SEGMENT_SIZE_KB - 1) / DCN31_CRB_SEGMENT_SIZE_KB;
+
+	if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) {
+		if (compbuf_size_segments > hubbub2->compbuf_size_segments) {
+			REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);
+		}
+		/* Should never be hit, if it is we have an erroneous hw config*/
+		ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+				+ hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs);
+		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);
+		REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100);
+		hubbub2->compbuf_size_segments = compbuf_size_segments;
+	}
+}
+
+static uint32_t convert_and_clamp(
+	uint32_t wm_ns,
+	uint32_t refclk_mhz,
+	uint32_t clamp_value)
+{
+	uint32_t ret_val = 0;
+	ret_val = wm_ns * refclk_mhz;
+	ret_val /= 1000;
+
+	if (ret_val > clamp_value)
+		ret_val = clamp_value;
+
+	return ret_val;
+}
+
+static bool hubbub31_program_urgent_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* Repeat for water mark set A, B, C and D. */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) {
+		hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.urgent_ns, prog_wm_value);
+	} else if (watermarks->a.urgent_ns < hubbub2->watermarks.a.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
+			> hubbub2->watermarks.a.frac_urg_bw_flip) {
+		hubbub2->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip);
+	} else if (watermarks->a.frac_urg_bw_flip
+			< hubbub2->watermarks.a.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
+			> hubbub2->watermarks.a.frac_urg_bw_nom) {
+		hubbub2->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
+	} else if (watermarks->a.frac_urg_bw_nom
+			< hubbub2->watermarks.a.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) {
+		hubbub2->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value);
+	} else if (watermarks->a.urgent_latency_ns < hubbub2->watermarks.a.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) {
+		hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.urgent_ns, prog_wm_value);
+	} else if (watermarks->b.urgent_ns < hubbub2->watermarks.b.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->b.frac_urg_bw_flip
+			> hubbub2->watermarks.b.frac_urg_bw_flip) {
+		hubbub2->watermarks.b.frac_urg_bw_flip = watermarks->b.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->b.frac_urg_bw_flip);
+	} else if (watermarks->b.frac_urg_bw_flip
+			< hubbub2->watermarks.b.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.frac_urg_bw_nom
+			> hubbub2->watermarks.b.frac_urg_bw_nom) {
+		hubbub2->watermarks.b.frac_urg_bw_nom = watermarks->b.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->b.frac_urg_bw_nom);
+	} else if (watermarks->b.frac_urg_bw_nom
+			< hubbub2->watermarks.b.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) {
+		hubbub2->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value);
+	} else if (watermarks->b.urgent_latency_ns < hubbub2->watermarks.b.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) {
+		hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.urgent_ns, prog_wm_value);
+	} else if (watermarks->c.urgent_ns < hubbub2->watermarks.c.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->c.frac_urg_bw_flip
+			> hubbub2->watermarks.c.frac_urg_bw_flip) {
+		hubbub2->watermarks.c.frac_urg_bw_flip = watermarks->c.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->c.frac_urg_bw_flip);
+	} else if (watermarks->c.frac_urg_bw_flip
+			< hubbub2->watermarks.c.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.frac_urg_bw_nom
+			> hubbub2->watermarks.c.frac_urg_bw_nom) {
+		hubbub2->watermarks.c.frac_urg_bw_nom = watermarks->c.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->c.frac_urg_bw_nom);
+	} else if (watermarks->c.frac_urg_bw_nom
+			< hubbub2->watermarks.c.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub2->watermarks.c.urgent_latency_ns) {
+		hubbub2->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value);
+	} else if (watermarks->c.urgent_latency_ns < hubbub2->watermarks.c.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.urgent_ns > hubbub2->watermarks.d.urgent_ns) {
+		hubbub2->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.urgent_ns, prog_wm_value);
+	} else if (watermarks->d.urgent_ns < hubbub2->watermarks.d.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->d.frac_urg_bw_flip
+			> hubbub2->watermarks.d.frac_urg_bw_flip) {
+		hubbub2->watermarks.d.frac_urg_bw_flip = watermarks->d.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->d.frac_urg_bw_flip);
+	} else if (watermarks->d.frac_urg_bw_flip
+			< hubbub2->watermarks.d.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.frac_urg_bw_nom
+			> hubbub2->watermarks.d.frac_urg_bw_nom) {
+		hubbub2->watermarks.d.frac_urg_bw_nom = watermarks->d.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->d.frac_urg_bw_nom);
+	} else if (watermarks->d.frac_urg_bw_nom
+			< hubbub2->watermarks.d.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub2->watermarks.d.urgent_latency_ns) {
+		hubbub2->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value);
+	} else if (watermarks->d.urgent_latency_ns < hubbub2->watermarks.d.urgent_latency_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub31_program_stutter_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns =
+				watermarks->a.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->a.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns =
+				watermarks->b.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->b.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns =
+				watermarks->c.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->c.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns =
+				watermarks->d.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->d.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub31_program_pstate_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.a.cstate_pstate.pstate_change_ns =
+				watermarks->a.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.a.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.b.cstate_pstate.pstate_change_ns =
+				watermarks->b.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.b.cstate_pstate.pstate_change_ns)
+		wm_pending = false;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.c.cstate_pstate.pstate_change_ns =
+				watermarks->c.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.c.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.d.cstate_pstate.pstate_change_ns =
+				watermarks->d.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.d.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub31_program_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	bool wm_pending = false;
+
+	if (hubbub31_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub31_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub31_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	/*
+	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
+	 * If the memory controller is fully utilized and the DCHub requestors are
+	 * well ahead of their amortized schedule, then it is safe to prevent the next winner
+	 * from being committed and sent to the fabric.
+	 * The utilization of the memory controller is approximated by ensuring that
+	 * the number of outstanding requests is greater than a threshold specified
+	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
+	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
+	 *
+	 * TODO: Revisit request limit after figure out right number. request limit for RM isn't decided yet, set maximum value (0x1FF)
+	 * to turn off it for now.
+	 */
+	/*REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
+			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
+
+	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
+	return wm_pending;
+}
+
+static void hubbub3_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
+		unsigned int bytes_per_element)
+{
+	/* copied from DML.  might want to refactor DML to leverage from DML */
+	/* DML : get_blk256_size */
+	if (bytes_per_element == 1) {
+		*blk256_width = 16;
+		*blk256_height = 16;
+	} else if (bytes_per_element == 2) {
+		*blk256_width = 16;
+		*blk256_height = 8;
+	} else if (bytes_per_element == 4) {
+		*blk256_width = 8;
+		*blk256_height = 8;
+	} else if (bytes_per_element == 8) {
+		*blk256_width = 8;
+		*blk256_height = 4;
+	}
+}
+
+static void hubbub31_det_request_size(
+		unsigned int detile_buf_size,
+		unsigned int height,
+		unsigned int width,
+		unsigned int bpe,
+		bool *req128_horz_wc,
+		bool *req128_vert_wc)
+{
+	unsigned int blk256_height = 0;
+	unsigned int blk256_width = 0;
+	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
+
+	hubbub3_get_blk256_size(&blk256_width, &blk256_height, bpe);
+
+	swath_bytes_horz_wc = width * blk256_height * bpe;
+	swath_bytes_vert_wc = height * blk256_width * bpe;
+
+	*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
+			false : /* full 256B request */
+			true; /* half 128b request */
+
+	*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
+			false : /* full 256B request */
+			true; /* half 128b request */
+}
+
+static bool hubbub31_get_dcc_compression_cap(struct hubbub *hubbub,
+		const struct dc_dcc_surface_param *input,
+		struct dc_surface_dcc_cap *output)
+{
+	struct dc *dc = hubbub->ctx->dc;
+	enum dcc_control dcc_control;
+	unsigned int bpe;
+	enum segment_order segment_order_horz, segment_order_vert;
+	bool req128_horz_wc, req128_vert_wc;
+
+	memset(output, 0, sizeof(*output));
+
+	if (dc->debug.disable_dcc == DCC_DISABLE)
+		return false;
+
+	if (!hubbub->funcs->dcc_support_pixel_format(input->format,
+			&bpe))
+		return false;
+
+	if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
+			&segment_order_horz, &segment_order_vert))
+		return false;
+
+	hubbub31_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
+			input->surface_size.height,  input->surface_size.width,
+			bpe, &req128_horz_wc, &req128_vert_wc);
+
+	if (!req128_horz_wc && !req128_vert_wc) {
+		dcc_control = dcc_control__256_256_xxx;
+	} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
+		if (!req128_horz_wc)
+			dcc_control = dcc_control__256_256_xxx;
+		else if (segment_order_horz == segment_order__contiguous)
+			dcc_control = dcc_control__128_128_xxx;
+		else
+			dcc_control = dcc_control__256_64_64;
+	} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
+		if (!req128_vert_wc)
+			dcc_control = dcc_control__256_256_xxx;
+		else if (segment_order_vert == segment_order__contiguous)
+			dcc_control = dcc_control__128_128_xxx;
+		else
+			dcc_control = dcc_control__256_64_64;
+	} else {
+		if ((req128_horz_wc &&
+			segment_order_horz == segment_order__non_contiguous) ||
+			(req128_vert_wc &&
+			segment_order_vert == segment_order__non_contiguous))
+			/* access_dir not known, must use most constraining */
+			dcc_control = dcc_control__256_64_64;
+		else
+			/* reg128 is true for either horz and vert
+			 * but segment_order is contiguous
+			 */
+			dcc_control = dcc_control__128_128_xxx;
+	}
+
+	/* Exception for 64KB_R_X */
+	if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
+		dcc_control = dcc_control__128_128_xxx;
+
+	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
+		dcc_control != dcc_control__256_256_xxx)
+		return false;
+
+	switch (dcc_control) {
+	case dcc_control__256_256_xxx:
+		output->grph.rgb.max_uncompressed_blk_size = 256;
+		output->grph.rgb.max_compressed_blk_size = 256;
+		output->grph.rgb.independent_64b_blks = false;
+		output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1;
+		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
+		break;
+	case dcc_control__128_128_xxx:
+		output->grph.rgb.max_uncompressed_blk_size = 128;
+		output->grph.rgb.max_compressed_blk_size = 128;
+		output->grph.rgb.independent_64b_blks = false;
+		output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1;
+		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
+		break;
+	case dcc_control__256_64_64:
+		output->grph.rgb.max_uncompressed_blk_size = 256;
+		output->grph.rgb.max_compressed_blk_size = 64;
+		output->grph.rgb.independent_64b_blks = true;
+		output->grph.rgb.dcc_controls.dcc_256_64_64 = 1;
+		break;
+	case dcc_control__256_128_128:
+		output->grph.rgb.max_uncompressed_blk_size = 256;
+		output->grph.rgb.max_compressed_blk_size = 128;
+		output->grph.rgb.independent_64b_blks = false;
+		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
+		break;
+	}
+	output->capable = true;
+	output->const_color_support = true;
+
+	return true;
+}
+
+static int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub,
+		struct dcn_hubbub_phys_addr_config *pa_config)
+{
+	hubbub3_init_dchub_sys_ctx(hubbub, pa_config);
+
+	dcn21_dchvm_init(hubbub);
+
+	return NUM_VMID;
+}
+
+static void hubbub31_get_dchub_ref_freq(struct hubbub *hubbub,
+		unsigned int dccg_ref_freq_inKhz,
+		unsigned int *dchub_ref_freq_inKhz)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t ref_div = 0;
+	uint32_t ref_en = 0;
+	unsigned int dc_refclk_khz = 24000;
+
+	REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
+			DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en);
+
+	if (ref_en) {
+		if (ref_div == 2)
+			*dchub_ref_freq_inKhz = dc_refclk_khz / 2;
+		else
+			*dchub_ref_freq_inKhz = dc_refclk_khz;
+
+		/*
+		 * The external Reference Clock may change based on the board or
+		 * platform requirements and the programmable integer divide must
+		 * be programmed to provide a suitable DLG RefClk frequency between
+		 * a minimum of 20MHz and maximum of 50MHz
+		 */
+		if (*dchub_ref_freq_inKhz < 20000 || *dchub_ref_freq_inKhz > 50000)
+			ASSERT_CRITICAL(false);
+
+		return;
+	} else {
+		*dchub_ref_freq_inKhz = dc_refclk_khz;
+
+		// HUBBUB global timer must be enabled.
+		ASSERT_CRITICAL(false);
+		return;
+	}
+}
+
+static const struct hubbub_funcs hubbub31_funcs = {
+	.update_dchub = hubbub2_update_dchub,
+	.init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx,
+	.init_vm_ctx = hubbub2_init_vm_ctx,
+	.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
+	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+	.get_dcc_compression_cap = hubbub31_get_dcc_compression_cap,
+	.wm_read_state = hubbub21_wm_read_state,
+	.get_dchub_ref_freq = hubbub31_get_dchub_ref_freq,
+	.program_watermarks = hubbub31_program_watermarks,
+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
+	.program_det_size = dcn31_program_det_size,
+	.program_compbuf_size = dcn31_program_compbuf_size,
+	.init_crb = dcn31_init_crb
+};
+
+void hubbub31_construct(struct dcn20_hubbub *hubbub31,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb)
+{
+
+	hubbub3_construct(hubbub31, ctx, hubbub_regs, hubbub_shift, hubbub_mask);
+	hubbub31->base.funcs = &hubbub31_funcs;
+	hubbub31->detile_buf_size = det_size_kb * 1024;
+	hubbub31->pixel_chunk_size = pixel_chunk_size_kb * 1024;
+	hubbub31->crb_size_segs = config_return_buffer_size_kb / DCN31_CRB_SEGMENT_SIZE_KB;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
new file mode 100644
index 000000000000..8ec98cbcbd47
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBBUB_DCN31_H__
+#define __DC_HUBBUB_DCN31_H__
+
+#include "dcn21/dcn21_hubbub.h"
+
+#define HUBBUB_REG_LIST_DCN31(id)\
+	HUBBUB_REG_LIST_DCN30(id),\
+	SR(DCHVM_CTRL0),\
+	SR(DCHVM_MEM_CTRL),\
+	SR(DCHVM_CLK_CTRL),\
+	SR(DCHVM_RIOMMU_CTRL0),\
+	SR(DCHVM_RIOMMU_STAT0),\
+	SR(DCHUBBUB_DET0_CTRL),\
+	SR(DCHUBBUB_DET1_CTRL),\
+	SR(DCHUBBUB_DET2_CTRL),\
+	SR(DCHUBBUB_DET3_CTRL),\
+	SR(DCHUBBUB_COMPBUF_CTRL),\
+	SR(COMPBUF_RESERVED_SPACE),\
+	SR(DCHUBBUB_DEBUG_CTRL_0),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D)
+
+#define HUBBUB_MASK_SH_LIST_DCN31(mask_sh)\
+	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
+	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+	HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh)
+
+
+void hubbub31_construct(struct dcn20_hubbub *hubbub3,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
new file mode 100644
index 000000000000..53b792b997b7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dce_calcs.h"
+#include "reg_helper.h"
+#include "basics/conversion.h"
+#include "dcn31_hubp.h"
+
+#define REG(reg)\
+	hubp2->hubp_regs->reg
+
+#define CTX \
+	hubp2->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
+
+void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);
+	REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);
+}
+
+void hubp31_soft_reset(struct hubp *hubp, bool reset)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	REG_UPDATE(DCHUBP_CNTL, HUBP_SOFT_RESET, reset);
+}
+
+static struct hubp_funcs dcn31_hubp_funcs = {
+	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+	.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
+	.hubp_program_surface_config = hubp3_program_surface_config,
+	.hubp_is_flip_pending = hubp2_is_flip_pending,
+	.hubp_setup = hubp3_setup,
+	.hubp_setup_interdependent = hubp2_setup_interdependent,
+	.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
+	.set_blank = hubp2_set_blank,
+	.dcc_control = hubp3_dcc_control,
+	.mem_program_viewport = min_set_viewport,
+	.set_cursor_attributes	= hubp2_cursor_set_attributes,
+	.set_cursor_position	= hubp2_cursor_set_position,
+	.hubp_clk_cntl = hubp2_clk_cntl,
+	.hubp_vtg_sel = hubp2_vtg_sel,
+	.dmdata_set_attributes = hubp3_dmdata_set_attributes,
+	.dmdata_load = hubp2_dmdata_load,
+	.dmdata_status_done = hubp2_dmdata_status_done,
+	.hubp_read_state = hubp3_read_state,
+	.hubp_clear_underflow = hubp2_clear_underflow,
+	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+	.hubp_init = hubp3_init,
+	.set_unbounded_requesting = hubp31_set_unbounded_requesting,
+	.hubp_soft_reset = hubp31_soft_reset,
+	.hubp_in_blank = hubp1_in_blank,
+};
+
+bool hubp31_construct(
+	struct dcn20_hubp *hubp2,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn_hubp2_registers *hubp_regs,
+	const struct dcn_hubp2_shift *hubp_shift,
+	const struct dcn_hubp2_mask *hubp_mask)
+{
+	hubp2->base.funcs = &dcn31_hubp_funcs;
+	hubp2->base.ctx = ctx;
+	hubp2->hubp_regs = hubp_regs;
+	hubp2->hubp_shift = hubp_shift;
+	hubp2->hubp_mask = hubp_mask;
+	hubp2->base.inst = inst;
+	hubp2->base.opp_id = OPP_ID_INVALID;
+	hubp2->base.mpcc_id = 0xf;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h
new file mode 100644
index 000000000000..c31a7b8f81ee
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBP_DCN31_H__
+#define __DC_HUBP_DCN31_H__
+
+#include "dcn20/dcn20_hubp.h"
+#include "dcn21/dcn21_hubp.h"
+#include "dcn30/dcn30_hubp.h"
+
+#define HUBP_MASK_SH_LIST_DCN31(mask_sh)\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
+	HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
+	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\
+	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_REQ_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
+
+
+bool hubp31_construct(
+		struct dcn20_hubp *hubp2,
+		struct dc_context *ctx,
+		uint32_t inst,
+		const struct dcn_hubp2_registers *hubp_regs,
+		const struct dcn_hubp2_shift *hubp_shift,
+		const struct dcn_hubp2_mask *hubp_mask);
+
+void hubp31_soft_reset(struct hubp *hubp, bool reset);
+
+void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);
+
+#endif /* __DC_HUBP_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
new file mode 100644
index 000000000000..fc1fc1a4bf8b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dm_helpers.h"
+#include "core_types.h"
+#include "resource.h"
+#include "dccg.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "reg_helper.h"
+#include "abm.h"
+#include "hubp.h"
+#include "dchubbub.h"
+#include "timing_generator.h"
+#include "opp.h"
+#include "ipp.h"
+#include "mpc.h"
+#include "mcif_wb.h"
+#include "dc_dmub_srv.h"
+#include "dcn31_hwseq.h"
+#include "link_hwss.h"
+#include "dpcd_defs.h"
+#include "dce/dmub_outbox.h"
+#include "dc_link_dp.h"
+#include "inc/link_dpcd.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+	hws->ctx
+#define REG(reg)\
+	hws->regs->reg
+#define DC_LOGGER \
+		dc->ctx->logger
+
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hws->shifts->field_name, hws->masks->field_name
+
+void dcn31_init_hw(struct dc *dc)
+{
+	struct abm **abms = dc->res_pool->multiple_abms;
+	struct dce_hwseq *hws = dc->hwseq;
+	struct dc_bios *dcb = dc->ctx->dc_bios;
+	struct resource_pool *res_pool = dc->res_pool;
+	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
+	int i, j;
+	int edp_num;
+
+	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+
+	// Initialize the dccg
+	if (res_pool->dccg->funcs->dccg_init)
+		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+
+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+
+		REG_WRITE(REFCLK_CNTL, 0);
+		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+
+		if (!dc->debug.disable_clock_gate) {
+			/* enable all DCN clock gating */
+			REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+
+			REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+		}
+
+		//Enable ability to power gate / don't force power on permanently
+		if (hws->funcs.enable_power_gating_plane)
+			hws->funcs.enable_power_gating_plane(hws, true);
+
+		return;
+	}
+
+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+		hws->funcs.bios_golden_init(dc);
+		hws->funcs.disable_vga(dc->hwseq);
+	}
+
+	if (dc->debug.enable_mem_low_power.bits.dmcu) {
+		// Force ERAM to shutdown if DMCU is not enabled
+		if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
+			REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
+		}
+	}
+
+	// Set default OPTC memory power states
+	if (dc->debug.enable_mem_low_power.bits.optc) {
+		// Shutdown when unassigned and light sleep in VBLANK
+		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
+	}
+
+	if (dc->debug.enable_mem_low_power.bits.vga) {
+		// Power down VGA memory
+		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
+	}
+
+	if (dc->ctx->dc_bios->fw_info_valid) {
+		res_pool->ref_clocks.xtalin_clock_inKhz =
+				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+
+		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+			if (res_pool->dccg && res_pool->hubbub) {
+
+				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+						res_pool->ref_clocks.dccg_ref_clock_inKhz,
+						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+			} else {
+				// Not all ASICs have DCCG sw component
+				res_pool->ref_clocks.dccg_ref_clock_inKhz =
+						res_pool->ref_clocks.xtalin_clock_inKhz;
+				res_pool->ref_clocks.dchub_ref_clock_inKhz =
+						res_pool->ref_clocks.xtalin_clock_inKhz;
+			}
+		}
+	} else
+		ASSERT_CRITICAL(false);
+
+	for (i = 0; i < dc->link_count; i++) {
+		/* Power up AND update implementation according to the
+		 * required signal (which may be different from the
+		 * default signal on connector).
+		 */
+		struct dc_link *link = dc->links[i];
+
+		link->link_enc->funcs->hw_init(link->link_enc);
+
+		/* Check for enabled DIG to identify enabled display */
+		if (link->link_enc->funcs->is_dig_enabled &&
+			link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			link->link_status.link_active = true;
+	}
+
+	/* Power gate DSCs */
+	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+		if (hws->funcs.dsc_pg_control != NULL)
+			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+
+	/* we want to turn off all dp displays before doing detection */
+	if (dc->config.power_down_display_on_boot) {
+		uint8_t dpcd_power_state = '\0';
+		enum dc_status status = DC_ERROR_UNEXPECTED;
+
+		for (i = 0; i < dc->link_count; i++) {
+			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
+				continue;
+
+			/* if any of the displays are lit up turn them off */
+			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+						     &dpcd_power_state, sizeof(dpcd_power_state));
+			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
+				/* blank dp stream before power off receiver*/
+				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
+					unsigned int fe;
+
+					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
+										dc->links[i]->link_enc);
+					if (fe == ENGINE_ID_UNKNOWN)
+						continue;
+
+					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+						if (fe == dc->res_pool->stream_enc[j]->id) {
+							dc->res_pool->stream_enc[j]->funcs->dp_blank(
+										dc->res_pool->stream_enc[j]);
+							break;
+						}
+					}
+				}
+				dp_receiver_power_ctrl(dc->links[i], false);
+			}
+		}
+	}
+
+	/* If taking control over from VBIOS, we may want to optimize our first
+	 * mode set, so we need to skip powering down pipes until we know which
+	 * pipes we want to use.
+	 * Otherwise, if taking control is not possible, we need to power
+	 * everything down.
+	 */
+	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+		hws->funcs.init_pipes(dc, dc->current_state);
+		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
+			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
+					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
+	}
+
+	/* In headless boot cases, DIG may be turned
+	 * on which causes HW/SW discrepancies.
+	 * To avoid this, power down hardware on boot
+	 * if DIG is turned on and seamless boot not enabled
+	 */
+	if (dc->config.power_down_display_on_boot) {
+		struct dc_link *edp_links[MAX_NUM_EDP];
+		struct dc_link *edp_link;
+
+		get_edp_links(dc, edp_links, &edp_num);
+		if (edp_num) {
+			for (i = 0; i < edp_num; i++) {
+				edp_link = edp_links[i];
+				if (edp_link->link_enc->funcs->is_dig_enabled &&
+						edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
+						dc->hwss.edp_backlight_control &&
+						dc->hwss.power_down &&
+						dc->hwss.edp_power_control) {
+					dc->hwss.edp_backlight_control(edp_link, false);
+					dc->hwss.power_down(dc);
+					dc->hwss.edp_power_control(edp_link, false);
+				}
+			}
+		} else {
+			for (i = 0; i < dc->link_count; i++) {
+				struct dc_link *link = dc->links[i];
+
+				if (link->link_enc->funcs->is_dig_enabled &&
+						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
+						dc->hwss.power_down) {
+					dc->hwss.power_down(dc);
+					break;
+				}
+
+			}
+		}
+	}
+
+	for (i = 0; i < res_pool->audio_count; i++) {
+		struct audio *audio = res_pool->audios[i];
+
+		audio->funcs->hw_init(audio);
+	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		struct dc_link *link = dc->links[i];
+
+		if (link->panel_cntl)
+			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (abms[i] != NULL)
+			abms[i]->funcs->abm_init(abms[i], backlight);
+	}
+
+	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+
+	if (!dc->debug.disable_clock_gate) {
+		/* enable all DCN clock gating */
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+	}
+	if (hws->funcs.enable_power_gating_plane)
+		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
+	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
+		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
+
+	if (dc->clk_mgr->funcs->notify_wm_ranges)
+		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
+
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+
+	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+		dc->res_pool->hubbub->funcs->force_pstate_change_control(
+				dc->res_pool->hubbub, false, false);
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
+}
+
+void dcn31_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t org_ip_request_cntl = 0;
+
+	if (hws->ctx->dc->debug.disable_dsc_power_gate)
+		return;
+
+	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
+
+	switch (dsc_inst) {
+	case 0: /* DSC0 */
+		REG_UPDATE(DOMAIN16_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN16_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 1: /* DSC1 */
+		REG_UPDATE(DOMAIN17_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN17_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 2: /* DSC2 */
+		REG_UPDATE(DOMAIN18_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN18_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+}
+
+
+void dcn31_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable)
+{
+	bool force_on = true; /* disable power gating */
+
+	if (enable)
+		force_on = false;
+
+	/* DCHUBP0/1/2/3/4/5 */
+	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+
+	/* DPP0/1/2/3/4/5 */
+	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+
+	/* DCS0/1/2/3/4/5 */
+	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+}
+
+void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
+{
+	bool is_hdmi_tmds;
+	bool is_dp;
+
+	ASSERT(pipe_ctx->stream);
+
+	if (pipe_ctx->stream_res.stream_enc == NULL)
+		return;  /* this is not root pipe */
+
+	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
+	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
+
+	if (!is_hdmi_tmds)
+		return;
+
+	if (is_hdmi_tmds)
+		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
+			pipe_ctx->stream_res.stream_enc,
+			&pipe_ctx->stream_res.encoder_info_frame);
+	else {
+		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
+			pipe_ctx->stream_res.stream_enc,
+			&pipe_ctx->stream_res.encoder_info_frame);
+	}
+}
+
+void dcn31_z10_restore(struct dc *dc)
+{
+	union dmub_rb_cmd cmd;
+
+	/*
+	 * DMUB notifies whether restore is required.
+	 * Optimization to avoid sending commands when not required.
+	 */
+	if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
+		return;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
+	cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
+
+	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+}
+
+void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+
+	if (hws->ctx->dc->debug.disable_hubp_power_gate)
+		return;
+
+	if (REG(DOMAIN0_PG_CONFIG) == 0)
+		return;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 1:
+		REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 2:
+		REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 3:
+		REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+}
+
+int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+{
+	struct dcn_hubbub_phys_addr_config config;
+
+	config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
+	config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
+	config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
+	config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
+	config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
+	config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
+	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
+	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
+
+	if (pa_config->gart_config.base_addr_is_mc_addr) {
+		/* Convert from MC address to offset into FB */
+		config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
+				pa_config->system_aperture.fb_base +
+				pa_config->system_aperture.fb_offset;
+	} else
+		config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
+
+	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
+}
+
+static void dcn31_reset_back_end_for_pipe(
+		struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		struct dc_state *context)
+{
+	struct dc_link *link;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+	if (pipe_ctx->stream_res.stream_enc == NULL) {
+		pipe_ctx->stream = NULL;
+		return;
+	}
+	ASSERT(!pipe_ctx->top_pipe);
+
+	dc->hwss.set_abm_immediate_disable(pipe_ctx);
+
+	pipe_ctx->stream_res.tg->funcs->set_dsc_config(
+			pipe_ctx->stream_res.tg,
+			OPTC_DSC_DISABLED, 0, 0);
+	pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
+
+	pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
+	if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
+		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
+				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+	if (pipe_ctx->stream_res.tg->funcs->set_drr)
+		pipe_ctx->stream_res.tg->funcs->set_drr(
+				pipe_ctx->stream_res.tg, NULL);
+
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		link = pipe_ctx->stream->link;
+		/* DPMS may already disable or */
+		/* dpms_off status is incorrect due to fastboot
+		 * feature. When system resume from S4 with second
+		 * screen only, the dpms_off would be true but
+		 * VBIOS lit up eDP, so check link status too.
+		 */
+		if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
+			core_link_disable_stream(pipe_ctx);
+		else if (pipe_ctx->stream_res.audio)
+			dc->hwss.disable_audio_stream(pipe_ctx);
+
+		/* free acquired resources */
+		if (pipe_ctx->stream_res.audio) {
+			/*disable az_endpoint*/
+			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+
+			/*free audio*/
+			if (dc->caps.dynamic_audio == true) {
+				/*we have to dynamic arbitrate the audio endpoints*/
+				/*we free the resource, need reset is_audio_acquired*/
+				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
+						pipe_ctx->stream_res.audio, false);
+				pipe_ctx->stream_res.audio = NULL;
+			}
+		}
+	} else if (pipe_ctx->stream_res.dsc) {
+			dp_set_dsc_enable(pipe_ctx, false);
+	}
+
+	pipe_ctx->stream = NULL;
+	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
+					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
+}
+
+void dcn31_reset_hw_ctx_wrap(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	int i;
+	struct dce_hwseq *hws = dc->hwseq;
+
+	/* Reset Back End*/
+	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
+		struct pipe_ctx *pipe_ctx_old =
+			&dc->current_state->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe_ctx_old->stream)
+			continue;
+
+		if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
+			continue;
+
+		if (!pipe_ctx->stream ||
+				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
+			struct clock_source *old_clk = pipe_ctx_old->clock_source;
+
+			dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
+			if (hws->funcs.enable_stream_gating)
+				hws->funcs.enable_stream_gating(dc, pipe_ctx);
+			if (old_clk)
+				old_clk->funcs->cs_power_down(old_clk);
+		}
+	}
+}
+
+bool dcn31_is_abm_supported(struct dc *dc,
+		struct dc_state *context, struct dc_stream_state *stream)
+{
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe_ctx->stream == stream &&
+				(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
+			return true;
+	}
+	return false;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
new file mode 100644
index 000000000000..ff72f0fdd5be
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
@@ -0,0 +1,56 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN31_H__
+#define __DC_HWSS_DCN31_H__
+
+#include "hw_sequencer_private.h"
+
+struct dc;
+
+void dcn31_init_hw(struct dc *dc);
+
+void dcn31_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on);
+
+void dcn31_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable);
+
+void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);
+
+void dcn31_z10_restore(struct dc *dc);
+
+void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+void dcn31_reset_hw_ctx_wrap(
+		struct dc *dc,
+		struct dc_state *context);
+bool dcn31_is_abm_supported(struct dc *dc,
+		struct dc_state *context, struct dc_stream_state *stream);
+
+#endif /* __DC_HWSS_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
new file mode 100644
index 000000000000..e3048f8827d2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_hw_sequencer.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn21/dcn21_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dcn301/dcn301_hwseq.h"
+#include "dcn31/dcn31_hwseq.h"
+
+static const struct hw_sequencer_funcs dcn31_funcs = {
+	.program_gamut_remap = dcn10_program_gamut_remap,
+	.init_hw = dcn31_init_hw,
+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+	.apply_ctx_for_surface = NULL,
+	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
+	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.update_dchub = dcn10_update_dchub,
+	.update_pending_status = dcn10_update_pending_status,
+	.program_output_csc = dcn20_program_output_csc,
+	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+	.update_info_frame = dcn31_update_info_frame,
+	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+	.enable_stream = dcn20_enable_stream,
+	.disable_stream = dce110_disable_stream,
+	.unblank_stream = dcn20_unblank_stream,
+	.blank_stream = dce110_blank_stream,
+	.enable_audio_stream = dce110_enable_audio_stream,
+	.disable_audio_stream = dce110_disable_audio_stream,
+	.disable_plane = dcn20_disable_plane,
+	.pipe_control_lock = dcn20_pipe_control_lock,
+	.interdependent_update_lock = dcn10_lock_all_pipes,
+	.cursor_lock = dcn10_cursor_lock,
+	.prepare_bandwidth = dcn20_prepare_bandwidth,
+	.optimize_bandwidth = dcn20_optimize_bandwidth,
+	.update_bandwidth = dcn20_update_bandwidth,
+	.set_drr = dcn10_set_drr,
+	.get_position = dcn10_get_position,
+	.set_static_screen_control = dcn10_set_static_screen_control,
+	.setup_stereo = dcn10_setup_stereo,
+	.set_avmute = dcn30_set_avmute,
+	.log_hw_state = dcn10_log_hw_state,
+	.get_hw_state = dcn10_get_hw_state,
+	.clear_status_bits = dcn10_clear_status_bits,
+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.edp_power_control = dce110_edp_power_control,
+	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+	.set_cursor_position = dcn10_set_cursor_position,
+	.set_cursor_attribute = dcn10_set_cursor_attribute,
+	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+	.set_clock = dcn10_set_clock,
+	.get_clock = dcn10_get_clock,
+	.program_triplebuffer = dcn20_program_triple_buffer,
+	.enable_writeback = dcn30_enable_writeback,
+	.disable_writeback = dcn30_disable_writeback,
+	.update_writeback = dcn30_update_writeback,
+	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
+	.dmdata_status_done = dcn20_dmdata_status_done,
+	.program_dmdata_engine = dcn30_program_dmdata_engine,
+	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
+	.init_sys_ctx = dcn31_init_sys_ctx,
+	.init_vm_ctx = dcn20_init_vm_ctx,
+	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
+	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+	.calc_vupdate_position = dcn10_calc_vupdate_position,
+	.apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations,
+	.set_backlight_level = dcn21_set_backlight_level,
+	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
+	.set_pipe = dcn21_set_pipe,
+	.z10_restore = dcn31_z10_restore,
+	.is_abm_supported = dcn31_is_abm_supported,
+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
+};
+
+static const struct hwseq_private_funcs dcn31_private_funcs = {
+	.init_pipes = dcn10_init_pipes,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+	.update_mpcc = dcn20_update_mpcc,
+	.set_input_transfer_func = dcn30_set_input_transfer_func,
+	.set_output_transfer_func = dcn30_set_output_transfer_func,
+	.power_down = dce110_power_down,
+	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+	.blank_pixel_data = dcn20_blank_pixel_data,
+	.reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
+	.enable_stream_timing = dcn20_enable_stream_timing,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.disable_stream_gating = dcn20_disable_stream_gating,
+	.enable_stream_gating = dcn20_enable_stream_gating,
+	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+	.did_underflow_occur = dcn10_did_underflow_occur,
+	.init_blank = dcn20_init_blank,
+	.disable_vga = dcn20_disable_vga,
+	.bios_golden_init = dcn10_bios_golden_init,
+	.plane_atomic_disable = dcn20_plane_atomic_disable,
+	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
+	.enable_power_gating_plane = dcn31_enable_power_gating_plane,
+	.hubp_pg_control = dcn31_hubp_pg_control,
+	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
+	.update_odm = dcn20_update_odm,
+	.dsc_pg_control = dcn31_dsc_pg_control,
+	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
+	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
+	.dccg_init = dcn20_dccg_init,
+	.set_blend_lut = dcn30_set_blend_lut,
+	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
+};
+
+void dcn31_hw_sequencer_construct(struct dc *dc)
+{
+	dc->hwss = dcn31_funcs;
+	dc->hwseq->funcs = dcn31_private_funcs;
+
+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		dc->hwss.init_hw = dcn20_fpga_init_hw;
+		dc->hwseq->funcs.init_pipes = NULL;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h
new file mode 100644
index 000000000000..a3db08c8bd35
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DCN31_INIT_H__
+#define __DC_DCN31_INIT_H__
+
+struct dc;
+
+void dcn31_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_DCN31_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
new file mode 100644
index 000000000000..a4b1d98f0007
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn31_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+
+#define REG(reg)\
+	optc1->tg_regs->reg
+
+#define CTX \
+	optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+		struct dc_crtc_timing *timing)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+	int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
+			/ opp_cnt;
+	uint32_t memory_mask = 0;
+	int mem_count_per_opp = (mpcc_hactive + 2559) / 2560;
+
+	/* Assume less than 6 pipes */
+	if (opp_cnt == 4) {
+		if (mem_count_per_opp == 1)
+			memory_mask = 0xf;
+		else {
+			ASSERT(mem_count_per_opp == 2);
+			memory_mask = 0xff;
+		}
+	} else if (mem_count_per_opp == 1)
+		memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+	else if (mem_count_per_opp == 2)
+		memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+	else if (mem_count_per_opp == 3)
+		memory_mask = 0x77;
+	else if (mem_count_per_opp == 4)
+		memory_mask = 0xff;
+
+	if (REG(OPTC_MEMORY_CONFIG))
+		REG_SET(OPTC_MEMORY_CONFIG, 0,
+			OPTC_MEM_SEL, memory_mask);
+
+	if (opp_cnt == 2) {
+		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 1,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1]);
+	} else if (opp_cnt == 4) {
+		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 3,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1],
+				OPTC_SEG2_SRC_SEL, opp_id[2],
+				OPTC_SEG3_SRC_SEL, opp_id[3]);
+	}
+
+	REG_UPDATE(OPTC_WIDTH_CONTROL,
+			OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+	optc1->opp_count = opp_cnt;
+}
+
+/**
+ * Enable CRTC
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+static bool optc31_enable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+			OPTC_SEG0_SRC_SEL, optc->inst);
+
+	/* VTG enable first is for HW workaround */
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 1);
+
+	REG_SEQ_START();
+
+	/* Enable CRTC */
+	REG_UPDATE_2(OTG_CONTROL,
+			OTG_DISABLE_POINT_CNTL, 2,
+			OTG_MASTER_EN, 1);
+
+	REG_SEQ_SUBMIT();
+	REG_SEQ_WAIT_DONE();
+
+	return true;
+}
+
+/* disable_crtc - call ASIC Control Object to disable Timing generator. */
+static bool optc31_disable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* disable otg request until end of the first line
+	 * in the vertical blank region
+	 */
+	REG_UPDATE(OTG_CONTROL,
+			OTG_MASTER_EN, 0);
+
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL,
+			OTG_BUSY, 0,
+			1, 100000);
+
+	return true;
+}
+
+static bool optc31_immediate_disable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_UPDATE_2(OTG_CONTROL,
+			OTG_DISABLE_POINT_CNTL, 0,
+			OTG_MASTER_EN, 0);
+
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL,
+			OTG_BUSY, 0,
+			1, 100000);
+
+	return true;
+}
+
+static void optc31_set_drr(
+	struct timing_generator *optc,
+	const struct drr_params *params)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	if (params != NULL &&
+		params->vertical_total_max > 0 &&
+		params->vertical_total_min > 0) {
+
+		if (params->vertical_total_mid != 0) {
+
+			REG_SET(OTG_V_TOTAL_MID, 0,
+				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+					OTG_VTOTAL_MID_FRAME_NUM,
+					(uint8_t)params->vertical_total_mid_frame_num);
+
+		}
+
+		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
+
+		/*
+		 * MIN_MASK_EN is gone and MASK is now always enabled.
+		 *
+		 * To get it to it work with manual trigger we need to make sure
+		 * we program the correct bit.
+		 */
+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+				OTG_V_TOTAL_MIN_SEL, 1,
+				OTG_V_TOTAL_MAX_SEL, 1,
+				OTG_FORCE_LOCK_ON_EVENT, 0,
+				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
+
+		// Setup manual flow control for EOF via TRIG_A
+		optc->funcs->setup_manual_trigger(optc);
+
+	} else {
+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+				OTG_SET_V_TOTAL_MIN_MASK, 0,
+				OTG_V_TOTAL_MIN_SEL, 0,
+				OTG_V_TOTAL_MAX_SEL, 0,
+				OTG_FORCE_LOCK_ON_EVENT, 0);
+
+		optc->funcs->set_vtotal_min_max(optc, 0, 0);
+	}
+}
+
+static struct timing_generator_funcs dcn31_tg_funcs = {
+		.validate_timing = optc1_validate_timing,
+		.program_timing = optc1_program_timing,
+		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+		.program_global_sync = optc1_program_global_sync,
+		.enable_crtc = optc31_enable_crtc,
+		.disable_crtc = optc31_disable_crtc,
+		.immediate_disable_crtc = optc31_immediate_disable_crtc,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.is_counter_moving = optc1_is_counter_moving,
+		.get_position = optc1_get_position,
+		.get_frame_count = optc1_get_vblank_counter,
+		.get_scanoutpos = optc1_get_crtc_scanoutpos,
+		.get_otg_active_size = optc1_get_otg_active_size,
+		.set_early_control = optc1_set_early_control,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.wait_for_state = optc1_wait_for_state,
+		.set_blank_color = optc3_program_blank_color,
+		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+		.triplebuffer_lock = optc3_triplebuffer_lock,
+		.triplebuffer_unlock = optc2_triplebuffer_unlock,
+		.enable_reset_trigger = optc1_enable_reset_trigger,
+		.enable_crtc_reset = optc1_enable_crtc_reset,
+		.disable_reset_trigger = optc1_disable_reset_trigger,
+		.lock = optc3_lock,
+		.is_locked = optc1_is_locked,
+		.unlock = optc1_unlock,
+		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+		.enable_optc_clock = optc1_enable_optc_clock,
+		.set_drr = optc31_set_drr,
+		.set_vtotal_min_max = optc1_set_vtotal_min_max,
+		.set_static_screen_control = optc1_set_static_screen_control,
+		.program_stereo = optc1_program_stereo,
+		.is_stereo_left_eye = optc1_is_stereo_left_eye,
+		.tg_init = optc3_tg_init,
+		.is_tg_enabled = optc1_is_tg_enabled,
+		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+		.clear_optc_underflow = optc1_clear_optc_underflow,
+		.setup_global_swap_lock = NULL,
+		.get_crc = optc1_get_crc,
+		.configure_crc = optc2_configure_crc,
+		.set_dsc_config = optc3_set_dsc_config,
+		.set_dwb_source = NULL,
+		.set_odm_bypass = optc3_set_odm_bypass,
+		.set_odm_combine = optc31_set_odm_combine,
+		.get_optc_source = optc2_get_optc_source,
+		.set_out_mux = optc3_set_out_mux,
+		.set_drr_trigger_window = optc3_set_drr_trigger_window,
+		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+		.set_gsl = optc2_set_gsl,
+		.set_gsl_source_select = optc2_set_gsl_source_select,
+		.set_vtg_params = optc1_set_vtg_params,
+		.program_manual_trigger = optc2_program_manual_trigger,
+		.setup_manual_trigger = optc2_setup_manual_trigger,
+		.get_hw_timing = optc1_get_hw_timing,
+};
+
+void dcn31_timing_generator_init(struct optc *optc1)
+{
+	optc1->base.funcs = &dcn31_tg_funcs;
+
+	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+	optc1->min_h_blank = 32;
+	optc1->min_v_blank = 3;
+	optc1->min_v_blank_interlace = 5;
+	optc1->min_h_sync_width = 4;
+	optc1->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
new file mode 100644
index 000000000000..d8ef2f0d0c95
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN31_H__
+#define __DC_OPTC_DCN31_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define OPTC_COMMON_REG_LIST_DCN3_1(inst) \
+	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+	SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+	SRI(OTG_VREADY_PARAM, OTG, inst),\
+	SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
+	SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+	SRI(OTG_H_TOTAL, OTG, inst),\
+	SRI(OTG_H_BLANK_START_END, OTG, inst),\
+	SRI(OTG_H_SYNC_A, OTG, inst),\
+	SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+	SRI(OTG_V_TOTAL, OTG, inst),\
+	SRI(OTG_V_BLANK_START_END, OTG, inst),\
+	SRI(OTG_V_SYNC_A, OTG, inst),\
+	SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_CONTROL, OTG, inst),\
+	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_STATUS, OTG, inst),\
+	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+	SRI(OTG_TRIGA_CNTL, OTG, inst),\
+	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+	SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+	SRI(OTG_STATUS, OTG, inst),\
+	SRI(OTG_STATUS_POSITION, OTG, inst),\
+	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+	SRI(OTG_M_CONST_DTO0, OTG, inst),\
+	SRI(OTG_M_CONST_DTO1, OTG, inst),\
+	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+	SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+	SRI(CONTROL, VTG, inst),\
+	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+	SRI(OTG_GSL_CONTROL, OTG, inst),\
+	SRI(OTG_CRC_CNTL, OTG, inst),\
+	SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+	SRI(OTG_CRC0_DATA_B, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+	SR(GSL_SOURCE_SELECT),\
+	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+	SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+	SRI(OTG_DSC_START_POSITION, OTG, inst),\
+	SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+	SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+	SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+	SRI(OTG_CRC_CNTL2, OTG, inst),\
+	SR(DWB_SOURCE_SELECT)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\
+	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+	SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+	SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+	SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+	SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+	SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+	SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+	SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+	SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh)
+
+void dcn31_timing_generator_init(struct optc *optc1);
+
+#endif /* __DC_OPTC_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
new file mode 100644
index 000000000000..7db268da6976
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dc_dmub_srv.h"
+#include "dcn31_panel_cntl.h"
+#include "atom.h"
+
+#define TO_DCN31_PANEL_CNTL(panel_cntl)\
+	container_of(panel_cntl, struct dcn31_panel_cntl, base)
+
+#define CTX \
+	dcn31_panel_cntl->base.ctx
+
+#define DC_LOGGER \
+	dcn31_panel_cntl->base.ctx->logger
+
+static bool dcn31_query_backlight_info(struct panel_cntl *panel_cntl, union dmub_rb_cmd *cmd)
+{
+	struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl);
+	struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;
+
+	if (!dc_dmub_srv)
+		return false;
+
+	memset(cmd, 0, sizeof(*cmd));
+	cmd->panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;
+	cmd->panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO;
+	cmd->panel_cntl.header.payload_bytes = sizeof(cmd->panel_cntl.data);
+	cmd->panel_cntl.data.inst = dcn31_panel_cntl->base.inst;
+
+	return dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, cmd);
+}
+
+static uint32_t dcn31_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return 0;
+
+	return cmd.panel_cntl.data.current_backlight;
+}
+
+uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
+{
+	struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl);
+	struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;
+	union dmub_rb_cmd cmd;
+
+	if (!dc_dmub_srv)
+		return 0;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;
+	cmd.panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_HW_INIT;
+	cmd.panel_cntl.header.payload_bytes = sizeof(cmd.panel_cntl.data);
+	cmd.panel_cntl.data.inst = dcn31_panel_cntl->base.inst;
+	cmd.panel_cntl.data.bl_pwm_cntl = panel_cntl->stored_backlight_registers.BL_PWM_CNTL;
+	cmd.panel_cntl.data.bl_pwm_period_cntl = panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL;
+	cmd.panel_cntl.data.bl_pwm_ref_div1 =
+		panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
+
+	if (!dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, &cmd))
+		return 0;
+
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL = cmd.panel_cntl.data.bl_pwm_cntl;
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 0; /* unused */
+	panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = cmd.panel_cntl.data.bl_pwm_period_cntl;
+	panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV =
+		cmd.panel_cntl.data.bl_pwm_ref_div1;
+
+	return cmd.panel_cntl.data.current_backlight;
+}
+
+void dcn31_panel_cntl_destroy(struct panel_cntl **panel_cntl)
+{
+	struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(*panel_cntl);
+
+	kfree(dcn31_panel_cntl);
+	*panel_cntl = NULL;
+}
+
+bool dcn31_is_panel_backlight_on(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return 0;
+
+	return cmd.panel_cntl.data.is_backlight_on;
+}
+
+bool dcn31_is_panel_powered_on(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return 0;
+
+	return cmd.panel_cntl.data.is_powered_on;
+}
+
+void dcn31_store_backlight_level(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return;
+
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL = cmd.panel_cntl.data.bl_pwm_cntl;
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 0; /* unused */
+	panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = cmd.panel_cntl.data.bl_pwm_period_cntl;
+	panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV =
+		cmd.panel_cntl.data.bl_pwm_ref_div1;
+}
+
+static const struct panel_cntl_funcs dcn31_link_panel_cntl_funcs = {
+	.destroy = dcn31_panel_cntl_destroy,
+	.hw_init = dcn31_panel_cntl_hw_init,
+	.is_panel_backlight_on = dcn31_is_panel_backlight_on,
+	.is_panel_powered_on = dcn31_is_panel_powered_on,
+	.store_backlight_level = dcn31_store_backlight_level,
+	.get_current_backlight = dcn31_get_16_bit_backlight_from_pwm,
+};
+
+void dcn31_panel_cntl_construct(
+	struct dcn31_panel_cntl *dcn31_panel_cntl,
+	const struct panel_cntl_init_data *init_data)
+{
+	dcn31_panel_cntl->base.funcs = &dcn31_link_panel_cntl_funcs;
+	dcn31_panel_cntl->base.ctx = init_data->ctx;
+	dcn31_panel_cntl->base.inst = init_data->inst;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h
new file mode 100644
index 000000000000..d33ccd6ef8c3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_PANEL_CNTL__DCN31_H__
+#define __DC_PANEL_CNTL__DCN31_H__
+
+#include "panel_cntl.h"
+#include "dce/dce_panel_cntl.h"
+
+struct dcn31_panel_cntl {
+	struct panel_cntl base;
+};
+
+void dcn31_panel_cntl_construct(
+	struct dcn31_panel_cntl *dcn31_panel_cntl,
+	const struct panel_cntl_init_data *init_data);
+
+#endif /* __DC_PANEL_CNTL__DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
new file mode 100644
index 000000000000..c67bc9544f5d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -0,0 +1,2195 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn31/dcn31_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn31_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31/dcn31_hubbub.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn31/dcn31_hubp.h"
+#include "irq/dcn31/irq_service_dcn31.h"
+#include "dcn30/dcn30_dpp.h"
+#include "dcn31/dcn31_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dce110/dce110_resource.h"
+#include "dml/display_mode_vba.h"
+#include "dcn31/dcn31_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dcn31_panel_cntl.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn30/dcn30_mmhubbub.h"
+
+// TODO: change include headers /amd/include/asic_reg after upstream
+#include "yellow_carp_offset.h"
+#include "dcn/dcn_3_1_2_offset.h"
+#include "dcn/dcn_3_1_2_sh_mask.h"
+#include "nbio/nbio_7_2_0_offset.h"
+#include "dpcs/dpcs_4_2_0_offset.h"
+#include "dpcs/dpcs_4_2_0_sh_mask.h"
+#include "mmhub/mmhub_2_3_0_offset.h"
+#include "mmhub/mmhub_2_3_0_sh_mask.h"
+
+
+#define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dmub_psr.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+
+#include "link_enc_cfg.h"
+
+#define DC_LOGGER_INIT(logger)
+#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
+#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
+
+#define DCN3_1_DEFAULT_DET_SIZE 384
+
+struct _vcs_dpi_ip_params_st dcn3_1_ip = {
+	.gpuvm_enable = 1,
+	.gpuvm_max_page_table_levels = 1,
+	.hostvm_enable = 1,
+	.hostvm_max_page_table_levels = 2,
+	.rob_buffer_size_kbytes = 64,
+	.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
+	.config_return_buffer_size_in_kbytes = 1792,
+	.compressed_buffer_segment_size_in_kbytes = 64,
+	.meta_fifo_size_in_kentries = 32,
+	.zero_size_buffer_entries = 512,
+	.compbuf_reserved_space_64b = 256,
+	.compbuf_reserved_space_zs = 64,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.meta_chunk_size_kbytes = 2,
+	.min_meta_chunk_size_bytes = 256,
+	.writeback_chunk_size_kbytes = 8,
+	.ptoi_supported = false,
+	.num_dsc = 3,
+	.maximum_dsc_bits_per_component = 10,
+	.dsc422_native_support = false,
+	.is_line_buffer_bpp_fixed = true,
+	.line_buffer_fixed_bpp = 48,
+	.line_buffer_size_bits = 789504,
+	.max_line_buffer_lines = 12,
+	.writeback_interface_buffer_size_kbytes = 90,
+	.max_num_dpp = 4,
+	.max_num_otg = 4,
+	.max_num_hdmi_frl_outputs = 1,
+	.max_num_wb = 1,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 6,
+	.max_vscl_ratio = 6,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dpte_buffer_size_in_pte_reqs_luma = 64,
+	.dpte_buffer_size_in_pte_reqs_chroma = 34,
+	.dispclk_ramp_margin_percent = 1,
+	.max_inter_dcn_tile_repeaters = 8,
+	.cursor_buffer_size = 16,
+	.cursor_chunk_size = 2,
+	.writeback_line_buffer_buffer_size = 0,
+	.writeback_min_hscl_ratio = 1,
+	.writeback_min_vscl_ratio = 1,
+	.writeback_max_hscl_ratio = 1,
+	.writeback_max_vscl_ratio = 1,
+	.writeback_max_hscl_taps = 1,
+	.writeback_max_vscl_taps = 1,
+	.dppclk_delay_subtotal = 46,
+	.dppclk_delay_scl = 50,
+	.dppclk_delay_scl_lb_only = 16,
+	.dppclk_delay_cnvc_formatter = 27,
+	.dppclk_delay_cnvc_cursor = 6,
+	.dispclk_delay_subtotal = 119,
+	.dynamic_metadata_vm_enabled = false,
+	.odm_combine_4to1_supported = false,
+	.dcc_supported = true,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
+		/*TODO: correct dispclk/dppclk voltage level determination*/
+	.clock_limits = {
+		{
+			.state = 0,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 600.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 186.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 1,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 209.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 2,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 209.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 3,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 371.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 4,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 417.0,
+			.dtbclk_mhz = 625.0,
+		},
+	},
+	.num_states = 5,
+	.sr_exit_time_us = 9.0,
+	.sr_enter_plus_exit_time_us = 11.0,
+	.sr_exit_z8_time_us = 402.0,
+	.sr_enter_plus_exit_z8_time_us = 520.0,
+	.writeback_latency_us = 12.0,
+	.round_trip_ping_latency_dcfclk_cycles = 106,
+	.urgent_latency_pixel_data_only_us = 4.0,
+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+	.urgent_latency_vm_data_only_us = 4.0,
+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+	.pct_ideal_sdp_bw_after_urgent = 80.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
+	.max_avg_sdp_bw_use_normal_percent = 60.0,
+	.max_avg_dram_bw_use_normal_percent = 60.0,
+	.fabric_datapath_to_dcn_data_return_bytes = 32,
+	.return_bus_width_bytes = 64,
+	.downspread_percent = 0.38,
+	.dcn_downspread_percent = 0.5,
+	.gpuvm_min_page_size_bytes = 4096,
+	.hostvm_min_page_size_bytes = 4096,
+	.do_urgent_latency_adjustment = false,
+	.urgent_latency_adjustment_fabric_clock_component_us = 0,
+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
+};
+
+enum dcn31_clk_src_array_id {
+	DCN31_CLK_SRC_PLL0,
+	DCN31_CLK_SRC_PLL1,
+	DCN31_CLK_SRC_PLL2,
+	DCN31_CLK_SRC_PLL3,
+	DCN31_CLK_SRC_PLL4,
+	DCN30_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
+					reg ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+					reg ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+	NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+	NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
+					regBIF_BX1_ ## reg_name
+
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+	MMHUB_BASE__INST0_SEG ## seg
+
+#define MMHUB_BASE(seg) \
+	MMHUB_BASE_INNER(seg)
+
+#define MMHUB_SR(reg_name)\
+		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
+					mm ## reg_name
+
+/* CLOCK */
+#define CLK_BASE_INNER(seg) \
+	CLK_BASE__INST0_SEG ## seg
+
+#define CLK_BASE(seg) \
+	CLK_BASE_INNER(seg)
+
+#define CLK_SRI(reg_name, block, inst)\
+	.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## _ ## inst ## _ ## reg_name
+
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, C),
+	clk_src_regs(3, D),
+	clk_src_regs(4, E)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+		ABM_DCN301_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+		AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4),
+	audio_regs(5),
+	audio_regs(6)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+	VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+	vpg_regs(0),
+	vpg_regs(1),
+	vpg_regs(2),
+	vpg_regs(3),
+	vpg_regs(4),
+	vpg_regs(5),
+	vpg_regs(6),
+	vpg_regs(7),
+	vpg_regs(8),
+	vpg_regs(9),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+	DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+	DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+	AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+	afmt_regs(0),
+	afmt_regs(1),
+	afmt_regs(2),
+	afmt_regs(3),
+	afmt_regs(4),
+	afmt_regs(5)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+	DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+	stream_enc_regs(4)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+	DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4)
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+	LE_DCN31_REG_LIST(id), \
+	UNIPHY_DCN2_REG_LIST(phyid), \
+	DPCS_DCN31_REG_LIST(id), \
+}
+
+static const struct dce110_aux_registers_shift aux_shift = {
+	DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+	DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+	link_regs(0, A),
+	link_regs(1, B),
+	link_regs(2, C),
+	link_regs(3, D),
+	link_regs(4, E)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
+	DPCS_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
+	DPCS_DCN31_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+	DPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+	dpp_regs(0),
+	dpp_regs(1),
+	dpp_regs(2),
+	dpp_regs(3)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
+};
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+	OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+	OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST0(id), \
+	.AUXN_IMPCAL = 0, \
+	.AUXP_IMPCAL = 0, \
+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4)
+};
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+	dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+	mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+	DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+	dsc_regsDCN20(0),
+	dsc_regsDCN20(1),
+	dsc_regsDCN20(2)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
+		MPC_RMU_REG_LIST_DCN3AG(0),
+		MPC_RMU_REG_LIST_DCN3AG(1),
+		//MPC_RMU_REG_LIST_DCN3AG(2),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
+
+static const struct dcn_optc_registers optc_regs[] = {
+	optc_regs(0),
+	optc_regs(1),
+	optc_regs(2),
+	optc_regs(3)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+	HUBP_REG_LIST_DCN30(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3)
+};
+
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN31(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN31(_MASK)
+};
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN31(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN31(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN31()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN31(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN31(_MASK)
+};
+
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
+			## id ## _ ## reg_name_post ## _BASE_IDX) + \
+			reg ## reg_name_pre ## id ## _ ## reg_name_post
+
+
+#define HWSEQ_DCN31_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(DMU_MEM_PWR_CNTL), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN31_REG_LIST()
+};
+
+#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
+	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN31_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+		DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+	vmid_regs(0),
+	vmid_regs(1),
+	vmid_regs(2),
+	vmid_regs(3),
+	vmid_regs(4),
+	vmid_regs(5),
+	vmid_regs(6),
+	vmid_regs(7),
+	vmid_regs(8),
+	vmid_regs(9),
+	vmid_regs(10),
+	vmid_regs(11),
+	vmid_regs(12),
+	vmid_regs(13),
+	vmid_regs(14),
+	vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn31 = {
+	.num_timing_generator = 4,
+	.num_opp = 4,
+	.num_video_plane = 4,
+	.num_audio = 5,
+	.num_stream_encoder = 5,
+	.num_dig_link_enc = 5,
+	.num_pll = 5,
+	.num_dwb = 1,
+	.num_ddc = 5,
+	.num_vmid = 16,
+	.num_mpc_3dlut = 2,
+	.num_dsc = 3,
+};
+
+static const struct dc_plane_cap plane_cap = {
+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+	.blends_with_above = true,
+	.blends_with_below = true,
+	.per_pixel_alpha = true,
+
+	.pixel_format_support = {
+			.argb8888 = true,
+			.nv12 = true,
+			.fp16 = true,
+			.p010 = false,
+			.ayuv = false,
+	},
+
+	.max_upscale_factor = {
+			.argb8888 = 16000,
+			.nv12 = 16000,
+			.fp16 = 16000
+	},
+
+	// 6:1 downscaling ratio: 1000/6 = 166.666
+	.max_downscale_factor = {
+			.argb8888 = 167,
+			.nv12 = 167,
+			.fp16 = 167
+	},
+	64,
+	64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = false,
+	.clock_trace = true,
+	.disable_pplib_clock_request = false,
+	.pipe_split_policy = MPC_SPLIT_AVOID,
+	.force_single_disp_pipe_split = false,
+	.disable_dcc = DCC_ENABLE,
+	.vsr_support = true,
+	.performance_trace = false,
+	.max_downscale_src_width = 7680,/*upto 8K*/
+	.disable_pplib_wm_range = false,
+	.scl_reset_length10 = true,
+	.sanity_checks = false,
+	.underflow_assert_delay_us = 0xFFFFFFFF,
+	.dwb_fi_phase = -1, // -1 = disable,
+	.dmub_command_table = true,
+	.pstate_enabled = true,
+	.use_max_lb = true,
+	.enable_mem_low_power = {
+		.bits = {
+			.vga = false,
+			.i2c = false,
+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
+			.dscl = false,
+			.cm = false,
+			.mpc = false,
+			.optc = false,
+		}
+	},
+	.optimize_edp_link_rate = true,
+	.enable_sw_cntl_psr = true,
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = true,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = false,
+	.scl_reset_length10 = true,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+	.enable_tri_buf = true,
+	.use_max_lb = true
+};
+
+static void dcn31_dpp_destroy(struct dpp **dpp)
+{
+	kfree(TO_DCN20_DPP(*dpp));
+	*dpp = NULL;
+}
+
+static struct dpp *dcn31_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn3_dpp *dpp =
+		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp)
+		return NULL;
+
+	if (dpp3_construct(dpp, ctx, inst,
+			&dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp);
+	return NULL;
+}
+
+static struct output_pixel_processor *dcn31_opp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp =
+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp, ctx, inst,
+			&opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp->base;
+}
+
+static struct dce_aux *dcn31_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst],
+					&aux_mask,
+					&aux_shift,
+					ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct dce_i2c_hw *dcn31_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+static struct mpc *dcn31_mpc_create(
+		struct dc_context *ctx,
+		int num_mpcc,
+		int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+					  GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn30_mpc_construct(mpc30, ctx,
+			&mpc_regs,
+			&mpc_shift,
+			&mpc_mask,
+			num_mpcc,
+			num_rmu);
+
+	return &mpc30->base;
+}
+
+static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
+					  GFP_KERNEL);
+
+	if (!hubbub3)
+		return NULL;
+
+	hubbub31_construct(hubbub3, ctx,
+			&hubbub_reg,
+			&hubbub_shift,
+			&hubbub_mask,
+			dcn3_1_ip.det_buffer_size_kbytes,
+			dcn3_1_ip.pixel_chunk_size_kbytes,
+			dcn3_1_ip.config_return_buffer_size_in_kbytes);
+
+
+	for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub3->base;
+}
+
+static struct timing_generator *dcn31_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance)
+{
+	struct optc *tgn10 =
+		kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn31_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+static struct link_encoder *dcn31_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 =
+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn31_link_encoder_construct(enc20,
+			enc_init_data,
+			&link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter],
+			&link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source],
+			&le_shift,
+			&le_mask);
+
+	return &enc20->enc10.base;
+}
+
+/* Create a minimal link encoder object not associated with a particular
+ * physical connector.
+ * resource_funcs.link_enc_create_minimal
+ */
+static struct link_encoder *dcn31_link_enc_create_minimal(
+		struct dc_context *ctx, enum engine_id eng_id)
+{
+	struct dcn20_link_encoder *enc20;
+
+	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+		return NULL;
+
+	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+	if (!enc20)
+		return NULL;
+
+	dcn31_link_encoder_construct_minimal(
+			enc20,
+			ctx,
+			&link_enc_feature,
+			&link_enc_regs[eng_id - ENGINE_ID_DIGA],
+			eng_id);
+
+	return &enc20->enc10.base;
+}
+
+struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+	struct dcn31_panel_cntl *panel_cntl =
+		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
+
+	if (!panel_cntl)
+		return NULL;
+
+	dcn31_panel_cntl_construct(panel_cntl, init_data);
+
+	return &panel_cntl->base;
+}
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn31_create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn31_vpg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst,
+			&vpg_regs[inst],
+			&vpg_shift,
+			&vpg_mask);
+
+	return &vpg3->base;
+}
+
+static struct afmt *dcn31_afmt_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst,
+			&afmt_regs[inst],
+			&afmt_shift,
+			&afmt_mask);
+
+	return &afmt3->base;
+}
+
+static struct stream_encoder *dcn31_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGF) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn31_vpg_create(ctx, vpg_inst);
+	afmt = dcn31_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt)
+		return NULL;
+
+	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+					eng_id, vpg, afmt,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+static struct dce_hwseq *dcn31_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = dcn31_create_audio,
+	.create_stream_encoder = dcn31_stream_encoder_create,
+	.create_hwseq = dcn31_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+	.read_dce_straps = NULL,
+	.create_audio = NULL,
+	.create_stream_encoder = NULL,
+	.create_hwseq = dcn31_hwseq_create,
+};
+
+static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL) {
+			if (pool->base.stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+				pool->base.stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+				pool->base.stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+			pool->base.stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		if (pool->base.dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->base.dscs[i]);
+	}
+
+	if (pool->base.mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->base.mpc));
+		pool->base.mpc = NULL;
+	}
+	if (pool->base.hubbub != NULL) {
+		kfree(pool->base.hubbub);
+		pool->base.hubbub = NULL;
+	}
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.dpps[i] != NULL)
+			dcn31_dpp_destroy(&pool->base.dpps[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+			pool->base.hubps[i] = NULL;
+		}
+
+		if (pool->base.irqs != NULL) {
+			dal_irq_service_destroy(&pool->base.irqs);
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		if (pool->base.opps[i] != NULL)
+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+		if (pool->base.dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+			pool->base.dwbc[i] = NULL;
+		}
+		if (pool->base.mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+			pool->base.mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.audio_count; i++) {
+		if (pool->base.audios[i])
+			dce_aud_destroy(&pool->base.audios[i]);
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+			pool->base.clock_sources[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+		if (pool->base.mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->base.mpc_lut[i]);
+			pool->base.mpc_lut[i] = NULL;
+		}
+		if (pool->base.mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->base.mpc_shaper[i]);
+			pool->base.mpc_shaper[i] = NULL;
+		}
+	}
+
+	if (pool->base.dp_clock_source != NULL) {
+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+		pool->base.dp_clock_source = NULL;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->base.multiple_abms[i]);
+	}
+
+	if (pool->base.psr != NULL)
+		dmub_psr_destroy(&pool->base.psr);
+
+	if (pool->base.dccg != NULL)
+		dcn_dccg_destroy(&pool->base.dccg);
+}
+
+static struct hubp *dcn31_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 =
+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp31_construct(hubp2, ctx, inst,
+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+						    GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx,
+				&dwbc30_regs[i],
+				&dwbc30_shift,
+				&dwbc30_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+						    GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn30_mmhubbub_construct(mcif_wb30, ctx,
+				&mcif_wb30_regs[i],
+				&mcif_wb30_shift,
+				&mcif_wb30_mask,
+				i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+static struct display_stream_compressor *dcn31_dsc_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc =
+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+	return &dsc->base;
+}
+
+static void dcn31_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
+
+	dcn31_resource_destruct(dcn31_pool);
+	kfree(dcn31_pool);
+	*pool = NULL;
+}
+
+static struct clock_source *dcn31_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static bool is_dual_plane(enum surface_pixel_format format)
+{
+	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
+}
+
+static int dcn31_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	bool fast_validate)
+{
+	int i, pipe_cnt;
+	struct resource_context *res_ctx = &context->res_ctx;
+	struct pipe_ctx *pipe;
+
+	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
+
+	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+		struct dc_crtc_timing *timing;
+
+		if (!res_ctx->pipe_ctx[i].stream)
+			continue;
+		pipe = &res_ctx->pipe_ctx[i];
+		timing = &pipe->stream->timing;
+
+		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
+		pipes[pipe_cnt].pipe.src.gpuvm = true;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
+		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
+		pipes[pipe_cnt].pipe.src.dcc_rate = 3;
+		pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+
+		if (pipes[pipe_cnt].dout.dsc_enable) {
+			switch (timing->display_color_depth) {
+			case COLOR_DEPTH_888:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 8;
+				break;
+			case COLOR_DEPTH_101010:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 10;
+				break;
+			case COLOR_DEPTH_121212:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 12;
+				break;
+			default:
+				ASSERT(0);
+				break;
+			}
+		}
+
+		pipe_cnt++;
+	}
+	context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
+	dc->config.enable_4to1MPC = false;
+	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
+		if (is_dual_plane(pipe->plane_state->format)
+				&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
+			dc->config.enable_4to1MPC = true;
+		} else if (!is_dual_plane(pipe->plane_state->format)) {
+			context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
+			pipes[0].pipe.src.unbounded_req_mode = true;
+		}
+	}
+
+	return pipe_cnt;
+}
+
+static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
+{
+	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
+	}
+}
+
+static void dcn31_calculate_wm_and_dlg_fp(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	int i, pipe_idx;
+	double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+
+	if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
+		dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
+
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+
+#if 0 // TODO
+	/* Set B:
+	 * TODO
+	 */
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
+		if (vlevel == 0) {
+			pipes[0].clks_cfg.voltage = 1;
+			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
+		}
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+
+	/* Set C:
+	 * TODO
+	 */
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	/* Set D:
+	 * TODO
+	 */
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+#endif
+
+	/* Set A:
+	 * All clocks min required
+	 *
+	 * Set A calculated last so that following calculations are based on Set A
+	 */
+	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
+	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	/* TODO: remove: */
+	context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
+	context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
+	context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
+	/* end remove*/
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+
+		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
+		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+		if (dc->config.forced_clocks) {
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+		}
+		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
+		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
+
+		pipe_idx++;
+	}
+
+	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
+}
+
+static void dcn31_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	DC_FP_START();
+	dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
+	DC_FP_END();
+}
+
+static struct dc_cap_funcs cap_funcs = {
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	struct clk_limit_table *clk_table = &bw_params->clk_table;
+	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
+	unsigned int i, closest_clk_lvl;
+	int j;
+
+	// Default clock levels are used for diags, which may lead to overclocking.
+	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+		int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+
+		dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
+		dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
+		dcn3_1_soc.num_chans = bw_params->num_channels;
+
+		ASSERT(clk_table->num_entries);
+
+		/* Prepass to find max clocks independent of voltage level. */
+		for (i = 0; i < clk_table->num_entries; ++i) {
+			if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
+				max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
+			if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
+				max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
+		}
+
+		for (i = 0; i < clk_table->num_entries; i++) {
+			/* loop backwards*/
+			for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
+				if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
+					closest_clk_lvl = j;
+					break;
+				}
+			}
+
+			clock_limits[i].state = i;
+
+			/* Clocks dependent on voltage level. */
+			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+
+			/* Clocks independent of voltage level. */
+			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+				dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+
+			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+				dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+
+			clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+		}
+		for (i = 0; i < clk_table->num_entries; i++)
+			dcn3_1_soc.clock_limits[i] = clock_limits[i];
+		if (clk_table->num_entries) {
+			dcn3_1_soc.num_states = clk_table->num_entries;
+		}
+	}
+
+	dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+		dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
+	else
+		dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
+}
+
+static struct resource_funcs dcn31_res_pool_funcs = {
+	.destroy = dcn31_destroy_resource_pool,
+	.link_enc_create = dcn31_link_encoder_create,
+	.link_enc_create_minimal = dcn31_link_enc_create_minimal,
+	.link_encs_assign = link_enc_cfg_link_encs_assign,
+	.link_enc_unassign = link_enc_cfg_link_enc_unassign,
+	.panel_cntl_create = dcn31_panel_cntl_create,
+	.validate_bandwidth = dcn30_validate_bandwidth,
+	.calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
+	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
+	.populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
+	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
+	.update_bw_bounding_box = dcn31_update_bw_bounding_box,
+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+};
+
+static struct clock_source *dcn30_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static bool dcn31_resource_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dcn31_resource_pool *pool)
+{
+	int i;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+
+	DC_FP_START();
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_dcn31;
+
+	pool->base.funcs = &dcn31_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
+	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
+	dc->caps.dmdata_alloc_size = 2048;
+
+	dc->caps.max_slave_planes = 1;
+	dc->caps.max_slave_yuv_planes = 1;
+	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+	dc->caps.is_apu = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
+
+	dc->caps.color.dpp.hw_3d_lut = 1;
+	dc->caps.color.dpp.ogam_ram = 1;
+	// no OGAM ROM on DCN301
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+		dc->debug = debug_defaults_diags;
+	} else
+		dc->debug = debug_defaults_diags;
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL0,
+				&clk_src_regs[0], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL1,
+				&clk_src_regs[1], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs[2], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs[3], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL4,
+				&clk_src_regs[4], false);
+
+	pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->base.dp_clock_source =
+			dcn31_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_ID_DP_DTO,
+				&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* TODO: DCCG */
+	pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->base.dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* TODO: IRQ */
+	init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
+	if (!pool->base.irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->base.hubbub = dcn31_hubbub_create(ctx);
+	if (pool->base.hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs and TGs */
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
+		if (pool->base.hubps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
+		if (pool->base.dpps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		pool->base.opps[i] = dcn31_opp_create(ctx, i);
+		if (pool->base.opps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		pool->base.timing_generators[i] = dcn31_timing_generator_create(
+				ctx, i);
+		if (pool->base.timing_generators[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+	}
+	pool->base.timing_generator_count = i;
+
+	/* PSR */
+	pool->base.psr = dmub_psr_create(ctx);
+	if (pool->base.psr == NULL) {
+		dm_error("DC: failed to create psr obj!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* ABM */
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
+				&abm_regs[i],
+				&abm_shift,
+				&abm_mask);
+		if (pool->base.multiple_abms[i] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* MPC and DSC */
+	pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
+	if (pool->base.mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
+		if (pool->base.dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB and MMHUBBUB */
+	if (!dcn31_dwbc_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->base.sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+			&res_create_funcs : &res_create_maximus_funcs)))
+			goto create_fail;
+
+	/* HW Sequencer and Plane caps */
+	dcn31_hw_sequencer_construct(dc);
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	DC_FP_END();
+
+	return true;
+
+create_fail:
+
+	DC_FP_END();
+	dcn31_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn31_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc)
+{
+	struct dcn31_resource_pool *pool =
+		kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
new file mode 100644
index 000000000000..93571c976996
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN31_RESOURCE_H_
+#define _DCN31_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN31_RES_POOL(pool)\
+	container_of(pool, struct dcn31_resource_pool, base)
+
+struct dcn31_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn31_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN31_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
index cac0b2c0d31b..a9170b9f84d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
@@ -32,6 +32,9 @@ struct cp_psp_stream_config {
 	uint8_t otg_inst;
 	uint8_t dig_be;
 	uint8_t dig_fe;
+	uint8_t link_enc_idx;
+	uint8_t stream_enc_idx;
+	uint8_t phy_idx;
 	uint8_t assr_enabled;
 	uint8_t mst_enabled;
 	void *dm_stream_ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 7617fab9e1f9..9ab854293ace 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -34,6 +34,8 @@
 #include "dc.h"
 
 struct dp_mst_stream_allocation_table;
+struct aux_payload;
+enum aux_return_code_type;
 
 /*
  * Allocate memory accessible by the GPU
@@ -158,6 +160,17 @@ void dm_set_dcn_clocks(
 		struct dc_context *ctx,
 		struct dc_clocks *clks);
 
-bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable);
+bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable);
 
+void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us);
+
+// 0x1 = Result_OK, 0xFE = Result_UnkmownCmd
+#define IS_SMU_TIMEOUT(result) \
+	(!(result == 0x1 || result == 0xFE))
+
+int dm_helper_dmub_aux_transfer_sync(
+		struct dc_context *ctx,
+		const struct dc_link *link,
+		struct aux_payload *payload,
+		enum aux_return_code_type *operation_result);
 #endif /* __DM_HELPERS__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index fb41140e8381..4440d08743aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -245,6 +245,8 @@ struct pp_smu_funcs_nv {
 #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
 #define PP_SMU_NUM_FCLK_DPM_LEVELS    4
 #define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
+#define PP_SMU_NUM_DCLK_DPM_LEVELS    8
+#define PP_SMU_NUM_VCLK_DPM_LEVELS    8
 
 struct dpm_clock {
   uint32_t  Freq;    // In MHz
@@ -258,6 +260,8 @@ struct dpm_clocks {
 	struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS];
 	struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS];
 	struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS];
+	struct dpm_clock VClocks[PP_SMU_NUM_VCLK_DPM_LEVELS];
+	struct dpm_clock DClocks[PP_SMU_NUM_DCLK_DPM_LEVELS];
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 6bb7f2905821..d34024fd798a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -62,6 +62,8 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) -Wframe-larger-than=2048
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags)
@@ -72,6 +74,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
 endif
 CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
@@ -86,6 +90,7 @@ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_
 DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
 DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
+DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
 endif
 
 AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 9729cf292e84..d3b5b6fedf04 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2895,7 +2895,7 @@ static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 			RoundedUpMaxSwathSizeBytesC = 0.0;
 
 		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
-				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
+				<= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) {
 			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
 			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
 		} else {
@@ -2904,17 +2904,17 @@ static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 		}
 
 		if (mode_lib->vba.SwathHeightC[k] == 0) {
-			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024;
+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024;
 			mode_lib->vba.DETBufferSizeC[k] = 0;
 		} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
-			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 / 2;
-			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 / 2;
 		} else {
-			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 * 2 / 3;
-			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 / 3;
 		}
 	}
@@ -3819,7 +3819,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		mode_lib->vba.MaximumSwathWidthInDETBuffer =
 				dml_min(
 						mode_lib->vba.MaximumSwathWidthSupport,
-						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
+						mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0
 								/ (locals->BytePerPixelInDETY[k]
 										* locals->MinSwathHeightY[k]
 										+ locals->BytePerPixelInDETC[k]
@@ -4322,7 +4322,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					locals->RoundedUpMaxSwathSizeBytesC = 0;
 				}
 
-				if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte * 1024 / 2) {
+				if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024 / 2) {
 					locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
 					locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
 				} else {
@@ -4331,15 +4331,15 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				}
 
 				if (locals->BytePerPixelInDETC[k] == 0) {
-					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
 					locals->LinesInDETChroma = 0;
 				} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
-					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] /
+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] /
 							locals->SwathWidthYPerState[i][j][k];
-					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
+					locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
 				} else {
-					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
-					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
+					locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
 				}
 
 				locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 51098c2c9854..fbed5304692d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2968,7 +2968,7 @@ static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 			RoundedUpMaxSwathSizeBytesC = 0.0;
 
 		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
-				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
+				<= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) {
 			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
 			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
 		} else {
@@ -2977,17 +2977,17 @@ static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 		}
 
 		if (mode_lib->vba.SwathHeightC[k] == 0) {
-			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024;
+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024;
 			mode_lib->vba.DETBufferSizeC[k] = 0;
 		} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
-			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 / 2;
-			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 / 2;
 		} else {
-			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 * 2 / 3;
-			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
 					* 1024.0 / 3;
 		}
 	}
@@ -3926,7 +3926,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
 		mode_lib->vba.MaximumSwathWidthInDETBuffer =
 				dml_min(
 						mode_lib->vba.MaximumSwathWidthSupport,
-						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
+						mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0
 								/ (locals->BytePerPixelInDETY[k]
 										* locals->MinSwathHeightY[k]
 										+ locals->BytePerPixelInDETC[k]
@@ -4443,7 +4443,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
 					locals->RoundedUpMaxSwathSizeBytesC = 0;
 				}
 
-				if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte * 1024 / 2) {
+				if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024 / 2) {
 					locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
 					locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
 				} else {
@@ -4452,15 +4452,15 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
 				}
 
 				if (locals->BytePerPixelInDETC[k] == 0) {
-					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
 					locals->LinesInDETChroma = 0;
 				} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
-					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] /
+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] /
 							locals->SwathWidthYPerState[i][j][k];
-					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
+					locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
 				} else {
-					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
-					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
+					locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
 				}
 
 				locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 398210d1af34..c26e742e8137 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -148,7 +148,7 @@ static double CalculateDCCConfiguration(
 		bool                 DCCProgrammingAssumesScanDirectionUnknown,
 		unsigned int         ViewportWidth,
 		unsigned int         ViewportHeight,
-		double               DETBufferSize,
+		unsigned int         DETBufferSize,
 		unsigned int         RequestHeight256Byte,
 		unsigned int         SwathHeight,
 		enum dm_swizzle_mode TilingFormat,
@@ -289,7 +289,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 		unsigned int MaxLineBufferLines,
 		unsigned int LineBufferSize,
 		unsigned int DPPOutputBufferPixels,
-		double DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		unsigned int WritebackInterfaceLumaBufferSize,
 		unsigned int WritebackInterfaceChromaBufferSize,
 		double DCFCLK,
@@ -354,11 +354,11 @@ static void CalculateDCFCLKDeepSleep(
 		double DPPCLK[],
 		double *DCFCLKDeepSleep);
 static void CalculateDETBufferSize(
-		double DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		unsigned int SwathHeightY,
 		unsigned int SwathHeightC,
-		double *DETBufferSizeY,
-		double *DETBufferSizeC);
+		unsigned int *DETBufferSizeY,
+		unsigned int *DETBufferSizeC);
 static void CalculateUrgentBurstFactor(
 		unsigned int DETBufferSizeInKByte,
 		unsigned int SwathHeightY,
@@ -1074,7 +1074,7 @@ static double CalculateDCCConfiguration(
 		bool DCCProgrammingAssumesScanDirectionUnknown,
 		unsigned int ViewportWidth,
 		unsigned int ViewportHeight,
-		double DETBufferSize,
+		unsigned int DETBufferSize,
 		unsigned int RequestHeight256Byte,
 		unsigned int SwathHeight,
 		enum dm_swizzle_mode TilingFormat,
@@ -2246,7 +2246,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			}
 
 			CalculateUrgentBurstFactor(
-					mode_lib->vba.DETBufferSizeInKByte,
+					mode_lib->vba.DETBufferSizeInKByte[0],
 					mode_lib->vba.SwathHeightY[k],
 					mode_lib->vba.SwathHeightC[k],
 					locals->SwathWidthY[k],
@@ -2415,7 +2415,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 				mode_lib->vba.MaxLineBufferLines,
 				mode_lib->vba.LineBufferSize,
 				mode_lib->vba.DPPOutputBufferPixels,
-				mode_lib->vba.DETBufferSizeInKByte,
+				mode_lib->vba.DETBufferSizeInKByte[0],
 				mode_lib->vba.WritebackInterfaceLumaBufferSize,
 				mode_lib->vba.WritebackInterfaceChromaBufferSize,
 				mode_lib->vba.DCFCLK,
@@ -2588,7 +2588,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
 			mode_lib->vba.ViewportWidth[k],
 			mode_lib->vba.ViewportHeight[k],
-			mode_lib->vba.DETBufferSizeInKByte * 1024,
+			mode_lib->vba.DETBufferSizeInKByte[0] * 1024,
 			locals->BlockHeight256BytesY[k],
 			mode_lib->vba.SwathHeightY[k],
 			mode_lib->vba.SurfaceTiling[k],
@@ -2689,13 +2689,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 	// Stutter Efficiency
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		CalculateDETBufferSize(
-			mode_lib->vba.DETBufferSizeInKByte,
+			mode_lib->vba.DETBufferSizeInKByte[0],
 			mode_lib->vba.SwathHeightY[k],
 			mode_lib->vba.SwathHeightC[k],
 			&locals->DETBufferSizeY[k],
 			&locals->DETBufferSizeC[k]);
 
-		locals->LinesInDETY[k] = locals->DETBufferSizeY[k]
+		locals->LinesInDETY[k] = (double)locals->DETBufferSizeY[k]
 				/ locals->BytePerPixelDETY[k] / locals->SwathWidthY[k];
 		locals->LinesInDETYRoundedDownToSwath[k] = dml_floor(
 				locals->LinesInDETY[k],
@@ -2984,7 +2984,7 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 			RoundedUpMaxSwathSizeBytesC = 0.0;
 
 		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
-				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
+				<= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) {
 			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
 			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
 		} else {
@@ -2993,7 +2993,7 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 		}
 
 		CalculateDETBufferSize(
-				mode_lib->vba.DETBufferSizeInKByte,
+				mode_lib->vba.DETBufferSizeInKByte[0],
 				mode_lib->vba.SwathHeightY[k],
 				mode_lib->vba.SwathHeightC[k],
 				&mode_lib->vba.DETBufferSizeY[k],
@@ -3888,7 +3888,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		mode_lib->vba.MaximumSwathWidthInDETBuffer =
 				dml_min(
 						mode_lib->vba.MaximumSwathWidthSupport,
-						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
+						mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0
 								/ (locals->BytePerPixelInDETY[k]
 										* locals->MinSwathHeightY[k]
 										+ locals->BytePerPixelInDETC[k]
@@ -4437,7 +4437,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					mode_lib->vba.RoundedUpMaxSwathSizeBytesC = 0.0;
 				}
 				if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY + mode_lib->vba.RoundedUpMaxSwathSizeBytesC
-						<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
+						<= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) {
 					locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k];
 					locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k];
 				} else {
@@ -4801,7 +4801,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					}
 
 					CalculateUrgentBurstFactor(
-							mode_lib->vba.DETBufferSizeInKByte,
+							mode_lib->vba.DETBufferSizeInKByte[0],
 							locals->SwathHeightYThisState[k],
 							locals->SwathHeightCThisState[k],
 							locals->SwathWidthYThisState[k],
@@ -4975,7 +4975,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					mode_lib->vba.MaxLineBufferLines,
 					mode_lib->vba.LineBufferSize,
 					mode_lib->vba.DPPOutputBufferPixels,
-					mode_lib->vba.DETBufferSizeInKByte,
+					mode_lib->vba.DETBufferSizeInKByte[0],
 					mode_lib->vba.WritebackInterfaceLumaBufferSize,
 					mode_lib->vba.WritebackInterfaceChromaBufferSize,
 					mode_lib->vba.DCFCLKPerState[i],
@@ -5230,7 +5230,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 		unsigned int MaxLineBufferLines,
 		unsigned int LineBufferSize,
 		unsigned int DPPOutputBufferPixels,
-		double DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		unsigned int WritebackInterfaceLumaBufferSize,
 		unsigned int WritebackInterfaceChromaBufferSize,
 		double DCFCLK,
@@ -5285,8 +5285,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 	double EffectiveLBLatencyHidingC;
 	double DPPOutputBufferLinesY;
 	double DPPOutputBufferLinesC;
-	double DETBufferSizeY;
-	double DETBufferSizeC;
+	unsigned int DETBufferSizeY;
+	unsigned int DETBufferSizeC;
 	double LinesInDETY[DC__NUM_DPP__MAX];
 	double LinesInDETC;
 	unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
@@ -5382,12 +5382,12 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 				&DETBufferSizeY,
 				&DETBufferSizeC);
 
-		LinesInDETY[k] = DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
+		LinesInDETY[k] = (double)DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
 		LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
 		FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k]
 				* (HTotal[k] / PixelClock[k]) / VRatio[k];
 		if (BytePerPixelDETC[k] > 0) {
-			LinesInDETC = DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0);
+			LinesInDETC = (double)DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0);
 			LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
 			FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath
 					* (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2);
@@ -5574,11 +5574,11 @@ static void CalculateDCFCLKDeepSleep(
 }
 
 static void CalculateDETBufferSize(
-		double DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		unsigned int SwathHeightY,
 		unsigned int SwathHeightC,
-		double *DETBufferSizeY,
-		double *DETBufferSizeC)
+		unsigned int *DETBufferSizeY,
+		unsigned int *DETBufferSizeC)
 {
 	if (SwathHeightC == 0) {
 		*DETBufferSizeY = DETBufferSizeInKByte * 1024;
@@ -5625,8 +5625,8 @@ static void CalculateUrgentBurstFactor(
 	double DETBufferSizeInTimeLumaPre;
 	double DETBufferSizeInTimeChroma;
 	double DETBufferSizeInTimeChromaPre;
-	double DETBufferSizeY;
-	double DETBufferSizeC;
+	unsigned int DETBufferSizeY;
+	unsigned int DETBufferSizeC;
 
 	*NotEnoughUrgentLatencyHiding = 0;
 	*NotEnoughUrgentLatencyHidingPre = 0;
@@ -5663,7 +5663,7 @@ static void CalculateUrgentBurstFactor(
 			&DETBufferSizeY,
 			&DETBufferSizeC);
 
-	LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / SwathWidthY;
+	LinesInDETLuma = (double)DETBufferSizeY / BytePerPixelInDETY / SwathWidthY;
 	DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;
 	if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {
 		*NotEnoughUrgentLatencyHiding = 1;
@@ -5687,7 +5687,7 @@ static void CalculateUrgentBurstFactor(
 	}
 
 	if (BytePerPixelInDETC > 0) {
-		LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / (SwathWidthY / 2);
+		LinesInDETChroma = (double)DETBufferSizeC / BytePerPixelInDETC / (SwathWidthY / 2);
 		DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime
 				/ (VRatio / 2);
 		if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index cb3f70a71b51..9d2016d8fafe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -64,6 +64,7 @@ typedef struct {
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0xffffffff
 #define DCN30_MAX_DSC_IMAGE_WIDTH 5184
+#define DCN30_MAX_FMT_420_BUFFER_WIDTH 4096
 
 static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
 static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -299,7 +300,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 		unsigned int MaxLineBufferLines,
 		unsigned int LineBufferSize,
 		unsigned int DPPOutputBufferPixels,
-		double DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		unsigned int WritebackInterfaceBufferSize,
 		double DCFCLK,
 		double ReturnBW,
@@ -318,8 +319,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 		unsigned int DPPPerPlane[],
 		bool DCCEnable[],
 		double DPPCLK[],
-		double DETBufferSizeY[],
-		double DETBufferSizeC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
 		unsigned int SwathHeightY[],
 		unsigned int SwathHeightC[],
 		unsigned int LBBitPerPixel[],
@@ -570,7 +571,7 @@ static void CalculateStutterEfficiency(
 		double SRExitTime,
 		bool SynchronizedVBlank,
 		int DPPPerPlane[],
-		double DETBufferSizeY[],
+		unsigned int DETBufferSizeY[],
 		int BytePerPixelY[],
 		double BytePerPixelDETY[],
 		double SwathWidthY[],
@@ -603,7 +604,7 @@ static void CalculateStutterEfficiency(
 static void CalculateSwathAndDETConfiguration(
 		bool ForceSingleDPP,
 		int NumberOfActivePlanes,
-		long DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		double MaximumSwathWidthLuma[],
 		double MaximumSwathWidthChroma[],
 		enum scan_direction_class SourceScan[],
@@ -635,8 +636,8 @@ static void CalculateSwathAndDETConfiguration(
 		double SwathWidthChroma[],
 		int SwathHeightY[],
 		int SwathHeightC[],
-		double DETBufferSizeY[],
-		double DETBufferSizeC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
 		bool ViewportSizeSupportPerPlane[],
 		bool *ViewportSizeSupport);
 static void CalculateSwathWidth(
@@ -2052,7 +2053,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			v->DISPCLKWithoutRamping,
 			v->DISPCLKDPPCLKVCOSpeed);
 	v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
-			v->soc.clock_limits[mode_lib->soc.num_states].dispclk_mhz,
+			v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz,
 			v->DISPCLKDPPCLKVCOSpeed);
 	if (v->DISPCLKWithoutRampingRoundedToDFSGranularity
 			> v->MaxDispclkRoundedToDFSGranularity) {
@@ -2613,7 +2614,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			CalculateUrgentBurstFactor(
 					v->swath_width_luma_ub[k],
 					v->swath_width_chroma_ub[k],
-					v->DETBufferSizeInKByte,
+					v->DETBufferSizeInKByte[0],
 					v->SwathHeightY[k],
 					v->SwathHeightC[k],
 					v->HTotal[k] / v->PixelClock[k],
@@ -2635,7 +2636,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			CalculateUrgentBurstFactor(
 					v->swath_width_luma_ub[k],
 					v->swath_width_chroma_ub[k],
-					v->DETBufferSizeInKByte,
+					v->DETBufferSizeInKByte[0],
 					v->SwathHeightY[k],
 					v->SwathHeightC[k],
 					v->HTotal[k] / v->PixelClock[k],
@@ -2808,7 +2809,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			v->MaxLineBufferLines,
 			v->LineBufferSize,
 			v->DPPOutputBufferPixels,
-			v->DETBufferSizeInKByte,
+			v->DETBufferSizeInKByte[0],
 			v->WritebackInterfaceBufferSize,
 			v->DCFCLK,
 			v->ReturnBW,
@@ -3027,7 +3028,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 				v->SurfaceWidthC[k],
 				v->SurfaceHeightY[k],
 				v->SurfaceHeightC[k],
-				v->DETBufferSizeInKByte * 1024,
+				v->DETBufferSizeInKByte[0] * 1024,
 				v->BlockHeight256BytesY[k],
 				v->BlockHeight256BytesC[k],
 				v->SurfaceTiling[k],
@@ -3177,7 +3178,7 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 	CalculateSwathAndDETConfiguration(
 			false,
 			mode_lib->vba.NumberOfActivePlanes,
-			mode_lib->vba.DETBufferSizeInKByte,
+			mode_lib->vba.DETBufferSizeInKByte[0],
 			dummy1,
 			dummy2,
 			mode_lib->vba.SourceScan,
@@ -3911,7 +3912,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	CalculateSwathAndDETConfiguration(
 			true,
 			v->NumberOfActivePlanes,
-			v->DETBufferSizeInKByte,
+			v->DETBufferSizeInKByte[0],
 			v->MaximumSwathWidthLuma,
 			v->MaximumSwathWidthChroma,
 			v->SourceScan,
@@ -3957,20 +3958,20 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
 				v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
 						* (1.0 + v->DISPCLKRampingMargin / 100.0);
-				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]
-						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {
+				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
 					v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 				}
 				v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
 						* (1 + v->DISPCLKRampingMargin / 100.0);
-				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]
-						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {
+				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
 					v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 				}
 				v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
 						* (1 + v->DISPCLKRampingMargin / 100.0);
-				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]
-						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {
+				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
 					v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 				}
 
@@ -3987,19 +3988,30 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
 					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
 					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
-				} else if (v->DSCEnabled[k] && (v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH)) {
-					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
-					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
 				} else {
 					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
 					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
-					/*420 format workaround*/
-					if (v->HActive[k] > 4096 && v->OutputFormat[k] == dm_420) {
+				}
+				if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+					}
+				}
+				if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
 						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
 						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
 					}
 				}
-
 				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
 					v->MPCCombine[i][j][k] = false;
 					v->NoOfDPP[i][j][k] = 4;
@@ -4281,42 +4293,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		}
 	}
 
-	for (i = 0; i < v->soc.num_states; i++) {
-		v->DSCCLKRequiredMoreThanSupported[i] = false;
-		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-			if (v->BlendingAndTiming[k] == k) {
-				if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
-					if (v->OutputFormat[k] == dm_420) {
-						v->DSCFormatFactor = 2;
-					} else if (v->OutputFormat[k] == dm_444) {
-						v->DSCFormatFactor = 1;
-					} else if (v->OutputFormat[k] == dm_n422) {
-						v->DSCFormatFactor = 2;
-					} else {
-						v->DSCFormatFactor = 1;
-					}
-					if (v->RequiresDSC[i][k] == true) {
-						if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
-							if (v->PixelClockBackEnd[k] / 12.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
-							if (v->PixelClockBackEnd[k] / 6.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						} else {
-							if (v->PixelClockBackEnd[k] / 3.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						}
-					}
-				}
-			}
-		}
-	}
+	/* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */
+
 	for (i = 0; i < v->soc.num_states; i++) {
 		v->NotEnoughDSCUnits[i] = false;
 		v->TotalDSCUnitsRequired = 0.0;
@@ -4399,7 +4377,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			CalculateSwathAndDETConfiguration(
 					false,
 					v->NumberOfActivePlanes,
-					v->DETBufferSizeInKByte,
+					v->DETBufferSizeInKByte[0],
 					v->MaximumSwathWidthLuma,
 					v->MaximumSwathWidthChroma,
 					v->SourceScan,
@@ -4622,7 +4600,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				CalculateUrgentBurstFactor(
 						v->swath_width_luma_ub_this_state[k],
 						v->swath_width_chroma_ub_this_state[k],
-						v->DETBufferSizeInKByte,
+						v->DETBufferSizeInKByte[0],
 						v->SwathHeightYThisState[k],
 						v->SwathHeightCThisState[k],
 						v->HTotal[k] / v->PixelClock[k],
@@ -5025,7 +5003,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					CalculateUrgentBurstFactor(
 							v->swath_width_luma_ub_this_state[k],
 							v->swath_width_chroma_ub_this_state[k],
-							v->DETBufferSizeInKByte,
+							v->DETBufferSizeInKByte[0],
 							v->SwathHeightYThisState[k],
 							v->SwathHeightCThisState[k],
 							v->HTotal[k] / v->PixelClock[k],
@@ -5197,7 +5175,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 					v->MaxLineBufferLines,
 					v->LineBufferSize,
 					v->DPPOutputBufferPixels,
-					v->DETBufferSizeInKByte,
+					v->DETBufferSizeInKByte[0],
 					v->WritebackInterfaceBufferSize,
 					v->DCFCLKState[i][j],
 					v->ReturnBWPerState[i][j],
@@ -5319,7 +5297,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		for (j = 0; j < 2; j++) {
 			if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
 					&& v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
-					&& v->NotEnoughDSCUnits[i] == 0 && v->DSCCLKRequiredMoreThanSupported[i] == 0
+					&& v->NotEnoughDSCUnits[i] == 0
 					&& v->DTBCLKRequiredMoreThanSupported[i] == 0
 					&& v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1
 					&& EnoughWritebackUnits == 1 && WritebackModeSupport == 1
@@ -5369,7 +5347,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 		unsigned int MaxLineBufferLines,
 		unsigned int LineBufferSize,
 		unsigned int DPPOutputBufferPixels,
-		double DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		unsigned int WritebackInterfaceBufferSize,
 		double DCFCLK,
 		double ReturnBW,
@@ -5388,8 +5366,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 		unsigned int DPPPerPlane[],
 		bool DCCEnable[],
 		double DPPCLK[],
-		double DETBufferSizeY[],
-		double DETBufferSizeC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
 		unsigned int SwathHeightY[],
 		unsigned int SwathHeightC[],
 		unsigned int LBBitPerPixel[],
@@ -6126,7 +6104,7 @@ static void CalculateStutterEfficiency(
 		double SRExitTime,
 		bool SynchronizedVBlank,
 		int DPPPerPlane[],
-		double DETBufferSizeY[],
+		unsigned int DETBufferSizeY[],
 		int BytePerPixelY[],
 		double BytePerPixelDETY[],
 		double SwathWidthY[],
@@ -6273,7 +6251,7 @@ static void CalculateStutterEfficiency(
 static void CalculateSwathAndDETConfiguration(
 		bool ForceSingleDPP,
 		int NumberOfActivePlanes,
-		long DETBufferSizeInKByte,
+		unsigned int DETBufferSizeInKByte,
 		double MaximumSwathWidthLuma[],
 		double MaximumSwathWidthChroma[],
 		enum scan_direction_class SourceScan[],
@@ -6305,8 +6283,8 @@ static void CalculateSwathAndDETConfiguration(
 		double SwathWidthChroma[],
 		int SwathHeightY[],
 		int SwathHeightC[],
-		double DETBufferSizeY[],
-		double DETBufferSizeC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
 		bool ViewportSizeSupportPerPlane[],
 		bool *ViewportSizeSupport)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
new file mode 100644
index 000000000000..a9667068c690
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -0,0 +1,7510 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dc.h"
+#include "dc_link.h"
+#include "../display_mode_lib.h"
+#include "display_mode_vba_31.h"
+#include "../dml_inline_defs.h"
+
+/*
+ * NOTE:
+ *   This file is gcc-parsable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0xffffffff
+#define DCN31_MAX_DSC_IMAGE_WIDTH 5184
+#define DCN31_MAX_FMT_420_BUFFER_WIDTH 4096
+
+// For DML-C changes that hasn't been propagated to VBA yet
+//#define __DML_VBA_ALLOW_DELTA__
+
+// Move these to ip paramaters/constant
+
+// At which vstartup the DML start to try if the mode can be supported
+#define __DML_VBA_MIN_VSTARTUP__    9
+
+// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
+#define __DML_ARB_TO_RET_DELAY__    (7 + 95)
+
+// fudge factor for min dcfclk calclation
+#define __DML_MIN_DCFCLK_FACTOR__   1.15
+
+typedef struct {
+	double DPPCLK;
+	double DISPCLK;
+	double PixelClock;
+	double DCFCLKDeepSleep;
+	unsigned int DPPPerPlane;
+	bool ScalerEnabled;
+	enum scan_direction_class SourceScan;
+	unsigned int BlockWidth256BytesY;
+	unsigned int BlockHeight256BytesY;
+	unsigned int BlockWidth256BytesC;
+	unsigned int BlockHeight256BytesC;
+	unsigned int InterlaceEnable;
+	unsigned int NumberOfCursors;
+	unsigned int VBlank;
+	unsigned int HTotal;
+	unsigned int DCCEnable;
+	bool ODMCombineIsEnabled;
+	enum source_format_class SourcePixelFormat;
+	int BytePerPixelY;
+	int BytePerPixelC;
+	bool ProgressiveToInterlaceUnitInOPP;
+} Pipe;
+
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0xffffffff
+
+static bool CalculateBytePerPixelAnd256BBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double *BytePerPixelDETY,
+		double *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC);
+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib);
+static unsigned int dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output);
+static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output);
+static bool CalculatePrefetchSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		Pipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		double VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		double VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		double *DSTXAfterScaler,
+		double *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix);
+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
+static void CalculateDCCConfiguration(
+		bool DCCEnabled,
+		bool DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceWidthLuma,
+		unsigned int SurfaceWidthChroma,
+		unsigned int SurfaceHeightLuma,
+		unsigned int SurfaceHeightChroma,
+		double DETBufferSize,
+		unsigned int RequestHeight256ByteLuma,
+		unsigned int RequestHeight256ByteChroma,
+		enum dm_swizzle_mode TilingFormat,
+		unsigned int BytePerPixelY,
+		unsigned int BytePerPixelC,
+		double BytePerPixelDETY,
+		double BytePerPixelDETC,
+		enum scan_direction_class ScanOrientation,
+		unsigned int *MaxUncompressedBlockLuma,
+		unsigned int *MaxUncompressedBlockChroma,
+		unsigned int *MaxCompressedBlockLuma,
+		unsigned int *MaxCompressedBlockChroma,
+		unsigned int *IndependentBlockLuma,
+		unsigned int *IndependentBlockChroma);
+static double CalculatePrefetchSourceLines(
+		struct display_mode_lib *mode_lib,
+		double VRatio,
+		double vtaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		unsigned int ViewportYStart,
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath);
+static unsigned int CalculateVMAndRowBytes(
+		struct display_mode_lib *mode_lib,
+		bool DCCEnable,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum scan_direction_class ScanDirection,
+		unsigned int SwathWidth,
+		unsigned int ViewportHeight,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMinPageSize,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int *MacroTileWidth,
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		bool *PTEBufferSizeNotExceeded,
+		int *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		int *vm_group_bytes,
+		unsigned int *dpte_group_bytes,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		int *DPDE0BytesFrame,
+		int *MetaPTEBytesFrame);
+static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime);
+static void CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		double *meta_row_bw,
+		double *dpte_row_bw);
+
+static void CalculateFlipSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe);
+static double CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		int WritebackDestinationWidth,
+		int WritebackDestinationHeight,
+		int WritebackSourceHeight,
+		unsigned int HTotal);
+
+static void CalculateVupdateAndDynamicMetadataParameters(
+		int MaxInterDCNTileRepeaters,
+		double DPPCLK,
+		double DISPCLK,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		int HTotal,
+		int VBlank,
+		int DynamicMetadataTransmittedBytes,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix);
+
+static void CalculateWatermarksAndDRAMSpeedChangeSupport(
+		struct display_mode_lib *mode_lib,
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActivePlanes,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizedVBlank,
+		unsigned int dpte_group_bytes[],
+		unsigned int MetaChunkSize,
+		double UrgentLatency,
+		double ExtraLatency,
+		double WritebackLatency,
+		double WritebackChunkSize,
+		double SOCCLK,
+		double DRAMClockChangeLatency,
+		double SRExitTime,
+		double SREnterPlusExitTime,
+		double SRExitZ8Time,
+		double SREnterPlusExitZ8Time,
+		double DCFCLKDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int vtaps[],
+		unsigned int VTAPsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerPlane[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		int unsigned CompressedBufferSizeInkByte,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double *UrgentWatermark,
+		double *WritebackUrgentWatermark,
+		double *DRAMClockChangeWatermark,
+		double *WritebackDRAMClockChangeWatermark,
+		double *StutterExitWatermark,
+		double *StutterEnterPlusExitWatermark,
+		double *Z8StutterExitWatermark,
+		double *Z8StutterEnterPlusExitWatermark,
+		double *MinActiveDRAMClockChangeLatencySupported);
+
+static void CalculateDCFCLKDeepSleep(
+		struct display_mode_lib *mode_lib,
+		unsigned int NumberOfActivePlanes,
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		int ReturnBusWidth,
+		double *DCFCLKDeepSleep);
+
+static void CalculateUrgentBurstFactor(
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double LineTime,
+		double UrgentLatency,
+		double CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double VRatio,
+		double VRatioC,
+		double BytePerPixelInDETY,
+		double BytePerPixelInDETC,
+		double DETBufferSizeY,
+		double DETBufferSizeC,
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool *NotEnoughUrgentLatencyHiding);
+
+static void UseMinimumDCFCLK(
+		struct display_mode_lib *mode_lib,
+		int MaxInterDCNTileRepeaters,
+		int MaxPrefetchMode,
+		double FinalDRAMClockChangeLatency,
+		double SREnterPlusExitTime,
+		int ReturnBusWidth,
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		int PixelChunkSizeInKByte,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		enum immediate_flip_requirement ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+		int VTotal[],
+		int VActive[],
+		int DynamicMetadataTransmittedBytes[],
+		int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFCLKDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		double TotalVActivePixelBandwidth[][2],
+		double TotalVActiveCursorBandwidth[][2],
+		double TotalMetaRowBandwidth[][2],
+		double TotalDPTERowBandwidth[][2],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX],
+		double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		double DCFCLKState[][2]);
+
+static void CalculatePixelDeliveryTimes(
+		unsigned int NumberOfActivePlanes,
+		double VRatio[],
+		double VRatioChroma[],
+		double VRatioPrefetchY[],
+		double VRatioPrefetchC[],
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		unsigned int NumberOfCursors[],
+		unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int BlockWidth256BytesY[],
+		unsigned int BlockHeight256BytesY[],
+		unsigned int BlockWidth256BytesC[],
+		unsigned int BlockHeight256BytesC[],
+		double DisplayPipeLineDeliveryTimeLuma[],
+		double DisplayPipeLineDeliveryTimeChroma[],
+		double DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeLuma[],
+		double DisplayPipeRequestDeliveryTimeChroma[],
+		double DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double CursorRequestDeliveryTime[],
+		double CursorRequestDeliveryTimePrefetch[]);
+
+static void CalculateMetaAndPTETimes(
+		int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		int MetaChunkSize,
+		int MinMetaChunkSizeBytes,
+		int HTotal[],
+		double VRatio[],
+		double VRatioChroma[],
+		double DestinationLinesToRequestRowInVBlank[],
+		double DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		int dpte_row_height[],
+		int dpte_row_height_chroma[],
+		int meta_row_width[],
+		int meta_row_width_chroma[],
+		int meta_row_height[],
+		int meta_row_height_chroma[],
+		int meta_req_width[],
+		int meta_req_width_chroma[],
+		int meta_req_height[],
+		int meta_req_height_chroma[],
+		int dpte_group_bytes[],
+		int PTERequestSizeY[],
+		int PTERequestSizeC[],
+		int PixelPTEReqWidthY[],
+		int PixelPTEReqHeightY[],
+		int PixelPTEReqWidthC[],
+		int PixelPTEReqHeightC[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[]);
+
+static void CalculateVMGroupAndRequestTimes(
+		unsigned int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int HTotal[],
+		int BytePerPixelC[],
+		double DestinationLinesToRequestVMInVBlank[],
+		double DestinationLinesToRequestVMInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		int vm_group_bytes[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		int meta_pte_bytes_per_frame_ub_l[],
+		int meta_pte_bytes_per_frame_ub_c[],
+		double TimePerVMGroupVBlank[],
+		double TimePerVMGroupFlip[],
+		double TimePerVMRequestVBlank[],
+		double TimePerVMRequestFlip[]);
+
+static void CalculateStutterEfficiency(
+		struct display_mode_lib *mode_lib,
+		int CompressedBufferSizeInkByte,
+		bool UnboundedRequestEnabled,
+		int ConfigReturnBufferSizeInKByte,
+		int MetaFIFOSizeInKEntries,
+		int ZeroSizeBufferEntries,
+		int NumberOfActivePlanes,
+		int ROBBufferSizeInKByte,
+		double TotalDataReadBandwidth,
+		double DCFCLK,
+		double ReturnBW,
+		double COMPBUF_RESERVED_SPACE_64B,
+		double COMPBUF_RESERVED_SPACE_ZS,
+		double SRExitTime,
+		double SRExitZ8Time,
+		bool SynchronizedVBlank,
+		double Z8StutterEnterPlusExitWatermark,
+		double StutterEnterPlusExitWatermark,
+		bool ProgressiveToInterlaceUnitInOPP,
+		bool Interlace[],
+		double MinTTUVBlank[],
+		int DPPPerPlane[],
+		unsigned int DETBufferSizeY[],
+		int BytePerPixelY[],
+		double BytePerPixelDETY[],
+		double SwathWidthY[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		double NetDCCRateLuma[],
+		double NetDCCRateChroma[],
+		double DCCFractionOfZeroSizeRequestsLuma[],
+		double DCCFractionOfZeroSizeRequestsChroma[],
+		int HTotal[],
+		int VTotal[],
+		double PixelClock[],
+		double VRatio[],
+		enum scan_direction_class SourceScan[],
+		int BlockHeight256BytesY[],
+		int BlockWidth256BytesY[],
+		int BlockHeight256BytesC[],
+		int BlockWidth256BytesC[],
+		int DCCYMaxUncompressedBlock[],
+		int DCCCMaxUncompressedBlock[],
+		int VActive[],
+		bool DCCEnable[],
+		bool WritebackEnable[],
+		double ReadBandwidthPlaneLuma[],
+		double ReadBandwidthPlaneChroma[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double *StutterEfficiencyNotIncludingVBlank,
+		double *StutterEfficiency,
+		int *NumberOfStutterBurstsPerFrame,
+		double *Z8StutterEfficiencyNotIncludingVBlank,
+		double *Z8StutterEfficiency,
+		int *Z8NumberOfStutterBurstsPerFrame,
+		double *StutterPeriod);
+
+static void CalculateSwathAndDETConfiguration(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		unsigned int DETBufferSizeInKByte,
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum scan_direction_class SourceScan[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BlendingAndTiming[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		int DPPPerPlane[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool ViewportSizeSupportPerPlane[],
+		bool *ViewportSizeSupport);
+static void CalculateSwathWidth(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		enum source_format_class SourcePixelFormat[],
+		enum scan_direction_class SourceScan[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		int BlendingAndTiming[],
+		int HActive[],
+		double HRatio[],
+		int DPPPerPlane[],
+		double SwathWidthSingleDPPY[],
+		double SwathWidthSingleDPPC[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		int MaximumSwathHeightY[],
+		int MaximumSwathHeightC[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[]);
+
+static double CalculateExtraLatency(
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		double DCFCLK,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels);
+
+static double CalculateExtraLatencyBytes(
+		int ReorderingBytes,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels);
+
+static double CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClockSingle);
+
+static void CalculateUnboundedRequestAndCompressedBufferSize(
+		unsigned int DETBufferSizeInKByte,
+		int ConfigReturnBufferSizeInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		int TotalActiveDPP,
+		bool NoChromaPlanes,
+		int MaxNumDPP,
+		int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class *Output,
+		bool *UnboundedRequestEnabled,
+		int *CompressedBufferSizeInkByte);
+
+static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
+
+void dml31_recalculate(struct display_mode_lib *mode_lib)
+{
+	ModeSupportAndSystemConfiguration(mode_lib);
+	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
+	DisplayPipeConfiguration(mode_lib);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Calling DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation\n", __func__);
+#endif
+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
+}
+
+static unsigned int dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output)
+{
+	// valid bpc         = source bits per component in the set of {8, 10, 12}
+	// valid bpp         = increments of 1/16 of a bit
+	//                    min = 6/7/8 in N420/N422/444, respectively
+	//                    max = such that compression is 1:1
+	//valid sliceWidth  = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
+	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
+
+	// fixed value
+	unsigned int rcModelSize = 8192;
+
+	// N422/N420 operate at 2 pixels per clock
+	unsigned int pixelsPerClock = 0, lstall, D, initalXmitDelay, w, s, ix, wx, P, l0, a, ax, L, Delay, pixels;
+
+	if (pixelFormat == dm_420)
+		pixelsPerClock = 2;
+	else if (pixelFormat == dm_444)
+		pixelsPerClock = 1;
+	else if (pixelFormat == dm_n422)
+		pixelsPerClock = 2;
+	// #all other modes operate at 1 pixel per clock
+	else
+		pixelsPerClock = 1;
+
+	//initial transmit delay as per PPS
+	initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock);
+
+	//compute ssm delay
+	if (bpc == 8)
+		D = 81;
+	else if (bpc == 10)
+		D = 89;
+	else
+		D = 113;
+
+	//divide by pixel per cycle to compute slice width as seen by DSC
+	w = sliceWidth / pixelsPerClock;
+
+	//422 mode has an additional cycle of delay
+	if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
+		s = 0;
+	else
+		s = 1;
+
+	//main calculation for the dscce
+	ix = initalXmitDelay + 45;
+	wx = (w + 2) / 3;
+	P = 3 * wx - w;
+	l0 = ix / w;
+	a = ix + P * l0;
+	ax = (a + 2) / 3 + D + 6 + 1;
+	L = (ax + wx - 1) / wx;
+	if ((ix % w) == 0 && P != 0)
+		lstall = 1;
+	else
+		lstall = 0;
+	Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22;
+
+	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
+	pixels = Delay * 3 * pixelsPerClock;
+	return pixels;
+}
+
+static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output)
+{
+	unsigned int Delay = 0;
+
+	if (pixelFormat == dm_420) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 2;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 13;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 3;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else if (pixelFormat == dm_n422) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 1;
+		//   dscc - input deserializer
+		Delay = Delay + 5;
+		//  dscc - input cdc fifo
+		Delay = Delay + 25;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 10;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   sft
+		Delay = Delay + 1;
+	}
+
+	return Delay;
+}
+
+static bool CalculatePrefetchSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		Pipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		double VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		double VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		double *DSTXAfterScaler,
+		double *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix)
+{
+	bool MyError = false;
+	unsigned int DPPCycles, DISPCLKCycles;
+	double DSTTotalPixelsAfterScaler;
+	double LineTime;
+	double dst_y_prefetch_equ;
+	double Tsw_oto;
+	double prefetch_bw_oto;
+	double Tvm_oto;
+	double Tr0_oto;
+	double Tvm_oto_lines;
+	double Tr0_oto_lines;
+	double dst_y_prefetch_oto;
+	double TimeForFetchingMetaPTE = 0;
+	double TimeForFetchingRowInVBlank = 0;
+	double LinesToRequestPrefetchPixelData = 0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double trip_to_mem;
+	double Tvm_trips;
+	double Tr0_trips;
+	double Tvm_trips_rounded;
+	double Tr0_trips_rounded;
+	double Lsw_oto;
+	double Tpre_rounded;
+	double prefetch_bw_equ;
+	double Tvm_equ;
+	double Tr0_equ;
+	double Tdmbf;
+	double Tdmec;
+	double Tdmsks;
+	double prefetch_sw_bytes;
+	double bytes_pp;
+	double dep_bytes;
+	int max_vratio_pre = 4;
+	double min_Lsw;
+	double Tsw_est1 = 0;
+	double Tsw_est3 = 0;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	} else {
+		HostVMDynamicLevelsTrips = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMEnable=%d HostVMEnable=%d HostVMInefficiencyFactor=%f\n", __func__, GPUVMEnable, HostVMEnable, HostVMInefficiencyFactor);
+#endif
+	CalculateVupdateAndDynamicMetadataParameters(
+			MaxInterDCNTileRepeaters,
+			myPipe->DPPCLK,
+			myPipe->DISPCLK,
+			myPipe->DCFCLKDeepSleep,
+			myPipe->PixelClock,
+			myPipe->HTotal,
+			myPipe->VBlank,
+			DynamicMetadataTransmittedBytes,
+			DynamicMetadataLinesBeforeActiveRequired,
+			myPipe->InterlaceEnable,
+			myPipe->ProgressiveToInterlaceUnitInOPP,
+			TSetup,
+			&Tdmbf,
+			&Tdmec,
+			&Tdmsks,
+			VUpdateOffsetPix,
+			VUpdateWidthPix,
+			VReadyOffsetPix);
+
+	LineTime = myPipe->HTotal / myPipe->PixelClock;
+	trip_to_mem = UrgentLatency;
+	Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (DynamicMetadataVMEnabled == true && GPUVMEnable == true) {
+#else
+	if (DynamicMetadataVMEnabled == true) {
+#endif
+		*Tdmdl = TWait + Tvm_trips + trip_to_mem;
+	} else {
+		*Tdmdl = TWait + UrgentExtraLatency;
+	}
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (DynamicMetadataEnable == false) {
+		*Tdmdl = 0.0;
+	}
+#endif
+
+	if (DynamicMetadataEnable == true) {
+		if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) {
+			*NotEnoughTimeForDynamicMetadata = true;
+			dml_print("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__);
+			dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, Tdmbf);
+			dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec);
+			dml_print("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", __func__, Tdmsks);
+			dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", __func__, *Tdmdl);
+		} else {
+			*NotEnoughTimeForDynamicMetadata = false;
+		}
+	} else {
+		*NotEnoughTimeForDynamicMetadata = false;
+	}
+
+	*Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0);
+
+	if (myPipe->ScalerEnabled)
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL;
+	else
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly;
+
+	DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
+
+	DISPCLKCycles = DISPCLKDelaySubtotal;
+
+	if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
+		return true;
+
+	*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DPPCycles: %d\n", __func__, DPPCycles);
+	dml_print("DML::%s: PixelClock: %f\n", __func__, myPipe->PixelClock);
+	dml_print("DML::%s: DPPCLK: %f\n", __func__, myPipe->DPPCLK);
+	dml_print("DML::%s: DISPCLKCycles: %d\n", __func__, DISPCLKCycles);
+	dml_print("DML::%s: DISPCLK: %f\n", __func__, myPipe->DISPCLK);
+	dml_print("DML::%s: DSCDelay: %d\n", __func__, DSCDelay);
+	dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__, *DSTXAfterScaler);
+	dml_print("DML::%s: ODMCombineIsEnabled: %d\n", __func__, myPipe->ODMCombineIsEnabled);
+#endif
+
+	*DSTXAfterScaler = *DSTXAfterScaler + ((myPipe->ODMCombineIsEnabled) ? 18 : 0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
+
+	if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
+		*DSTYAfterScaler = 1;
+	else
+		*DSTYAfterScaler = 0;
+
+	DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler;
+	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
+	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal));
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DSTXAfterScaler: %d (final)\n", __func__, *DSTXAfterScaler);
+#endif
+
+	MyError = false;
+
+	Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1);
+	Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
+	Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (!myPipe->DCCEnable) {
+		Tr0_trips = 0.0;
+		Tr0_trips_rounded = 0.0;
+	}
+#endif
+
+	if (!GPUVMEnable) {
+		Tvm_trips = 0.0;
+		Tvm_trips_rounded = 0.0;
+	}
+
+	if (GPUVMEnable) {
+		if (GPUVMPageTableLevels >= 3) {
+			*Tno_bw = UrgentExtraLatency + trip_to_mem * ((GPUVMPageTableLevels - 2) - 1);
+		} else {
+			*Tno_bw = 0;
+		}
+	} else if (!myPipe->DCCEnable) {
+		*Tno_bw = LineTime;
+	} else {
+		*Tno_bw = LineTime / 4;
+	}
+
+	if (myPipe->SourcePixelFormat == dm_420_8 || myPipe->SourcePixelFormat == dm_420_10 || myPipe->SourcePixelFormat == dm_420_12)
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC / 4;
+	else
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC;
+
+	prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC;
+	prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerPlane, prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
+
+	min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre;
+	Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
+	Tsw_oto = Lsw_oto * LineTime;
+
+	prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC) / Tsw_oto;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML: HTotal: %d\n", myPipe->HTotal);
+	dml_print("DML: prefetch_bw_oto: %f\n", prefetch_bw_oto);
+	dml_print("DML: PrefetchSourceLinesY: %f\n", PrefetchSourceLinesY);
+	dml_print("DML: swath_width_luma_ub: %d\n", swath_width_luma_ub);
+	dml_print("DML: BytePerPixelY: %d\n", myPipe->BytePerPixelY);
+	dml_print("DML: Tsw_oto: %f\n", Tsw_oto);
+#endif
+
+	if (GPUVMEnable == true)
+		Tvm_oto = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, Tvm_trips, LineTime / 4.0);
+	else
+		Tvm_oto = LineTime / 4.0;
+
+	if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+		Tr0_oto = dml_max4((MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, Tr0_trips, // PREVIOUS_ERROR (missing this term)
+				LineTime - Tvm_oto,
+				LineTime / 4);
+	} else {
+		Tr0_oto = (LineTime - Tvm_oto) / 2.0;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Tvm_trips = %f\n", __func__, Tvm_trips);
+	dml_print("DML::%s: Tr0_trips = %f\n", __func__, Tr0_trips);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, MetaRowByte);
+	dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+	dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+	dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+	dml_print("DML::%s: prefetch_bw_oto = %f\n", __func__, prefetch_bw_oto);
+	dml_print("DML::%s: Tr0_oto = %f\n", __func__, Tr0_oto);
+	dml_print("DML::%s: Tvm_oto = %f\n", __func__, Tvm_oto);
+#endif
+
+	Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
+	Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
+	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto;
+	dst_y_prefetch_equ =  VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal);
+	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
+	Tpre_rounded = dst_y_prefetch_equ * LineTime;
+
+	dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor, MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor);
+
+	if (prefetch_sw_bytes < dep_bytes)
+		prefetch_sw_bytes = 2 * dep_bytes;
+
+	dml_print("DML: dst_y_prefetch_oto: %f\n", dst_y_prefetch_oto);
+	dml_print("DML: Tvm_oto_lines: %f\n", Tvm_oto_lines);
+	dml_print("DML: Tr0_oto_lines: %f\n", Tr0_oto_lines);
+	dml_print("DML: Lsw_oto: %f\n", Lsw_oto);
+	dml_print("DML: LineTime: %f\n", LineTime);
+	dml_print("DML: dst_y_prefetch_equ: %f (after round)\n", dst_y_prefetch_equ);
+
+	dml_print("DML: LineTime: %f\n", LineTime);
+	dml_print("DML: VStartup: %d\n", VStartup);
+	dml_print("DML: Tvstartup: %fus - time between vstartup and first pixel of active\n", VStartup * LineTime);
+	dml_print("DML: TSetup: %fus - time from vstartup to vready\n", *TSetup);
+	dml_print("DML: TCalc: %fus - time for calculations in dchub starting at vready\n", TCalc);
+	dml_print("DML: TWait: %fus - time for fabric to become ready max(pstate exit,cstate enter/exit, urgent latency) after TCalc\n", TWait);
+	dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf);
+	dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec);
+	dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks);
+	dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", *Tdmdl_vm);
+	dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", *Tdmdl);
+	dml_print("DML: DSTXAfterScaler: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", *DSTXAfterScaler);
+	dml_print("DML: DSTYAfterScaler: %f lines - number of lines of pipeline and buffer delay after scaler \n", *DSTYAfterScaler);
+
+	*PrefetchBandwidth = 0;
+	*DestinationLinesToRequestVMInVBlank = 0;
+	*DestinationLinesToRequestRowInVBlank = 0;
+	*VRatioPrefetchY = 0;
+	*VRatioPrefetchC = 0;
+	*RequiredPrefetchPixDataBWLuma = 0;
+	if (dst_y_prefetch_equ > 1) {
+		double PrefetchBandwidth1;
+		double PrefetchBandwidth2;
+		double PrefetchBandwidth3;
+		double PrefetchBandwidth4;
+
+		if (Tpre_rounded - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw);
+			Tsw_est1 = prefetch_sw_bytes / PrefetchBandwidth1;
+		} else {
+			PrefetchBandwidth1 = 0;
+		}
+
+		if (VStartup == MaxVStartup && Tsw_est1 / LineTime < min_Lsw && Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw);
+		}
+
+		if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0)
+			PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded);
+		else
+			PrefetchBandwidth2 = 0;
+
+		if (Tpre_rounded - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - Tvm_trips_rounded);
+			Tsw_est3 = prefetch_sw_bytes / PrefetchBandwidth3;
+		} else {
+			PrefetchBandwidth3 = 0;
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Tpre_rounded: %f\n", __func__, Tpre_rounded);
+		dml_print("DML::%s: Tvm_trips_rounded: %f\n", __func__, Tvm_trips_rounded);
+		dml_print("DML::%s: PrefetchBandwidth3: %f\n", __func__, PrefetchBandwidth3);
+#endif
+		if (VStartup == MaxVStartup && Tsw_est3 / LineTime < min_Lsw && Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded);
+		}
+
+		if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0)
+			PrefetchBandwidth4 = prefetch_sw_bytes / (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded);
+		else
+			PrefetchBandwidth4 = 0;
+
+		{
+			bool Case1OK;
+			bool Case2OK;
+			bool Case3OK;
+
+			if (PrefetchBandwidth1 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 >= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= Tr0_trips_rounded) {
+					Case1OK = true;
+				} else {
+					Case1OK = false;
+				}
+			} else {
+				Case1OK = false;
+			}
+
+			if (PrefetchBandwidth2 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 >= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < Tr0_trips_rounded) {
+					Case2OK = true;
+				} else {
+					Case2OK = false;
+				}
+			} else {
+				Case2OK = false;
+			}
+
+			if (PrefetchBandwidth3 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 < Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= Tr0_trips_rounded) {
+					Case3OK = true;
+				} else {
+					Case3OK = false;
+				}
+			} else {
+				Case3OK = false;
+			}
+
+			if (Case1OK) {
+				prefetch_bw_equ = PrefetchBandwidth1;
+			} else if (Case2OK) {
+				prefetch_bw_equ = PrefetchBandwidth2;
+			} else if (Case3OK) {
+				prefetch_bw_equ = PrefetchBandwidth3;
+			} else {
+				prefetch_bw_equ = PrefetchBandwidth4;
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Case1OK: %d\n", __func__, Case1OK);
+			dml_print("DML::%s: Case2OK: %d\n", __func__, Case2OK);
+			dml_print("DML::%s: Case3OK: %d\n", __func__, Case3OK);
+			dml_print("DML::%s: prefetch_bw_equ: %f\n", __func__, prefetch_bw_equ);
+#endif
+
+			if (prefetch_bw_equ > 0) {
+				if (GPUVMEnable == true) {
+					Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
+				} else {
+					Tvm_equ = LineTime / 4;
+				}
+
+				if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+					Tr0_equ = dml_max4(
+							(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_equ,
+							Tr0_trips,
+							(LineTime - Tvm_equ) / 2,
+							LineTime / 4);
+				} else {
+					Tr0_equ = (LineTime - Tvm_equ) / 2;
+				}
+			} else {
+				Tvm_equ = 0;
+				Tr0_equ = 0;
+				dml_print("DML: prefetch_bw_equ equals 0! %s:%d\n", __FILE__, __LINE__);
+			}
+		}
+
+		if (dst_y_prefetch_oto < dst_y_prefetch_equ) {
+			*DestinationLinesForPrefetch = dst_y_prefetch_oto;
+			TimeForFetchingMetaPTE = Tvm_oto;
+			TimeForFetchingRowInVBlank = Tr0_oto;
+			*PrefetchBandwidth = prefetch_bw_oto;
+		} else {
+			*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+			TimeForFetchingMetaPTE = Tvm_equ;
+			TimeForFetchingRowInVBlank = Tr0_equ;
+			*PrefetchBandwidth = prefetch_bw_equ;
+		}
+
+		*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
+
+		*DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+		LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch
+		// See note above dated 5/30/2018
+		//                      - ((NumberOfCursors > 0 || GPUVMEnable || DCCEnable) ?
+				- ((GPUVMEnable || myPipe->DCCEnable) ? (*DestinationLinesToRequestVMInVBlank + 2 * *DestinationLinesToRequestRowInVBlank) : 0.0); // TODO: Did someone else add this??
+#else
+				LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank;
+#endif
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: DestinationLinesForPrefetch = %f\n", __func__, *DestinationLinesForPrefetch);
+		dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", __func__, *DestinationLinesToRequestVMInVBlank);
+		dml_print("DML::%s: TimeForFetchingRowInVBlank = %f\n", __func__, TimeForFetchingRowInVBlank);
+		dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+		dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", __func__, *DestinationLinesToRequestRowInVBlank);
+		dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+		dml_print("DML::%s: LinesToRequestPrefetchPixelData = %f\n", __func__, LinesToRequestPrefetchPixelData);
+#endif
+
+		if (LinesToRequestPrefetchPixelData > 0 && prefetch_bw_equ > 0) {
+
+			*VRatioPrefetchY = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+			dml_print("DML::%s: SwathHeightY = %d\n", __func__, SwathHeightY);
+			dml_print("DML::%s: VInitPreFillY = %f\n", __func__, VInitPreFillY);
+#endif
+			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
+					*VRatioPrefetchY = dml_max(
+							(double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData,
+							(double) MaxNumSwathY * SwathHeightY / (LinesToRequestPrefetchPixelData - (VInitPreFillY - 3.0) / 2.0));
+					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+				} else {
+					MyError = true;
+					dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+					*VRatioPrefetchY = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+				dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+				dml_print("DML::%s: MaxNumSwathY = %d\n", __func__, MaxNumSwathY);
+#endif
+			}
+
+			*VRatioPrefetchC = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+			dml_print("DML::%s: SwathHeightC = %d\n", __func__, SwathHeightC);
+			dml_print("DML::%s: VInitPreFillC = %f\n", __func__, VInitPreFillC);
+#endif
+			if ((SwathHeightC > 4)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
+					*VRatioPrefetchC = dml_max(
+							*VRatioPrefetchC,
+							(double) MaxNumSwathC * SwathHeightC / (LinesToRequestPrefetchPixelData - (VInitPreFillC - 3.0) / 2.0));
+					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+				} else {
+					MyError = true;
+					dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+					*VRatioPrefetchC = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+				dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC);
+				dml_print("DML::%s: MaxNumSwathC = %d\n", __func__, MaxNumSwathC);
+#endif
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY);
+			dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+#endif
+
+			*RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData * myPipe->BytePerPixelY * swath_width_luma_ub / LineTime;
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: RequiredPrefetchPixDataBWLuma = %f\n", __func__, *RequiredPrefetchPixDataBWLuma);
+#endif
+
+			*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * myPipe->BytePerPixelC * swath_width_chroma_ub
+					/ LineTime;
+		} else {
+			MyError = true;
+			dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+			dml_print("DML: LinesToRequestPrefetchPixelData: %f, should be > 0\n", LinesToRequestPrefetchPixelData);
+			*VRatioPrefetchY = 0;
+			*VRatioPrefetchC = 0;
+			*RequiredPrefetchPixDataBWLuma = 0;
+			*RequiredPrefetchPixDataBWChroma = 0;
+		}
+
+		dml_print(
+				"DML: Tpre: %fus - sum of time to request meta pte, 2 x data pte + meta data, swaths\n",
+				(double) LinesToRequestPrefetchPixelData * LineTime + 2.0 * TimeForFetchingRowInVBlank + TimeForFetchingMetaPTE);
+		dml_print("DML:  Tvm: %fus - time to fetch page tables for meta surface\n", TimeForFetchingMetaPTE);
+		dml_print("DML:  Tr0: %fus - time to fetch first row of data pagetables and first row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank);
+		dml_print(
+				"DML:  Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n",
+				(double) LinesToRequestPrefetchPixelData * LineTime);
+		dml_print("DML: To: %fus - time for propagation from scaler to optc\n",
+			  (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) /
+			  (double) myPipe->HTotal)) * LineTime);
+		dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - To > 0\n");
+		dml_print("DML: Tslack(pre): %fus - time left over in schedule\n",
+				VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank
+						- (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - *TSetup);
+		dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
+
+	} else {
+		MyError = true;
+		dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+	}
+
+	{
+		double prefetch_vm_bw;
+		double prefetch_row_bw;
+
+		if (PDEAndMetaPTEBytesFrame == 0) {
+			prefetch_vm_bw = 0;
+		} else if (*DestinationLinesToRequestVMInVBlank > 0) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+			dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+			dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", __func__, *DestinationLinesToRequestVMInVBlank);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+#endif
+			prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInVBlank * LineTime);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw);
+#endif
+		} else {
+			prefetch_vm_bw = 0;
+			MyError = true;
+			dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+		}
+
+		if (MetaRowByte + PixelPTEBytesPerRow == 0) {
+			prefetch_row_bw = 0;
+		} else if (*DestinationLinesToRequestRowInVBlank > 0) {
+			prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInVBlank * LineTime);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+			dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+			dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", __func__, *DestinationLinesToRequestRowInVBlank);
+			dml_print("DML::%s: prefetch_row_bw = %f\n", __func__, prefetch_row_bw);
+#endif
+		} else {
+			prefetch_row_bw = 0;
+			MyError = true;
+			dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+		}
+
+		*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
+	}
+
+	if (MyError) {
+		*PrefetchBandwidth = 0;
+		TimeForFetchingMetaPTE = 0;
+		TimeForFetchingRowInVBlank = 0;
+		*DestinationLinesToRequestVMInVBlank = 0;
+		*DestinationLinesToRequestRowInVBlank = 0;
+		*DestinationLinesForPrefetch = 0;
+		LinesToRequestPrefetchPixelData = 0;
+		*VRatioPrefetchY = 0;
+		*VRatioPrefetchC = 0;
+		*RequiredPrefetchPixDataBWLuma = 0;
+		*RequiredPrefetchPixDataBWChroma = 0;
+	}
+
+	return MyError;
+}
+
+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed)
+{
+	return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1);
+}
+
+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
+{
+	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
+}
+
+static void CalculateDCCConfiguration(
+		bool DCCEnabled,
+		bool DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceWidthLuma,
+		unsigned int SurfaceWidthChroma,
+		unsigned int SurfaceHeightLuma,
+		unsigned int SurfaceHeightChroma,
+		double DETBufferSize,
+		unsigned int RequestHeight256ByteLuma,
+		unsigned int RequestHeight256ByteChroma,
+		enum dm_swizzle_mode TilingFormat,
+		unsigned int BytePerPixelY,
+		unsigned int BytePerPixelC,
+		double BytePerPixelDETY,
+		double BytePerPixelDETC,
+		enum scan_direction_class ScanOrientation,
+		unsigned int *MaxUncompressedBlockLuma,
+		unsigned int *MaxUncompressedBlockChroma,
+		unsigned int *MaxCompressedBlockLuma,
+		unsigned int *MaxCompressedBlockChroma,
+		unsigned int *IndependentBlockLuma,
+		unsigned int *IndependentBlockChroma)
+{
+	int yuv420;
+	int horz_div_l;
+	int horz_div_c;
+	int vert_div_l;
+	int vert_div_c;
+
+	int swath_buf_size;
+	double detile_buf_vp_horz_limit;
+	double detile_buf_vp_vert_limit;
+
+	int MAS_vp_horz_limit;
+	int MAS_vp_vert_limit;
+	int max_vp_horz_width;
+	int max_vp_vert_height;
+	int eff_surf_width_l;
+	int eff_surf_width_c;
+	int eff_surf_height_l;
+	int eff_surf_height_c;
+
+	int full_swath_bytes_horz_wc_l;
+	int full_swath_bytes_horz_wc_c;
+	int full_swath_bytes_vert_wc_l;
+	int full_swath_bytes_vert_wc_c;
+	int req128_horz_wc_l;
+	int req128_horz_wc_c;
+	int req128_vert_wc_l;
+	int req128_vert_wc_c;
+	int segment_order_horz_contiguous_luma;
+	int segment_order_horz_contiguous_chroma;
+	int segment_order_vert_contiguous_luma;
+	int segment_order_vert_contiguous_chroma;
+
+	typedef enum {
+		REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
+	} RequestType;
+	RequestType RequestLuma;
+	RequestType RequestChroma;
+
+	yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12) ? 1 : 0);
+	horz_div_l = 1;
+	horz_div_c = 1;
+	vert_div_l = 1;
+	vert_div_c = 1;
+
+	if (BytePerPixelY == 1)
+		vert_div_l = 0;
+	if (BytePerPixelC == 1)
+		vert_div_c = 0;
+	if (BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_s || TilingFormat == dm_sw_64kb_s_t || TilingFormat == dm_sw_64kb_s_x))
+		horz_div_l = 0;
+	if (BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_s || TilingFormat == dm_sw_64kb_s_t || TilingFormat == dm_sw_64kb_s_x))
+		horz_div_c = 0;
+
+	if (BytePerPixelC == 0) {
+		swath_buf_size = DETBufferSize / 2 - 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l));
+		detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l));
+	} else {
+		swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size
+				/ ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)
+						+ (double) RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420));
+		detile_buf_vp_vert_limit = (double) swath_buf_size
+				/ (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l) + 256.0 / RequestHeight256ByteChroma / (1 + vert_div_c) / (1 + yuv420));
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		detile_buf_vp_horz_limit = 1.5 * detile_buf_vp_horz_limit;
+		detile_buf_vp_vert_limit = 1.5 * detile_buf_vp_vert_limit;
+	}
+
+	detile_buf_vp_horz_limit = dml_floor(detile_buf_vp_horz_limit - 1, 16);
+	detile_buf_vp_vert_limit = dml_floor(detile_buf_vp_vert_limit - 1, 16);
+
+	MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 5760;
+	MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760);
+	max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
+	max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
+	eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma);
+	eff_surf_width_c = eff_surf_width_l / (1 + yuv420);
+	eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma);
+	eff_surf_height_c = eff_surf_height_l / (1 + yuv420);
+
+	full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY;
+	full_swath_bytes_vert_wc_l = eff_surf_height_l * 256 / RequestHeight256ByteLuma;
+	if (BytePerPixelC > 0) {
+		full_swath_bytes_horz_wc_c = eff_surf_width_c * RequestHeight256ByteChroma * BytePerPixelC;
+		full_swath_bytes_vert_wc_c = eff_surf_height_c * 256 / RequestHeight256ByteChroma;
+	} else {
+		full_swath_bytes_horz_wc_c = 0;
+		full_swath_bytes_vert_wc_c = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256);
+		full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256);
+		full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256);
+		full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256);
+	}
+
+	if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 0;
+	} else if (full_swath_bytes_horz_wc_l < 1.5 * full_swath_bytes_horz_wc_c && 2 * full_swath_bytes_horz_wc_l + full_swath_bytes_horz_wc_c <= DETBufferSize) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 1;
+	} else if (full_swath_bytes_horz_wc_l >= 1.5 * full_swath_bytes_horz_wc_c && full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 0;
+	} else {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 1;
+	}
+
+	if (2 * full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSize) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 0;
+	} else if (full_swath_bytes_vert_wc_l < 1.5 * full_swath_bytes_vert_wc_c && 2 * full_swath_bytes_vert_wc_l + full_swath_bytes_vert_wc_c <= DETBufferSize) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 1;
+	} else if (full_swath_bytes_vert_wc_l >= 1.5 * full_swath_bytes_vert_wc_c && full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSize) {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 0;
+	} else {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 1;
+	}
+
+	if (BytePerPixelY == 2 || (BytePerPixelY == 4 && TilingFormat != dm_sw_64kb_r_x)) {
+		segment_order_horz_contiguous_luma = 0;
+	} else {
+		segment_order_horz_contiguous_luma = 1;
+	}
+	if ((BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))
+			|| (BytePerPixelY == 4 && TilingFormat == dm_sw_64kb_r_x)) {
+		segment_order_vert_contiguous_luma = 0;
+	} else {
+		segment_order_vert_contiguous_luma = 1;
+	}
+	if (BytePerPixelC == 2 || (BytePerPixelC == 4 && TilingFormat != dm_sw_64kb_r_x)) {
+		segment_order_horz_contiguous_chroma = 0;
+	} else {
+		segment_order_horz_contiguous_chroma = 1;
+	}
+	if ((BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))
+			|| (BytePerPixelC == 4 && TilingFormat == dm_sw_64kb_r_x)) {
+		segment_order_vert_contiguous_chroma = 0;
+	} else {
+		segment_order_vert_contiguous_chroma = 1;
+	}
+
+	if (DCCProgrammingAssumesScanDirectionUnknown == true) {
+		if (req128_horz_wc_l == 0 && req128_vert_wc_l == 0) {
+			RequestLuma = REQ_256Bytes;
+		} else if ((req128_horz_wc_l == 1 && segment_order_horz_contiguous_luma == 0) || (req128_vert_wc_l == 1 && segment_order_vert_contiguous_luma == 0)) {
+			RequestLuma = REQ_128BytesNonContiguous;
+		} else {
+			RequestLuma = REQ_128BytesContiguous;
+		}
+		if (req128_horz_wc_c == 0 && req128_vert_wc_c == 0) {
+			RequestChroma = REQ_256Bytes;
+		} else if ((req128_horz_wc_c == 1 && segment_order_horz_contiguous_chroma == 0) || (req128_vert_wc_c == 1 && segment_order_vert_contiguous_chroma == 0)) {
+			RequestChroma = REQ_128BytesNonContiguous;
+		} else {
+			RequestChroma = REQ_128BytesContiguous;
+		}
+	} else if (ScanOrientation != dm_vert) {
+		if (req128_horz_wc_l == 0) {
+			RequestLuma = REQ_256Bytes;
+		} else if (segment_order_horz_contiguous_luma == 0) {
+			RequestLuma = REQ_128BytesNonContiguous;
+		} else {
+			RequestLuma = REQ_128BytesContiguous;
+		}
+		if (req128_horz_wc_c == 0) {
+			RequestChroma = REQ_256Bytes;
+		} else if (segment_order_horz_contiguous_chroma == 0) {
+			RequestChroma = REQ_128BytesNonContiguous;
+		} else {
+			RequestChroma = REQ_128BytesContiguous;
+		}
+	} else {
+		if (req128_vert_wc_l == 0) {
+			RequestLuma = REQ_256Bytes;
+		} else if (segment_order_vert_contiguous_luma == 0) {
+			RequestLuma = REQ_128BytesNonContiguous;
+		} else {
+			RequestLuma = REQ_128BytesContiguous;
+		}
+		if (req128_vert_wc_c == 0) {
+			RequestChroma = REQ_256Bytes;
+		} else if (segment_order_vert_contiguous_chroma == 0) {
+			RequestChroma = REQ_128BytesNonContiguous;
+		} else {
+			RequestChroma = REQ_128BytesContiguous;
+		}
+	}
+
+	if (RequestLuma == REQ_256Bytes) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 256;
+		*IndependentBlockLuma = 0;
+	} else if (RequestLuma == REQ_128BytesContiguous) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 128;
+		*IndependentBlockLuma = 128;
+	} else {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 64;
+		*IndependentBlockLuma = 64;
+	}
+
+	if (RequestChroma == REQ_256Bytes) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 256;
+		*IndependentBlockChroma = 0;
+	} else if (RequestChroma == REQ_128BytesContiguous) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 128;
+		*IndependentBlockChroma = 128;
+	} else {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 64;
+		*IndependentBlockChroma = 64;
+	}
+
+	if (DCCEnabled != true || BytePerPixelC == 0) {
+		*MaxUncompressedBlockChroma = 0;
+		*MaxCompressedBlockChroma = 0;
+		*IndependentBlockChroma = 0;
+	}
+
+	if (DCCEnabled != true) {
+		*MaxUncompressedBlockLuma = 0;
+		*MaxCompressedBlockLuma = 0;
+		*IndependentBlockLuma = 0;
+	}
+}
+
+static double CalculatePrefetchSourceLines(
+		struct display_mode_lib *mode_lib,
+		double VRatio,
+		double vtaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		unsigned int ViewportYStart,
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int MaxPartialSwath;
+
+	if (ProgressiveToInterlaceUnitInOPP)
+		*VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
+	else
+		*VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
+
+	if (!v->IgnoreViewportPositioning) {
+
+		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
+
+		if (*VInitPreFill > 1.0)
+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight;
+		else
+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight;
+		MaxPartialSwath = dml_max(1U, MaxPartialSwath);
+
+	} else {
+
+		if (ViewportYStart != 0)
+			dml_print("WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n");
+
+		*MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
+
+		if (*VInitPreFill > 1.0)
+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight;
+		else
+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) % SwathHeight;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VRatio = %f\n", __func__, VRatio);
+	dml_print("DML::%s: vtaps = %f\n", __func__, vtaps);
+	dml_print("DML::%s: VInitPreFill = %f\n", __func__, *VInitPreFill);
+	dml_print("DML::%s: ProgressiveToInterlaceUnitInOPP = %d\n", __func__, ProgressiveToInterlaceUnitInOPP);
+	dml_print("DML::%s: IgnoreViewportPositioning = %d\n", __func__, v->IgnoreViewportPositioning);
+	dml_print("DML::%s: SwathHeight = %d\n", __func__, SwathHeight);
+	dml_print("DML::%s: MaxPartialSwath = %d\n", __func__, MaxPartialSwath);
+	dml_print("DML::%s: MaxNumSwath = %d\n", __func__, *MaxNumSwath);
+	dml_print("DML::%s: Prefetch source lines = %d\n", __func__, *MaxNumSwath * SwathHeight + MaxPartialSwath);
+#endif
+	return *MaxNumSwath * SwathHeight + MaxPartialSwath;
+}
+
+static unsigned int CalculateVMAndRowBytes(
+		struct display_mode_lib *mode_lib,
+		bool DCCEnable,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum scan_direction_class ScanDirection,
+		unsigned int SwathWidth,
+		unsigned int ViewportHeight,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMinPageSize,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int *MacroTileWidth,
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		bool *PTEBufferSizeNotExceeded,
+		int *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		int *vm_group_bytes,
+		unsigned int *dpte_group_bytes,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		int *DPDE0BytesFrame,
+		int *MetaPTEBytesFrame)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int MPDEBytesFrame;
+	unsigned int DCCMetaSurfaceBytes;
+	unsigned int MacroTileSizeBytes;
+	unsigned int MacroTileHeight;
+	unsigned int ExtraDPDEBytesFrame;
+	unsigned int PDEAndMetaPTEBytesFrame;
+	unsigned int PixelPTEReqHeightPTEs = 0;
+	unsigned int HostVMDynamicLevels = 0;
+	double FractionOfPTEReturnDrop;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048) {
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		} else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		} else {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+		}
+	}
+
+	*MetaRequestHeight = 8 * BlockHeight256Bytes;
+	*MetaRequestWidth = 8 * BlockWidth256Bytes;
+	if (ScanDirection != dm_vert) {
+		*meta_row_height = *MetaRequestHeight;
+		*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth;
+		*MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0;
+	} else {
+		*meta_row_height = *MetaRequestWidth;
+		*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight;
+		*MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0;
+	}
+	DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256;
+	if (GPUVMEnable == true) {
+		*MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64;
+		MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1);
+	} else {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+	}
+
+	if (DCCEnable != true) {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+		*MetaRowByte = 0;
+	}
+
+	if (SurfaceTiling == dm_sw_linear) {
+		MacroTileSizeBytes = 256;
+		MacroTileHeight = BlockHeight256Bytes;
+	} else {
+		MacroTileSizeBytes = 65536;
+		MacroTileHeight = 16 * BlockHeight256Bytes;
+	}
+	*MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight;
+
+	if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {
+		if (ScanDirection != dm_vert) {
+			*DPDE0BytesFrame = 64
+					* (dml_ceil(
+							((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes)
+									/ (8 * 2097152),
+							1) + 1);
+		} else {
+			*DPDE0BytesFrame = 64
+					* (dml_ceil(
+							((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes)
+									/ (8 * 2097152),
+							1) + 1);
+		}
+		ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2);
+	} else {
+		*DPDE0BytesFrame = 0;
+		ExtraDPDEBytesFrame = 0;
+	}
+
+	PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame + ExtraDPDEBytesFrame;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MetaPTEBytesFrame = %d\n", __func__, *MetaPTEBytesFrame);
+	dml_print("DML::%s: MPDEBytesFrame = %d\n", __func__, MPDEBytesFrame);
+	dml_print("DML::%s: DPDE0BytesFrame = %d\n", __func__, *DPDE0BytesFrame);
+	dml_print("DML::%s: ExtraDPDEBytesFrame= %d\n", __func__, ExtraDPDEBytesFrame);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+#endif
+
+	if (HostVMEnable == true) {
+		PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * HostVMDynamicLevels);
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+#endif
+
+	if (SurfaceTiling == dm_sw_linear) {
+		PixelPTEReqHeightPTEs = 1;
+		*PixelPTEReqHeight = 1;
+		*PixelPTEReqWidth = 32768.0 / BytePerPixel;
+		*PTERequestSize = 64;
+		FractionOfPTEReturnDrop = 0;
+	} else if (MacroTileSizeBytes == 4096) {
+		PixelPTEReqHeightPTEs = 1;
+		*PixelPTEReqHeight = MacroTileHeight;
+		*PixelPTEReqWidth = 8 * *MacroTileWidth;
+		*PTERequestSize = 64;
+		if (ScanDirection != dm_vert)
+			FractionOfPTEReturnDrop = 0;
+		else
+			FractionOfPTEReturnDrop = 7 / 8;
+	} else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) {
+		PixelPTEReqHeightPTEs = 16;
+		*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
+		*PixelPTEReqWidth = 16 * BlockWidth256Bytes;
+		*PTERequestSize = 128;
+		FractionOfPTEReturnDrop = 0;
+	} else {
+		PixelPTEReqHeightPTEs = 1;
+		*PixelPTEReqHeight = MacroTileHeight;
+		*PixelPTEReqWidth = 8 * *MacroTileWidth;
+		*PTERequestSize = 64;
+		FractionOfPTEReturnDrop = 0;
+	}
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
+		*dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
+	} else if (ScanDirection != dm_vert) {
+		*dpte_row_height = *PixelPTEReqHeight;
+		*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
+	} else {
+		*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
+		*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
+	}
+
+	if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) <= 64 * PTEBufferSizeInRequests) {
+		*PTEBufferSizeNotExceeded = true;
+	} else {
+		*PTEBufferSizeNotExceeded = false;
+	}
+
+	if (GPUVMEnable != true) {
+		*PixelPTEBytesPerRow = 0;
+		*PTEBufferSizeNotExceeded = true;
+	}
+
+	dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %i\n", *MetaPTEBytesFrame);
+
+	if (HostVMEnable == true) {
+		*PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * HostVMDynamicLevels);
+	}
+
+	if (HostVMEnable == true) {
+		*vm_group_bytes = 512;
+		*dpte_group_bytes = 512;
+	} else if (GPUVMEnable == true) {
+		*vm_group_bytes = 2048;
+		if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection == dm_vert) {
+			*dpte_group_bytes = 512;
+		} else {
+			*dpte_group_bytes = 2048;
+		}
+	} else {
+		*vm_group_bytes = 0;
+		*dpte_group_bytes = 0;
+	}
+	return PDEAndMetaPTEBytesFrame;
+}
+
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int j, k;
+	double HostVMInefficiencyFactor = 1.0;
+	bool NoChromaPlanes = true;
+	int ReorderBytes;
+	double VMDataOnlyReturnBW;
+	double MaxTotalRDBandwidth = 0;
+	int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
+
+	v->WritebackDISPCLK = 0.0;
+	v->DISPCLKWithRamping = 0;
+	v->DISPCLKWithoutRamping = 0;
+	v->GlobalDPPCLK = 0.0;
+	/* DAL custom code: need to update ReturnBW in case min dcfclk is overriden */
+	{
+	double IdealFabricAndSDPPortBandwidthPerState = dml_min(
+			v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
+			v->FabricClockPerState[v->VoltageLevel] * v->FabricDatapathToDCNDataReturn);
+	double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth;
+	if (v->HostVMEnable != true) {
+		v->ReturnBW = dml_min(
+				IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+				IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
+	} else {
+		v->ReturnBW = dml_min(
+				IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+				IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
+	}
+	}
+	/* End DAL custom code */
+
+	// DISPCLK and DPPCLK Calculation
+	//
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->WritebackEnable[k]) {
+			v->WritebackDISPCLK = dml_max(
+					v->WritebackDISPCLK,
+					dml31_CalculateWriteBackDISPCLK(
+							v->WritebackPixelFormat[k],
+							v->PixelClock[k],
+							v->WritebackHRatio[k],
+							v->WritebackVRatio[k],
+							v->WritebackHTaps[k],
+							v->WritebackVTaps[k],
+							v->WritebackSourceWidth[k],
+							v->WritebackDestinationWidth[k],
+							v->HTotal[k],
+							v->WritebackLineBufferSize));
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->HRatio[k] > 1) {
+			v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
+					v->MaxDCHUBToPSCLThroughput,
+					v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
+		} else {
+			v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+		}
+
+		v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
+				* dml_max(
+						v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
+						dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
+
+		if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
+			v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
+		}
+
+		if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
+				&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
+			v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
+			v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
+		} else {
+			if (v->HRatioChroma[k] > 1) {
+				v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
+						v->MaxDCHUBToPSCLThroughput,
+						v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
+			} else {
+				v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+			}
+			v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
+					* dml_max3(
+							v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
+							v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
+							1.0);
+
+			if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
+				v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
+			}
+
+			v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] != k)
+			continue;
+		if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
+			v->DISPCLKWithRamping = dml_max(
+					v->DISPCLKWithRamping,
+					v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
+							* (1 + v->DISPCLKRampingMargin / 100));
+			v->DISPCLKWithoutRamping = dml_max(
+					v->DISPCLKWithoutRamping,
+					v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
+		} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
+			v->DISPCLKWithRamping = dml_max(
+					v->DISPCLKWithRamping,
+					v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
+							* (1 + v->DISPCLKRampingMargin / 100));
+			v->DISPCLKWithoutRamping = dml_max(
+					v->DISPCLKWithoutRamping,
+					v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
+		} else {
+			v->DISPCLKWithRamping = dml_max(
+					v->DISPCLKWithRamping,
+					v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
+			v->DISPCLKWithoutRamping = dml_max(
+					v->DISPCLKWithoutRamping,
+					v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
+		}
+	}
+
+	v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK);
+	v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK);
+
+	ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
+	v->DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithRamping, v->DISPCLKDPPCLKVCOSpeed);
+	v->DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithoutRamping, v->DISPCLKDPPCLKVCOSpeed);
+	v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
+			v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
+			v->DISPCLKDPPCLKVCOSpeed);
+	if (v->DISPCLKWithoutRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
+		v->DISPCLK_calculated = v->DISPCLKWithoutRampingRoundedToDFSGranularity;
+	} else if (v->DISPCLKWithRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
+		v->DISPCLK_calculated = v->MaxDispclkRoundedToDFSGranularity;
+	} else {
+		v->DISPCLK_calculated = v->DISPCLKWithRampingRoundedToDFSGranularity;
+	}
+	v->DISPCLK = v->DISPCLK_calculated;
+	DTRACE("   dispclk_mhz (calculated) = %f", v->DISPCLK_calculated);
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
+	}
+	v->GlobalDPPCLK = RoundToDFSGranularityUp(v->GlobalDPPCLK, v->DISPCLKDPPCLKVCOSpeed);
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
+		DTRACE("   dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->DPPCLK[k] = v->DPPCLK_calculated[k];
+	}
+
+	// Urgent and B P-State/DRAM Clock Change Watermark
+	DTRACE("   dcfclk_mhz         = %f", v->DCFCLK);
+	DTRACE("   return_bus_bw      = %f", v->ReturnBW);
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		CalculateBytePerPixelAnd256BBlockSizes(
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				&v->BytePerPixelY[k],
+				&v->BytePerPixelC[k],
+				&v->BytePerPixelDETY[k],
+				&v->BytePerPixelDETC[k],
+				&v->BlockHeight256BytesY[k],
+				&v->BlockHeight256BytesC[k],
+				&v->BlockWidth256BytesY[k],
+				&v->BlockWidth256BytesC[k]);
+	}
+
+	CalculateSwathWidth(
+			false,
+			v->NumberOfActivePlanes,
+			v->SourcePixelFormat,
+			v->SourceScan,
+			v->ViewportWidth,
+			v->ViewportHeight,
+			v->SurfaceWidthY,
+			v->SurfaceWidthC,
+			v->SurfaceHeightY,
+			v->SurfaceHeightC,
+			v->ODMCombineEnabled,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->BlockHeight256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesY,
+			v->BlockWidth256BytesC,
+			v->BlendingAndTiming,
+			v->HActive,
+			v->HRatio,
+			v->DPPPerPlane,
+			v->SwathWidthSingleDPPY,
+			v->SwathWidthSingleDPPC,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			v->dummyinteger3,
+			v->dummyinteger4,
+			v->swath_width_luma_ub,
+			v->swath_width_chroma_ub);
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
+				* v->VRatio[k];
+		v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
+				* v->VRatioChroma[k];
+		DTRACE("   read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
+	}
+
+	// DCFCLK Deep Sleep
+	CalculateDCFCLKDeepSleep(
+			mode_lib,
+			v->NumberOfActivePlanes,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->VRatio,
+			v->VRatioChroma,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			v->DPPPerPlane,
+			v->HRatio,
+			v->HRatioChroma,
+			v->PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			v->DPPCLK,
+			v->ReadBandwidthPlaneLuma,
+			v->ReadBandwidthPlaneChroma,
+			v->ReturnBusWidth,
+			&v->DCFCLKDeepSleep);
+
+	// DSCCLK
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
+			v->DSCCLK_calculated[k] = 0.0;
+		} else {
+			if (v->OutputFormat[k] == dm_420)
+				v->DSCFormatFactor = 2;
+			else if (v->OutputFormat[k] == dm_444)
+				v->DSCFormatFactor = 1;
+			else if (v->OutputFormat[k] == dm_n422)
+				v->DSCFormatFactor = 2;
+			else
+				v->DSCFormatFactor = 1;
+			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
+				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
+						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
+				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
+						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else
+				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
+						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		}
+	}
+
+	// DSC Delay
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		double BPP = v->OutputBpp[k];
+
+		if (v->DSCEnabled[k] && BPP != 0) {
+			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
+				v->DSCDelay[k] = dscceComputeDelay(
+						v->DSCInputBitPerComponent[k],
+						BPP,
+						dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
+						v->NumberOfDSCSlices[k],
+						v->OutputFormat[k],
+						v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
+			} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
+				v->DSCDelay[k] = 2
+						* (dscceComputeDelay(
+								v->DSCInputBitPerComponent[k],
+								BPP,
+								dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
+								v->NumberOfDSCSlices[k] / 2.0,
+								v->OutputFormat[k],
+								v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+			} else {
+				v->DSCDelay[k] = 4
+						* (dscceComputeDelay(
+								v->DSCInputBitPerComponent[k],
+								BPP,
+								dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
+								v->NumberOfDSCSlices[k] / 4.0,
+								v->OutputFormat[k],
+								v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+			}
+			v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
+		} else {
+			v->DSCDelay[k] = 0;
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k)
+		for (j = 0; j < v->NumberOfActivePlanes; ++j) // NumberOfPlanes
+			if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
+				v->DSCDelay[k] = v->DSCDelay[j];
+
+	// Prefetch
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		unsigned int PDEAndMetaPTEBytesFrameY;
+		unsigned int PixelPTEBytesPerRowY;
+		unsigned int MetaRowByteY;
+		unsigned int MetaRowByteC;
+		unsigned int PDEAndMetaPTEBytesFrameC;
+		unsigned int PixelPTEBytesPerRowC;
+		bool PTEBufferSizeNotExceededY;
+		bool PTEBufferSizeNotExceededC;
+
+		if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
+				|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
+			if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
+				v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2;
+				v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
+			} else {
+				v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
+				v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
+			}
+
+			PDEAndMetaPTEBytesFrameC = CalculateVMAndRowBytes(
+					mode_lib,
+					v->DCCEnable[k],
+					v->BlockHeight256BytesC[k],
+					v->BlockWidth256BytesC[k],
+					v->SourcePixelFormat[k],
+					v->SurfaceTiling[k],
+					v->BytePerPixelC[k],
+					v->SourceScan[k],
+					v->SwathWidthC[k],
+					v->ViewportHeightChroma[k],
+					v->GPUVMEnable,
+					v->HostVMEnable,
+					v->HostVMMaxNonCachedPageTableLevels,
+					v->GPUVMMinPageSize,
+					v->HostVMMinPageSize,
+					v->PTEBufferSizeInRequestsForChroma,
+					v->PitchC[k],
+					v->DCCMetaPitchC[k],
+					&v->MacroTileWidthC[k],
+					&MetaRowByteC,
+					&PixelPTEBytesPerRowC,
+					&PTEBufferSizeNotExceededC,
+					&v->dpte_row_width_chroma_ub[k],
+					&v->dpte_row_height_chroma[k],
+					&v->meta_req_width_chroma[k],
+					&v->meta_req_height_chroma[k],
+					&v->meta_row_width_chroma[k],
+					&v->meta_row_height_chroma[k],
+					&v->dummyinteger1,
+					&v->dummyinteger2,
+					&v->PixelPTEReqWidthC[k],
+					&v->PixelPTEReqHeightC[k],
+					&v->PTERequestSizeC[k],
+					&v->dpde0_bytes_per_frame_ub_c[k],
+					&v->meta_pte_bytes_per_frame_ub_c[k]);
+
+			v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
+					mode_lib,
+					v->VRatioChroma[k],
+					v->VTAPsChroma[k],
+					v->Interlace[k],
+					v->ProgressiveToInterlaceUnitInOPP,
+					v->SwathHeightC[k],
+					v->ViewportYStartC[k],
+					&v->VInitPreFillC[k],
+					&v->MaxNumSwathC[k]);
+		} else {
+			v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
+			v->PTEBufferSizeInRequestsForChroma = 0;
+			PixelPTEBytesPerRowC = 0;
+			PDEAndMetaPTEBytesFrameC = 0;
+			MetaRowByteC = 0;
+			v->MaxNumSwathC[k] = 0;
+			v->PrefetchSourceLinesC[k] = 0;
+		}
+
+		PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
+				mode_lib,
+				v->DCCEnable[k],
+				v->BlockHeight256BytesY[k],
+				v->BlockWidth256BytesY[k],
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				v->BytePerPixelY[k],
+				v->SourceScan[k],
+				v->SwathWidthY[k],
+				v->ViewportHeight[k],
+				v->GPUVMEnable,
+				v->HostVMEnable,
+				v->HostVMMaxNonCachedPageTableLevels,
+				v->GPUVMMinPageSize,
+				v->HostVMMinPageSize,
+				v->PTEBufferSizeInRequestsForLuma,
+				v->PitchY[k],
+				v->DCCMetaPitchY[k],
+				&v->MacroTileWidthY[k],
+				&MetaRowByteY,
+				&PixelPTEBytesPerRowY,
+				&PTEBufferSizeNotExceededY,
+				&v->dpte_row_width_luma_ub[k],
+				&v->dpte_row_height[k],
+				&v->meta_req_width[k],
+				&v->meta_req_height[k],
+				&v->meta_row_width[k],
+				&v->meta_row_height[k],
+				&v->vm_group_bytes[k],
+				&v->dpte_group_bytes[k],
+				&v->PixelPTEReqWidthY[k],
+				&v->PixelPTEReqHeightY[k],
+				&v->PTERequestSizeY[k],
+				&v->dpde0_bytes_per_frame_ub_l[k],
+				&v->meta_pte_bytes_per_frame_ub_l[k]);
+
+		v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
+				mode_lib,
+				v->VRatio[k],
+				v->vtaps[k],
+				v->Interlace[k],
+				v->ProgressiveToInterlaceUnitInOPP,
+				v->SwathHeightY[k],
+				v->ViewportYStartY[k],
+				&v->VInitPreFillY[k],
+				&v->MaxNumSwathY[k]);
+		v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
+		v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
+		v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
+
+		CalculateRowBandwidth(
+				v->GPUVMEnable,
+				v->SourcePixelFormat[k],
+				v->VRatio[k],
+				v->VRatioChroma[k],
+				v->DCCEnable[k],
+				v->HTotal[k] / v->PixelClock[k],
+				MetaRowByteY,
+				MetaRowByteC,
+				v->meta_row_height[k],
+				v->meta_row_height_chroma[k],
+				PixelPTEBytesPerRowY,
+				PixelPTEBytesPerRowC,
+				v->dpte_row_height[k],
+				v->dpte_row_height_chroma[k],
+				&v->meta_row_bw[k],
+				&v->dpte_row_bw[k]);
+	}
+
+	v->TotalDCCActiveDPP = 0;
+	v->TotalActiveDPP = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
+		if (v->DCCEnable[k])
+			v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
+		if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
+				|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
+			NoChromaPlanes = false;
+	}
+
+	ReorderBytes = v->NumberOfChannels
+			* dml_max3(
+					v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	VMDataOnlyReturnBW = dml_min(
+			dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
+					* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+			v->DRAMSpeed * v->NumberOfChannels * v->DRAMChannelWidth
+					* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: v->ReturnBusWidth = %f\n", __func__, v->ReturnBusWidth);
+	dml_print("DML::%s: v->DCFCLK = %f\n", __func__, v->DCFCLK);
+	dml_print("DML::%s: v->FabricClock = %f\n", __func__, v->FabricClock);
+	dml_print("DML::%s: v->FabricDatapathToDCNDataReturn = %f\n", __func__, v->FabricDatapathToDCNDataReturn);
+	dml_print("DML::%s: v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = %f\n", __func__, v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency);
+	dml_print("DML::%s: v->DRAMSpeed = %f\n", __func__, v->DRAMSpeed);
+	dml_print("DML::%s: v->NumberOfChannels = %f\n", __func__, v->NumberOfChannels);
+	dml_print("DML::%s: v->DRAMChannelWidth = %f\n", __func__, v->DRAMChannelWidth);
+	dml_print("DML::%s: v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n", __func__, v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly);
+	dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, v->ReturnBW);
+#endif
+
+	if (v->GPUVMEnable && v->HostVMEnable)
+		HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW;
+
+	v->UrgentExtraLatency = CalculateExtraLatency(
+			v->RoundTripPingLatencyCycles,
+			ReorderBytes,
+			v->DCFCLK,
+			v->TotalActiveDPP,
+			v->PixelChunkSizeInKByte,
+			v->TotalDCCActiveDPP,
+			v->MetaChunkSize,
+			v->ReturnBW,
+			v->GPUVMEnable,
+			v->HostVMEnable,
+			v->NumberOfActivePlanes,
+			v->DPPPerPlane,
+			v->dpte_group_bytes,
+			HostVMInefficiencyFactor,
+			v->HostVMMinPageSize,
+			v->HostVMMaxNonCachedPageTableLevels);
+
+	v->TCalc = 24.0 / v->DCFCLKDeepSleep;
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k) {
+			if (v->WritebackEnable[k] == true) {
+				v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
+						+ CalculateWriteBackDelay(
+								v->WritebackPixelFormat[k],
+								v->WritebackHRatio[k],
+								v->WritebackVRatio[k],
+								v->WritebackVTaps[k],
+								v->WritebackDestinationWidth[k],
+								v->WritebackDestinationHeight[k],
+								v->WritebackSourceHeight[k],
+								v->HTotal[k]) / v->DISPCLK;
+			} else
+				v->WritebackDelay[v->VoltageLevel][k] = 0;
+			for (j = 0; j < v->NumberOfActivePlanes; ++j) {
+				if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
+					v->WritebackDelay[v->VoltageLevel][k] = dml_max(
+							v->WritebackDelay[v->VoltageLevel][k],
+							v->WritebackLatency
+									+ CalculateWriteBackDelay(
+											v->WritebackPixelFormat[j],
+											v->WritebackHRatio[j],
+											v->WritebackVRatio[j],
+											v->WritebackVTaps[j],
+											v->WritebackDestinationWidth[j],
+											v->WritebackDestinationHeight[j],
+											v->WritebackSourceHeight[j],
+											v->HTotal[k]) / v->DISPCLK);
+				}
+			}
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k)
+		for (j = 0; j < v->NumberOfActivePlanes; ++j)
+			if (v->BlendingAndTiming[k] == j)
+				v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->MaxVStartupLines[k] =
+				(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
+						dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
+						v->VTotal[k] - v->VActive[k]
+								- dml_max(
+										1.0,
+										dml_ceil(
+												(double) v->WritebackDelay[v->VoltageLevel][k]
+														/ (v->HTotal[k] / v->PixelClock[k]),
+												1));
+		if (v->MaxVStartupLines[k] > 1023)
+			v->MaxVStartupLines[k] = 1023;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
+		dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
+#endif
+	}
+
+	v->MaximumMaxVStartupLines = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k)
+		v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
+
+	// VBA_DELTA
+	// We don't really care to iterate between the various prefetch modes
+	//v->PrefetchERROR = CalculateMinAndMaxPrefetchMode(v->AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &v->MinPrefetchMode, &v->MaxPrefetchMode);
+
+	v->UrgentLatency = CalculateUrgentLatency(
+			v->UrgentLatencyPixelDataOnly,
+			v->UrgentLatencyPixelMixedWithVMData,
+			v->UrgentLatencyVMDataOnly,
+			v->DoUrgentLatencyAdjustment,
+			v->UrgentLatencyAdjustmentFabricClockComponent,
+			v->UrgentLatencyAdjustmentFabricClockReference,
+			v->FabricClock);
+
+	v->FractionOfUrgentBandwidth = 0.0;
+	v->FractionOfUrgentBandwidthImmediateFlip = 0.0;
+
+	v->VStartupLines = __DML_VBA_MIN_VSTARTUP__;
+
+	do {
+		double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
+		bool DestinationLineTimesForPrefetchLessThan2 = false;
+		bool VRatioPrefetchMoreThan4 = false;
+		double TWait = CalculateTWait(PrefetchMode, v->DRAMClockChangeLatency, v->UrgentLatency, v->SREnterPlusExitTime);
+		MaxTotalRDBandwidth = 0;
+
+		dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, v->VStartupLines);
+
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			Pipe myPipe;
+
+			myPipe.DPPCLK = v->DPPCLK[k];
+			myPipe.DISPCLK = v->DISPCLK;
+			myPipe.PixelClock = v->PixelClock[k];
+			myPipe.DCFCLKDeepSleep = v->DCFCLKDeepSleep;
+			myPipe.DPPPerPlane = v->DPPPerPlane[k];
+			myPipe.ScalerEnabled = v->ScalerEnabled[k];
+			myPipe.SourceScan = v->SourceScan[k];
+			myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
+			myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
+			myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
+			myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
+			myPipe.InterlaceEnable = v->Interlace[k];
+			myPipe.NumberOfCursors = v->NumberOfCursors[k];
+			myPipe.VBlank = v->VTotal[k] - v->VActive[k];
+			myPipe.HTotal = v->HTotal[k];
+			myPipe.DCCEnable = v->DCCEnable[k];
+			myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
+					|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
+			myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
+			myPipe.BytePerPixelY = v->BytePerPixelY[k];
+			myPipe.BytePerPixelC = v->BytePerPixelC[k];
+			myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
+			v->ErrorResult[k] = CalculatePrefetchSchedule(
+					mode_lib,
+					HostVMInefficiencyFactor,
+					&myPipe,
+					v->DSCDelay[k],
+					v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
+					v->DPPCLKDelaySCL,
+					v->DPPCLKDelaySCLLBOnly,
+					v->DPPCLKDelayCNVCCursor,
+					v->DISPCLKDelaySubtotal,
+					(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
+					v->OutputFormat[k],
+					v->MaxInterDCNTileRepeaters,
+					dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
+					v->MaxVStartupLines[k],
+					v->GPUVMMaxPageTableLevels,
+					v->GPUVMEnable,
+					v->HostVMEnable,
+					v->HostVMMaxNonCachedPageTableLevels,
+					v->HostVMMinPageSize,
+					v->DynamicMetadataEnable[k],
+					v->DynamicMetadataVMEnabled,
+					v->DynamicMetadataLinesBeforeActiveRequired[k],
+					v->DynamicMetadataTransmittedBytes[k],
+					v->UrgentLatency,
+					v->UrgentExtraLatency,
+					v->TCalc,
+					v->PDEAndMetaPTEBytesFrame[k],
+					v->MetaRowByte[k],
+					v->PixelPTEBytesPerRow[k],
+					v->PrefetchSourceLinesY[k],
+					v->SwathWidthY[k],
+					v->VInitPreFillY[k],
+					v->MaxNumSwathY[k],
+					v->PrefetchSourceLinesC[k],
+					v->SwathWidthC[k],
+					v->VInitPreFillC[k],
+					v->MaxNumSwathC[k],
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					v->SwathHeightY[k],
+					v->SwathHeightC[k],
+					TWait,
+					&v->DSTXAfterScaler[k],
+					&v->DSTYAfterScaler[k],
+					&v->DestinationLinesForPrefetch[k],
+					&v->PrefetchBandwidth[k],
+					&v->DestinationLinesToRequestVMInVBlank[k],
+					&v->DestinationLinesToRequestRowInVBlank[k],
+					&v->VRatioPrefetchY[k],
+					&v->VRatioPrefetchC[k],
+					&v->RequiredPrefetchPixDataBWLuma[k],
+					&v->RequiredPrefetchPixDataBWChroma[k],
+					&v->NotEnoughTimeForDynamicMetadata[k],
+					&v->Tno_bw[k],
+					&v->prefetch_vmrow_bw[k],
+					&v->Tdmdl_vm[k],
+					&v->Tdmdl[k],
+					&v->TSetup[k],
+					&v->VUpdateOffsetPix[k],
+					&v->VUpdateWidthPix[k],
+					&v->VReadyOffsetPix[k]);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
+#endif
+			v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
+		}
+
+		v->NoEnoughUrgentLatencyHiding = false;
+		v->NoEnoughUrgentLatencyHidingPre = false;
+
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+					/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
+			v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+					/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
+
+			CalculateUrgentBurstFactor(
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					v->SwathHeightY[k],
+					v->SwathHeightC[k],
+					v->HTotal[k] / v->PixelClock[k],
+					v->UrgentLatency,
+					v->CursorBufferSize,
+					v->CursorWidth[k][0],
+					v->CursorBPP[k][0],
+					v->VRatio[k],
+					v->VRatioChroma[k],
+					v->BytePerPixelDETY[k],
+					v->BytePerPixelDETC[k],
+					v->DETBufferSizeY[k],
+					v->DETBufferSizeC[k],
+					&v->UrgBurstFactorCursor[k],
+					&v->UrgBurstFactorLuma[k],
+					&v->UrgBurstFactorChroma[k],
+					&v->NoUrgentLatencyHiding[k]);
+
+			CalculateUrgentBurstFactor(
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					v->SwathHeightY[k],
+					v->SwathHeightC[k],
+					v->HTotal[k] / v->PixelClock[k],
+					v->UrgentLatency,
+					v->CursorBufferSize,
+					v->CursorWidth[k][0],
+					v->CursorBPP[k][0],
+					v->VRatioPrefetchY[k],
+					v->VRatioPrefetchC[k],
+					v->BytePerPixelDETY[k],
+					v->BytePerPixelDETC[k],
+					v->DETBufferSizeY[k],
+					v->DETBufferSizeC[k],
+					&v->UrgBurstFactorCursorPre[k],
+					&v->UrgBurstFactorLumaPre[k],
+					&v->UrgBurstFactorChromaPre[k],
+					&v->NoUrgentLatencyHidingPre[k]);
+
+			MaxTotalRDBandwidth = MaxTotalRDBandwidth
+					+ dml_max3(
+							v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+							v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
+									+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
+									+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
+									+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
+							v->DPPPerPlane[k]
+									* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
+											+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
+									+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
+
+			MaxTotalRDBandwidthNoUrgentBurst = MaxTotalRDBandwidthNoUrgentBurst
+					+ dml_max3(
+							v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+							v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
+									+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
+							v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
+									+ v->cursor_bw_pre[k]);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
+
+			dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
+			dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
+
+			dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
+			dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
+			dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
+			dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, MaxTotalRDBandwidthNoUrgentBurst);
+#endif
+
+			if (v->DestinationLinesForPrefetch[k] < 2)
+				DestinationLineTimesForPrefetchLessThan2 = true;
+
+			if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
+				VRatioPrefetchMoreThan4 = true;
+
+			if (v->NoUrgentLatencyHiding[k] == true)
+				v->NoEnoughUrgentLatencyHiding = true;
+
+			if (v->NoUrgentLatencyHidingPre[k] == true)
+				v->NoEnoughUrgentLatencyHidingPre = true;
+		}
+
+		v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: MaxTotalRDBandwidthNoUrgentBurst=%f \n", __func__, MaxTotalRDBandwidthNoUrgentBurst);
+		dml_print("DML::%s: ReturnBW=%f \n", __func__, v->ReturnBW);
+		dml_print("DML::%s: FractionOfUrgentBandwidth=%f \n", __func__, v->FractionOfUrgentBandwidth);
+#endif
+
+		if (MaxTotalRDBandwidth <= v->ReturnBW && v->NoEnoughUrgentLatencyHiding == 0 && v->NoEnoughUrgentLatencyHidingPre == 0
+				&& !VRatioPrefetchMoreThan4 && !DestinationLineTimesForPrefetchLessThan2)
+			v->PrefetchModeSupported = true;
+		else {
+			v->PrefetchModeSupported = false;
+			dml_print("DML::%s: ***failed***. Bandwidth violation. Results are NOT valid\n", __func__);
+			dml_print("DML::%s: MaxTotalRDBandwidth:%f AvailReturnBandwidth:%f\n", __func__, MaxTotalRDBandwidth, v->ReturnBW);
+			dml_print("DML::%s: VRatioPrefetch %s more than 4\n", __func__, (VRatioPrefetchMoreThan4) ? "is" : "is not");
+			dml_print("DML::%s: DestinationLines for Prefetch %s less than 2\n", __func__, (DestinationLineTimesForPrefetchLessThan2) ? "is" : "is not");
+		}
+
+		// PREVIOUS_ERROR
+		// This error result check was done after the PrefetchModeSupported. So we will
+		// still try to calculate flip schedule even prefetch mode not supported
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
+				v->PrefetchModeSupported = false;
+				dml_print("DML::%s: ***failed***. Prefetch schedule violation. Results are NOT valid\n", __func__);
+			}
+		}
+
+		if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {
+			v->BandwidthAvailableForImmediateFlip = v->ReturnBW;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
+						- dml_max(
+								v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
+										+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
+										+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
+								v->DPPPerPlane[k]
+										* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
+												+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
+										+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
+			}
+
+			v->TotImmediateFlipBytes = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
+						+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
+			}
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				CalculateFlipSchedule(
+						mode_lib,
+						HostVMInefficiencyFactor,
+						v->UrgentExtraLatency,
+						v->UrgentLatency,
+						v->GPUVMMaxPageTableLevels,
+						v->HostVMEnable,
+						v->HostVMMaxNonCachedPageTableLevels,
+						v->GPUVMEnable,
+						v->HostVMMinPageSize,
+						v->PDEAndMetaPTEBytesFrame[k],
+						v->MetaRowByte[k],
+						v->PixelPTEBytesPerRow[k],
+						v->BandwidthAvailableForImmediateFlip,
+						v->TotImmediateFlipBytes,
+						v->SourcePixelFormat[k],
+						v->HTotal[k] / v->PixelClock[k],
+						v->VRatio[k],
+						v->VRatioChroma[k],
+						v->Tno_bw[k],
+						v->DCCEnable[k],
+						v->dpte_row_height[k],
+						v->meta_row_height[k],
+						v->dpte_row_height_chroma[k],
+						v->meta_row_height_chroma[k],
+						&v->DestinationLinesToRequestVMInImmediateFlip[k],
+						&v->DestinationLinesToRequestRowInImmediateFlip[k],
+						&v->final_flip_bw[k],
+						&v->ImmediateFlipSupportedForPipe[k]);
+			}
+
+			v->total_dcn_read_bw_with_flip = 0.0;
+			v->total_dcn_read_bw_with_flip_no_urgent_burst = 0.0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
+						+ dml_max3(
+								v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+								v->DPPPerPlane[k] * v->final_flip_bw[k]
+										+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
+										+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
+										+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
+								v->DPPPerPlane[k]
+										* (v->final_flip_bw[k]
+												+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
+												+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
+										+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
+				v->total_dcn_read_bw_with_flip_no_urgent_burst = v->total_dcn_read_bw_with_flip_no_urgent_burst
+						+ dml_max3(
+								v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+								v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
+										+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
+								v->DPPPerPlane[k]
+										* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
+												+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
+			}
+			v->FractionOfUrgentBandwidthImmediateFlip = v->total_dcn_read_bw_with_flip_no_urgent_burst / v->ReturnBW;
+
+			v->ImmediateFlipSupported = true;
+			if (v->total_dcn_read_bw_with_flip > v->ReturnBW) {
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: total_dcn_read_bw_with_flip %f (bw w/ flip too high!)\n", __func__, v->total_dcn_read_bw_with_flip);
+#endif
+				v->ImmediateFlipSupported = false;
+				v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth;
+			}
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				if (v->ImmediateFlipSupportedForPipe[k] == false) {
+#ifdef __DML_VBA_DEBUG__
+					dml_print("DML::%s: Pipe %0d not supporting iflip\n",
+						  __func__, k);
+#endif
+					v->ImmediateFlipSupported = false;
+				}
+			}
+		} else {
+			v->ImmediateFlipSupported = false;
+		}
+
+		v->PrefetchAndImmediateFlipSupported =
+				(v->PrefetchModeSupported == true
+						&& ((!v->ImmediateFlipSupport && !v->HostVMEnable
+								&& v->ImmediateFlipRequirement != dm_immediate_flip_required) || v->ImmediateFlipSupported)) ?
+						true : false;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
+		dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required);
+		dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
+		dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
+		dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
+		dml_print("DML::%s: PrefetchAndImmediateFlipSupported %d\n", __func__, v->PrefetchAndImmediateFlipSupported);
+#endif
+		dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup is %d\n", __func__, v->VStartupLines, v->MaximumMaxVStartupLines);
+
+		v->VStartupLines = v->VStartupLines + 1;
+	} while (!v->PrefetchAndImmediateFlipSupported && v->VStartupLines <= v->MaximumMaxVStartupLines);
+	ASSERT(v->PrefetchAndImmediateFlipSupported);
+
+	// Unbounded Request Enabled
+	CalculateUnboundedRequestAndCompressedBufferSize(
+			v->DETBufferSizeInKByte[0],
+			v->ConfigReturnBufferSizeInKByte,
+			v->UseUnboundedRequesting,
+			v->TotalActiveDPP,
+			NoChromaPlanes,
+			v->MaxNumDPP,
+			v->CompressedBufferSegmentSizeInkByte,
+			v->Output,
+			&v->UnboundedRequestEnabled,
+			&v->CompressedBufferSizeInkByte);
+
+	//Watermarks and NB P-State/DRAM Clock Change Support
+	{
+		enum clock_change_support DRAMClockChangeSupport; // dummy
+		CalculateWatermarksAndDRAMSpeedChangeSupport(
+				mode_lib,
+				PrefetchMode,
+				v->NumberOfActivePlanes,
+				v->MaxLineBufferLines,
+				v->LineBufferSize,
+				v->WritebackInterfaceBufferSize,
+				v->DCFCLK,
+				v->ReturnBW,
+				v->SynchronizedVBlank,
+				v->dpte_group_bytes,
+				v->MetaChunkSize,
+				v->UrgentLatency,
+				v->UrgentExtraLatency,
+				v->WritebackLatency,
+				v->WritebackChunkSize,
+				v->SOCCLK,
+				v->DRAMClockChangeLatency,
+				v->SRExitTime,
+				v->SREnterPlusExitTime,
+				v->SRExitZ8Time,
+				v->SREnterPlusExitZ8Time,
+				v->DCFCLKDeepSleep,
+				v->DETBufferSizeY,
+				v->DETBufferSizeC,
+				v->SwathHeightY,
+				v->SwathHeightC,
+				v->LBBitPerPixel,
+				v->SwathWidthY,
+				v->SwathWidthC,
+				v->HRatio,
+				v->HRatioChroma,
+				v->vtaps,
+				v->VTAPsChroma,
+				v->VRatio,
+				v->VRatioChroma,
+				v->HTotal,
+				v->PixelClock,
+				v->BlendingAndTiming,
+				v->DPPPerPlane,
+				v->BytePerPixelDETY,
+				v->BytePerPixelDETC,
+				v->DSTXAfterScaler,
+				v->DSTYAfterScaler,
+				v->WritebackEnable,
+				v->WritebackPixelFormat,
+				v->WritebackDestinationWidth,
+				v->WritebackDestinationHeight,
+				v->WritebackSourceHeight,
+				v->UnboundedRequestEnabled,
+				v->CompressedBufferSizeInkByte,
+				&DRAMClockChangeSupport,
+				&v->UrgentWatermark,
+				&v->WritebackUrgentWatermark,
+				&v->DRAMClockChangeWatermark,
+				&v->WritebackDRAMClockChangeWatermark,
+				&v->StutterExitWatermark,
+				&v->StutterEnterPlusExitWatermark,
+				&v->Z8StutterExitWatermark,
+				&v->Z8StutterEnterPlusExitWatermark,
+				&v->MinActiveDRAMClockChangeLatencySupported);
+
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->WritebackEnable[k] == true) {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
+						0,
+						v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
+			} else {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
+			}
+		}
+	}
+
+	//Display Pipeline Delivery Time in Prefetch, Groups
+	CalculatePixelDeliveryTimes(
+			v->NumberOfActivePlanes,
+			v->VRatio,
+			v->VRatioChroma,
+			v->VRatioPrefetchY,
+			v->VRatioPrefetchC,
+			v->swath_width_luma_ub,
+			v->swath_width_chroma_ub,
+			v->DPPPerPlane,
+			v->HRatio,
+			v->HRatioChroma,
+			v->PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			v->DPPCLK,
+			v->BytePerPixelC,
+			v->SourceScan,
+			v->NumberOfCursors,
+			v->CursorWidth,
+			v->CursorBPP,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesC,
+			v->BlockHeight256BytesC,
+			v->DisplayPipeLineDeliveryTimeLuma,
+			v->DisplayPipeLineDeliveryTimeChroma,
+			v->DisplayPipeLineDeliveryTimeLumaPrefetch,
+			v->DisplayPipeLineDeliveryTimeChromaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeLuma,
+			v->DisplayPipeRequestDeliveryTimeChroma,
+			v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
+			v->CursorRequestDeliveryTime,
+			v->CursorRequestDeliveryTimePrefetch);
+
+	CalculateMetaAndPTETimes(
+			v->NumberOfActivePlanes,
+			v->GPUVMEnable,
+			v->MetaChunkSize,
+			v->MinMetaChunkSizeBytes,
+			v->HTotal,
+			v->VRatio,
+			v->VRatioChroma,
+			v->DestinationLinesToRequestRowInVBlank,
+			v->DestinationLinesToRequestRowInImmediateFlip,
+			v->DCCEnable,
+			v->PixelClock,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->SourceScan,
+			v->dpte_row_height,
+			v->dpte_row_height_chroma,
+			v->meta_row_width,
+			v->meta_row_width_chroma,
+			v->meta_row_height,
+			v->meta_row_height_chroma,
+			v->meta_req_width,
+			v->meta_req_width_chroma,
+			v->meta_req_height,
+			v->meta_req_height_chroma,
+			v->dpte_group_bytes,
+			v->PTERequestSizeY,
+			v->PTERequestSizeC,
+			v->PixelPTEReqWidthY,
+			v->PixelPTEReqHeightY,
+			v->PixelPTEReqWidthC,
+			v->PixelPTEReqHeightC,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+			v->DST_Y_PER_PTE_ROW_NOM_L,
+			v->DST_Y_PER_PTE_ROW_NOM_C,
+			v->DST_Y_PER_META_ROW_NOM_L,
+			v->DST_Y_PER_META_ROW_NOM_C,
+			v->TimePerMetaChunkNominal,
+			v->TimePerChromaMetaChunkNominal,
+			v->TimePerMetaChunkVBlank,
+			v->TimePerChromaMetaChunkVBlank,
+			v->TimePerMetaChunkFlip,
+			v->TimePerChromaMetaChunkFlip,
+			v->time_per_pte_group_nom_luma,
+			v->time_per_pte_group_vblank_luma,
+			v->time_per_pte_group_flip_luma,
+			v->time_per_pte_group_nom_chroma,
+			v->time_per_pte_group_vblank_chroma,
+			v->time_per_pte_group_flip_chroma);
+
+	CalculateVMGroupAndRequestTimes(
+			v->NumberOfActivePlanes,
+			v->GPUVMEnable,
+			v->GPUVMMaxPageTableLevels,
+			v->HTotal,
+			v->BytePerPixelC,
+			v->DestinationLinesToRequestVMInVBlank,
+			v->DestinationLinesToRequestVMInImmediateFlip,
+			v->DCCEnable,
+			v->PixelClock,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+			v->vm_group_bytes,
+			v->dpde0_bytes_per_frame_ub_l,
+			v->dpde0_bytes_per_frame_ub_c,
+			v->meta_pte_bytes_per_frame_ub_l,
+			v->meta_pte_bytes_per_frame_ub_c,
+			v->TimePerVMGroupVBlank,
+			v->TimePerVMGroupFlip,
+			v->TimePerVMRequestVBlank,
+			v->TimePerVMRequestFlip);
+
+	// Min TTUVBlank
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (PrefetchMode == 0) {
+			v->AllowDRAMClockChangeDuringVBlank[k] = true;
+			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
+			v->MinTTUVBlank[k] = dml_max(
+					v->DRAMClockChangeWatermark,
+					dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
+		} else if (PrefetchMode == 1) {
+			v->AllowDRAMClockChangeDuringVBlank[k] = false;
+			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
+			v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
+		} else {
+			v->AllowDRAMClockChangeDuringVBlank[k] = false;
+			v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
+			v->MinTTUVBlank[k] = v->UrgentWatermark;
+		}
+		if (!v->DynamicMetadataEnable[k])
+			v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
+	}
+
+	// DCC Configuration
+	v->ActiveDPPs = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
+				v->SourcePixelFormat[k],
+				v->SurfaceWidthY[k],
+				v->SurfaceWidthC[k],
+				v->SurfaceHeightY[k],
+				v->SurfaceHeightC[k],
+				v->DETBufferSizeInKByte[0] * 1024,
+				v->BlockHeight256BytesY[k],
+				v->BlockHeight256BytesC[k],
+				v->SurfaceTiling[k],
+				v->BytePerPixelY[k],
+				v->BytePerPixelC[k],
+				v->BytePerPixelDETY[k],
+				v->BytePerPixelDETC[k],
+				v->SourceScan[k],
+				&v->DCCYMaxUncompressedBlock[k],
+				&v->DCCCMaxUncompressedBlock[k],
+				&v->DCCYMaxCompressedBlock[k],
+				&v->DCCCMaxCompressedBlock[k],
+				&v->DCCYIndependentBlock[k],
+				&v->DCCCIndependentBlock[k]);
+	}
+
+	// VStartup Adjustment
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		bool isInterlaceTiming;
+		double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
+#endif
+
+		v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
+		dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
+#endif
+
+		v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
+		if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
+			v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
+		}
+
+		isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
+
+		v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k])
+				- v->VFrontPorch[k])
+				+ dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0))
+				+ dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
+
+		v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
+
+		if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
+				<= (isInterlaceTiming ?
+						dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
+						(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
+		} else {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
+		dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
+		dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
+		dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
+		dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
+		dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
+		dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
+		dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
+#endif
+	}
+
+	{
+		//Maximum Bandwidth Used
+		double TotalWRBandwidth = 0;
+		double MaxPerPlaneVActiveWRBandwidth = 0;
+		double WRBandwidth = 0;
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
+				WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+						/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
+			} else if (v->WritebackEnable[k] == true) {
+				WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+						/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
+			}
+			TotalWRBandwidth = TotalWRBandwidth + WRBandwidth;
+			MaxPerPlaneVActiveWRBandwidth = dml_max(MaxPerPlaneVActiveWRBandwidth, WRBandwidth);
+		}
+
+		v->TotalDataReadBandwidth = 0;
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
+		}
+	}
+	// Stutter Efficiency
+	CalculateStutterEfficiency(
+			mode_lib,
+			v->CompressedBufferSizeInkByte,
+			v->UnboundedRequestEnabled,
+			v->ConfigReturnBufferSizeInKByte,
+			v->MetaFIFOSizeInKEntries,
+			v->ZeroSizeBufferEntries,
+			v->NumberOfActivePlanes,
+			v->ROBBufferSizeInKByte,
+			v->TotalDataReadBandwidth,
+			v->DCFCLK,
+			v->ReturnBW,
+			v->COMPBUF_RESERVED_SPACE_64B,
+			v->COMPBUF_RESERVED_SPACE_ZS,
+			v->SRExitTime,
+			v->SRExitZ8Time,
+			v->SynchronizedVBlank,
+			v->StutterEnterPlusExitWatermark,
+			v->Z8StutterEnterPlusExitWatermark,
+			v->ProgressiveToInterlaceUnitInOPP,
+			v->Interlace,
+			v->MinTTUVBlank,
+			v->DPPPerPlane,
+			v->DETBufferSizeY,
+			v->BytePerPixelY,
+			v->BytePerPixelDETY,
+			v->SwathWidthY,
+			v->SwathHeightY,
+			v->SwathHeightC,
+			v->DCCRateLuma,
+			v->DCCRateChroma,
+			v->DCCFractionOfZeroSizeRequestsLuma,
+			v->DCCFractionOfZeroSizeRequestsChroma,
+			v->HTotal,
+			v->VTotal,
+			v->PixelClock,
+			v->VRatio,
+			v->SourceScan,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesC,
+			v->DCCYMaxUncompressedBlock,
+			v->DCCCMaxUncompressedBlock,
+			v->VActive,
+			v->DCCEnable,
+			v->WritebackEnable,
+			v->ReadBandwidthPlaneLuma,
+			v->ReadBandwidthPlaneChroma,
+			v->meta_row_bw,
+			v->dpte_row_bw,
+			&v->StutterEfficiencyNotIncludingVBlank,
+			&v->StutterEfficiency,
+			&v->NumberOfStutterBurstsPerFrame,
+			&v->Z8StutterEfficiencyNotIncludingVBlank,
+			&v->Z8StutterEfficiency,
+			&v->Z8NumberOfStutterBurstsPerFrame,
+			&v->StutterPeriod);
+}
+
+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	// Display Pipe Configuration
+	double BytePerPixDETY[DC__NUM_DPP__MAX];
+	double BytePerPixDETC[DC__NUM_DPP__MAX];
+	int BytePerPixY[DC__NUM_DPP__MAX];
+	int BytePerPixC[DC__NUM_DPP__MAX];
+	int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
+	int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
+	int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
+	int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
+	double dummy1[DC__NUM_DPP__MAX];
+	double dummy2[DC__NUM_DPP__MAX];
+	double dummy3[DC__NUM_DPP__MAX];
+	double dummy4[DC__NUM_DPP__MAX];
+	int dummy5[DC__NUM_DPP__MAX];
+	int dummy6[DC__NUM_DPP__MAX];
+	bool dummy7[DC__NUM_DPP__MAX];
+	bool dummysinglestring;
+
+	unsigned int k;
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+
+		CalculateBytePerPixelAnd256BBlockSizes(
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				&BytePerPixY[k],
+				&BytePerPixC[k],
+				&BytePerPixDETY[k],
+				&BytePerPixDETC[k],
+				&Read256BytesBlockHeightY[k],
+				&Read256BytesBlockHeightC[k],
+				&Read256BytesBlockWidthY[k],
+				&Read256BytesBlockWidthC[k]);
+	}
+
+	CalculateSwathAndDETConfiguration(
+			false,
+			v->NumberOfActivePlanes,
+			v->DETBufferSizeInKByte[0],
+			dummy1,
+			dummy2,
+			v->SourceScan,
+			v->SourcePixelFormat,
+			v->SurfaceTiling,
+			v->ViewportWidth,
+			v->ViewportHeight,
+			v->SurfaceWidthY,
+			v->SurfaceWidthC,
+			v->SurfaceHeightY,
+			v->SurfaceHeightC,
+			Read256BytesBlockHeightY,
+			Read256BytesBlockHeightC,
+			Read256BytesBlockWidthY,
+			Read256BytesBlockWidthC,
+			v->ODMCombineEnabled,
+			v->BlendingAndTiming,
+			BytePerPixY,
+			BytePerPixC,
+			BytePerPixDETY,
+			BytePerPixDETC,
+			v->HActive,
+			v->HRatio,
+			v->HRatioChroma,
+			v->DPPPerPlane,
+			dummy5,
+			dummy6,
+			dummy3,
+			dummy4,
+			v->SwathHeightY,
+			v->SwathHeightC,
+			v->DETBufferSizeY,
+			v->DETBufferSizeC,
+			dummy7,
+			&dummysinglestring);
+}
+
+static bool CalculateBytePerPixelAnd256BBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double *BytePerPixelDETY,
+		double *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC)
+{
+	if (SourcePixelFormat == dm_444_64) {
+		*BytePerPixelDETY = 8;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 8;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_16) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_rgbe_alpha) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 1;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 1;
+	} else if (SourcePixelFormat == dm_420_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 2;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 2;
+	} else if (SourcePixelFormat == dm_420_12) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 4;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	} else {
+		*BytePerPixelDETY = 4.0 / 3;
+		*BytePerPixelDETC = 8.0 / 3;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	}
+
+	if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16
+			|| SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+		} else if (SourcePixelFormat == dm_444_64) {
+			*BlockHeight256BytesY = 4;
+		} else if (SourcePixelFormat == dm_444_8) {
+			*BlockHeight256BytesY = 16;
+		} else {
+			*BlockHeight256BytesY = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockHeight256BytesC = 0;
+		*BlockWidth256BytesC = 0;
+	} else {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+			*BlockHeight256BytesC = 1;
+		} else if (SourcePixelFormat == dm_rgbe_alpha) {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 16;
+		} else if (SourcePixelFormat == dm_420_8) {
+			*BlockHeight256BytesY = 16;
+			*BlockHeight256BytesC = 8;
+		} else {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;
+	}
+	return true;
+}
+
+static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime)
+{
+	if (PrefetchMode == 0) {
+		return dml_max(DRAMClockChangeLatency + UrgentLatency, dml_max(SREnterPlusExitTime, UrgentLatency));
+	} else if (PrefetchMode == 1) {
+		return dml_max(SREnterPlusExitTime, UrgentLatency);
+	} else {
+		return UrgentLatency;
+	}
+}
+
+double dml31_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		long WritebackSourceWidth,
+		long WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize)
+{
+	double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
+
+	DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
+	DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
+	DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
+	return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
+}
+
+static double CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		int WritebackDestinationWidth,
+		int WritebackDestinationHeight,
+		int WritebackSourceHeight,
+		unsigned int HTotal)
+{
+	double CalculateWriteBackDelay;
+	double Line_length;
+	double Output_lines_last_notclamped;
+	double WritebackVInit;
+
+	WritebackVInit = (WritebackVRatio + WritebackVTaps + 1) / 2;
+	Line_length = dml_max((double) WritebackDestinationWidth, dml_ceil(WritebackDestinationWidth / 6.0, 1) * WritebackVTaps);
+	Output_lines_last_notclamped = WritebackDestinationHeight - 1 - dml_ceil((WritebackSourceHeight - WritebackVInit) / WritebackVRatio, 1);
+	if (Output_lines_last_notclamped < 0) {
+		CalculateWriteBackDelay = 0;
+	} else {
+		CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length + (HTotal - WritebackDestinationWidth) + 80;
+	}
+	return CalculateWriteBackDelay;
+}
+
+static void CalculateVupdateAndDynamicMetadataParameters(
+		int MaxInterDCNTileRepeaters,
+		double DPPCLK,
+		double DISPCLK,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		int HTotal,
+		int VBlank,
+		int DynamicMetadataTransmittedBytes,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix)
+{
+	double TotalRepeaterDelayTime;
+
+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK);
+	*VUpdateWidthPix = dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock, 1.0);
+	*VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0);
+	*VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
+	*TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;
+	*Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
+	*Tdmec = HTotal / PixelClock;
+	if (DynamicMetadataLinesBeforeActiveRequired == 0) {
+		*Tdmsks = VBlank * HTotal / PixelClock / 2.0;
+	} else {
+		*Tdmsks = DynamicMetadataLinesBeforeActiveRequired * HTotal / PixelClock;
+	}
+	if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
+		*Tdmsks = *Tdmsks / 2;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VUpdateWidthPix = %d\n", __func__, *VUpdateWidthPix);
+	dml_print("DML::%s: VReadyOffsetPix = %d\n", __func__, *VReadyOffsetPix);
+	dml_print("DML::%s: VUpdateOffsetPix = %d\n", __func__, *VUpdateOffsetPix);
+#endif
+}
+
+static void CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		double *meta_row_bw,
+		double *dpte_row_bw)
+{
+	if (DCCEnable != true) {
+		*meta_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || SourcePixelFormat == dm_rgbe_alpha) {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) + VRatioChroma * MetaRowByteChroma / (meta_row_height_chroma * LineTime);
+	} else {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
+	}
+
+	if (GPUVMEnable != true) {
+		*dpte_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || SourcePixelFormat == dm_rgbe_alpha) {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)
+				+ VRatioChroma * PixelPTEBytesPerRowChroma / (dpte_row_height_chroma * LineTime);
+	} else {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
+	}
+}
+
+static void CalculateFlipSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe)
+{
+	double min_row_time = 0.0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double TimeForFetchingMetaPTEImmediateFlip;
+	double TimeForFetchingRowInVBlankImmediateFlip;
+	double ImmediateFlipBW;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	} else {
+		HostVMDynamicLevelsTrips = 0;
+	}
+
+	if (GPUVMEnable == true || DCCEnable == true) {
+		ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
+	}
+
+	if (GPUVMEnable == true) {
+		TimeForFetchingMetaPTEImmediateFlip = dml_max3(
+				Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
+				UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
+				LineTime / 4.0);
+	} else {
+		TimeForFetchingMetaPTEImmediateFlip = 0;
+	}
+
+	*DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
+	if ((GPUVMEnable == true || DCCEnable == true)) {
+		TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
+				(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW,
+				UrgentLatency * (HostVMDynamicLevelsTrips + 1),
+				LineTime / 4);
+	} else {
+		TimeForFetchingRowInVBlankImmediateFlip = 0;
+	}
+
+	*DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
+
+	if (GPUVMEnable == true) {
+		*final_flip_bw = dml_max(
+				PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime),
+				(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime));
+	} else if ((GPUVMEnable == true || DCCEnable == true)) {
+		*final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime);
+	} else {
+		*final_flip_bw = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma);
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma);
+		} else {
+			min_row_time = dml_min4(
+					dpte_row_height * LineTime / VRatio,
+					meta_row_height * LineTime / VRatio,
+					dpte_row_height_chroma * LineTime / VRatioChroma,
+					meta_row_height_chroma * LineTime / VRatioChroma);
+		}
+	} else {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dpte_row_height * LineTime / VRatio;
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = meta_row_height * LineTime / VRatio;
+		} else {
+			min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
+		}
+	}
+
+	if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16
+			|| TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) {
+		*ImmediateFlipSupportedForPipe = false;
+	} else {
+		*ImmediateFlipSupportedForPipe = true;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestVMInImmediateFlip);
+	dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestRowInImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n", __func__, TimeForFetchingRowInVBlankImmediateFlip);
+	dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time);
+	dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe);
+#endif
+
+}
+
+static double TruncToValidBPP(
+		double LinkBitRate,
+		int Lanes,
+		int HTotal,
+		int HActive,
+		double PixelClock,
+		double DesiredBPP,
+		bool DSCEnable,
+		enum output_encoder_class Output,
+		enum output_format_class Format,
+		unsigned int DSCInputBitPerComponent,
+		int DSCSlices,
+		int AudioRate,
+		int AudioLayout,
+		enum odm_combine_mode ODMCombine)
+{
+	double MaxLinkBPP;
+	int MinDSCBPP;
+	double MaxDSCBPP;
+	int NonDSCBPP0;
+	int NonDSCBPP1;
+	int NonDSCBPP2;
+
+	if (Format == dm_420) {
+		NonDSCBPP0 = 12;
+		NonDSCBPP1 = 15;
+		NonDSCBPP2 = 18;
+		MinDSCBPP = 6;
+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;
+	} else if (Format == dm_444) {
+		NonDSCBPP0 = 24;
+		NonDSCBPP1 = 30;
+		NonDSCBPP2 = 36;
+		MinDSCBPP = 8;
+		MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
+	} else {
+		if (Output == dm_hdmi) {
+			NonDSCBPP0 = 24;
+			NonDSCBPP1 = 24;
+			NonDSCBPP2 = 24;
+		} else {
+			NonDSCBPP0 = 16;
+			NonDSCBPP1 = 20;
+			NonDSCBPP2 = 24;
+		}
+		if (Format == dm_n422) {
+			MinDSCBPP = 7;
+			MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0;
+		} else {
+			MinDSCBPP = 8;
+			MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16.0;
+		}
+	}
+
+	if (DSCEnable && Output == dm_dp) {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock * (1 - 2.4 / 100);
+	} else {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock;
+	}
+
+	if (ODMCombine == dm_odm_combine_mode_4to1 && MaxLinkBPP > 16) {
+		MaxLinkBPP = 16;
+	} else if (ODMCombine == dm_odm_combine_mode_2to1 && MaxLinkBPP > 32) {
+		MaxLinkBPP = 32;
+	}
+
+	if (DesiredBPP == 0) {
+		if (DSCEnable) {
+			if (MaxLinkBPP < MinDSCBPP) {
+				return BPP_INVALID;
+			} else if (MaxLinkBPP >= MaxDSCBPP) {
+				return MaxDSCBPP;
+			} else {
+				return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0;
+			}
+		} else {
+			if (MaxLinkBPP >= NonDSCBPP2) {
+				return NonDSCBPP2;
+			} else if (MaxLinkBPP >= NonDSCBPP1) {
+				return NonDSCBPP1;
+			} else if (MaxLinkBPP >= NonDSCBPP0) {
+				return 16.0;
+			} else {
+				return BPP_INVALID;
+			}
+		}
+	} else {
+		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <= NonDSCBPP0))
+				|| (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
+			return BPP_INVALID;
+		} else {
+			return DesiredBPP;
+		}
+	}
+	return BPP_INVALID;
+}
+
+void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+
+	int i, j;
+	unsigned int k, m;
+	int ReorderingBytes;
+	int MinPrefetchMode = 0, MaxPrefetchMode = 2;
+	bool NoChroma = true;
+	bool EnoughWritebackUnits = true;
+	bool P2IWith420 = false;
+	bool DSCOnlyIfNecessaryWithBPP = false;
+	bool DSC422NativeNotSupported = false;
+	double MaxTotalVActiveRDBandwidth;
+	bool ViewportExceedsSurface = false;
+	bool FMTBufferExceeded = false;
+
+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
+
+	CalculateMinAndMaxPrefetchMode(
+		mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
+		&MinPrefetchMode, &MaxPrefetchMode);
+
+	/*Scale Ratio, taps Support Check*/
+
+	v->ScaleRatioAndTapsSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->ScalerEnabled[k] == false
+				&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
+						&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
+						&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
+						&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
+						|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
+			v->ScaleRatioAndTapsSupport = false;
+		} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
+				|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
+				|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
+				|| v->VRatio[k] > v->vtaps[k]
+				|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
+						&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
+						&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
+						&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
+								|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
+								|| v->HRatioChroma[k] > v->MaxHSCLRatio
+								|| v->VRatioChroma[k] > v->MaxVSCLRatio
+								|| v->HRatioChroma[k] > v->HTAPsChroma[k]
+								|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
+			v->ScaleRatioAndTapsSupport = false;
+		}
+	}
+	/*Source Format, Pixel Format and Scan Support Check*/
+
+	v->SourceFormatPixelAndScanSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
+				|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t
+						|| v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) {
+			v->SourceFormatPixelAndScanSupport = false;
+		}
+	}
+	/*Bandwidth Support Check*/
+
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		CalculateBytePerPixelAnd256BBlockSizes(
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				&v->BytePerPixelY[k],
+				&v->BytePerPixelC[k],
+				&v->BytePerPixelInDETY[k],
+				&v->BytePerPixelInDETC[k],
+				&v->Read256BlockHeightY[k],
+				&v->Read256BlockHeightC[k],
+				&v->Read256BlockWidthY[k],
+				&v->Read256BlockWidthC[k]);
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->SourceScan[k] != dm_vert) {
+			v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
+			v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
+		} else {
+			v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
+			v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
+		}
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
+				/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
+		v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
+				/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
+			v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+					/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
+		} else if (v->WritebackEnable[k] == true) {
+			v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+					/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
+		} else {
+			v->WriteBandwidth[k] = 0.0;
+		}
+	}
+
+	/*Writeback Latency support check*/
+
+	v->WritebackLatencySupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
+			v->WritebackLatencySupport = false;
+		}
+	}
+
+	/*Writeback Mode Support Check*/
+
+	v->TotalNumberOfActiveWriteback = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true) {
+			v->TotalNumberOfActiveWriteback = v->TotalNumberOfActiveWriteback + 1;
+		}
+	}
+
+	if (v->TotalNumberOfActiveWriteback > v->MaxNumWriteback) {
+		EnoughWritebackUnits = false;
+	}
+
+	/*Writeback Scale Ratio and Taps Support Check*/
+
+	v->WritebackScaleRatioAndTapsSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true) {
+			if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
+					|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
+					|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
+					|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
+					|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
+					|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
+					|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
+				v->WritebackScaleRatioAndTapsSupport = false;
+			}
+			if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
+				v->WritebackScaleRatioAndTapsSupport = false;
+			}
+		}
+	}
+	/*Maximum DISPCLK/DPPCLK Support check*/
+
+	v->WritebackRequiredDISPCLK = 0.0;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true) {
+			v->WritebackRequiredDISPCLK = dml_max(
+					v->WritebackRequiredDISPCLK,
+					dml31_CalculateWriteBackDISPCLK(
+							v->WritebackPixelFormat[k],
+							v->PixelClock[k],
+							v->WritebackHRatio[k],
+							v->WritebackVRatio[k],
+							v->WritebackHTaps[k],
+							v->WritebackVTaps[k],
+							v->WritebackSourceWidth[k],
+							v->WritebackDestinationWidth[k],
+							v->HTotal[k],
+							v->WritebackLineBufferSize));
+		}
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->HRatio[k] > 1.0) {
+			v->PSCL_FACTOR[k] = dml_min(
+					v->MaxDCHUBToPSCLThroughput,
+					v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
+		} else {
+			v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+		}
+		if (v->BytePerPixelC[k] == 0.0) {
+			v->PSCL_FACTOR_CHROMA[k] = 0.0;
+			v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
+					* dml_max3(
+							v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
+							v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
+							1.0);
+			if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
+				v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
+			}
+		} else {
+			if (v->HRatioChroma[k] > 1.0) {
+				v->PSCL_FACTOR_CHROMA[k] = dml_min(
+						v->MaxDCHUBToPSCLThroughput,
+						v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
+			} else {
+				v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+			}
+			v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
+					* dml_max5(
+							v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
+							v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
+							v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
+							v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
+							1.0);
+			if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
+					&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
+				v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
+			}
+		}
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		int MaximumSwathWidthSupportLuma;
+		int MaximumSwathWidthSupportChroma;
+
+		if (v->SurfaceTiling[k] == dm_sw_linear) {
+			MaximumSwathWidthSupportLuma = 8192.0;
+		} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
+			MaximumSwathWidthSupportLuma = 2880.0;
+		} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
+			MaximumSwathWidthSupportLuma = 3840.0;
+		} else {
+			MaximumSwathWidthSupportLuma = 5760.0;
+		}
+
+		if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
+			MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0;
+		} else {
+			MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma;
+		}
+		v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
+				/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
+		if (v->BytePerPixelC[k] == 0.0) {
+			v->MaximumSwathWidthInLineBufferChroma = 0;
+		} else {
+			v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
+					/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
+		}
+		v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
+		v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
+	}
+
+	CalculateSwathAndDETConfiguration(
+			true,
+			v->NumberOfActivePlanes,
+			v->DETBufferSizeInKByte[0],
+			v->MaximumSwathWidthLuma,
+			v->MaximumSwathWidthChroma,
+			v->SourceScan,
+			v->SourcePixelFormat,
+			v->SurfaceTiling,
+			v->ViewportWidth,
+			v->ViewportHeight,
+			v->SurfaceWidthY,
+			v->SurfaceWidthC,
+			v->SurfaceHeightY,
+			v->SurfaceHeightC,
+			v->Read256BlockHeightY,
+			v->Read256BlockHeightC,
+			v->Read256BlockWidthY,
+			v->Read256BlockWidthC,
+			v->odm_combine_dummy,
+			v->BlendingAndTiming,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->BytePerPixelInDETY,
+			v->BytePerPixelInDETC,
+			v->HActive,
+			v->HRatio,
+			v->HRatioChroma,
+			v->NoOfDPPThisState,
+			v->swath_width_luma_ub_this_state,
+			v->swath_width_chroma_ub_this_state,
+			v->SwathWidthYThisState,
+			v->SwathWidthCThisState,
+			v->SwathHeightYThisState,
+			v->SwathHeightCThisState,
+			v->DETBufferSizeYThisState,
+			v->DETBufferSizeCThisState,
+			v->SingleDPPViewportSizeSupportPerPlane,
+			&v->ViewportSizeSupport[0][0]);
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			v->MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDispclk[i], v->DISPCLKDPPCLKVCOSpeed);
+			v->MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDppclk[i], v->DISPCLKDPPCLKVCOSpeed);
+			v->RequiredDISPCLK[i][j] = 0.0;
+			v->DISPCLK_DPPCLK_Support[i][j] = true;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						* (1.0 + v->DISPCLKRampingMargin / 100.0);
+				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i]
+						&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+					v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
+							* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				}
+				v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						* (1 + v->DISPCLKRampingMargin / 100.0);
+				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i]
+						&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+					v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
+							* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				}
+				v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						* (1 + v->DISPCLKRampingMargin / 100.0);
+				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i]
+						&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+					v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
+							* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				}
+
+				if (v->ODMCombinePolicy == dm_odm_combine_policy_none
+						|| !(v->Output[k] == dm_dp ||
+						     v->Output[k] == dm_edp)) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
+
+					if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
+						FMTBufferExceeded = true;
+				} else if (v->ODMCombinePolicy == dm_odm_combine_policy_2to1) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+				} else if (v->ODMCombinePolicy == dm_odm_combine_policy_4to1
+						|| v->PlaneRequiredDISPCLKWithODMCombine2To1 > v->MaxDispclkRoundedDownToDFSGranularity) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+				} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+				} else {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
+				}
+				if (v->DSCEnabled[k] && v->HActive[k] > DCN31_MAX_DSC_IMAGE_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN31_MAX_DSC_IMAGE_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+					}
+				}
+				if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+
+						if (v->HActive[k] / 4 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
+							FMTBufferExceeded = true;
+					} else {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+					}
+				}
+				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					v->MPCCombine[i][j][k] = false;
+					v->NoOfDPP[i][j][k] = 4;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
+				} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					v->MPCCombine[i][j][k] = false;
+					v->NoOfDPP[i][j][k] = 2;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
+				} else if ((v->WhenToDoMPCCombine == dm_mpc_never
+						|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+								<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
+					v->MPCCombine[i][j][k] = false;
+					v->NoOfDPP[i][j][k] = 1;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				} else {
+					v->MPCCombine[i][j][k] = true;
+					v->NoOfDPP[i][j][k] = 2;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
+				}
+				v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
+				if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						> v->MaxDppclkRoundedDownToDFSGranularity)
+						|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
+					v->DISPCLK_DPPCLK_Support[i][j] = false;
+				}
+			}
+			v->TotalNumberOfActiveDPP[i][j] = 0;
+			v->TotalNumberOfSingleDPPPlanes[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
+				if (v->NoOfDPP[i][j][k] == 1)
+					v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] + 1;
+				if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
+						|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
+					NoChroma = false;
+			}
+
+			// UPTO
+			if (j == 1 && v->WhenToDoMPCCombine != dm_mpc_never
+					&& !UnboundedRequest(v->UseUnboundedRequesting, v->TotalNumberOfActiveDPP[i][j], NoChroma, v->Output[0])) {
+				while (!(v->TotalNumberOfActiveDPP[i][j] >= v->MaxNumDPP || v->TotalNumberOfSingleDPPPlanes[i][j] == 0)) {
+					double BWOfNonSplitPlaneOfMaximumBandwidth;
+					unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth;
+					BWOfNonSplitPlaneOfMaximumBandwidth = 0;
+					NumberOfNonSplitPlaneOfMaximumBandwidth = 0;
+					for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+						if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
+								&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
+							BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
+							NumberOfNonSplitPlaneOfMaximumBandwidth = k;
+						}
+					}
+					v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;
+					v->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
+					v->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
+							v->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
+									* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
+					v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + 1;
+					v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] - 1;
+				}
+			}
+			if (v->TotalNumberOfActiveDPP[i][j] > v->MaxNumDPP) {
+				v->RequiredDISPCLK[i][j] = 0.0;
+				v->DISPCLK_DPPCLK_Support[i][j] = true;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
+					if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
+						v->MPCCombine[i][j][k] = true;
+						v->NoOfDPP[i][j][k] = 2;
+						v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
+								* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
+					} else {
+						v->MPCCombine[i][j][k] = false;
+						v->NoOfDPP[i][j][k] = 1;
+						v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
+								* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+					}
+					if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+							&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+						v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+								* (1.0 + v->DISPCLKRampingMargin / 100.0);
+					} else {
+						v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+					}
+					v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
+					if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+							> v->MaxDppclkRoundedDownToDFSGranularity)
+							|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
+						v->DISPCLK_DPPCLK_Support[i][j] = false;
+					}
+				}
+				v->TotalNumberOfActiveDPP[i][j] = 0.0;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
+				}
+			}
+			v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
+			if (v->MaxDispclkRoundedDownToDFSGranularity < v->WritebackRequiredDISPCLK) {
+				v->DISPCLK_DPPCLK_Support[i][j] = false;
+			}
+		}
+	}
+
+	/*Total Available Pipes Support Check*/
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			if (v->TotalNumberOfActiveDPP[i][j] <= v->MaxNumDPP) {
+				v->TotalAvailablePipesSupport[i][j] = true;
+			} else {
+				v->TotalAvailablePipesSupport[i][j] = false;
+			}
+		}
+	}
+	/*Display IO and DSC Support Check*/
+
+	v->NonsupportedDSCInputBPC = false;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
+				|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
+			v->NonsupportedDSCInputBPC = true;
+		}
+	}
+
+	/*Number Of DSC Slices*/
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k) {
+			if (v->PixelClockBackEnd[k] > 3200) {
+				v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
+			} else if (v->PixelClockBackEnd[k] > 1360) {
+				v->NumberOfDSCSlices[k] = 8;
+			} else if (v->PixelClockBackEnd[k] > 680) {
+				v->NumberOfDSCSlices[k] = 4;
+			} else if (v->PixelClockBackEnd[k] > 340) {
+				v->NumberOfDSCSlices[k] = 2;
+			} else {
+				v->NumberOfDSCSlices[k] = 1;
+			}
+		} else {
+			v->NumberOfDSCSlices[k] = 0;
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			v->RequiresDSC[i][k] = false;
+			v->RequiresFEC[i][k] = false;
+			if (v->BlendingAndTiming[k] == k) {
+				if (v->Output[k] == dm_hdmi) {
+					v->RequiresDSC[i][k] = false;
+					v->RequiresFEC[i][k] = false;
+					v->OutputBppPerState[i][k] = TruncToValidBPP(
+							dml_min(600.0, v->PHYCLKPerState[i]) * 10,
+							3,
+							v->HTotal[k],
+							v->HActive[k],
+							v->PixelClockBackEnd[k],
+							v->ForcedOutputLinkBPP[k],
+							false,
+							v->Output[k],
+							v->OutputFormat[k],
+							v->DSCInputBitPerComponent[k],
+							v->NumberOfDSCSlices[k],
+							v->AudioSampleRate[k],
+							v->AudioSampleLayout[k],
+							v->ODMCombineEnablePerState[i][k]);
+				} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
+					if (v->DSCEnable[k] == true) {
+						v->RequiresDSC[i][k] = true;
+						v->LinkDSCEnable = true;
+						if (v->Output[k] == dm_dp) {
+							v->RequiresFEC[i][k] = true;
+						} else {
+							v->RequiresFEC[i][k] = false;
+						}
+					} else {
+						v->RequiresDSC[i][k] = false;
+						v->LinkDSCEnable = false;
+						v->RequiresFEC[i][k] = false;
+					}
+
+					v->Outbpp = BPP_INVALID;
+					if (v->PHYCLKPerState[i] >= 270.0) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 2700,
+								v->OutputLinkDPLanes[k],
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						// TODO: Need some other way to handle this nonsense
+						// v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR"
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 5400,
+								v->OutputLinkDPLanes[k],
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						// TODO: Need some other way to handle this nonsense
+						// v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR2"
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 8100,
+								v->OutputLinkDPLanes[k],
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						// TODO: Need some other way to handle this nonsense
+						// v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR3"
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[i] >= 10000.0 / 18) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 10000,
+								4,
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						//v->OutputTypeAndRatePerState[i][k] = v->Output[k] & "10x4";
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[i] >= 12000.0 / 18) {
+						v->Outbpp = TruncToValidBPP(
+								12000,
+								4,
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						//v->OutputTypeAndRatePerState[i][k] = v->Output[k] & "12x4";
+					}
+				}
+			} else {
+				v->OutputBppPerState[i][k] = 0;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		v->LinkCapacitySupport[i] = true;
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			if (v->BlendingAndTiming[k] == k
+					&& (v->Output[k] == dm_dp ||
+					    v->Output[k] == dm_edp ||
+					    v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
+				v->LinkCapacitySupport[i] = false;
+			}
+		}
+	}
+
+	// UPTO 2172
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k
+				&& (v->Output[k] == dm_dp ||
+				    v->Output[k] == dm_edp ||
+				    v->Output[k] == dm_hdmi)) {
+			if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
+				P2IWith420 = true;
+			}
+			if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
+					&& !v->DSC422NativeSupport) {
+				DSC422NativeNotSupported = true;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		v->ODMCombine4To1SupportCheckOK[i] = true;
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
+					&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
+							|| v->Output[k] == dm_hdmi)) {
+				v->ODMCombine4To1SupportCheckOK[i] = false;
+			}
+		}
+	}
+
+	/* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		v->NotEnoughDSCUnits[i] = false;
+		v->TotalDSCUnitsRequired = 0.0;
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			if (v->RequiresDSC[i][k] == true) {
+				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 4.0;
+				} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 2.0;
+				} else {
+					v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 1.0;
+				}
+			}
+		}
+		if (v->TotalDSCUnitsRequired > v->NumberOfDSC) {
+			v->NotEnoughDSCUnits[i] = true;
+		}
+	}
+	/*DSC Delay per state*/
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			if (v->OutputBppPerState[i][k] == BPP_INVALID) {
+				v->BPP = 0.0;
+			} else {
+				v->BPP = v->OutputBppPerState[i][k];
+			}
+			if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
+				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
+					v->DSCDelayPerState[i][k] = dscceComputeDelay(
+							v->DSCInputBitPerComponent[k],
+							v->BPP,
+							dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
+							v->NumberOfDSCSlices[k],
+							v->OutputFormat[k],
+							v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
+				} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					v->DSCDelayPerState[i][k] = 2.0
+							* (dscceComputeDelay(
+									v->DSCInputBitPerComponent[k],
+									v->BPP,
+									dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
+									v->NumberOfDSCSlices[k] / 2,
+									v->OutputFormat[k],
+									v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+				} else {
+					v->DSCDelayPerState[i][k] = 4.0
+							* (dscceComputeDelay(
+									v->DSCInputBitPerComponent[k],
+									v->BPP,
+									dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
+									v->NumberOfDSCSlices[k] / 4,
+									v->OutputFormat[k],
+									v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+				}
+				v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
+			} else {
+				v->DSCDelayPerState[i][k] = 0.0;
+			}
+		}
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			for (m = 0; m < v->NumberOfActivePlanes; m++) {
+				if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
+					v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
+				}
+			}
+		}
+	}
+
+	//Calculate Swath, DET Configuration, DCFCLKDeepSleep
+	//
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
+				v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
+				v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
+			}
+
+			CalculateSwathAndDETConfiguration(
+					false,
+					v->NumberOfActivePlanes,
+					v->DETBufferSizeInKByte[0],
+					v->MaximumSwathWidthLuma,
+					v->MaximumSwathWidthChroma,
+					v->SourceScan,
+					v->SourcePixelFormat,
+					v->SurfaceTiling,
+					v->ViewportWidth,
+					v->ViewportHeight,
+					v->SurfaceWidthY,
+					v->SurfaceWidthC,
+					v->SurfaceHeightY,
+					v->SurfaceHeightC,
+					v->Read256BlockHeightY,
+					v->Read256BlockHeightC,
+					v->Read256BlockWidthY,
+					v->Read256BlockWidthC,
+					v->ODMCombineEnableThisState,
+					v->BlendingAndTiming,
+					v->BytePerPixelY,
+					v->BytePerPixelC,
+					v->BytePerPixelInDETY,
+					v->BytePerPixelInDETC,
+					v->HActive,
+					v->HRatio,
+					v->HRatioChroma,
+					v->NoOfDPPThisState,
+					v->swath_width_luma_ub_this_state,
+					v->swath_width_chroma_ub_this_state,
+					v->SwathWidthYThisState,
+					v->SwathWidthCThisState,
+					v->SwathHeightYThisState,
+					v->SwathHeightCThisState,
+					v->DETBufferSizeYThisState,
+					v->DETBufferSizeCThisState,
+					v->dummystring,
+					&v->ViewportSizeSupport[i][j]);
+
+			CalculateDCFCLKDeepSleep(
+					mode_lib,
+					v->NumberOfActivePlanes,
+					v->BytePerPixelY,
+					v->BytePerPixelC,
+					v->VRatio,
+					v->VRatioChroma,
+					v->SwathWidthYThisState,
+					v->SwathWidthCThisState,
+					v->NoOfDPPThisState,
+					v->HRatio,
+					v->HRatioChroma,
+					v->PixelClock,
+					v->PSCL_FACTOR,
+					v->PSCL_FACTOR_CHROMA,
+					v->RequiredDPPCLKThisState,
+					v->ReadBandwidthLuma,
+					v->ReadBandwidthChroma,
+					v->ReturnBusWidth,
+					&v->ProjectedDCFCLKDeepSleep[i][j]);
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
+				v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
+				v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
+				v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
+				v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
+				v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
+				v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
+				v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
+			}
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+				/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			bool NotUrgentLatencyHiding[DC__NUM_DPP__MAX];
+
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
+				v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
+				v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
+				v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
+				v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
+				v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
+				v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
+				v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
+			}
+
+			v->TotalNumberOfDCCActiveDPP[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				if (v->DCCEnable[k] == true) {
+					v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
+				}
+			}
+
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
+						|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
+
+					if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
+							&& v->SourceScan[k] != dm_vert) {
+						v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma)
+								/ 2;
+						v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
+					} else {
+						v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
+						v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
+					}
+
+					v->PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
+							mode_lib,
+							v->DCCEnable[k],
+							v->Read256BlockHeightC[k],
+							v->Read256BlockWidthC[k],
+							v->SourcePixelFormat[k],
+							v->SurfaceTiling[k],
+							v->BytePerPixelC[k],
+							v->SourceScan[k],
+							v->SwathWidthCThisState[k],
+							v->ViewportHeightChroma[k],
+							v->GPUVMEnable,
+							v->HostVMEnable,
+							v->HostVMMaxNonCachedPageTableLevels,
+							v->GPUVMMinPageSize,
+							v->HostVMMinPageSize,
+							v->PTEBufferSizeInRequestsForChroma,
+							v->PitchC[k],
+							0.0,
+							&v->MacroTileWidthC[k],
+							&v->MetaRowBytesC,
+							&v->DPTEBytesPerRowC,
+							&v->PTEBufferSizeNotExceededC[i][j][k],
+							&v->dummyinteger7,
+							&v->dpte_row_height_chroma[k],
+							&v->dummyinteger28,
+							&v->dummyinteger26,
+							&v->dummyinteger23,
+							&v->meta_row_height_chroma[k],
+							&v->dummyinteger8,
+							&v->dummyinteger9,
+							&v->dummyinteger19,
+							&v->dummyinteger20,
+							&v->dummyinteger17,
+							&v->dummyinteger10,
+							&v->dummyinteger11);
+
+					v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
+							mode_lib,
+							v->VRatioChroma[k],
+							v->VTAPsChroma[k],
+							v->Interlace[k],
+							v->ProgressiveToInterlaceUnitInOPP,
+							v->SwathHeightCThisState[k],
+							v->ViewportYStartC[k],
+							&v->PrefillC[k],
+							&v->MaxNumSwC[k]);
+				} else {
+					v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
+					v->PTEBufferSizeInRequestsForChroma = 0;
+					v->PDEAndMetaPTEBytesPerFrameC = 0.0;
+					v->MetaRowBytesC = 0.0;
+					v->DPTEBytesPerRowC = 0.0;
+					v->PrefetchLinesC[i][j][k] = 0.0;
+					v->PTEBufferSizeNotExceededC[i][j][k] = true;
+				}
+				v->PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
+						mode_lib,
+						v->DCCEnable[k],
+						v->Read256BlockHeightY[k],
+						v->Read256BlockWidthY[k],
+						v->SourcePixelFormat[k],
+						v->SurfaceTiling[k],
+						v->BytePerPixelY[k],
+						v->SourceScan[k],
+						v->SwathWidthYThisState[k],
+						v->ViewportHeight[k],
+						v->GPUVMEnable,
+						v->HostVMEnable,
+						v->HostVMMaxNonCachedPageTableLevels,
+						v->GPUVMMinPageSize,
+						v->HostVMMinPageSize,
+						v->PTEBufferSizeInRequestsForLuma,
+						v->PitchY[k],
+						v->DCCMetaPitchY[k],
+						&v->MacroTileWidthY[k],
+						&v->MetaRowBytesY,
+						&v->DPTEBytesPerRowY,
+						&v->PTEBufferSizeNotExceededY[i][j][k],
+						&v->dummyinteger7,
+						&v->dpte_row_height[k],
+						&v->dummyinteger29,
+						&v->dummyinteger27,
+						&v->dummyinteger24,
+						&v->meta_row_height[k],
+						&v->dummyinteger25,
+						&v->dpte_group_bytes[k],
+						&v->dummyinteger21,
+						&v->dummyinteger22,
+						&v->dummyinteger18,
+						&v->dummyinteger5,
+						&v->dummyinteger6);
+				v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
+						mode_lib,
+						v->VRatio[k],
+						v->vtaps[k],
+						v->Interlace[k],
+						v->ProgressiveToInterlaceUnitInOPP,
+						v->SwathHeightYThisState[k],
+						v->ViewportYStartY[k],
+						&v->PrefillY[k],
+						&v->MaxNumSwY[k]);
+				v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
+				v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
+				v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
+
+				CalculateRowBandwidth(
+						v->GPUVMEnable,
+						v->SourcePixelFormat[k],
+						v->VRatio[k],
+						v->VRatioChroma[k],
+						v->DCCEnable[k],
+						v->HTotal[k] / v->PixelClock[k],
+						v->MetaRowBytesY,
+						v->MetaRowBytesC,
+						v->meta_row_height[k],
+						v->meta_row_height_chroma[k],
+						v->DPTEBytesPerRowY,
+						v->DPTEBytesPerRowC,
+						v->dpte_row_height[k],
+						v->dpte_row_height_chroma[k],
+						&v->meta_row_bandwidth[i][j][k],
+						&v->dpte_row_bandwidth[i][j][k]);
+			}
+			v->UrgLatency[i] = CalculateUrgentLatency(
+					v->UrgentLatencyPixelDataOnly,
+					v->UrgentLatencyPixelMixedWithVMData,
+					v->UrgentLatencyVMDataOnly,
+					v->DoUrgentLatencyAdjustment,
+					v->UrgentLatencyAdjustmentFabricClockComponent,
+					v->UrgentLatencyAdjustmentFabricClockReference,
+					v->FabricClockPerState[i]);
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				CalculateUrgentBurstFactor(
+						v->swath_width_luma_ub_this_state[k],
+						v->swath_width_chroma_ub_this_state[k],
+						v->SwathHeightYThisState[k],
+						v->SwathHeightCThisState[k],
+						v->HTotal[k] / v->PixelClock[k],
+						v->UrgLatency[i],
+						v->CursorBufferSize,
+						v->CursorWidth[k][0],
+						v->CursorBPP[k][0],
+						v->VRatio[k],
+						v->VRatioChroma[k],
+						v->BytePerPixelInDETY[k],
+						v->BytePerPixelInDETC[k],
+						v->DETBufferSizeYThisState[k],
+						v->DETBufferSizeCThisState[k],
+						&v->UrgentBurstFactorCursor[k],
+						&v->UrgentBurstFactorLuma[k],
+						&v->UrgentBurstFactorChroma[k],
+						&NotUrgentLatencyHiding[k]);
+			}
+
+			v->NotEnoughUrgentLatencyHidingA[i][j] = false;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				if (NotUrgentLatencyHiding[k]) {
+					v->NotEnoughUrgentLatencyHidingA[i][j] = true;
+				}
+			}
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
+						+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
+				v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
+			}
+
+			v->TotalVActivePixelBandwidth[i][j] = 0;
+			v->TotalVActiveCursorBandwidth[i][j] = 0;
+			v->TotalMetaRowBandwidth[i][j] = 0;
+			v->TotalDPTERowBandwidth[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
+				v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
+				v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
+				v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
+			}
+		}
+	}
+
+	//Calculate Return BW
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				if (v->BlendingAndTiming[k] == k) {
+					if (v->WritebackEnable[k] == true) {
+						v->WritebackDelayTime[k] = v->WritebackLatency
+								+ CalculateWriteBackDelay(
+										v->WritebackPixelFormat[k],
+										v->WritebackHRatio[k],
+										v->WritebackVRatio[k],
+										v->WritebackVTaps[k],
+										v->WritebackDestinationWidth[k],
+										v->WritebackDestinationHeight[k],
+										v->WritebackSourceHeight[k],
+										v->HTotal[k]) / v->RequiredDISPCLK[i][j];
+					} else {
+						v->WritebackDelayTime[k] = 0.0;
+					}
+					for (m = 0; m < v->NumberOfActivePlanes; m++) {
+						if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
+							v->WritebackDelayTime[k] = dml_max(
+									v->WritebackDelayTime[k],
+									v->WritebackLatency
+											+ CalculateWriteBackDelay(
+													v->WritebackPixelFormat[m],
+													v->WritebackHRatio[m],
+													v->WritebackVRatio[m],
+													v->WritebackVTaps[m],
+													v->WritebackDestinationWidth[m],
+													v->WritebackDestinationHeight[m],
+													v->WritebackSourceHeight[m],
+													v->HTotal[m]) / v->RequiredDISPCLK[i][j]);
+						}
+					}
+				}
+			}
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				for (m = 0; m < v->NumberOfActivePlanes; m++) {
+					if (v->BlendingAndTiming[k] == m) {
+						v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
+					}
+				}
+			}
+			v->MaxMaxVStartup[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->MaximumVStartup[i][j][k] =
+						(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
+								dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
+								v->VTotal[k] - v->VActive[k]
+										- dml_max(
+												1.0,
+												dml_ceil(
+														1.0 * v->WritebackDelayTime[k]
+																/ (v->HTotal[k]
+																		/ v->PixelClock[k]),
+														1.0));
+				if (v->MaximumVStartup[i][j][k] > 1023)
+					v->MaximumVStartup[i][j][k] = 1023;
+				v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
+			}
+		}
+	}
+
+	ReorderingBytes = v->NumberOfChannels
+			* dml_max3(
+					v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			v->DCFCLKState[i][j] = v->DCFCLKPerState[i];
+		}
+	}
+
+	if (v->UseMinimumRequiredDCFCLK == true) {
+		UseMinimumDCFCLK(
+				mode_lib,
+				v->MaxInterDCNTileRepeaters,
+				MaxPrefetchMode,
+				v->DRAMClockChangeLatency,
+				v->SREnterPlusExitTime,
+				v->ReturnBusWidth,
+				v->RoundTripPingLatencyCycles,
+				ReorderingBytes,
+				v->PixelChunkSizeInKByte,
+				v->MetaChunkSize,
+				v->GPUVMEnable,
+				v->GPUVMMaxPageTableLevels,
+				v->HostVMEnable,
+				v->NumberOfActivePlanes,
+				v->HostVMMinPageSize,
+				v->HostVMMaxNonCachedPageTableLevels,
+				v->DynamicMetadataVMEnabled,
+				v->ImmediateFlipRequirement,
+				v->ProgressiveToInterlaceUnitInOPP,
+				v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation,
+				v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+				v->VTotal,
+				v->VActive,
+				v->DynamicMetadataTransmittedBytes,
+				v->DynamicMetadataLinesBeforeActiveRequired,
+				v->Interlace,
+				v->RequiredDPPCLK,
+				v->RequiredDISPCLK,
+				v->UrgLatency,
+				v->NoOfDPP,
+				v->ProjectedDCFCLKDeepSleep,
+				v->MaximumVStartup,
+				v->TotalVActivePixelBandwidth,
+				v->TotalVActiveCursorBandwidth,
+				v->TotalMetaRowBandwidth,
+				v->TotalDPTERowBandwidth,
+				v->TotalNumberOfActiveDPP,
+				v->TotalNumberOfDCCActiveDPP,
+				v->dpte_group_bytes,
+				v->PrefetchLinesY,
+				v->PrefetchLinesC,
+				v->swath_width_luma_ub_all_states,
+				v->swath_width_chroma_ub_all_states,
+				v->BytePerPixelY,
+				v->BytePerPixelC,
+				v->HTotal,
+				v->PixelClock,
+				v->PDEAndMetaPTEBytesPerFrame,
+				v->DPTEBytesPerRow,
+				v->MetaRowBytes,
+				v->DynamicMetadataEnable,
+				v->VActivePixelBandwidth,
+				v->VActiveCursorBandwidth,
+				v->ReadBandwidthLuma,
+				v->ReadBandwidthChroma,
+				v->DCFCLKPerState,
+				v->DCFCLKState);
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double IdealFabricAndSDPPortBandwidthPerState = dml_min(
+					v->ReturnBusWidth * v->DCFCLKState[i][j],
+					v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn);
+			double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth;
+			double PixelDataOnlyReturnBWPerState = dml_min(
+					IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+					IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
+			double PixelMixedWithVMDataReturnBWPerState = dml_min(
+					IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+					IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
+
+			if (v->HostVMEnable != true) {
+				v->ReturnBWPerState[i][j] = PixelDataOnlyReturnBWPerState;
+			} else {
+				v->ReturnBWPerState[i][j] = PixelMixedWithVMDataReturnBWPerState;
+			}
+		}
+	}
+
+	//Re-ordering Buffer Support Check
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			if ((v->ROBBufferSizeInKByte - v->PixelChunkSizeInKByte) * 1024 / v->ReturnBWPerState[i][j]
+					> (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerState[i][j]) {
+				v->ROBSupport[i][j] = true;
+			} else {
+				v->ROBSupport[i][j] = false;
+			}
+		}
+	}
+
+	//Vertical Active BW support check
+
+	MaxTotalVActiveRDBandwidth = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
+					dml_min(
+							v->ReturnBusWidth * v->DCFCLKState[i][j],
+							v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
+							* v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100,
+					v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
+							* v->MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100);
+
+			if (MaxTotalVActiveRDBandwidth <= v->MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
+				v->TotalVerticalActiveBandwidthSupport[i][j] = true;
+			} else {
+				v->TotalVerticalActiveBandwidthSupport[i][j] = false;
+			}
+		}
+	}
+
+	v->UrgentLatency = CalculateUrgentLatency(
+			v->UrgentLatencyPixelDataOnly,
+			v->UrgentLatencyPixelMixedWithVMData,
+			v->UrgentLatencyVMDataOnly,
+			v->DoUrgentLatencyAdjustment,
+			v->UrgentLatencyAdjustmentFabricClockComponent,
+			v->UrgentLatencyAdjustmentFabricClockReference,
+			v->FabricClock);
+	//Prefetch Check
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double VMDataOnlyReturnBWPerState;
+			double HostVMInefficiencyFactor = 1;
+			int NextPrefetchModeState = MinPrefetchMode;
+			bool UnboundedRequestEnabledThisState = false;
+			int CompressedBufferSizeInkByteThisState = 0;
+			double dummy;
+
+			v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
+
+			v->BandwidthWithoutPrefetchSupported[i][j] = true;
+			if (v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]
+					+ v->TotalDPTERowBandwidth[i][j] > v->ReturnBWPerState[i][j] || v->NotEnoughUrgentLatencyHidingA[i][j]) {
+				v->BandwidthWithoutPrefetchSupported[i][j] = false;
+			}
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
+				v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
+				v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
+				v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
+				v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
+				v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
+				v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
+				v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
+				v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
+			}
+
+			VMDataOnlyReturnBWPerState = dml_min(
+					dml_min(
+							v->ReturnBusWidth * v->DCFCLKState[i][j],
+							v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
+							* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+					v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
+							* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
+			if (v->GPUVMEnable && v->HostVMEnable)
+				HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState;
+
+			v->ExtraLatency = CalculateExtraLatency(
+					v->RoundTripPingLatencyCycles,
+					ReorderingBytes,
+					v->DCFCLKState[i][j],
+					v->TotalNumberOfActiveDPP[i][j],
+					v->PixelChunkSizeInKByte,
+					v->TotalNumberOfDCCActiveDPP[i][j],
+					v->MetaChunkSize,
+					v->ReturnBWPerState[i][j],
+					v->GPUVMEnable,
+					v->HostVMEnable,
+					v->NumberOfActivePlanes,
+					v->NoOfDPPThisState,
+					v->dpte_group_bytes,
+					HostVMInefficiencyFactor,
+					v->HostVMMinPageSize,
+					v->HostVMMaxNonCachedPageTableLevels);
+
+			v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
+			do {
+				v->PrefetchModePerState[i][j] = NextPrefetchModeState;
+				v->MaxVStartup = v->NextMaxVStartup;
+
+				v->TWait = CalculateTWait(
+						v->PrefetchModePerState[i][j],
+						v->DRAMClockChangeLatency,
+						v->UrgLatency[i],
+						v->SREnterPlusExitTime);
+
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					Pipe myPipe;
+
+					myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
+					myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
+					myPipe.PixelClock = v->PixelClock[k];
+					myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
+					myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
+					myPipe.ScalerEnabled = v->ScalerEnabled[k];
+					myPipe.SourceScan = v->SourceScan[k];
+					myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
+					myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
+					myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
+					myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
+					myPipe.InterlaceEnable = v->Interlace[k];
+					myPipe.NumberOfCursors = v->NumberOfCursors[k];
+					myPipe.VBlank = v->VTotal[k] - v->VActive[k];
+					myPipe.HTotal = v->HTotal[k];
+					myPipe.DCCEnable = v->DCCEnable[k];
+					myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
+							|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
+					myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
+					myPipe.BytePerPixelY = v->BytePerPixelY[k];
+					myPipe.BytePerPixelC = v->BytePerPixelC[k];
+					myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
+					v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
+							mode_lib,
+							HostVMInefficiencyFactor,
+							&myPipe,
+							v->DSCDelayPerState[i][k],
+							v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
+							v->DPPCLKDelaySCL,
+							v->DPPCLKDelaySCLLBOnly,
+							v->DPPCLKDelayCNVCCursor,
+							v->DISPCLKDelaySubtotal,
+							v->SwathWidthYThisState[k] / v->HRatio[k],
+							v->OutputFormat[k],
+							v->MaxInterDCNTileRepeaters,
+							dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
+							v->MaximumVStartup[i][j][k],
+							v->GPUVMMaxPageTableLevels,
+							v->GPUVMEnable,
+							v->HostVMEnable,
+							v->HostVMMaxNonCachedPageTableLevels,
+							v->HostVMMinPageSize,
+							v->DynamicMetadataEnable[k],
+							v->DynamicMetadataVMEnabled,
+							v->DynamicMetadataLinesBeforeActiveRequired[k],
+							v->DynamicMetadataTransmittedBytes[k],
+							v->UrgLatency[i],
+							v->ExtraLatency,
+							v->TimeCalc,
+							v->PDEAndMetaPTEBytesPerFrame[i][j][k],
+							v->MetaRowBytes[i][j][k],
+							v->DPTEBytesPerRow[i][j][k],
+							v->PrefetchLinesY[i][j][k],
+							v->SwathWidthYThisState[k],
+							v->PrefillY[k],
+							v->MaxNumSwY[k],
+							v->PrefetchLinesC[i][j][k],
+							v->SwathWidthCThisState[k],
+							v->PrefillC[k],
+							v->MaxNumSwC[k],
+							v->swath_width_luma_ub_this_state[k],
+							v->swath_width_chroma_ub_this_state[k],
+							v->SwathHeightYThisState[k],
+							v->SwathHeightCThisState[k],
+							v->TWait,
+							&v->DSTXAfterScaler[k],
+							&v->DSTYAfterScaler[k],
+							&v->LineTimesForPrefetch[k],
+							&v->PrefetchBW[k],
+							&v->LinesForMetaPTE[k],
+							&v->LinesForMetaAndDPTERow[k],
+							&v->VRatioPreY[i][j][k],
+							&v->VRatioPreC[i][j][k],
+							&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
+							&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
+							&v->NoTimeForDynamicMetadata[i][j][k],
+							&v->Tno_bw[k],
+							&v->prefetch_vmrow_bw[k],
+							&v->dummy7[k],
+							&v->dummy8[k],
+							&v->dummy13[k],
+							&v->VUpdateOffsetPix[k],
+							&v->VUpdateWidthPix[k],
+							&v->VReadyOffsetPix[k]);
+				}
+
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					CalculateUrgentBurstFactor(
+							v->swath_width_luma_ub_this_state[k],
+							v->swath_width_chroma_ub_this_state[k],
+							v->SwathHeightYThisState[k],
+							v->SwathHeightCThisState[k],
+							v->HTotal[k] / v->PixelClock[k],
+							v->UrgentLatency,
+							v->CursorBufferSize,
+							v->CursorWidth[k][0],
+							v->CursorBPP[k][0],
+							v->VRatioPreY[i][j][k],
+							v->VRatioPreC[i][j][k],
+							v->BytePerPixelInDETY[k],
+							v->BytePerPixelInDETC[k],
+							v->DETBufferSizeYThisState[k],
+							v->DETBufferSizeCThisState[k],
+							&v->UrgentBurstFactorCursorPre[k],
+							&v->UrgentBurstFactorLumaPre[k],
+							&v->UrgentBurstFactorChroma[k],
+							&v->NotUrgentLatencyHidingPre[k]);
+				}
+
+				v->MaximumReadBandwidthWithPrefetch = 0.0;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+							/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
+
+					v->MaximumReadBandwidthWithPrefetch =
+							v->MaximumReadBandwidthWithPrefetch
+									+ dml_max4(
+											v->VActivePixelBandwidth[i][j][k],
+											v->VActiveCursorBandwidth[i][j][k]
+													+ v->NoOfDPP[i][j][k]
+															* (v->meta_row_bandwidth[i][j][k]
+																	+ v->dpte_row_bandwidth[i][j][k]),
+											v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
+											v->NoOfDPP[i][j][k]
+													* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
+															* v->UrgentBurstFactorLumaPre[k]
+															+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
+																	* v->UrgentBurstFactorChromaPre[k])
+													+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
+				}
+
+				v->NotEnoughUrgentLatencyHidingPre = false;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					if (v->NotUrgentLatencyHidingPre[k] == true) {
+						v->NotEnoughUrgentLatencyHidingPre = true;
+					}
+				}
+
+				v->PrefetchSupported[i][j] = true;
+				if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
+						|| v->NotEnoughUrgentLatencyHidingPre == 1) {
+					v->PrefetchSupported[i][j] = false;
+				}
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
+							|| v->NoTimeForPrefetch[i][j][k] == true) {
+						v->PrefetchSupported[i][j] = false;
+					}
+				}
+
+				v->DynamicMetadataSupported[i][j] = true;
+				for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+					if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
+						v->DynamicMetadataSupported[i][j] = false;
+					}
+				}
+
+				v->VRatioInPrefetchSupported[i][j] = true;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
+						v->VRatioInPrefetchSupported[i][j] = false;
+					}
+				}
+				v->AnyLinesForVMOrRowTooLarge = false;
+				for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+					if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
+						v->AnyLinesForVMOrRowTooLarge = true;
+					}
+				}
+
+				v->NextPrefetchMode = v->NextPrefetchMode + 1;
+
+				if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {
+					v->BandwidthAvailableForImmediateFlip = v->ReturnBWPerState[i][j];
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
+								- dml_max(
+										v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
+										v->NoOfDPP[i][j][k]
+												* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
+														* v->UrgentBurstFactorLumaPre[k]
+														+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
+																* v->UrgentBurstFactorChromaPre[k])
+												+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
+					}
+					v->TotImmediateFlipBytes = 0.0;
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
+								+ v->NoOfDPP[i][j][k] * v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
+								+ v->DPTEBytesPerRow[i][j][k];
+					}
+
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						CalculateFlipSchedule(
+								mode_lib,
+								HostVMInefficiencyFactor,
+								v->ExtraLatency,
+								v->UrgLatency[i],
+								v->GPUVMMaxPageTableLevels,
+								v->HostVMEnable,
+								v->HostVMMaxNonCachedPageTableLevels,
+								v->GPUVMEnable,
+								v->HostVMMinPageSize,
+								v->PDEAndMetaPTEBytesPerFrame[i][j][k],
+								v->MetaRowBytes[i][j][k],
+								v->DPTEBytesPerRow[i][j][k],
+								v->BandwidthAvailableForImmediateFlip,
+								v->TotImmediateFlipBytes,
+								v->SourcePixelFormat[k],
+								v->HTotal[k] / v->PixelClock[k],
+								v->VRatio[k],
+								v->VRatioChroma[k],
+								v->Tno_bw[k],
+								v->DCCEnable[k],
+								v->dpte_row_height[k],
+								v->meta_row_height[k],
+								v->dpte_row_height_chroma[k],
+								v->meta_row_height_chroma[k],
+								&v->DestinationLinesToRequestVMInImmediateFlip[k],
+								&v->DestinationLinesToRequestRowInImmediateFlip[k],
+								&v->final_flip_bw[k],
+								&v->ImmediateFlipSupportedForPipe[k]);
+					}
+					v->total_dcn_read_bw_with_flip = 0.0;
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
+								+ dml_max3(
+										v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
+										v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
+												+ v->VActiveCursorBandwidth[i][j][k],
+										v->NoOfDPP[i][j][k]
+												* (v->final_flip_bw[k]
+														+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
+																* v->UrgentBurstFactorLumaPre[k]
+														+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
+																* v->UrgentBurstFactorChromaPre[k])
+												+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
+					}
+					v->ImmediateFlipSupportedForState[i][j] = true;
+					if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) {
+						v->ImmediateFlipSupportedForState[i][j] = false;
+					}
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						if (v->ImmediateFlipSupportedForPipe[k] == false) {
+							v->ImmediateFlipSupportedForState[i][j] = false;
+						}
+					}
+				} else {
+					v->ImmediateFlipSupportedForState[i][j] = false;
+				}
+
+				if (v->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || v->AnyLinesForVMOrRowTooLarge == false) {
+					v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
+					NextPrefetchModeState = NextPrefetchModeState + 1;
+				} else {
+					v->NextMaxVStartup = v->NextMaxVStartup - 1;
+				}
+				v->NextPrefetchMode = v->NextPrefetchMode + 1;
+			} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
+					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required)
+							|| v->ImmediateFlipSupportedForState[i][j] == true))
+					|| (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode)));
+
+			CalculateUnboundedRequestAndCompressedBufferSize(
+					v->DETBufferSizeInKByte[0],
+					v->ConfigReturnBufferSizeInKByte,
+					v->UseUnboundedRequesting,
+					v->TotalNumberOfActiveDPP[i][j],
+					NoChroma,
+					v->MaxNumDPP,
+					v->CompressedBufferSegmentSizeInkByte,
+					v->Output,
+					&UnboundedRequestEnabledThisState,
+					&CompressedBufferSizeInkByteThisState);
+
+			CalculateWatermarksAndDRAMSpeedChangeSupport(
+					mode_lib,
+					v->PrefetchModePerState[i][j],
+					v->NumberOfActivePlanes,
+					v->MaxLineBufferLines,
+					v->LineBufferSize,
+					v->WritebackInterfaceBufferSize,
+					v->DCFCLKState[i][j],
+					v->ReturnBWPerState[i][j],
+					v->SynchronizedVBlank,
+					v->dpte_group_bytes,
+					v->MetaChunkSize,
+					v->UrgLatency[i],
+					v->ExtraLatency,
+					v->WritebackLatency,
+					v->WritebackChunkSize,
+					v->SOCCLKPerState[i],
+					v->DRAMClockChangeLatency,
+					v->SRExitTime,
+					v->SREnterPlusExitTime,
+					v->SRExitZ8Time,
+					v->SREnterPlusExitZ8Time,
+					v->ProjectedDCFCLKDeepSleep[i][j],
+					v->DETBufferSizeYThisState,
+					v->DETBufferSizeCThisState,
+					v->SwathHeightYThisState,
+					v->SwathHeightCThisState,
+					v->LBBitPerPixel,
+					v->SwathWidthYThisState,
+					v->SwathWidthCThisState,
+					v->HRatio,
+					v->HRatioChroma,
+					v->vtaps,
+					v->VTAPsChroma,
+					v->VRatio,
+					v->VRatioChroma,
+					v->HTotal,
+					v->PixelClock,
+					v->BlendingAndTiming,
+					v->NoOfDPPThisState,
+					v->BytePerPixelInDETY,
+					v->BytePerPixelInDETC,
+					v->DSTXAfterScaler,
+					v->DSTYAfterScaler,
+					v->WritebackEnable,
+					v->WritebackPixelFormat,
+					v->WritebackDestinationWidth,
+					v->WritebackDestinationHeight,
+					v->WritebackSourceHeight,
+					UnboundedRequestEnabledThisState,
+					CompressedBufferSizeInkByteThisState,
+					&v->DRAMClockChangeSupport[i][j],
+					&v->UrgentWatermark,
+					&v->WritebackUrgentWatermark,
+					&v->DRAMClockChangeWatermark,
+					&v->WritebackDRAMClockChangeWatermark,
+					&dummy,
+					&dummy,
+					&dummy,
+					&dummy,
+					&v->MinActiveDRAMClockChangeLatencySupported);
+		}
+	}
+
+	/*PTE Buffer Size Check*/
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			v->PTEBufferSizeNotExceeded[i][j] = true;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
+					v->PTEBufferSizeNotExceeded[i][j] = false;
+				}
+			}
+		}
+	}
+
+	/*Cursor Support Check*/
+	v->CursorSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->CursorWidth[k][0] > 0.0) {
+			if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
+				v->CursorSupport = false;
+			}
+		}
+	}
+
+	/*Valid Pitch Check*/
+	v->PitchSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
+		if (v->DCCEnable[k] == true) {
+			v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
+		} else {
+			v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
+		}
+		if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
+				&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
+				&& v->SourcePixelFormat[k] != dm_mono_8) {
+			v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
+			if (v->DCCEnable[k] == true) {
+				v->AlignedDCCMetaPitchC[k] = dml_ceil(
+						dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
+						64.0 * v->Read256BlockWidthC[k]);
+			} else {
+				v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
+			}
+		} else {
+			v->AlignedCPitch[k] = v->PitchC[k];
+			v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
+		}
+		if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
+				|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
+			v->PitchSupport = false;
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
+			ViewportExceedsSurface = true;
+			if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
+					&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
+					&& v->SourcePixelFormat[k] != dm_rgbe) {
+				if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
+						|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
+					ViewportExceedsSurface = true;
+				}
+			}
+		}
+	}
+
+	/*Mode Support, Voltage State and SOC Configuration*/
+	for (i = v->soc.num_states - 1; i >= 0; i--) {
+		for (j = 0; j < 2; j++) {
+			if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
+					&& v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
+					&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
+					&& v->DTBCLKRequiredMoreThanSupported[i] == false
+					&& v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
+					&& v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
+					&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
+					&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
+					&& v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
+					&& v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
+					&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
+					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required)
+							|| v->ImmediateFlipSupportedForState[i][j] == true)
+					&& FMTBufferExceeded == false) {
+				v->ModeSupport[i][j] = true;
+			} else {
+				v->ModeSupport[i][j] = false;
+			}
+		}
+	}
+
+	{
+		unsigned int MaximumMPCCombine = 0;
+		for (i = v->soc.num_states; i >= 0; i--) {
+			if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
+				v->VoltageLevel = i;
+				v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
+				if (v->ModeSupport[i][0] == true) {
+					MaximumMPCCombine = 0;
+				} else {
+					MaximumMPCCombine = 1;
+				}
+			}
+		}
+		v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
+		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
+			v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
+			v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
+		}
+		v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
+		v->DRAMSpeed = v->DRAMSpeedPerState[v->VoltageLevel];
+		v->FabricClock = v->FabricClockPerState[v->VoltageLevel];
+		v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
+		v->ReturnBW = v->ReturnBWPerState[v->VoltageLevel][MaximumMPCCombine];
+		v->maxMpcComb = MaximumMPCCombine;
+	}
+}
+
+static void CalculateWatermarksAndDRAMSpeedChangeSupport(
+		struct display_mode_lib *mode_lib,
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActivePlanes,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizedVBlank,
+		unsigned int dpte_group_bytes[],
+		unsigned int MetaChunkSize,
+		double UrgentLatency,
+		double ExtraLatency,
+		double WritebackLatency,
+		double WritebackChunkSize,
+		double SOCCLK,
+		double DRAMClockChangeLatency,
+		double SRExitTime,
+		double SREnterPlusExitTime,
+		double SRExitZ8Time,
+		double SREnterPlusExitZ8Time,
+		double DCFCLKDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int vtaps[],
+		unsigned int VTAPsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerPlane[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		int unsigned CompressedBufferSizeInkByte,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double *UrgentWatermark,
+		double *WritebackUrgentWatermark,
+		double *DRAMClockChangeWatermark,
+		double *WritebackDRAMClockChangeWatermark,
+		double *StutterExitWatermark,
+		double *StutterEnterPlusExitWatermark,
+		double *Z8StutterExitWatermark,
+		double *Z8StutterEnterPlusExitWatermark,
+		double *MinActiveDRAMClockChangeLatencySupported)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	double EffectiveLBLatencyHidingY;
+	double EffectiveLBLatencyHidingC;
+	double LinesInDETY[DC__NUM_DPP__MAX];
+	double LinesInDETC;
+	unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
+	unsigned int LinesInDETCRoundedDownToSwath;
+	double FullDETBufferingTimeY;
+	double FullDETBufferingTimeC;
+	double ActiveDRAMClockChangeLatencyMarginY;
+	double ActiveDRAMClockChangeLatencyMarginC;
+	double WritebackDRAMClockChangeLatencyMargin;
+	double PlaneWithMinActiveDRAMClockChangeMargin;
+	double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
+	double WritebackDRAMClockChangeLatencyHiding;
+	double TotalPixelBW = 0.0;
+	int k, j;
+
+	*UrgentWatermark = UrgentLatency + ExtraLatency;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency);
+	dml_print("DML::%s: ExtraLatency = %f\n", __func__, ExtraLatency);
+	dml_print("DML::%s: UrgentWatermark = %f\n", __func__, *UrgentWatermark);
+#endif
+
+	*DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, DRAMClockChangeLatency);
+	dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, *DRAMClockChangeWatermark);
+#endif
+
+	v->TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (WritebackEnable[k] == true) {
+			v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
+		}
+	}
+
+	if (v->TotalActiveWriteback <= 1) {
+		*WritebackUrgentWatermark = WritebackLatency;
+	} else {
+		*WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+	}
+
+	if (v->TotalActiveWriteback <= 1) {
+		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency;
+	} else {
+		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		TotalPixelBW = TotalPixelBW
+				+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k])
+						/ (HTotal[k] / PixelClock[k]);
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		double EffectiveDETBufferSizeY = DETBufferSizeY[k];
+
+		v->LBLatencyHidingSourceLinesY = dml_min(
+				(double) MaxLineBufferLines,
+				dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1);
+
+		v->LBLatencyHidingSourceLinesC = dml_min(
+				(double) MaxLineBufferLines,
+				dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1);
+
+		EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]);
+
+		EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
+
+		if (UnboundedRequestEnabled) {
+			EffectiveDETBufferSizeY = EffectiveDETBufferSizeY
+					+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] / (HTotal[k] / PixelClock[k]) / TotalPixelBW;
+		}
+
+		LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
+		LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
+		FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
+		if (BytePerPixelDETC[k] > 0) {
+			LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
+			LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
+			FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k];
+		} else {
+			LinesInDETC = 0;
+			FullDETBufferingTimeC = 999999;
+		}
+
+		ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY
+				- ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark;
+
+		if (NumberOfActivePlanes > 1) {
+			ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY
+					- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
+		}
+
+		if (BytePerPixelDETC[k] > 0) {
+			ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC
+					- ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark;
+
+			if (NumberOfActivePlanes > 1) {
+				ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC
+						- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k];
+			}
+			v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
+		} else {
+			v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
+		}
+
+		if (WritebackEnable[k] == true) {
+			WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024
+					/ (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
+			if (WritebackPixelFormat[k] == dm_444_64) {
+				WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2;
+			}
+			WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
+			v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
+		}
+	}
+
+	v->MinActiveDRAMClockChangeMargin = 999999;
+	PlaneWithMinActiveDRAMClockChangeMargin = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
+			v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
+			if (BlendingAndTiming[k] == k) {
+				PlaneWithMinActiveDRAMClockChangeMargin = k;
+			} else {
+				for (j = 0; j < NumberOfActivePlanes; ++j) {
+					if (BlendingAndTiming[k] == j) {
+						PlaneWithMinActiveDRAMClockChangeMargin = j;
+					}
+				}
+			}
+		}
+	}
+
+	*MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency;
+
+	SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
+				&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
+			SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
+		}
+	}
+
+	v->TotalNumberOfActiveOTG = 0;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (BlendingAndTiming[k] == k) {
+			v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
+		}
+	}
+
+	if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {
+		*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
+	} else if ((SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1
+			|| SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0) {
+		*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
+	} else {
+		*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	}
+
+	*StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
+	*StutterEnterPlusExitWatermark = (SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep);
+	*Z8StutterExitWatermark = SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
+	*Z8StutterEnterPlusExitWatermark = SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, *StutterExitWatermark);
+	dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, *StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, *Z8StutterExitWatermark);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, *Z8StutterEnterPlusExitWatermark);
+#endif
+}
+
+static void CalculateDCFCLKDeepSleep(
+		struct display_mode_lib *mode_lib,
+		unsigned int NumberOfActivePlanes,
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		int ReturnBusWidth,
+		double *DCFCLKDeepSleep)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	double DisplayPipeLineDeliveryTimeLuma;
+	double DisplayPipeLineDeliveryTimeChroma;
+	double ReadBandwidth = 0.0;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
+		}
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
+			}
+		}
+
+		if (BytePerPixelC[k] > 0) {
+			v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
+			__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
+		} else {
+			v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
+		}
+		v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
+
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
+	}
+
+	*DCFCLKDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / ReturnBusWidth);
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
+	}
+}
+
+static void CalculateUrgentBurstFactor(
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double LineTime,
+		double UrgentLatency,
+		double CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double VRatio,
+		double VRatioC,
+		double BytePerPixelInDETY,
+		double BytePerPixelInDETC,
+		double DETBufferSizeY,
+		double DETBufferSizeC,
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool *NotEnoughUrgentLatencyHiding)
+{
+	double LinesInDETLuma;
+	double LinesInDETChroma;
+	unsigned int LinesInCursorBuffer;
+	double CursorBufferSizeInTime;
+	double DETBufferSizeInTimeLuma;
+	double DETBufferSizeInTimeChroma;
+
+	*NotEnoughUrgentLatencyHiding = 0;
+
+	if (CursorWidth > 0) {
+		LinesInCursorBuffer = 1 << (unsigned int) dml_floor(dml_log2(CursorBufferSize * 1024.0 / (CursorWidth * CursorBPP / 8.0)), 1.0);
+		if (VRatio > 0) {
+			CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio;
+			if (CursorBufferSizeInTime - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorCursor = 0;
+			} else {
+				*UrgentBurstFactorCursor = CursorBufferSizeInTime / (CursorBufferSizeInTime - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorCursor = 1;
+		}
+	}
+
+	LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / swath_width_luma_ub;
+	if (VRatio > 0) {
+		DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;
+		if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {
+			*NotEnoughUrgentLatencyHiding = 1;
+			*UrgentBurstFactorLuma = 0;
+		} else {
+			*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency);
+		}
+	} else {
+		*UrgentBurstFactorLuma = 1;
+	}
+
+	if (BytePerPixelInDETC > 0) {
+		LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / swath_width_chroma_ub;
+		if (VRatio > 0) {
+			DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime / VRatio;
+			if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorChroma = 0;
+			} else {
+				*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma / (DETBufferSizeInTimeChroma - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorChroma = 1;
+		}
+	}
+}
+
+static void CalculatePixelDeliveryTimes(
+		unsigned int NumberOfActivePlanes,
+		double VRatio[],
+		double VRatioChroma[],
+		double VRatioPrefetchY[],
+		double VRatioPrefetchC[],
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		unsigned int NumberOfCursors[],
+		unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int BlockWidth256BytesY[],
+		unsigned int BlockHeight256BytesY[],
+		unsigned int BlockWidth256BytesC[],
+		unsigned int BlockHeight256BytesC[],
+		double DisplayPipeLineDeliveryTimeLuma[],
+		double DisplayPipeLineDeliveryTimeChroma[],
+		double DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeLuma[],
+		double DisplayPipeRequestDeliveryTimeChroma[],
+		double DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double CursorRequestDeliveryTime[],
+		double CursorRequestDeliveryTimePrefetch[])
+{
+	double req_per_swath_ub;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma[k] = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
+			}
+		}
+
+		if (VRatioPrefetchY[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (VRatioPrefetchC[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (SourceScan[k] != dm_vert) {
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
+		} else {
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
+		}
+		DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
+		DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeRequestDeliveryTimeChroma[k] = 0;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (SourceScan[k] != dm_vert) {
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
+			} else {
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
+			}
+			DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
+		dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
+		dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		int cursor_req_per_width;
+		cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
+		if (NumberOfCursors[k] > 0) {
+			if (VRatio[k] <= 1) {
+				CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
+			}
+			if (VRatioPrefetchY[k] <= 1) {
+				CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
+			}
+		} else {
+			CursorRequestDeliveryTime[k] = 0;
+			CursorRequestDeliveryTimePrefetch[k] = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", __func__, k, NumberOfCursors[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
+#endif
+	}
+}
+
+static void CalculateMetaAndPTETimes(
+		int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		int MetaChunkSize,
+		int MinMetaChunkSizeBytes,
+		int HTotal[],
+		double VRatio[],
+		double VRatioChroma[],
+		double DestinationLinesToRequestRowInVBlank[],
+		double DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		int dpte_row_height[],
+		int dpte_row_height_chroma[],
+		int meta_row_width[],
+		int meta_row_width_chroma[],
+		int meta_row_height[],
+		int meta_row_height_chroma[],
+		int meta_req_width[],
+		int meta_req_width_chroma[],
+		int meta_req_height[],
+		int meta_req_height_chroma[],
+		int dpte_group_bytes[],
+		int PTERequestSizeY[],
+		int PTERequestSizeC[],
+		int PixelPTEReqWidthY[],
+		int PixelPTEReqHeightY[],
+		int PixelPTEReqWidthC[],
+		int PixelPTEReqHeightC[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[])
+{
+	unsigned int meta_chunk_width;
+	unsigned int min_meta_chunk_width;
+	unsigned int meta_chunk_per_row_int;
+	unsigned int meta_row_remainder;
+	unsigned int meta_chunk_threshold;
+	unsigned int meta_chunks_per_row_ub;
+	unsigned int meta_chunk_width_chroma;
+	unsigned int min_meta_chunk_width_chroma;
+	unsigned int meta_chunk_per_row_int_chroma;
+	unsigned int meta_row_remainder_chroma;
+	unsigned int meta_chunk_threshold_chroma;
+	unsigned int meta_chunks_per_row_ub_chroma;
+	unsigned int dpte_group_width_luma;
+	unsigned int dpte_groups_per_row_luma_ub;
+	unsigned int dpte_group_width_chroma;
+	unsigned int dpte_groups_per_row_chroma_ub;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0) {
+			DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
+		} else {
+			DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
+		}
+		DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0) {
+			DST_Y_PER_META_ROW_NOM_C[k] = 0;
+		} else {
+			DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
+		}
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (DCCEnable[k] == true) {
+			meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
+			min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
+			meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
+			meta_row_remainder = meta_row_width[k] % meta_chunk_width;
+			if (SourceScan[k] != dm_vert) {
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
+			} else {
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
+			}
+			if (meta_row_remainder <= meta_chunk_threshold) {
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
+			} else {
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
+			}
+			TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			if (BytePerPixelC[k] == 0) {
+				TimePerChromaMetaChunkNominal[k] = 0;
+				TimePerChromaMetaChunkVBlank[k] = 0;
+				TimePerChromaMetaChunkFlip[k] = 0;
+			} else {
+				meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
+				min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
+				meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
+				meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
+				if (SourceScan[k] != dm_vert) {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
+				} else {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
+				}
+				if (meta_row_remainder_chroma <= meta_chunk_threshold_chroma) {
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 1;
+				} else {
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 2;
+				}
+				TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+			}
+		} else {
+			TimePerMetaChunkNominal[k] = 0;
+			TimePerMetaChunkVBlank[k] = 0;
+			TimePerMetaChunkFlip[k] = 0;
+			TimePerChromaMetaChunkNominal[k] = 0;
+			TimePerChromaMetaChunkVBlank[k] = 0;
+			TimePerChromaMetaChunkFlip[k] = 0;
+		}
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (GPUVMEnable == true) {
+			if (SourceScan[k] != dm_vert) {
+				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
+			} else {
+				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
+			}
+			dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
+			time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			if (BytePerPixelC[k] == 0) {
+				time_per_pte_group_nom_chroma[k] = 0;
+				time_per_pte_group_vblank_chroma[k] = 0;
+				time_per_pte_group_flip_chroma[k] = 0;
+			} else {
+				if (SourceScan[k] != dm_vert) {
+					dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
+				} else {
+					dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
+				}
+				dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
+				time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+			}
+		} else {
+			time_per_pte_group_nom_luma[k] = 0;
+			time_per_pte_group_vblank_luma[k] = 0;
+			time_per_pte_group_flip_luma[k] = 0;
+			time_per_pte_group_nom_chroma[k] = 0;
+			time_per_pte_group_vblank_chroma[k] = 0;
+			time_per_pte_group_flip_chroma[k] = 0;
+		}
+	}
+}
+
+static void CalculateVMGroupAndRequestTimes(
+		unsigned int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int HTotal[],
+		int BytePerPixelC[],
+		double DestinationLinesToRequestVMInVBlank[],
+		double DestinationLinesToRequestVMInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		int vm_group_bytes[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		int meta_pte_bytes_per_frame_ub_l[],
+		int meta_pte_bytes_per_frame_ub_c[],
+		double TimePerVMGroupVBlank[],
+		double TimePerVMGroupFlip[],
+		double TimePerVMRequestVBlank[],
+		double TimePerVMRequestFlip[])
+{
+	int num_group_per_lower_vm_stage;
+	int num_req_per_lower_vm_stage;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+							+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
+				} else {
+					num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
+					} else {
+						num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
+					} else {
+						num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
+					}
+				}
+			}
+
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
+				} else {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64
+								+ meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				}
+			}
+
+			TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+			TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+
+			if (GPUVMMaxPageTableLevels > 2) {
+				TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
+				TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
+				TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
+				TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
+			}
+
+		} else {
+			TimePerVMGroupVBlank[k] = 0;
+			TimePerVMGroupFlip[k] = 0;
+			TimePerVMRequestVBlank[k] = 0;
+			TimePerVMRequestFlip[k] = 0;
+		}
+	}
+}
+
+static void CalculateStutterEfficiency(
+		struct display_mode_lib *mode_lib,
+		int CompressedBufferSizeInkByte,
+		bool UnboundedRequestEnabled,
+		int ConfigReturnBufferSizeInKByte,
+		int MetaFIFOSizeInKEntries,
+		int ZeroSizeBufferEntries,
+		int NumberOfActivePlanes,
+		int ROBBufferSizeInKByte,
+		double TotalDataReadBandwidth,
+		double DCFCLK,
+		double ReturnBW,
+		double COMPBUF_RESERVED_SPACE_64B,
+		double COMPBUF_RESERVED_SPACE_ZS,
+		double SRExitTime,
+		double SRExitZ8Time,
+		bool SynchronizedVBlank,
+		double Z8StutterEnterPlusExitWatermark,
+		double StutterEnterPlusExitWatermark,
+		bool ProgressiveToInterlaceUnitInOPP,
+		bool Interlace[],
+		double MinTTUVBlank[],
+		int DPPPerPlane[],
+		unsigned int DETBufferSizeY[],
+		int BytePerPixelY[],
+		double BytePerPixelDETY[],
+		double SwathWidthY[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		double NetDCCRateLuma[],
+		double NetDCCRateChroma[],
+		double DCCFractionOfZeroSizeRequestsLuma[],
+		double DCCFractionOfZeroSizeRequestsChroma[],
+		int HTotal[],
+		int VTotal[],
+		double PixelClock[],
+		double VRatio[],
+		enum scan_direction_class SourceScan[],
+		int BlockHeight256BytesY[],
+		int BlockWidth256BytesY[],
+		int BlockHeight256BytesC[],
+		int BlockWidth256BytesC[],
+		int DCCYMaxUncompressedBlock[],
+		int DCCCMaxUncompressedBlock[],
+		int VActive[],
+		bool DCCEnable[],
+		bool WritebackEnable[],
+		double ReadBandwidthPlaneLuma[],
+		double ReadBandwidthPlaneChroma[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double *StutterEfficiencyNotIncludingVBlank,
+		double *StutterEfficiency,
+		int *NumberOfStutterBurstsPerFrame,
+		double *Z8StutterEfficiencyNotIncludingVBlank,
+		double *Z8StutterEfficiency,
+		int *Z8NumberOfStutterBurstsPerFrame,
+		double *StutterPeriod)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+
+	double DETBufferingTimeY;
+	double SwathWidthYCriticalPlane = 0;
+	double VActiveTimeCriticalPlane = 0;
+	double FrameTimeCriticalPlane = 0;
+	int BytePerPixelYCriticalPlane = 0;
+	double LinesToFinishSwathTransferStutterCriticalPlane = 0;
+	double MinTTUVBlankCriticalPlane = 0;
+	double TotalCompressedReadBandwidth;
+	double TotalRowReadBandwidth;
+	double AverageDCCCompressionRate;
+	double EffectiveCompressedBufferSize;
+	double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer;
+	double StutterBurstTime;
+	int TotalActiveWriteback;
+	double LinesInDETY;
+	double LinesInDETYRoundedDownToSwath;
+	double MaximumEffectiveCompressionLuma;
+	double MaximumEffectiveCompressionChroma;
+	double TotalZeroSizeRequestReadBandwidth;
+	double TotalZeroSizeCompressedReadBandwidth;
+	double AverageDCCZeroSizeFraction;
+	double AverageZeroSizeCompressionRate;
+	int TotalNumberOfActiveOTG = 0;
+	double LastStutterPeriod = 0.0;
+	double LastZ8StutterPeriod = 0.0;
+	int k;
+
+	TotalZeroSizeRequestReadBandwidth = 0;
+	TotalZeroSizeCompressedReadBandwidth = 0;
+	TotalRowReadBandwidth = 0;
+	TotalCompressedReadBandwidth = 0;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (DCCEnable[k] == true) {
+			if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k]) || (SourceScan[k] != dm_vert && BlockHeight256BytesY[k] > SwathHeightY[k])
+					|| DCCYMaxUncompressedBlock[k] < 256) {
+				MaximumEffectiveCompressionLuma = 2;
+			} else {
+				MaximumEffectiveCompressionLuma = 4;
+			}
+			TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
+			TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
+			TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+					+ ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
+			if (ReadBandwidthPlaneChroma[k] > 0) {
+				if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
+						|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k]) || DCCCMaxUncompressedBlock[k] < 256) {
+					MaximumEffectiveCompressionChroma = 2;
+				} else {
+					MaximumEffectiveCompressionChroma = 4;
+				}
+				TotalCompressedReadBandwidth = TotalCompressedReadBandwidth
+						+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
+				TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k];
+				TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+						+ ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
+			}
+		} else {
+			TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
+		}
+		TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
+	}
+
+	AverageDCCCompressionRate = TotalDataReadBandwidth / TotalCompressedReadBandwidth;
+	AverageDCCZeroSizeFraction = TotalZeroSizeRequestReadBandwidth / TotalDataReadBandwidth;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotalCompressedReadBandwidth = %f\n", __func__, TotalCompressedReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeRequestReadBandwidth = %f\n", __func__, TotalZeroSizeRequestReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeCompressedReadBandwidth = %f\n", __func__, TotalZeroSizeCompressedReadBandwidth);
+	dml_print("DML::%s: MaximumEffectiveCompressionLuma = %f\n", __func__, MaximumEffectiveCompressionLuma);
+	dml_print("DML::%s: MaximumEffectiveCompressionChroma = %f\n", __func__, MaximumEffectiveCompressionChroma);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: AverageDCCZeroSizeFraction = %f\n", __func__, AverageDCCZeroSizeFraction);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, CompressedBufferSizeInkByte);
+#endif
+
+	if (AverageDCCZeroSizeFraction == 1) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth / TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = MetaFIFOSizeInKEntries * 1024 * 64 * AverageZeroSizeCompressionRate + (ZeroSizeBufferEntries - COMPBUF_RESERVED_SPACE_ZS) * 64 * AverageZeroSizeCompressionRate;
+	} else if (AverageDCCZeroSizeFraction > 0) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth / TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = dml_min(
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				MetaFIFOSizeInKEntries * 1024 * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 / AverageDCCCompressionRate))
+					+ dml_min((ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate,
+						(ZeroSizeBufferEntries - COMPBUF_RESERVED_SPACE_ZS) * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+		dml_print("DML::%s: min 1 = %f\n", __func__, CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print(
+				"DML::%s: min 2 = %f\n",
+				__func__,
+				MetaFIFOSizeInKEntries * 1024 * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 / AverageDCCCompressionRate));
+		dml_print("DML::%s: min 3 = %f\n", __func__, ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 4 = %f\n", __func__, ZeroSizeBufferEntries * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+	} else {
+		EffectiveCompressedBufferSize = dml_min(
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate) + (ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate;
+		dml_print("DML::%s: min 1 = %f\n", __func__, CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 2 = %f\n", __func__, MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate);
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MetaFIFOSizeInKEntries = %d\n", __func__, MetaFIFOSizeInKEntries);
+	dml_print("DML::%s: AverageZeroSizeCompressionRate = %f\n", __func__, AverageZeroSizeCompressionRate);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+#endif
+
+	*StutterPeriod = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)
+				/ BytePerPixelDETY[k] / SwathWidthY[k];
+		LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
+		DETBufferingTimeY = LinesInDETYRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatio[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d DETBufferSizeY = %f\n", __func__, k, DETBufferSizeY[k]);
+		dml_print("DML::%s: k=%0d BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
+		dml_print("DML::%s: k=%0d SwathWidthY = %f\n", __func__, k, SwathWidthY[k]);
+		dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma = %f\n", __func__, k, ReadBandwidthPlaneLuma[k]);
+		dml_print("DML::%s: k=%0d TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
+		dml_print("DML::%s: k=%0d LinesInDETY = %f\n", __func__, k, LinesInDETY);
+		dml_print("DML::%s: k=%0d LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
+		dml_print("DML::%s: k=%0d HTotal = %d\n", __func__, k, HTotal[k]);
+		dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
+		dml_print("DML::%s: k=%0d VRatio = %f\n", __func__, k, VRatio[k]);
+		dml_print("DML::%s: k=%0d DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
+		dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
+#endif
+
+		if (k == 0 || DETBufferingTimeY < *StutterPeriod) {
+			bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
+
+			*StutterPeriod = DETBufferingTimeY;
+			FrameTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VTotal[k] / 2.0, 1.0) : VTotal[k]) * HTotal[k] / PixelClock[k];
+			VActiveTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VActive[k] / 2.0, 1.0) : VActive[k]) * HTotal[k] / PixelClock[k];
+			BytePerPixelYCriticalPlane = BytePerPixelY[k];
+			SwathWidthYCriticalPlane = SwathWidthY[k];
+			LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
+			MinTTUVBlankCriticalPlane = MinTTUVBlank[k];
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+			dml_print("DML::%s: MinTTUVBlankCriticalPlane = %f\n", __func__, MinTTUVBlankCriticalPlane);
+			dml_print("DML::%s: FrameTimeCriticalPlane = %f\n", __func__, FrameTimeCriticalPlane);
+			dml_print("DML::%s: VActiveTimeCriticalPlane = %f\n", __func__, VActiveTimeCriticalPlane);
+			dml_print("DML::%s: BytePerPixelYCriticalPlane = %d\n", __func__, BytePerPixelYCriticalPlane);
+			dml_print("DML::%s: SwathWidthYCriticalPlane = %f\n", __func__, SwathWidthYCriticalPlane);
+			dml_print("DML::%s: LinesToFinishSwathTransferStutterCriticalPlane = %f\n", __func__, LinesToFinishSwathTransferStutterCriticalPlane);
+#endif
+		}
+	}
+
+	PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth, EffectiveCompressedBufferSize);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ROBBufferSizeInKByte = %d\n", __func__, ROBBufferSizeInKByte);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", __func__, *StutterPeriod * TotalDataReadBandwidth);
+	dml_print("DML::%s: ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate + EffectiveCompressedBufferSize = %f\n", __func__, ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate + EffectiveCompressedBufferSize);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+	dml_print("DML::%s: PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, ReturnBW);
+	dml_print("DML::%s: TotalDataReadBandwidth = %f\n", __func__, TotalDataReadBandwidth);
+	dml_print("DML::%s: TotalRowReadBandwidth = %f\n", __func__, TotalRowReadBandwidth);
+	dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK);
+#endif
+
+	StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / ReturnBW
+			+ (*StutterPeriod * TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64)
+			+ *StutterPeriod * TotalRowReadBandwidth / ReturnBW;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Part 1 = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / ReturnBW);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth));
+	dml_print("DML::%s: Part 2 = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64));
+	dml_print("DML::%s: Part 3 = %f\n", __func__, *StutterPeriod * TotalRowReadBandwidth / ReturnBW);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+#endif
+	StutterBurstTime = dml_max(StutterBurstTime, LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW);
+
+	dml_print(
+			"DML::%s: Time to finish residue swath=%f\n",
+			__func__,
+			LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW);
+
+	TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (WritebackEnable[k]) {
+			TotalActiveWriteback = TotalActiveWriteback + 1;
+		}
+	}
+
+	if (TotalActiveWriteback == 0) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: SRExitTime = %f\n", __func__, SRExitTime);
+		dml_print("DML::%s: SRExitZ8Time = %f\n", __func__, SRExitZ8Time);
+		dml_print("DML::%s: StutterBurstTime = %f (final)\n", __func__, StutterBurstTime);
+		dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+#endif
+		*StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100;
+		*Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100;
+		*NumberOfStutterBurstsPerFrame = (*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0);
+		*Z8NumberOfStutterBurstsPerFrame = (*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0);
+	} else {
+		*StutterEfficiencyNotIncludingVBlank = 0.;
+		*Z8StutterEfficiencyNotIncludingVBlank = 0.;
+		*NumberOfStutterBurstsPerFrame = 0;
+		*Z8NumberOfStutterBurstsPerFrame = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VActiveTimeCriticalPlane = %f\n", __func__, VActiveTimeCriticalPlane);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *Z8StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: NumberOfStutterBurstsPerFrame = %d\n", __func__, *NumberOfStutterBurstsPerFrame);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+#endif
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k) {
+			TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1;
+		}
+	}
+
+	if (*StutterEfficiencyNotIncludingVBlank > 0) {
+		LastStutterPeriod = VActiveTimeCriticalPlane - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+
+		if ((SynchronizedVBlank || TotalNumberOfActiveOTG == 1) && LastStutterPeriod + MinTTUVBlankCriticalPlane > StutterEnterPlusExitWatermark) {
+			*StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitTime + StutterBurstTime * VActiveTimeCriticalPlane
+					/ *StutterPeriod) / FrameTimeCriticalPlane) * 100;
+		} else {
+			*StutterEfficiency = *StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*StutterEfficiency = 0;
+	}
+
+	if (*Z8StutterEfficiencyNotIncludingVBlank > 0) {
+		LastZ8StutterPeriod = VActiveTimeCriticalPlane - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+		if ((SynchronizedVBlank || TotalNumberOfActiveOTG == 1) && LastZ8StutterPeriod + MinTTUVBlankCriticalPlane > Z8StutterEnterPlusExitWatermark) {
+			*Z8StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitZ8Time + StutterBurstTime * VActiveTimeCriticalPlane
+					/ *StutterPeriod) / FrameTimeCriticalPlane) * 100;
+		} else {
+			*Z8StutterEfficiency = *Z8StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*Z8StutterEfficiency = 0.;
+	}
+
+	dml_print("DML::%s: LastZ8StutterPeriod = %f\n", __func__, LastZ8StutterPeriod);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, Z8StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+	dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+	dml_print("DML::%s: StutterEfficiency = %f\n", __func__, *StutterEfficiency);
+	dml_print("DML::%s: Z8StutterEfficiency = %f\n", __func__, *Z8StutterEfficiency);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+}
+
+static void CalculateSwathAndDETConfiguration(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		unsigned int DETBufferSizeInKByte,
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum scan_direction_class SourceScan[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BlendingAndTiming[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		int DPPPerPlane[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool ViewportSizeSupportPerPlane[],
+		bool *ViewportSizeSupport)
+{
+	int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+	int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+	int MinimumSwathHeightY;
+	int MinimumSwathHeightC;
+	int RoundedUpMaxSwathSizeBytesY;
+	int RoundedUpMaxSwathSizeBytesC;
+	int RoundedUpMinSwathSizeBytesY;
+	int RoundedUpMinSwathSizeBytesC;
+	int RoundedUpSwathSizeBytesY;
+	int RoundedUpSwathSizeBytesC;
+	double SwathWidthSingleDPP[DC__NUM_DPP__MAX];
+	double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX];
+	int k;
+
+	CalculateSwathWidth(
+			ForceSingleDPP,
+			NumberOfActivePlanes,
+			SourcePixelFormat,
+			SourceScan,
+			ViewportWidth,
+			ViewportHeight,
+			SurfaceWidthY,
+			SurfaceWidthC,
+			SurfaceHeightY,
+			SurfaceHeightC,
+			ODMCombineEnabled,
+			BytePerPixY,
+			BytePerPixC,
+			Read256BytesBlockHeightY,
+			Read256BytesBlockHeightC,
+			Read256BytesBlockWidthY,
+			Read256BytesBlockWidthC,
+			BlendingAndTiming,
+			HActive,
+			HRatio,
+			DPPPerPlane,
+			SwathWidthSingleDPP,
+			SwathWidthSingleDPPChroma,
+			SwathWidth,
+			SwathWidthChroma,
+			MaximumSwathHeightY,
+			MaximumSwathHeightC,
+			swath_width_luma_ub,
+			swath_width_chroma_ub);
+
+	*ViewportSizeSupport = true;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32 || SourcePixelFormat[k] == dm_444_16 || SourcePixelFormat[k] == dm_mono_16
+				|| SourcePixelFormat[k] == dm_mono_8 || SourcePixelFormat[k] == dm_rgbe)) {
+			if (SurfaceTiling[k] == dm_sw_linear
+					|| (SourcePixelFormat[k] == dm_444_64
+							&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
+							&& SourceScan[k] != dm_vert)) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+			} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+			} else {
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+			}
+			MinimumSwathHeightC = MaximumSwathHeightC[k];
+		} else {
+			if (SurfaceTiling[k] == dm_sw_linear) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+				MinimumSwathHeightC = MaximumSwathHeightC[k];
+			} else if (SourcePixelFormat[k] == dm_rgbe_alpha && SourceScan[k] == dm_vert) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+				MinimumSwathHeightC = MaximumSwathHeightC[k];
+			} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+				MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
+			} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+				MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
+			} else {
+				MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+			}
+		}
+
+		RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
+		RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY;
+		if (SourcePixelFormat[k] == dm_420_10) {
+			RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256);
+			RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256);
+		}
+		RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
+		RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC;
+		if (SourcePixelFormat[k] == dm_420_10) {
+			RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256);
+			RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256);
+		}
+
+		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
+		} else if (RoundedUpMaxSwathSizeBytesY >= 1.5 * RoundedUpMaxSwathSizeBytesC
+				&& RoundedUpMinSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) {
+			SwathHeightY[k] = MinimumSwathHeightY;
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
+		} else if (RoundedUpMaxSwathSizeBytesY < 1.5 * RoundedUpMaxSwathSizeBytesC
+				&& RoundedUpMaxSwathSizeBytesY + RoundedUpMinSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MinimumSwathHeightC;
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMinSwathSizeBytesC;
+		} else {
+			SwathHeightY[k] = MinimumSwathHeightY;
+			SwathHeightC[k] = MinimumSwathHeightC;
+			RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMinSwathSizeBytesC;
+		}
+		{
+		double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
+		if (SwathHeightC[k] == 0) {
+			DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024;
+			DETBufferSizeC[k] = 0;
+		} else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) {
+			DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2;
+			DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2;
+		} else {
+			DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024);
+			DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3;
+		}
+
+		if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k]
+				|| (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
+			*ViewportSizeSupport = false;
+			ViewportSizeSupportPerPlane[k] = false;
+		} else {
+			ViewportSizeSupportPerPlane[k] = true;
+		}
+		}
+	}
+}
+
+static void CalculateSwathWidth(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		enum source_format_class SourcePixelFormat[],
+		enum scan_direction_class SourceScan[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		int BlendingAndTiming[],
+		int HActive[],
+		double HRatio[],
+		int DPPPerPlane[],
+		double SwathWidthSingleDPPY[],
+		double SwathWidthSingleDPPC[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		int MaximumSwathHeightY[],
+		int MaximumSwathHeightC[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[])
+{
+	enum odm_combine_mode MainPlaneODMCombine;
+	int j, k;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: NumberOfActivePlanes = %d\n", __func__, NumberOfActivePlanes);
+#endif
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (SourceScan[k] != dm_vert) {
+			SwathWidthSingleDPPY[k] = ViewportWidth[k];
+		} else {
+			SwathWidthSingleDPPY[k] = ViewportHeight[k];
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
+		dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
+#endif
+
+		MainPlaneODMCombine = ODMCombineEnabled[k];
+		for (j = 0; j < NumberOfActivePlanes; ++j) {
+			if (BlendingAndTiming[k] == j) {
+				MainPlaneODMCombine = ODMCombineEnabled[j];
+			}
+		}
+
+		if (MainPlaneODMCombine == dm_odm_combine_mode_4to1) {
+			SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
+		} else if (MainPlaneODMCombine == dm_odm_combine_mode_2to1) {
+			SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
+		} else if (DPPPerPlane[k] == 2) {
+			SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
+		} else {
+			SwathWidthY[k] = SwathWidthSingleDPPY[k];
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d SwathWidthSingleDPPY=%f\n", __func__, k, SwathWidthSingleDPPY[k]);
+		dml_print("DML::%s: k=%d SwathWidthY=%f\n", __func__, k, SwathWidthY[k]);
+#endif
+
+		if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
+			SwathWidthC[k] = SwathWidthY[k] / 2;
+			SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
+		} else {
+			SwathWidthC[k] = SwathWidthY[k];
+			SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
+		}
+
+		if (ForceSingleDPP == true) {
+			SwathWidthY[k] = SwathWidthSingleDPPY[k];
+			SwathWidthC[k] = SwathWidthSingleDPPC[k];
+		}
+		{
+		int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
+		int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
+		int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
+		int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
+#endif
+
+		if (SourceScan[k] != dm_vert) {
+			MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
+			swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
+			if (BytePerPixC[k] > 0) {
+				swath_width_chroma_ub[k] = dml_min(
+						surface_width_ub_c,
+						(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		} else {
+			MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
+			swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
+			if (BytePerPixC[k] > 0) {
+				swath_width_chroma_ub[k] = dml_min(
+						surface_height_ub_c,
+						(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		}
+		}
+	}
+}
+
+static double CalculateExtraLatency(
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		double DCFCLK,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels)
+{
+	double ExtraLatencyBytes;
+	double ExtraLatency;
+
+	ExtraLatencyBytes = CalculateExtraLatencyBytes(
+			ReorderingBytes,
+			TotalNumberOfActiveDPP,
+			PixelChunkSizeInKByte,
+			TotalNumberOfDCCActiveDPP,
+			MetaChunkSize,
+			GPUVMEnable,
+			HostVMEnable,
+			NumberOfActivePlanes,
+			NumberOfDPP,
+			dpte_group_bytes,
+			HostVMInefficiencyFactor,
+			HostVMMinPageSize,
+			HostVMMaxNonCachedPageTableLevels);
+
+	ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: RoundTripPingLatencyCycles=%d\n", __func__, RoundTripPingLatencyCycles);
+	dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK);
+	dml_print("DML::%s: ExtraLatencyBytes=%f\n", __func__, ExtraLatencyBytes);
+	dml_print("DML::%s: ReturnBW=%f\n", __func__, ReturnBW);
+	dml_print("DML::%s: ExtraLatency=%f\n", __func__, ExtraLatency);
+#endif
+
+	return ExtraLatency;
+}
+
+static double CalculateExtraLatencyBytes(
+		int ReorderingBytes,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels)
+{
+	double ret;
+	int HostVMDynamicLevels = 0, k;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048) {
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		} else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		} else {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+		}
+	} else {
+		HostVMDynamicLevels = 0;
+	}
+
+	ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte + TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0;
+
+	if (GPUVMEnable == true) {
+		for (k = 0; k < NumberOfActivePlanes; ++k) {
+			ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
+		}
+	}
+	return ret;
+}
+
+static double CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClock)
+{
+	double ret;
+
+	ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
+	if (DoUrgentLatencyAdjustment == true) {
+		ret = ret + UrgentLatencyAdjustmentFabricClockComponent * (UrgentLatencyAdjustmentFabricClockReference / FabricClock - 1);
+	}
+	return ret;
+}
+
+static void UseMinimumDCFCLK(
+		struct display_mode_lib *mode_lib,
+		int MaxInterDCNTileRepeaters,
+		int MaxPrefetchMode,
+		double FinalDRAMClockChangeLatency,
+		double SREnterPlusExitTime,
+		int ReturnBusWidth,
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		int PixelChunkSizeInKByte,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		enum immediate_flip_requirement ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+		int VTotal[],
+		int VActive[],
+		int DynamicMetadataTransmittedBytes[],
+		int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFCLKDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		double TotalVActivePixelBandwidth[][2],
+		double TotalVActiveCursorBandwidth[][2],
+		double TotalMetaRowBandwidth[][2],
+		double TotalDPTERowBandwidth[][2],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX],
+		double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		double DCFCLKState[][2])
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	int dummy1, i, j, k;
+	double NormalEfficiency,  dummy2, dummy3;
+	double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
+
+	NormalEfficiency = PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0;
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX];
+			double PrefetchPixelLinesTime[DC__NUM_DPP__MAX];
+			double DCFCLKRequiredForPeakBandwidthPerPlane[DC__NUM_DPP__MAX];
+			double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX];
+			double MinimumTWait;
+			double NonDPTEBandwidth;
+			double DPTEBandwidth;
+			double DCFCLKRequiredForAverageBandwidth;
+			double ExtraLatencyBytes;
+			double ExtraLatencyCycles;
+			double DCFCLKRequiredForPeakBandwidth;
+			int NoOfDPPState[DC__NUM_DPP__MAX];
+			double MinimumTvmPlus2Tr0;
+
+			TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
+			for (k = 0; k < NumberOfActivePlanes; ++k) {
+				TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j]
+						+ NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] / (15.75 * HTotal[k] / PixelClock[k]);
+			}
+
+			for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
+				NoOfDPPState[k] = NoOfDPP[i][j][k];
+			}
+
+			MinimumTWait = CalculateTWait(MaxPrefetchMode, FinalDRAMClockChangeLatency, UrgLatency[i], SREnterPlusExitTime);
+			NonDPTEBandwidth = TotalVActivePixelBandwidth[i][j] + TotalVActiveCursorBandwidth[i][j] + TotalMetaRowBandwidth[i][j];
+			DPTEBandwidth = (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) ?
+					TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : TotalDPTERowBandwidth[i][j];
+			DCFCLKRequiredForAverageBandwidth = dml_max3(
+					ProjectedDCFCLKDeepSleep[i][j],
+					(NonDPTEBandwidth + TotalDPTERowBandwidth[i][j]) / ReturnBusWidth
+							/ (MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
+					(NonDPTEBandwidth + DPTEBandwidth / NormalEfficiency) / NormalEfficiency / ReturnBusWidth);
+
+			ExtraLatencyBytes = CalculateExtraLatencyBytes(
+					ReorderingBytes,
+					TotalNumberOfActiveDPP[i][j],
+					PixelChunkSizeInKByte,
+					TotalNumberOfDCCActiveDPP[i][j],
+					MetaChunkSize,
+					GPUVMEnable,
+					HostVMEnable,
+					NumberOfActivePlanes,
+					NoOfDPPState,
+					dpte_group_bytes,
+					1,
+					HostVMMinPageSize,
+					HostVMMaxNonCachedPageTableLevels);
+			ExtraLatencyCycles = RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth;
+			for (k = 0; k < NumberOfActivePlanes; ++k) {
+				double DCFCLKCyclesRequiredInPrefetch;
+				double ExpectedPrefetchBWAcceleration;
+				double PrefetchTime;
+
+				PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k] * swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
+						+ PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k] * BytePerPixelC[k]) / NormalEfficiency / ReturnBusWidth;
+				DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
+						+ PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth * (GPUVMMaxPageTableLevels > 2 ? 1 : 0)
+						+ 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth
+						+ 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
+				PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k]) * HTotal[k] / PixelClock[k];
+				ExpectedPrefetchBWAcceleration = (VActivePixelBandwidth[i][j][k] + VActiveCursorBandwidth[i][j][k])
+						/ (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
+				DynamicMetadataVMExtraLatency[k] =
+						(GPUVMEnable == true && DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
+								UrgLatency[i] * GPUVMMaxPageTableLevels * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
+				PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] - MinimumTWait
+						- UrgLatency[i]
+								* ((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels : GPUVMMaxPageTableLevels - 2)
+										* (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1)
+						- DynamicMetadataVMExtraLatency[k];
+
+				if (PrefetchTime > 0) {
+					double ExpectedVRatioPrefetch;
+					ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k]
+							/ (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
+					DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
+							* dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration;
+					if (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) {
+						DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
+								+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / ReturnBusWidth;
+					}
+				} else {
+					DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
+				}
+				if (DynamicMetadataEnable[k] == true) {
+					double TSetupPipe;
+					double TdmbfPipe;
+					double TdmsksPipe;
+					double TdmecPipe;
+					double AllowedTimeForUrgentExtraLatency;
+
+					CalculateVupdateAndDynamicMetadataParameters(
+							MaxInterDCNTileRepeaters,
+							RequiredDPPCLK[i][j][k],
+							RequiredDISPCLK[i][j],
+							ProjectedDCFCLKDeepSleep[i][j],
+							PixelClock[k],
+							HTotal[k],
+							VTotal[k] - VActive[k],
+							DynamicMetadataTransmittedBytes[k],
+							DynamicMetadataLinesBeforeActiveRequired[k],
+							Interlace[k],
+							ProgressiveToInterlaceUnitInOPP,
+							&TSetupPipe,
+							&TdmbfPipe,
+							&TdmecPipe,
+							&TdmsksPipe,
+							&dummy1,
+							&dummy2,
+							&dummy3);
+					AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] / PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
+							- TdmsksPipe - DynamicMetadataVMExtraLatency[k];
+					if (AllowedTimeForUrgentExtraLatency > 0) {
+						DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
+								DCFCLKRequiredForPeakBandwidthPerPlane[k],
+								ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
+					} else {
+						DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
+					}
+				}
+			}
+			DCFCLKRequiredForPeakBandwidth = 0;
+			for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
+				DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
+			}
+			MinimumTvmPlus2Tr0 = UrgLatency[i]
+					* (GPUVMEnable == true ?
+							(HostVMEnable == true ?
+									(GPUVMMaxPageTableLevels + 2) * (HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) :
+							0);
+			for (k = 0; k < NumberOfActivePlanes; ++k) {
+				double MaximumTvmPlus2Tr0PlusTsw;
+				MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] / PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
+				if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
+					DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i];
+				} else {
+					DCFCLKRequiredForPeakBandwidth = dml_max3(
+							DCFCLKRequiredForPeakBandwidth,
+							2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
+							(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
+				}
+			}
+			DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
+		}
+	}
+}
+
+static void CalculateUnboundedRequestAndCompressedBufferSize(
+		unsigned int DETBufferSizeInKByte,
+		int ConfigReturnBufferSizeInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		int TotalActiveDPP,
+		bool NoChromaPlanes,
+		int MaxNumDPP,
+		int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class *Output,
+		bool *UnboundedRequestEnabled,
+		int *CompressedBufferSizeInkByte)
+{
+	double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
+
+	*UnboundedRequestEnabled = UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, NoChromaPlanes, Output[0]);
+	*CompressedBufferSizeInkByte = (
+			*UnboundedRequestEnabled == true ?
+					ConfigReturnBufferSizeInKByte - TotalActiveDPP * actDETBufferSizeInKByte :
+					ConfigReturnBufferSizeInKByte - MaxNumDPP * actDETBufferSizeInKByte);
+	*CompressedBufferSizeInkByte = *CompressedBufferSizeInkByte * CompressedBufferSegmentSizeInkByteFinal / 64;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotalActiveDPP = %d\n", __func__, TotalActiveDPP);
+	dml_print("DML::%s: DETBufferSizeInKByte = %d\n", __func__, DETBufferSizeInKByte);
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal);
+	dml_print("DML::%s: actDETBufferSizeInKByte = %f\n", __func__, actDETBufferSizeInKByte);
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+#endif
+}
+
+static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output)
+{
+	bool ret_val = false;
+
+	ret_val = (UseUnboundedRequestingFinal != dm_unbounded_requesting_disable && TotalNumberOfActiveDPP == 1 && NoChroma);
+	if (UseUnboundedRequestingFinal == dm_unbounded_requesting_edp_only && Output != dm_edp) {
+		ret_val = false;
+	}
+	return (ret_val);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
new file mode 100644
index 000000000000..90be612f26b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML31_DISPLAY_MODE_VBA_H__
+#define __DML31_DISPLAY_MODE_VBA_H__
+
+void dml31_recalculate(struct display_mode_lib *mode_lib);
+void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
+double dml31_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		long   WritebackSourceWidth,
+		long   WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize);
+
+#endif /* __DML31_DISPLAY_MODE_VBA_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
new file mode 100644
index 000000000000..3def093ef88e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -0,0 +1,1724 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../display_mode_lib.h"
+#include "../display_mode_vba.h"
+#include "../dml_inline_defs.h"
+#include "display_rq_dlg_calc_31.h"
+
+static bool CalculateBytePerPixelAnd256BBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double *BytePerPixelDETY,
+		double *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC)
+{
+	if (SourcePixelFormat == dm_444_64) {
+		*BytePerPixelDETY = 8;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 8;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_16) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_rgbe_alpha) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 1;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 1;
+	} else if (SourcePixelFormat == dm_420_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 2;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 2;
+	} else if (SourcePixelFormat == dm_420_12) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 4;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	} else {
+		*BytePerPixelDETY = 4.0 / 3;
+		*BytePerPixelDETC = 8.0 / 3;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	}
+
+	if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16
+			|| SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+		} else if (SourcePixelFormat == dm_444_64) {
+			*BlockHeight256BytesY = 4;
+		} else if (SourcePixelFormat == dm_444_8) {
+			*BlockHeight256BytesY = 16;
+		} else {
+			*BlockHeight256BytesY = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockHeight256BytesC = 0;
+		*BlockWidth256BytesC = 0;
+	} else {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+			*BlockHeight256BytesC = 1;
+		} else if (SourcePixelFormat == dm_rgbe_alpha) {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 16;
+		} else if (SourcePixelFormat == dm_420_8) {
+			*BlockHeight256BytesY = 16;
+			*BlockHeight256BytesC = 8;
+		} else {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;
+	}
+	return true;
+}
+
+static bool is_dual_plane(enum source_format_class source_format)
+{
+	bool ret_val = 0;
+
+	if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha))
+		ret_val = 1;
+
+	return ret_val;
+}
+
+static double get_refcyc_per_delivery(
+		struct display_mode_lib *mode_lib,
+		double refclk_freq_in_mhz,
+		double pclk_freq_in_mhz,
+		unsigned int odm_combine,
+		unsigned int recout_width,
+		unsigned int hactive,
+		double vratio,
+		double hscale_pixel_rate,
+		unsigned int delivery_width,
+		unsigned int req_per_swath_ub)
+{
+	double refcyc_per_delivery = 0.0;
+
+	if (vratio <= 1.0) {
+		if (odm_combine)
+			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) ((unsigned int) odm_combine * 2)
+					* dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub;
+		else
+			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width / pclk_freq_in_mhz / (double) req_per_swath_ub;
+	} else {
+		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width / (double) hscale_pixel_rate / (double) req_per_swath_ub;
+	}
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
+	dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
+	dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
+	dml_print("DML_DLG: %s: hscale_pixel_rate  = %3.2f\n", __func__, hscale_pixel_rate);
+	dml_print("DML_DLG: %s: delivery_width     = %d\n", __func__, delivery_width);
+	dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
+#endif
+
+	return refcyc_per_delivery;
+
+}
+
+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
+{
+	if (tile_size == dm_256k_tile)
+		return (256 * 1024);
+	else if (tile_size == dm_64k_tile)
+		return (64 * 1024);
+	else
+		return (4 * 1024);
+}
+
+static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st rq_sizing)
+{
+	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
+
+	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
+
+	if (rq_sizing.min_chunk_bytes == 0)
+		rq_regs->min_chunk_size = 0;
+	else
+		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
+
+	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
+	if (rq_sizing.min_meta_chunk_bytes == 0)
+		rq_regs->min_meta_chunk_size = 0;
+	else
+		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
+
+	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
+	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
+}
+
+static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st rq_param)
+{
+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
+	unsigned int detile_buf_plane1_addr = 0;
+
+	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
+
+	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 1) - 3;
+
+	if (rq_param.yuv420) {
+		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
+		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 1) - 3;
+	}
+
+	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
+	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
+
+	// FIXME: take the max between luma, chroma chunk size?
+	// okay for now, as we are setting chunk_bytes to 8kb anyways
+	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param.yuv420 && rq_param.sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb
+		rq_regs->drq_expansion_mode = 0;
+	} else {
+		rq_regs->drq_expansion_mode = 2;
+	}
+	rq_regs->prq_expansion_mode = 1;
+	rq_regs->mrq_expansion_mode = 1;
+	rq_regs->crq_expansion_mode = 1;
+
+	// Note: detile_buf_plane1_addr is in unit of 1KB
+	if (rq_param.yuv420) {
+		if ((double) rq_param.misc.rq_l.stored_swath_bytes / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
+			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+					dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr);
+#endif
+		} else {
+			detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+					dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr);
+#endif
+		}
+	}
+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
+	dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d\n", __func__, detile_buf_plane1_addr);
+	dml_print("DML_DLG: %s: plane1_base_address = %0d\n", __func__, rq_regs->plane1_base_address);
+	dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_l.stored_swath_bytes);
+	dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_c.stored_swath_bytes);
+	dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param.dlg.rq_l.swath_height);
+	dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param.dlg.rq_c.swath_height);
+#endif
+}
+
+static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st pipe_src_param)
+{
+	unsigned int total_swath_bytes = 0;
+	unsigned int swath_bytes_l = 0;
+	unsigned int swath_bytes_c = 0;
+	unsigned int full_swath_bytes_packed_l = 0;
+	unsigned int full_swath_bytes_packed_c = 0;
+	bool req128_l = 0;
+	bool req128_c = 0;
+	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
+	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
+	unsigned int log2_swath_height_l = 0;
+	unsigned int log2_swath_height_c = 0;
+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
+
+	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
+	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
+#endif
+
+	if (rq_param->yuv420_10bpc) {
+		full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
+		full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+		dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l);
+		dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c);
+#endif
+	}
+
+	if (rq_param->yuv420)
+		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
+	else
+		total_swath_bytes = 2 * full_swath_bytes_packed_l;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
+	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
+#endif
+
+	if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
+		req128_l = 0;
+		req128_c = 0;
+		swath_bytes_l = full_swath_bytes_packed_l;
+		swath_bytes_c = full_swath_bytes_packed_c;
+	} else if (!rq_param->yuv420) {
+		req128_l = 1;
+		req128_c = 0;
+		swath_bytes_c = full_swath_bytes_packed_c;
+		swath_bytes_l = full_swath_bytes_packed_l / 2;
+	} else if ((double) full_swath_bytes_packed_l / (double) full_swath_bytes_packed_c < 1.5) {
+		req128_l = 0;
+		req128_c = 1;
+		swath_bytes_l = full_swath_bytes_packed_l;
+		swath_bytes_c = full_swath_bytes_packed_c / 2;
+
+		total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
+
+		if (total_swath_bytes > detile_buf_size_in_bytes) {
+			req128_l = 1;
+			swath_bytes_l = full_swath_bytes_packed_l / 2;
+		}
+	} else {
+		req128_l = 1;
+		req128_c = 0;
+		swath_bytes_l = full_swath_bytes_packed_l / 2;
+		swath_bytes_c = full_swath_bytes_packed_c;
+
+		total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
+
+		if (total_swath_bytes > detile_buf_size_in_bytes) {
+			req128_c = 1;
+			swath_bytes_c = full_swath_bytes_packed_c / 2;
+		}
+	}
+
+	if (rq_param->yuv420)
+		total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
+	else
+		total_swath_bytes = 2 * swath_bytes_l;
+
+	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
+	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
+	dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes);
+	dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes);
+#endif
+	if (surf_linear) {
+		log2_swath_height_l = 0;
+		log2_swath_height_c = 0;
+	} else {
+		unsigned int swath_height_l;
+		unsigned int swath_height_c;
+
+		if (!surf_vert) {
+			swath_height_l = rq_param->misc.rq_l.blk256_height;
+			swath_height_c = rq_param->misc.rq_c.blk256_height;
+		} else {
+			swath_height_l = rq_param->misc.rq_l.blk256_width;
+			swath_height_c = rq_param->misc.rq_c.blk256_width;
+		}
+
+		if (swath_height_l > 0)
+			log2_swath_height_l = dml_log2(swath_height_l);
+
+		if (req128_l && log2_swath_height_l > 0)
+			log2_swath_height_l -= 1;
+
+		if (swath_height_c > 0)
+			log2_swath_height_c = dml_log2(swath_height_c);
+
+		if (req128_c && log2_swath_height_c > 0)
+			log2_swath_height_c -= 1;
+	}
+
+	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
+	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
+	dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
+	dml_print("DML_DLG: %s: swath_height luma = %0d\n", __func__, rq_param->dlg.rq_l.swath_height);
+	dml_print("DML_DLG: %s: swath_height chroma = %0d\n", __func__, rq_param->dlg.rq_c.swath_height);
+#endif
+}
+
+static void get_meta_and_pte_attr(
+		struct display_mode_lib *mode_lib,
+		display_data_rq_dlg_params_st *rq_dlg_param,
+		display_data_rq_misc_params_st *rq_misc_param,
+		display_data_rq_sizing_params_st *rq_sizing_param,
+		unsigned int vp_width,
+		unsigned int vp_height,
+		unsigned int data_pitch,
+		unsigned int meta_pitch,
+		unsigned int source_format,
+		unsigned int tiling,
+		unsigned int macro_tile_size,
+		unsigned int source_scan,
+		unsigned int hostvm_enable,
+		unsigned int is_chroma,
+		unsigned int surface_height)
+{
+	bool surf_linear = (tiling == dm_sw_linear);
+	bool surf_vert = (source_scan == dm_vert);
+
+	unsigned int bytes_per_element;
+	unsigned int bytes_per_element_y;
+	unsigned int bytes_per_element_c;
+
+	unsigned int blk256_width = 0;
+	unsigned int blk256_height = 0;
+
+	unsigned int blk256_width_y = 0;
+	unsigned int blk256_height_y = 0;
+	unsigned int blk256_width_c = 0;
+	unsigned int blk256_height_c = 0;
+	unsigned int log2_bytes_per_element;
+	unsigned int log2_blk256_width;
+	unsigned int log2_blk256_height;
+	unsigned int blk_bytes;
+	unsigned int log2_blk_bytes;
+	unsigned int log2_blk_height;
+	unsigned int log2_blk_width;
+	unsigned int log2_meta_req_bytes;
+	unsigned int log2_meta_req_height;
+	unsigned int log2_meta_req_width;
+	unsigned int meta_req_width;
+	unsigned int meta_req_height;
+	unsigned int log2_meta_row_height;
+	unsigned int meta_row_width_ub;
+	unsigned int log2_meta_chunk_bytes;
+	unsigned int log2_meta_chunk_height;
+
+	//full sized meta chunk width in unit of data elements
+	unsigned int log2_meta_chunk_width;
+	unsigned int log2_min_meta_chunk_bytes;
+	unsigned int min_meta_chunk_width;
+	unsigned int meta_chunk_width;
+	unsigned int meta_chunk_per_row_int;
+	unsigned int meta_row_remainder;
+	unsigned int meta_chunk_threshold;
+	unsigned int meta_blk_height;
+	unsigned int meta_surface_bytes;
+	unsigned int vmpg_bytes;
+	unsigned int meta_pte_req_per_frame_ub;
+	unsigned int meta_pte_bytes_per_frame_ub;
+	const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes);
+	const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format));
+	const unsigned int dpte_buf_in_pte_reqs =
+			dual_plane_en ? (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma
+							+ mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma);
+
+	unsigned int log2_vmpg_height = 0;
+	unsigned int log2_vmpg_width = 0;
+	unsigned int log2_dpte_req_height_ptes = 0;
+	unsigned int log2_dpte_req_height = 0;
+	unsigned int log2_dpte_req_width = 0;
+	unsigned int log2_dpte_row_height_linear = 0;
+	unsigned int log2_dpte_row_height = 0;
+	unsigned int log2_dpte_group_width = 0;
+	unsigned int dpte_row_width_ub = 0;
+	unsigned int dpte_req_height = 0;
+	unsigned int dpte_req_width = 0;
+	unsigned int dpte_group_width = 0;
+	unsigned int log2_dpte_group_bytes = 0;
+	unsigned int log2_dpte_group_length = 0;
+	double byte_per_pixel_det_y;
+	double byte_per_pixel_det_c;
+
+	CalculateBytePerPixelAnd256BBlockSizes(
+			(enum source_format_class) (source_format),
+			(enum dm_swizzle_mode) (tiling),
+			&bytes_per_element_y,
+			&bytes_per_element_c,
+			&byte_per_pixel_det_y,
+			&byte_per_pixel_det_c,
+			&blk256_height_y,
+			&blk256_height_c,
+			&blk256_width_y,
+			&blk256_width_c);
+
+	if (!is_chroma) {
+		blk256_width = blk256_width_y;
+		blk256_height = blk256_height_y;
+		bytes_per_element = bytes_per_element_y;
+	} else {
+		blk256_width = blk256_width_c;
+		blk256_height = blk256_height_c;
+		bytes_per_element = bytes_per_element_c;
+	}
+
+	log2_bytes_per_element = dml_log2(bytes_per_element);
+
+	dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
+	dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
+	dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
+	dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
+
+	log2_blk256_width = dml_log2((double) blk256_width);
+	log2_blk256_height = dml_log2((double) blk256_height);
+	blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
+	log2_blk_bytes = dml_log2((double) blk_bytes);
+	log2_blk_height = 0;
+	log2_blk_width = 0;
+
+	// remember log rule
+	// "+" in log is multiply
+	// "-" in log is divide
+	// "/2" is like square root
+	// blk is vertical biased
+	if (tiling != dm_sw_linear)
+		log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
+	else
+		log2_blk_height = 0;	// blk height of 1
+
+	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
+
+	if (!surf_vert) {
+		int unsigned temp;
+
+		temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width;
+		if (data_pitch < blk256_width) {
+			dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width);
+		} else {
+			if (temp > data_pitch) {
+				if (data_pitch >= vp_width)
+					temp = data_pitch;
+				else
+					dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width);
+			}
+		}
+		rq_dlg_param->swath_width_ub = temp;
+		rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width;
+	} else {
+		int unsigned temp;
+
+		temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height;
+		if (surface_height < blk256_height) {
+			dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height);
+		} else {
+			if (temp > surface_height) {
+				if (surface_height >= vp_height)
+					temp = surface_height;
+				else
+					dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height);
+			}
+		}
+		rq_dlg_param->swath_width_ub = temp;
+		rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height;
+	}
+
+	if (!surf_vert)
+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height * bytes_per_element;
+	else
+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width * bytes_per_element;
+
+	rq_misc_param->blk256_height = blk256_height;
+	rq_misc_param->blk256_width = blk256_width;
+
+	// -------
+	// meta
+	// -------
+	log2_meta_req_bytes = 6;	// meta request is 64b and is 8x8byte meta element
+
+	// each 64b meta request for dcn is 8x8 meta elements and
+	// a meta element covers one 256b block of the the data surface.
+	log2_meta_req_height = log2_blk256_height + 3;	// meta req is 8x8 byte, each byte represent 1 blk256
+	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height;
+	meta_req_width = 1 << log2_meta_req_width;
+	meta_req_height = 1 << log2_meta_req_height;
+	log2_meta_row_height = 0;
+	meta_row_width_ub = 0;
+
+	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.
+	// calculate upper bound of the meta_row_width
+	if (!surf_vert) {
+		log2_meta_row_height = log2_meta_req_height;
+		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width;
+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
+	} else {
+		log2_meta_row_height = log2_meta_req_width;
+		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height;
+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
+	}
+	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
+
+	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
+
+	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
+	log2_meta_chunk_height = log2_meta_row_height;
+
+	//full sized meta chunk width in unit of data elements
+	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height;
+	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
+	min_meta_chunk_width = 1 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height);
+	meta_chunk_width = 1 << log2_meta_chunk_width;
+	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
+	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
+	meta_chunk_threshold = 0;
+	meta_blk_height = blk256_height * 64;
+	meta_surface_bytes = meta_pitch * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) * bytes_per_element / 256;
+	vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes;
+	meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 8 * vmpg_bytes, 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
+	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64;	//64B mpte request
+	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
+
+	dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
+	dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
+	dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n", __func__, meta_pte_req_per_frame_ub);
+	dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", __func__, meta_pte_bytes_per_frame_ub);
+
+	if (!surf_vert)
+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
+	else
+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
+
+	if (meta_row_remainder <= meta_chunk_threshold)
+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
+	else
+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
+
+	// ------
+	// dpte
+	// ------
+	if (surf_linear) {
+		log2_vmpg_height = 0;   // one line high
+	} else {
+		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
+	}
+	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
+
+	// only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
+	if (surf_linear) { //one 64B PTE request returns 8 PTEs
+		log2_dpte_req_height_ptes = 0;
+		log2_dpte_req_width = log2_vmpg_width + 3;
+		log2_dpte_req_height = 0;
+	} else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
+		//one 64B req gives 8x1 PTEs for 4KB tile
+		log2_dpte_req_height_ptes = 0;
+		log2_dpte_req_width = log2_blk_width + 3;
+		log2_dpte_req_height = log2_blk_height + 0;
+	} else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
+		//two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
+		log2_dpte_req_height_ptes = 4;
+		log2_dpte_req_width = log2_blk256_width + 4;		// log2_64KB_width
+		log2_dpte_req_height = log2_blk256_height + 4;		// log2_64KB_height
+	} else { //64KB page size and must 64KB tile block
+		 //one 64B req gives 8x1 PTEs for 64KB tile
+		log2_dpte_req_height_ptes = 0;
+		log2_dpte_req_width = log2_blk_width + 3;
+		log2_dpte_req_height = log2_blk_height + 0;
+	}
+
+	// The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
+	// log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
+	// That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
+	//log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
+	//log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
+	dpte_req_height = 1 << log2_dpte_req_height;
+	dpte_req_width = 1 << log2_dpte_req_width;
+
+	// calculate pitch dpte row buffer can hold
+	// round the result down to a power of two.
+	if (surf_linear) {
+		unsigned int dpte_row_height;
+
+		log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1);
+
+		dml_print("DML_DLG: %s: is_chroma                   = %d\n", __func__, is_chroma);
+		dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs        = %d\n", __func__, dpte_buf_in_pte_reqs);
+		dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear);
+
+		ASSERT(log2_dpte_row_height_linear >= 3);
+
+		if (log2_dpte_row_height_linear > 7)
+			log2_dpte_row_height_linear = 7;
+
+		log2_dpte_row_height = log2_dpte_row_height_linear;
+		// For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
+		// the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
+		dpte_row_height = 1 << log2_dpte_row_height;
+		dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + dpte_req_width;
+		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
+	} else {
+		// the upper bound of the dpte_row_width without dependency on viewport position follows.
+		// for tiled mode, row height is the same as req height and row store up to vp size upper bound
+		if (!surf_vert) {
+			log2_dpte_row_height = log2_dpte_req_height;
+			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) + dpte_req_width;
+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
+		} else {
+			log2_dpte_row_height = (log2_blk_width < log2_dpte_req_width) ? log2_blk_width : log2_dpte_req_width;
+			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) + dpte_req_height;
+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
+		}
+	}
+	if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
+	else
+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
+
+	rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
+
+	// the dpte_group_bytes is reduced for the specific case of vertical
+	// access of a tile surface that has dpte request of 8x1 ptes.
+	if (hostvm_enable)
+		rq_sizing_param->dpte_group_bytes = 512;
+	else {
+		if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
+			rq_sizing_param->dpte_group_bytes = 512;
+		else
+			rq_sizing_param->dpte_group_bytes = 2048;
+	}
+
+	//since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
+	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
+	log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
+
+	// full sized data pte group width in elements
+	if (!surf_vert)
+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
+	else
+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
+
+	//But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
+	if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
+		log2_dpte_group_width = log2_dpte_group_width - 1;
+
+	dpte_group_width = 1 << log2_dpte_group_width;
+
+	// since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
+	// the upper bound for the dpte groups per row is as follows.
+	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1);
+}
+
+static void get_surf_rq_param(
+		struct display_mode_lib *mode_lib,
+		display_data_rq_sizing_params_st *rq_sizing_param,
+		display_data_rq_dlg_params_st *rq_dlg_param,
+		display_data_rq_misc_params_st *rq_misc_param,
+		const display_pipe_params_st pipe_param,
+		bool is_chroma,
+		bool is_alpha)
+{
+	bool mode_422 = 0;
+	unsigned int vp_width = 0;
+	unsigned int vp_height = 0;
+	unsigned int data_pitch = 0;
+	unsigned int meta_pitch = 0;
+	unsigned int surface_height = 0;
+	unsigned int ppe = mode_422 ? 2 : 1;
+
+	// FIXME check if ppe apply for both luma and chroma in 422 case
+	if (is_chroma | is_alpha) {
+		vp_width = pipe_param.src.viewport_width_c / ppe;
+		vp_height = pipe_param.src.viewport_height_c;
+		data_pitch = pipe_param.src.data_pitch_c;
+		meta_pitch = pipe_param.src.meta_pitch_c;
+		surface_height = pipe_param.src.surface_height_y / 2.0;
+	} else {
+		vp_width = pipe_param.src.viewport_width / ppe;
+		vp_height = pipe_param.src.viewport_height;
+		data_pitch = pipe_param.src.data_pitch;
+		meta_pitch = pipe_param.src.meta_pitch;
+		surface_height = pipe_param.src.surface_height_y;
+	}
+
+	if (pipe_param.dest.odm_combine) {
+		unsigned int access_dir;
+		unsigned int full_src_vp_width;
+		unsigned int hactive_odm;
+		unsigned int src_hactive_odm;
+
+		access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
+		hactive_odm = pipe_param.dest.hactive / ((unsigned int) pipe_param.dest.odm_combine * 2);
+		if (is_chroma) {
+			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
+			src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_odm;
+		} else {
+			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
+			src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio * hactive_odm;
+		}
+
+		if (access_dir == 0) {
+			vp_width = dml_min(full_src_vp_width, src_hactive_odm);
+			dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
+		} else {
+			vp_height = dml_min(full_src_vp_width, src_hactive_odm);
+			dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height);
+
+		}
+		dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width);
+		dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm);
+		dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm);
+	}
+
+	rq_sizing_param->chunk_bytes = 8192;
+
+	if (is_alpha) {
+		rq_sizing_param->chunk_bytes = 4096;
+	}
+
+	if (rq_sizing_param->chunk_bytes == 64 * 1024)
+		rq_sizing_param->min_chunk_bytes = 0;
+	else
+		rq_sizing_param->min_chunk_bytes = 1024;
+
+	rq_sizing_param->meta_chunk_bytes = 2048;
+	rq_sizing_param->min_meta_chunk_bytes = 256;
+
+	if (pipe_param.src.hostvm)
+		rq_sizing_param->mpte_group_bytes = 512;
+	else
+		rq_sizing_param->mpte_group_bytes = 2048;
+
+	get_meta_and_pte_attr(
+			mode_lib,
+			rq_dlg_param,
+			rq_misc_param,
+			rq_sizing_param,
+			vp_width,
+			vp_height,
+			data_pitch,
+			meta_pitch,
+			pipe_param.src.source_format,
+			pipe_param.src.sw_mode,
+			pipe_param.src.macro_tile_size,
+			pipe_param.src.source_scan,
+			pipe_param.src.hostvm,
+			is_chroma,
+			surface_height);
+}
+
+static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st pipe_param)
+{
+	// get param for luma surface
+	rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 || pipe_param.src.source_format == dm_420_10 || pipe_param.src.source_format == dm_rgbe_alpha
+			|| pipe_param.src.source_format == dm_420_12;
+
+	rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
+
+	rq_param->rgbe_alpha = (pipe_param.src.source_format == dm_rgbe_alpha) ? 1 : 0;
+
+	get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_l), &(rq_param->dlg.rq_l), &(rq_param->misc.rq_l), pipe_param, 0, 0);
+
+	if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
+		// get param for chroma surface
+		get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_c), &(rq_param->dlg.rq_c), &(rq_param->misc.rq_c), pipe_param, 1, rq_param->rgbe_alpha);
+	}
+
+	// calculate how to split the det buffer space between luma and chroma
+	handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
+	print__rq_params_st(mode_lib, *rq_param);
+}
+
+void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st pipe_param)
+{
+	display_rq_params_st rq_param = {0};
+
+	memset(rq_regs, 0, sizeof(*rq_regs));
+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
+	extract_rq_regs(mode_lib, rq_regs, rq_param);
+
+	print__rq_regs_st(mode_lib, *rq_regs);
+}
+
+static void calculate_ttu_cursor(
+		struct display_mode_lib *mode_lib,
+		double *refcyc_per_req_delivery_pre_cur,
+		double *refcyc_per_req_delivery_cur,
+		double refclk_freq_in_mhz,
+		double ref_freq_to_pix_freq,
+		double hscale_pixel_rate_l,
+		double hscl_ratio,
+		double vratio_pre_l,
+		double vratio_l,
+		unsigned int cur_width,
+		enum cursor_bpp cur_bpp)
+{
+	unsigned int cur_src_width = cur_width;
+	unsigned int cur_req_size = 0;
+	unsigned int cur_req_width = 0;
+	double cur_width_ub = 0.0;
+	double cur_req_per_width = 0.0;
+	double hactive_cur = 0.0;
+
+	ASSERT(cur_src_width <= 256);
+
+	*refcyc_per_req_delivery_pre_cur = 0.0;
+	*refcyc_per_req_delivery_cur = 0.0;
+	if (cur_src_width > 0) {
+		unsigned int cur_bit_per_pixel = 0;
+
+		if (cur_bpp == dm_cur_2bit) {
+			cur_req_size = 64; // byte
+			cur_bit_per_pixel = 2;
+		} else { // 32bit
+			cur_bit_per_pixel = 32;
+			if (cur_src_width >= 1 && cur_src_width <= 16)
+				cur_req_size = 64;
+			else if (cur_src_width >= 17 && cur_src_width <= 31)
+				cur_req_size = 128;
+			else
+				cur_req_size = 256;
+		}
+
+		cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
+		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width;
+		cur_req_per_width = cur_width_ub / (double) cur_req_width;
+		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
+
+		if (vratio_pre_l <= 1.0) {
+			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
+		} else {
+			*refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
+		}
+
+		ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
+
+		if (vratio_l <= 1.0) {
+			*refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
+		} else {
+			*refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
+		}
+
+		dml_print("DML_DLG: %s: cur_req_width                     = %d\n", __func__, cur_req_width);
+		dml_print("DML_DLG: %s: cur_width_ub                      = %3.2f\n", __func__, cur_width_ub);
+		dml_print("DML_DLG: %s: cur_req_per_width                 = %3.2f\n", __func__, cur_req_per_width);
+		dml_print("DML_DLG: %s: hactive_cur                       = %3.2f\n", __func__, hactive_cur);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n", __func__, *refcyc_per_req_delivery_pre_cur);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n", __func__, *refcyc_per_req_delivery_cur);
+
+		ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
+	}
+}
+
+// Note: currently taken in as is.
+// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
+static void dml_rq_dlg_get_dlg_params(
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx,
+		display_dlg_regs_st *disp_dlg_regs,
+		display_ttu_regs_st *disp_ttu_regs,
+		const display_rq_dlg_params_st rq_dlg_param,
+		const display_dlg_sys_params_st dlg_sys_param,
+		const bool cstate_en,
+		const bool pstate_en,
+		const bool vm_en,
+		const bool ignore_viewport_pos,
+		const bool immediate_flip_support)
+{
+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
+	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
+	const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
+	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
+	const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
+	const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
+	unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
+
+	// -------------------------
+	// Section 1.15.2.1: OTG dependent Params
+	// -------------------------
+	// Timing
+	unsigned int htotal = dst->htotal;
+	unsigned int hblank_end = dst->hblank_end;
+	unsigned int vblank_start = dst->vblank_start;
+	unsigned int vblank_end = dst->vblank_end;
+
+	double dppclk_freq_in_mhz = clks->dppclk_mhz;
+	double refclk_freq_in_mhz = clks->refclk_mhz;
+	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
+	bool interlaced = dst->interlaced;
+	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
+	double min_ttu_vblank;
+	unsigned int dlg_vblank_start;
+	bool dual_plane;
+	bool mode_422;
+	unsigned int access_dir;
+	unsigned int vp_height_l;
+	unsigned int vp_width_l;
+	unsigned int vp_height_c;
+	unsigned int vp_width_c;
+
+	// Scaling
+	unsigned int htaps_l;
+	unsigned int htaps_c;
+	double hratio_l;
+	double hratio_c;
+	double vratio_l;
+	double vratio_c;
+	bool scl_enable;
+
+	unsigned int swath_width_ub_l;
+	unsigned int dpte_groups_per_row_ub_l;
+	unsigned int swath_width_ub_c;
+	unsigned int dpte_groups_per_row_ub_c;
+
+	unsigned int meta_chunks_per_row_ub_l;
+	unsigned int meta_chunks_per_row_ub_c;
+	unsigned int vupdate_offset;
+	unsigned int vupdate_width;
+	unsigned int vready_offset;
+
+	unsigned int dppclk_delay_subtotal;
+	unsigned int dispclk_delay_subtotal;
+
+	unsigned int vstartup_start;
+	unsigned int dst_x_after_scaler;
+	unsigned int dst_y_after_scaler;
+	double dst_y_prefetch;
+	double dst_y_per_vm_vblank;
+	double dst_y_per_row_vblank;
+	double dst_y_per_vm_flip;
+	double dst_y_per_row_flip;
+	double max_dst_y_per_vm_vblank;
+	double max_dst_y_per_row_vblank;
+	double vratio_pre_l;
+	double vratio_pre_c;
+	unsigned int req_per_swath_ub_l;
+	unsigned int req_per_swath_ub_c;
+	unsigned int meta_row_height_l;
+	unsigned int meta_row_height_c;
+	unsigned int swath_width_pixels_ub_l;
+	unsigned int swath_width_pixels_ub_c;
+	unsigned int scaler_rec_in_width_l;
+	unsigned int scaler_rec_in_width_c;
+	unsigned int dpte_row_height_l;
+	unsigned int dpte_row_height_c;
+	double hscale_pixel_rate_l;
+	double hscale_pixel_rate_c;
+	double min_hratio_fact_l;
+	double min_hratio_fact_c;
+	double refcyc_per_line_delivery_pre_l;
+	double refcyc_per_line_delivery_pre_c;
+	double refcyc_per_line_delivery_l;
+	double refcyc_per_line_delivery_c;
+
+	double refcyc_per_req_delivery_pre_l;
+	double refcyc_per_req_delivery_pre_c;
+	double refcyc_per_req_delivery_l;
+	double refcyc_per_req_delivery_c;
+
+	unsigned int full_recout_width;
+	double refcyc_per_req_delivery_pre_cur0;
+	double refcyc_per_req_delivery_cur0;
+	double refcyc_per_req_delivery_pre_cur1;
+	double refcyc_per_req_delivery_cur1;
+	int unsigned vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
+	int unsigned vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+
+	float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+	float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+	float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+
+	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
+	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
+
+	dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
+	dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
+	dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
+	dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
+	dml_print("DML_DLG: %s: immediate_flip_support  = %d\n", __func__, immediate_flip_support);
+
+	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0);
+
+	disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
+	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
+	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end;	// 15 bits
+
+	//set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
+	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
+
+	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
+
+	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
+
+	dml_print("DML_DLG: %s: min_ttu_vblank (us)         = %3.2f\n", __func__, min_ttu_vblank);
+	dml_print("DML_DLG: %s: min_dst_y_next_start        = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start);
+	dml_print("DML_DLG: %s: dlg_vblank_start            = 0x%0x\n", __func__, dlg_vblank_start);
+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq        = %3.2f\n", __func__, ref_freq_to_pix_freq);
+	dml_print("DML_DLG: %s: vba__min_dst_y_next_start   = 0x%0x\n", __func__, vba__min_dst_y_next_start);
+
+	//old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start);
+
+	// -------------------------
+	// Section 1.15.2.2: Prefetch, Active and TTU
+	// -------------------------
+	// Prefetch Calc
+	// Source
+	dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
+	mode_422 = 0;
+	access_dir = (src->source_scan == dm_vert);	// vp access direction: horizontal or vertical accessed
+	vp_height_l = src->viewport_height;
+	vp_width_l = src->viewport_width;
+	vp_height_c = src->viewport_height_c;
+	vp_width_c = src->viewport_width_c;
+
+	// Scaling
+	htaps_l = taps->htaps;
+	htaps_c = taps->htaps_c;
+	hratio_l = scl->hscl_ratio;
+	hratio_c = scl->hscl_ratio_c;
+	vratio_l = scl->vscl_ratio;
+	vratio_c = scl->vscl_ratio_c;
+	scl_enable = scl->scl_enable;
+
+	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
+	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
+	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
+	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
+
+	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
+	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
+	vupdate_offset = dst->vupdate_offset;
+	vupdate_width = dst->vupdate_width;
+	vready_offset = dst->vready_offset;
+
+	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
+	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
+
+	if (scl_enable)
+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
+	else
+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
+
+	dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
+
+	if (dout->dsc_enable) {
+		double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
+		dispclk_delay_subtotal += dsc_delay;
+	}
+
+	vstartup_start = dst->vstartup_start;
+	if (interlaced) {
+		if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0)
+			disp_dlg_regs->vready_after_vcount0 = 1;
+		else
+			disp_dlg_regs->vready_after_vcount0 = 0;
+	} else {
+		if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end)
+			disp_dlg_regs->vready_after_vcount0 = 1;
+		else
+			disp_dlg_regs->vready_after_vcount0 = 0;
+	}
+
+	dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
+	dml_print("DML_DLG: %s: vba__vready_after_vcount0 = %d\n", __func__, vba__vready_after_vcount0);
+	//old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0);
+
+	if (interlaced)
+		vstartup_start = vstartup_start / 2;
+
+	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+
+	// do some adjustment on the dst_after scaler to account for odm combine mode
+	dml_print("DML_DLG: %s: input dst_x_after_scaler   = %d\n", __func__, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: input dst_y_after_scaler   = %d\n", __func__, dst_y_after_scaler);
+
+	// need to figure out which side of odm combine we're in
+	if (dst->odm_combine) {
+		// figure out which pipes go together
+		bool visited[DC__NUM_PIPES__MAX];
+		unsigned int i, j, k;
+
+		for (k = 0; k < num_pipes; ++k) {
+			visited[k] = false;
+			pipe_index_in_combine[k] = 0;
+		}
+
+		for (i = 0; i < num_pipes; i++) {
+			if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
+
+				unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
+				unsigned int grp_idx = 0;
+
+				for (j = i; j < num_pipes; j++) {
+					if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {
+						pipe_index_in_combine[j] = grp_idx;
+						dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx);
+						grp_idx++;
+						visited[j] = true;
+					}
+				}
+			}
+		}
+
+	}
+
+	if (dst->odm_combine == dm_odm_combine_mode_disabled) {
+		disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq);
+	} else {
+		unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4
+		unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx];
+		disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq);
+	} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
+
+	dml_print("DML_DLG: %s: htotal                     = %d\n", __func__, htotal);
+	dml_print("DML_DLG: %s: dst_x_after_scaler[%d]     = %d\n", __func__, pipe_idx, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: dst_y_after_scaler[%d]     = %d\n", __func__, pipe_idx, dst_y_after_scaler);
+
+	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+
+	max_dst_y_per_vm_vblank = 32.0;        //U5.2
+	max_dst_y_per_row_vblank = 16.0;        //U4.2
+
+	// magic!
+	if (htotal <= 75) {
+		max_dst_y_per_vm_vblank = 100.0;
+		max_dst_y_per_row_vblank = 100.0;
+	}
+
+	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
+	dml_print("DML_DLG: %s: dst_y_per_vm_flip    = %3.2f\n", __func__, dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: dst_y_per_row_flip   = %3.2f\n", __func__, dst_y_per_row_flip);
+	dml_print("DML_DLG: %s: dst_y_per_vm_vblank  = %3.2f\n", __func__, dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
+
+	ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
+
+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
+
+	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+
+	dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l);
+	dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c);
+
+	// Active
+	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
+	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
+	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
+	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
+	swath_width_pixels_ub_l = 0;
+	swath_width_pixels_ub_c = 0;
+	scaler_rec_in_width_l = 0;
+	scaler_rec_in_width_c = 0;
+	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
+	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
+
+	if (mode_422) {
+		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
+		swath_width_pixels_ub_c = swath_width_ub_c * 2;
+	} else {
+		swath_width_pixels_ub_l = swath_width_ub_l * 1;
+		swath_width_pixels_ub_c = swath_width_ub_c * 1;
+	}
+
+	hscale_pixel_rate_l = 0.;
+	hscale_pixel_rate_c = 0.;
+	min_hratio_fact_l = 1.0;
+	min_hratio_fact_c = 1.0;
+
+	if (hratio_l <= 1)
+		min_hratio_fact_l = 2.0;
+	else if (htaps_l <= 6) {
+		if ((hratio_l * 2.0) > 4.0)
+			min_hratio_fact_l = 4.0;
+		else
+			min_hratio_fact_l = hratio_l * 2.0;
+	} else {
+		if (hratio_l > 4.0)
+			min_hratio_fact_l = 4.0;
+		else
+			min_hratio_fact_l = hratio_l;
+	}
+
+	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
+
+	dml_print("DML_DLG: %s: hratio_l = %3.2f\n", __func__, hratio_l);
+	dml_print("DML_DLG: %s: min_hratio_fact_l = %3.2f\n", __func__, min_hratio_fact_l);
+	dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
+
+	if (hratio_c <= 1)
+		min_hratio_fact_c = 2.0;
+	else if (htaps_c <= 6) {
+		if ((hratio_c * 2.0) > 4.0)
+			min_hratio_fact_c = 4.0;
+		else
+			min_hratio_fact_c = hratio_c * 2.0;
+	} else {
+		if (hratio_c > 4.0)
+			min_hratio_fact_c = 4.0;
+		else
+			min_hratio_fact_c = hratio_c;
+	}
+
+	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
+
+	refcyc_per_line_delivery_pre_l = 0.;
+	refcyc_per_line_delivery_pre_c = 0.;
+	refcyc_per_line_delivery_l = 0.;
+	refcyc_per_line_delivery_c = 0.;
+
+	refcyc_per_req_delivery_pre_l = 0.;
+	refcyc_per_req_delivery_pre_c = 0.;
+	refcyc_per_req_delivery_l = 0.;
+	refcyc_per_req_delivery_c = 0.;
+
+	full_recout_width = 0;
+	// In ODM
+	if (src->is_hsplit) {
+		// This "hack"  is only allowed (and valid) for MPC combine. In ODM
+		// combine, you MUST specify the full_recout_width...according to Oswin
+		if (dst->full_recout_width == 0 && !dst->odm_combine) {
+			dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", __func__);
+			full_recout_width = dst->recout_width * 2; // assume half split for dcn1
+		} else
+			full_recout_width = dst->full_recout_width;
+	} else
+		full_recout_width = dst->recout_width;
+
+	// As of DCN2, mpc_combine and odm_combine are mutually exclusive
+	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_pre_l,
+			hscale_pixel_rate_l,
+			swath_width_pixels_ub_l,
+			1); // per line
+
+	refcyc_per_line_delivery_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_l,
+			hscale_pixel_rate_l,
+			swath_width_pixels_ub_l,
+			1); // per line
+
+	dml_print("DML_DLG: %s: full_recout_width              = %d\n", __func__, full_recout_width);
+	dml_print("DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n", __func__, hscale_pixel_rate_l);
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n", __func__, refcyc_per_line_delivery_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_l     = %3.2f\n", __func__, vba__refcyc_per_line_delivery_l);
+
+	//old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_l", refcyc_per_line_delivery_pre_l, vba__refcyc_per_line_delivery_pre_l);
+	//old_impl_vs_vba_impl("refcyc_per_line_delivery_l", refcyc_per_line_delivery_l, vba__refcyc_per_line_delivery_l);
+
+	if (dual_plane) {
+		float vba__refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+		float vba__refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_pre_c,
+				hscale_pixel_rate_c,
+				swath_width_pixels_ub_c,
+				1); // per line
+
+		refcyc_per_line_delivery_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_c,
+				hscale_pixel_rate_c,
+				swath_width_pixels_ub_c,
+				1); // per line
+
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, refcyc_per_line_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n", __func__, refcyc_per_line_delivery_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_c     = %3.2f\n", __func__, vba__refcyc_per_line_delivery_c);
+
+		//old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_c", refcyc_per_line_delivery_pre_c, vba__refcyc_per_line_delivery_pre_c);
+		//old_impl_vs_vba_impl("refcyc_per_line_delivery_c", refcyc_per_line_delivery_c, vba__refcyc_per_line_delivery_c);
+	}
+
+	if (src->dynamic_metadata_enable && src->gpuvm)
+		disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	// TTU - Luma / Chroma
+	if (access_dir) {  // vertical access
+		scaler_rec_in_width_l = vp_height_l;
+		scaler_rec_in_width_c = vp_height_c;
+	} else {
+		scaler_rec_in_width_l = vp_width_l;
+		scaler_rec_in_width_c = vp_width_c;
+	}
+
+	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_pre_l,
+			hscale_pixel_rate_l,
+			scaler_rec_in_width_l,
+			req_per_swath_ub_l);  // per req
+
+	refcyc_per_req_delivery_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_l,
+			hscale_pixel_rate_l,
+			scaler_rec_in_width_l,
+			req_per_swath_ub_l);  // per req
+
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n", __func__, refcyc_per_req_delivery_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_l     = %3.2f\n", __func__, vba__refcyc_per_req_delivery_l);
+
+	//old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_l", refcyc_per_req_delivery_pre_l, vba__refcyc_per_req_delivery_pre_l);
+	//old_impl_vs_vba_impl("refcyc_per_req_delivery_l", refcyc_per_req_delivery_l, vba__refcyc_per_req_delivery_l);
+
+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
+
+	if (dual_plane) {
+		float vba__refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+		float vba__refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+
+		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_pre_c,
+				hscale_pixel_rate_c,
+				scaler_rec_in_width_c,
+				req_per_swath_ub_c);  // per req
+		refcyc_per_req_delivery_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_c,
+				hscale_pixel_rate_c,
+				scaler_rec_in_width_c,
+				req_per_swath_ub_c);  // per req
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, refcyc_per_req_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n", __func__, refcyc_per_req_delivery_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_c     = %3.2f\n", __func__, vba__refcyc_per_req_delivery_c);
+
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_c", refcyc_per_req_delivery_pre_c, vba__refcyc_per_req_delivery_pre_c);
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_c", refcyc_per_req_delivery_c, vba__refcyc_per_req_delivery_c);
+
+		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
+	}
+
+	// TTU - Cursor
+	refcyc_per_req_delivery_pre_cur0 = 0.0;
+	refcyc_per_req_delivery_cur0 = 0.0;
+
+	ASSERT(src->num_cursors <= 1);
+
+	if (src->num_cursors > 0) {
+		float vba__refcyc_per_req_delivery_pre_cur0;
+		float vba__refcyc_per_req_delivery_cur0;
+
+		calculate_ttu_cursor(
+				mode_lib,
+				&refcyc_per_req_delivery_pre_cur0,
+				&refcyc_per_req_delivery_cur0,
+				refclk_freq_in_mhz,
+				ref_freq_to_pix_freq,
+				hscale_pixel_rate_l,
+				scl->hscl_ratio,
+				vratio_pre_l,
+				vratio_l,
+				src->cur0_src_width,
+				(enum cursor_bpp) (src->cur0_bpp));
+
+		vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+		vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0     = %3.2f\n", __func__, refcyc_per_req_delivery_cur0);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_cur0);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_cur0     = %3.2f\n", __func__, vba__refcyc_per_req_delivery_cur0);
+
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_cur0", refcyc_per_req_delivery_pre_cur0, vba__refcyc_per_req_delivery_pre_cur0);
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_cur0", refcyc_per_req_delivery_cur0, vba__refcyc_per_req_delivery_cur0);
+	}
+
+	refcyc_per_req_delivery_pre_cur1 = 0.0;
+	refcyc_per_req_delivery_cur1 = 0.0;
+
+	// TTU - Misc
+	// all hard-coded
+
+	// Assignment to register structures
+	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler;	// in terms of line
+	ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8);
+	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq;	// in terms of refclk
+	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
+	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
+
+	disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
+	disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
+
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank  = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip    = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip   = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
+
+	// hack for FPGA
+	if (mode_lib->project == DML_PROJECT_DCN31_FPGA) {
+		if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) {
+			disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1;
+			dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n");
+		}
+	}
+
+	disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
+	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
+
+	if (dual_plane) {
+		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
+		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
+	}
+
+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
+	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
+
+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
+
+	disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
+	disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
+
+	if (dual_plane) {
+		disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
+		disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
+	}
+
+	disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;            // From VBA
+	disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;            // From VBA
+	disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
+	disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);   // From VBA
+
+	// Clamp to max for now
+	if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
+
+	if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
+
+	if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
+
+	if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
+
+	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
+	if (dual_plane) {
+		disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));
+		if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
+			dml_print(
+					"DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
+					__func__,
+					disp_dlg_regs->dst_y_per_pte_row_nom_c,
+					(unsigned int) dml_pow(2, 17) - 1);
+		}
+	}
+
+	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
+
+	disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
+
+	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
+			/ (double) dpte_groups_per_row_ub_l);
+	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
+	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
+			/ (double) meta_chunks_per_row_ub_l);
+	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
+
+	if (dual_plane) {
+		disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
+				/ (double) dpte_groups_per_row_ub_c);
+		if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
+			disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
+
+		// TODO: Is this the right calculation? Does htotal need to be halved?
+		disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
+				/ (double) meta_chunks_per_row_ub_c);
+		if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
+			disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
+	}
+
+	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1);
+	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1);
+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
+
+	disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1);
+	disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1);
+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
+
+	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
+	disp_dlg_regs->dst_y_offset_cur0 = 0;
+	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
+	disp_dlg_regs->dst_y_offset_cur1 = 0;
+
+	disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
+
+	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));
+
+	disp_ttu_regs->qos_level_low_wm = 0;
+	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
+
+	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
+	ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
+
+	disp_ttu_regs->qos_level_flip = 14;
+	disp_ttu_regs->qos_level_fixed_l = 8;
+	disp_ttu_regs->qos_level_fixed_c = 8;
+	disp_ttu_regs->qos_level_fixed_cur0 = 8;
+	disp_ttu_regs->qos_ramp_disable_l = 0;
+	disp_ttu_regs->qos_ramp_disable_c = 0;
+	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
+
+	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
+	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
+
+	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
+	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
+}
+
+void dml31_rq_dlg_get_dlg_reg(
+		struct display_mode_lib *mode_lib,
+		display_dlg_regs_st *dlg_regs,
+		display_ttu_regs_st *ttu_regs,
+		display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx,
+		const bool cstate_en,
+		const bool pstate_en,
+		const bool vm_en,
+		const bool ignore_viewport_pos,
+		const bool immediate_flip_support)
+{
+	display_rq_params_st rq_param = {0};
+	display_dlg_sys_params_st dlg_sys_param = {0};
+
+	// Get watermark and Tex.
+	dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes);
+
+	print__dlg_sys_params_st(mode_lib, dlg_sys_param);
+
+	// system parameter calculation done
+
+	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
+	dml_rq_dlg_get_dlg_params(
+			mode_lib,
+			e2e_pipe_param,
+			num_pipes,
+			pipe_idx,
+			dlg_regs,
+			ttu_regs,
+			rq_param.dlg,
+			dlg_sys_param,
+			cstate_en,
+			pstate_en,
+			vm_en,
+			ignore_viewport_pos,
+			immediate_flip_support);
+	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
new file mode 100644
index 000000000000..adf8518f761f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML31_DISPLAY_RQ_DLG_CALC_H__
+#define __DML31_DISPLAY_RQ_DLG_CALC_H__
+
+#include "../display_rq_dlg_helpers.h"
+
+struct display_mode_lib;
+
+// Function: dml_rq_dlg_get_rq_reg
+//  Main entry point for test to get the register values out of this DML class.
+//  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
+//  and then populate the rq_regs struct
+// Input:
+//  pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
+// Output:
+//  rq_regs - struct that holds all the RQ registers field value.
+//            See also: <display_rq_regs_st>
+void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
+		display_rq_regs_st *rq_regs,
+		const display_pipe_params_st pipe_param);
+
+// Function: dml_rq_dlg_get_dlg_reg
+//   Calculate and return DLG and TTU register struct given the system setting
+// Output:
+//  dlg_regs - output DLG register struct
+//  ttu_regs - output DLG TTU register struct
+// Input:
+//  e2e_pipe_param - "compacted" array of e2e pipe param struct
+//  num_pipes - num of active "pipe" or "route"
+//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
+//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
+//           Added for legacy or unrealistic timing tests.
+void dml31_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
+		display_dlg_regs_st          *dlg_regs,
+		display_ttu_regs_st          *ttu_regs,
+		display_e2e_pipe_params_st   *e2e_pipe_param,
+		const unsigned int            num_pipes,
+		const unsigned int            pipe_idx,
+		const bool                    cstate_en,
+		const bool                    pstate_en,
+		const bool                    vm_en,
+		const bool                    ignore_viewport_pos,
+		const bool                    immediate_flip_support);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 1f7b6ddf3020..8a5bd919aec8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -33,6 +33,8 @@
 #include "dcn21/display_rq_dlg_calc_21.h"
 #include "dcn30/display_mode_vba_30.h"
 #include "dcn30/display_rq_dlg_calc_30.h"
+#include "dcn31/display_mode_vba_31.h"
+#include "dcn31/display_rq_dlg_calc_31.h"
 #include "dml_logger.h"
 
 const struct dml_funcs dml20_funcs = {
@@ -63,6 +65,13 @@ const struct dml_funcs dml30_funcs = {
 	.rq_dlg_get_rq_reg = dml30_rq_dlg_get_rq_reg
 };
 
+const struct dml_funcs dml31_funcs = {
+	.validate = dml31_ModeSupportAndSystemConfigurationFull,
+	.recalculate = dml31_recalculate,
+	.rq_dlg_get_dlg_reg = dml31_rq_dlg_get_dlg_reg,
+	.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
+};
+
 void dml_init_instance(struct display_mode_lib *lib,
 		const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
 		const struct _vcs_dpi_ip_params_st *ip_params,
@@ -84,6 +93,10 @@ void dml_init_instance(struct display_mode_lib *lib,
 	case DML_PROJECT_DCN30:
 		lib->funcs = dml30_funcs;
 		break;
+	case DML_PROJECT_DCN31:
+	case DML_PROJECT_DCN31_FPGA:
+		lib->funcs = dml31_funcs;
+		break;
 
 	default:
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 6ae5df58a4fc..d42a0aeca6be 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -38,6 +38,8 @@ enum dml_project {
 	DML_PROJECT_NAVI10v2,
 	DML_PROJECT_DCN21,
 	DML_PROJECT_DCN30,
+	DML_PROJECT_DCN31,
+	DML_PROJECT_DCN31_FPGA,
 };
 
 struct display_mode_lib;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 2ece3690bfa3..64daa0507393 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -74,6 +74,8 @@ struct _vcs_dpi_soc_bounding_box_st {
 	unsigned int num_states;
 	double sr_exit_time_us;
 	double sr_enter_plus_exit_time_us;
+	double sr_exit_z8_time_us;
+	double sr_enter_plus_exit_z8_time_us;
 	double urgent_latency_us;
 	double urgent_latency_pixel_data_only_us;
 	double urgent_latency_pixel_mixed_with_vm_data_us;
@@ -209,6 +211,12 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int is_line_buffer_bpp_fixed;
 	unsigned int line_buffer_fixed_bpp;
 	unsigned int dcc_supported;
+	unsigned int config_return_buffer_size_in_kbytes;
+	unsigned int compressed_buffer_segment_size_in_kbytes;
+	unsigned int meta_fifo_size_in_kentries;
+	unsigned int zero_size_buffer_entries;
+	unsigned int compbuf_reserved_space_64b;
+	unsigned int compbuf_reserved_space_zs;
 
 	unsigned int IsLineBufferBppFixed;
 	unsigned int LineBufferFixedBpp;
@@ -253,6 +261,8 @@ struct _vcs_dpi_display_pipe_source_params_st {
 	unsigned int viewport_y_c;
 	unsigned int viewport_width_c;
 	unsigned int viewport_height_c;
+	unsigned int viewport_width_max;
+	unsigned int viewport_height_max;
 	unsigned int data_pitch;
 	unsigned int data_pitch_c;
 	unsigned int meta_pitch;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 2a967458065b..d3b1b6d4ce2f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -89,6 +89,10 @@ dml_get_attr_func(wm_memory_trip, mode_lib->vba.UrgentLatency);
 dml_get_attr_func(wm_writeback_urgent, mode_lib->vba.WritebackUrgentWatermark);
 dml_get_attr_func(wm_stutter_exit, mode_lib->vba.StutterExitWatermark);
 dml_get_attr_func(wm_stutter_enter_exit, mode_lib->vba.StutterEnterPlusExitWatermark);
+dml_get_attr_func(wm_z8_stutter_exit, mode_lib->vba.Z8StutterExitWatermark);
+dml_get_attr_func(wm_z8_stutter_enter_exit, mode_lib->vba.Z8StutterEnterPlusExitWatermark);
+dml_get_attr_func(stutter_efficiency_z8, mode_lib->vba.Z8StutterEfficiency);
+dml_get_attr_func(stutter_num_bursts_z8, mode_lib->vba.Z8NumberOfStutterBurstsPerFrame);
 dml_get_attr_func(wm_dram_clock_change, mode_lib->vba.DRAMClockChangeWatermark);
 dml_get_attr_func(wm_writeback_dram_clock_change, mode_lib->vba.WritebackDRAMClockChangeWatermark);
 dml_get_attr_func(stutter_efficiency, mode_lib->vba.StutterEfficiency);
@@ -153,11 +157,12 @@ dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_l_in_us, mode_lib->vba.TimeP
 dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_c_in_us, mode_lib->vba.TimePerChromaMetaChunkVBlank);
 dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_l_in_us, mode_lib->vba.TimePerMetaChunkFlip);
 dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_c_in_us, mode_lib->vba.TimePerChromaMetaChunkFlip);
-
 dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup);
 dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix);
 dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);
 dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);
+dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC);
+dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START);
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -226,6 +231,14 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.WritebackLatency = soc->writeback_latency_us;
 	mode_lib->vba.SRExitTime = soc->sr_exit_time_us;
 	mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
+	mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = soc->pct_ideal_sdp_bw_after_urgent;
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only;
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_vm_only;
+	mode_lib->vba.MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation =
+			soc->max_avg_sdp_bw_use_normal_percent;
+	mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us;
+	mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us;
 	mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
 	mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
 	mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
@@ -299,7 +312,15 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.MaxDCHUBToPSCLThroughput = ip->max_dchub_pscl_bw_pix_per_clk;
 	mode_lib->vba.MaxPSCLToLBThroughput = ip->max_pscl_lb_bw_pix_per_clk;
 	mode_lib->vba.ROBBufferSizeInKByte = ip->rob_buffer_size_kbytes;
-	mode_lib->vba.DETBufferSizeInKByte = ip->det_buffer_size_kbytes;
+	mode_lib->vba.DETBufferSizeInKByte[0] = ip->det_buffer_size_kbytes;
+	mode_lib->vba.ConfigReturnBufferSizeInKByte = ip->config_return_buffer_size_in_kbytes;
+	mode_lib->vba.CompressedBufferSegmentSizeInkByte = ip->compressed_buffer_segment_size_in_kbytes;
+	mode_lib->vba.MetaFIFOSizeInKEntries = ip->meta_fifo_size_in_kentries;
+	mode_lib->vba.ZeroSizeBufferEntries = ip->zero_size_buffer_entries;
+	mode_lib->vba.COMPBUF_RESERVED_SPACE_64B = ip->compbuf_reserved_space_64b;
+	mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs;
+	mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component;
+	mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support;
 
 	mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
 	mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
@@ -389,7 +410,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		visited[j] = true;
 
 		mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;
-
 		mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;
 		mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
 				(enum scan_direction_class) (src->source_scan);
@@ -429,6 +449,9 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c;
 		mode_lib->vba.HTotal[mode_lib->vba.NumberOfActivePlanes] = dst->htotal;
 		mode_lib->vba.VTotal[mode_lib->vba.NumberOfActivePlanes] = dst->vtotal;
+		mode_lib->vba.VFrontPorch[mode_lib->vba.NumberOfActivePlanes] = dst->vfront_porch;
+		mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_luma;
+		mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_chroma;
 		mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] =
 				src->dcc_use_global ?
 						ip->dcc_supported : src->dcc && ip->dcc_supported;
@@ -630,6 +653,19 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 				}
 			}
 		}
+		if (src->viewport_width_max) {
+			int hdiv_c = src->source_format >= dm_420_8 && src->source_format <= dm_422_10 ? 2 : 1;
+			int vdiv_c = src->source_format >= dm_420_8 && src->source_format <= dm_420_12 ? 2 : 1;
+
+			if (mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] > src->viewport_width_max)
+				mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_max;
+			if (mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] > src->viewport_height_max)
+				mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_max;
+			if (mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] > src->viewport_width_max / hdiv_c)
+				mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_max / hdiv_c;
+			if (mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] > src->viewport_height_max / vdiv_c)
+				mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_max / vdiv_c;
+		}
 
 		if (pipes[k].pipe.src.immediate_flip) {
 			mode_lib->vba.ImmediateFlipSupport = true;
@@ -662,6 +698,11 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		}
 	}
 
+	mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
+	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
+		if (pipes[k].pipe.src.unbounded_req_mode == 0)
+			mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting_disable;
+	}
 	// TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not since all pipes are specified
 	// Do we want the dscclk to automatically be halved? Guess not since the value is specified
 	mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 025aa5bd8ea0..d18a021d4d32 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -39,6 +39,10 @@ dml_get_attr_decl(wm_memory_trip);
 dml_get_attr_decl(wm_writeback_urgent);
 dml_get_attr_decl(wm_stutter_exit);
 dml_get_attr_decl(wm_stutter_enter_exit);
+dml_get_attr_decl(wm_z8_stutter_exit);
+dml_get_attr_decl(wm_z8_stutter_enter_exit);
+dml_get_attr_decl(stutter_efficiency_z8);
+dml_get_attr_decl(stutter_num_bursts_z8);
 dml_get_attr_decl(wm_dram_clock_change);
 dml_get_attr_decl(wm_writeback_dram_clock_change);
 dml_get_attr_decl(stutter_efficiency_no_vblank);
@@ -102,6 +106,8 @@ dml_get_pipe_attr_decl(vstartup);
 dml_get_pipe_attr_decl(vupdate_offset);
 dml_get_pipe_attr_decl(vupdate_width);
 dml_get_pipe_attr_decl(vready_offset);
+dml_get_pipe_attr_decl(vready_at_or_after_vsync);
+dml_get_pipe_attr_decl(min_dst_y_next_start);
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -233,7 +239,7 @@ struct vba_vars_st {
 	// IP Parameters
 	//
 	unsigned int ROBBufferSizeInKByte;
-	double DETBufferSizeInKByte;
+	unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
 	double DETBufferSizeInTime;
 	unsigned int DPPOutputBufferPixels;
 	unsigned int OPPOutputBufferLines;
@@ -351,8 +357,8 @@ struct vba_vars_st {
 
 	// Intermediates/Informational
 	bool ImmediateFlipSupport;
-	double DETBufferSizeY[DC__NUM_DPP__MAX];
-	double DETBufferSizeC[DC__NUM_DPP__MAX];
+	unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
+	unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
 	unsigned int SwathHeightY[DC__NUM_DPP__MAX];
 	unsigned int SwathHeightC[DC__NUM_DPP__MAX];
 	unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
@@ -631,8 +637,8 @@ struct vba_vars_st {
 	enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
 	double         dummy1[DC__NUM_DPP__MAX];
 	double         dummy2[DC__NUM_DPP__MAX];
-	double         dummy3[DC__NUM_DPP__MAX];
-	double         dummy4[DC__NUM_DPP__MAX];
+	unsigned int   dummy3[DC__NUM_DPP__MAX];
+	unsigned int   dummy4[DC__NUM_DPP__MAX];
 	double         dummy5;
 	double         dummy6;
 	double         dummy7[DC__NUM_DPP__MAX];
@@ -872,8 +878,8 @@ struct vba_vars_st {
 	int PercentMarginOverMinimumRequiredDCFCLK;
 	bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
 	enum immediate_flip_requirement ImmediateFlipRequirement;
-	double DETBufferSizeYThisState[DC__NUM_DPP__MAX];
-	double DETBufferSizeCThisState[DC__NUM_DPP__MAX];
+	unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
+	unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
 	bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
 	bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
 	int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
@@ -923,6 +929,46 @@ struct vba_vars_st {
 	bool ClampMinDCFCLK;
 	bool AllowDramClockChangeOneDisplayVactive;
 
+	double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
+	double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
+	double SRExitZ8Time;
+	double SREnterPlusExitZ8Time;
+	double Z8StutterExitWatermark;
+	double Z8StutterEnterPlusExitWatermark;
+	double Z8StutterEfficiencyNotIncludingVBlank;
+	double Z8StutterEfficiency;
+	double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
+	double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
+	double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
+	double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
+	double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
+	double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
+	double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
+	double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
+	bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
+	bool LinkCapacitySupport[DC__NUM_DPP__MAX];
+	bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
+	unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
+	unsigned int VFrontPorch[DC__NUM_DPP__MAX];
+	int ConfigReturnBufferSizeInKByte;
+	enum unbounded_requesting_policy UseUnboundedRequesting;
+	int CompressedBufferSegmentSizeInkByte;
+	int CompressedBufferSizeInkByte;
+	int MetaFIFOSizeInKEntries;
+	int ZeroSizeBufferEntries;
+	int COMPBUF_RESERVED_SPACE_64B;
+	int COMPBUF_RESERVED_SPACE_ZS;
+	bool UnboundedRequestEnabled;
+	bool DSC422NativeSupport;
+	bool NoEnoughUrgentLatencyHiding;
+	bool NoEnoughUrgentLatencyHidingPre;
+	int NumberOfStutterBurstsPerFrame;
+	int Z8NumberOfStutterBurstsPerFrame;
+	unsigned int MaximumDSCBitsPerComponent;
+	unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
 };
 
 bool CalculateMinAndMaxPrefetchMode(
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index be57088d185d..f403d8e84a8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -37,6 +37,8 @@ static uint32_t dsc_policy_max_target_bpp_limit = 16;
 /* default DSC policy enables DSC only when needed */
 static bool dsc_policy_enable_dsc_when_not_needed;
 
+static bool dsc_policy_disable_dsc_stream_overhead;
+
 static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)
 {
 
@@ -250,6 +252,7 @@ static bool intersect_dsc_caps(
 	if (pixel_encoding == PIXEL_ENCODING_YCBCR422 || pixel_encoding == PIXEL_ENCODING_YCBCR420)
 		dsc_common_caps->bpp_increment_div = min(dsc_common_caps->bpp_increment_div, (uint32_t)8);
 
+	dsc_common_caps->is_dp = dsc_sink_caps->is_dp;
 	return true;
 }
 
@@ -258,12 +261,63 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value)
 	return (value + 9) / 10;
 }
 
+static struct fixed31_32 compute_dsc_max_bandwidth_overhead(
+		const struct dc_crtc_timing *timing,
+		const int num_slices_h,
+		const bool is_dp)
+{
+	struct fixed31_32 max_dsc_overhead;
+	struct fixed31_32 refresh_rate;
+
+	if (dsc_policy_disable_dsc_stream_overhead || !is_dp)
+		return dc_fixpt_from_int(0);
+
+	/* use target bpp that can take entire target bandwidth */
+	refresh_rate = dc_fixpt_from_int(timing->pix_clk_100hz);
+	refresh_rate = dc_fixpt_div_int(refresh_rate, timing->h_total);
+	refresh_rate = dc_fixpt_div_int(refresh_rate, timing->v_total);
+	refresh_rate = dc_fixpt_mul_int(refresh_rate, 100);
+
+	max_dsc_overhead = dc_fixpt_from_int(num_slices_h);
+	max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, timing->v_total);
+	max_dsc_overhead = dc_fixpt_mul_int(max_dsc_overhead, 256);
+	max_dsc_overhead = dc_fixpt_div_int(max_dsc_overhead, 1000);
+	max_dsc_overhead = dc_fixpt_mul(max_dsc_overhead, refresh_rate);
+
+	return max_dsc_overhead;
+}
+
+static uint32_t compute_bpp_x16_from_target_bandwidth(
+		const uint32_t bandwidth_in_kbps,
+		const struct dc_crtc_timing *timing,
+		const uint32_t num_slices_h,
+		const uint32_t bpp_increment_div,
+		const bool is_dp)
+{
+	struct fixed31_32 overhead_in_kbps;
+	struct fixed31_32 effective_bandwidth_in_kbps;
+	struct fixed31_32 bpp_x16;
+
+	overhead_in_kbps = compute_dsc_max_bandwidth_overhead(
+				timing, num_slices_h, is_dp);
+	effective_bandwidth_in_kbps = dc_fixpt_from_int(bandwidth_in_kbps);
+	effective_bandwidth_in_kbps = dc_fixpt_sub(effective_bandwidth_in_kbps,
+			overhead_in_kbps);
+	bpp_x16 = dc_fixpt_mul_int(effective_bandwidth_in_kbps, 10);
+	bpp_x16 = dc_fixpt_div_int(bpp_x16, timing->pix_clk_100hz);
+	bpp_x16 = dc_fixpt_from_int(dc_fixpt_floor(dc_fixpt_mul_int(bpp_x16, bpp_increment_div)));
+	bpp_x16 = dc_fixpt_div_int(bpp_x16, bpp_increment_div);
+	bpp_x16 = dc_fixpt_mul_int(bpp_x16, 16);
+	return dc_fixpt_floor(bpp_x16);
+}
+
 /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock
  * and uncompressed bandwidth.
  */
 static void get_dsc_bandwidth_range(
 		const uint32_t min_bpp_x16,
 		const uint32_t max_bpp_x16,
+		const uint32_t num_slices_h,
 		const struct dsc_enc_caps *dsc_caps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_bw_range *range)
@@ -272,16 +326,21 @@ static void get_dsc_bandwidth_range(
 	range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing);
 
 	/* max dsc target bpp */
-	range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, max_bpp_x16);
+	range->max_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,
+			max_bpp_x16, num_slices_h, dsc_caps->is_dp);
 	range->max_target_bpp_x16 = max_bpp_x16;
 	if (range->max_kbps > range->stream_kbps) {
 		/* max dsc target bpp is capped to native bandwidth */
 		range->max_kbps = range->stream_kbps;
-		range->max_target_bpp_x16 = calc_dsc_bpp_x16(range->stream_kbps, timing->pix_clk_100hz, dsc_caps->bpp_increment_div);
+		range->max_target_bpp_x16 = compute_bpp_x16_from_target_bandwidth(
+				range->max_kbps, timing, num_slices_h,
+				dsc_caps->bpp_increment_div,
+				dsc_caps->is_dp);
 	}
 
 	/* min dsc target bpp */
-	range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, min_bpp_x16);
+	range->min_kbps = dc_dsc_stream_bandwidth_in_kbps(timing,
+			min_bpp_x16, num_slices_h, dsc_caps->is_dp);
 	range->min_target_bpp_x16 = min_bpp_x16;
 	if (range->min_kbps > range->max_kbps) {
 		/* min dsc target bpp is capped to max dsc bandwidth*/
@@ -290,7 +349,6 @@ static void get_dsc_bandwidth_range(
 	}
 }
 
-
 /* Decides if DSC should be used and calculates target bpp if it should, applying DSC policy.
  *
  * Returns:
@@ -303,6 +361,7 @@ static bool decide_dsc_target_bpp_x16(
 		const struct dsc_enc_caps *dsc_common_caps,
 		const int target_bandwidth_kbps,
 		const struct dc_crtc_timing *timing,
+		const int num_slices_h,
 		int *target_bpp_x16)
 {
 	bool should_use_dsc = false;
@@ -311,7 +370,7 @@ static bool decide_dsc_target_bpp_x16(
 	memset(&range, 0, sizeof(range));
 
 	get_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16,
-			dsc_common_caps, timing, &range);
+			num_slices_h, dsc_common_caps, timing, &range);
 	if (!policy->enable_dsc_when_not_needed && target_bandwidth_kbps >= range.stream_kbps) {
 		/* enough bandwidth without dsc */
 		*target_bpp_x16 = 0;
@@ -327,7 +386,10 @@ static bool decide_dsc_target_bpp_x16(
 		should_use_dsc = true;
 	} else if (target_bandwidth_kbps >= range.min_kbps) {
 		/* use target bpp that can take entire target bandwidth */
-		*target_bpp_x16 = calc_dsc_bpp_x16(target_bandwidth_kbps, timing->pix_clk_100hz, dsc_common_caps->bpp_increment_div);
+		*target_bpp_x16 = compute_bpp_x16_from_target_bandwidth(
+				target_bandwidth_kbps, timing, num_slices_h,
+				dsc_common_caps->bpp_increment_div,
+				dsc_common_caps->is_dp);
 		should_use_dsc = true;
 	} else {
 		/* not enough bandwidth to fulfill minimum requirement */
@@ -531,18 +593,6 @@ static bool setup_dsc_config(
 	if (!is_dsc_possible)
 		goto done;
 
-	if (target_bandwidth_kbps > 0) {
-		is_dsc_possible = decide_dsc_target_bpp_x16(
-				&policy,
-				&dsc_common_caps,
-				target_bandwidth_kbps,
-				timing,
-				&target_bpp);
-		dsc_cfg->bits_per_pixel = target_bpp;
-	}
-	if (!is_dsc_possible)
-		goto done;
-
 	sink_per_slice_throughput_mps = 0;
 
 	// Validate available DSC settings against the mode timing
@@ -690,12 +740,26 @@ static bool setup_dsc_config(
 
 	dsc_cfg->num_slices_v = pic_height/slice_height;
 
+	if (target_bandwidth_kbps > 0) {
+		is_dsc_possible = decide_dsc_target_bpp_x16(
+				&policy,
+				&dsc_common_caps,
+				target_bandwidth_kbps,
+				timing,
+				num_slices_h,
+				&target_bpp);
+		dsc_cfg->bits_per_pixel = target_bpp;
+	}
+	if (!is_dsc_possible)
+		goto done;
+
 	// Final decission: can we do DSC or not?
 	if (is_dsc_possible) {
 		// Fill out the rest of DSC settings
 		dsc_cfg->block_pred_enable = dsc_common_caps.is_block_pred_supported;
 		dsc_cfg->linebuf_depth = dsc_common_caps.lb_bit_depth;
 		dsc_cfg->version_minor = (dsc_common_caps.dsc_version & 0xf0) >> 4;
+		dsc_cfg->is_dp = dsc_sink_caps->is_dp;
 	}
 
 done:
@@ -806,6 +870,7 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da
 	dsc_sink_caps->branch_max_line_width = dpcd_dsc_branch_decoder_caps[DP_DSC_BRANCH_MAX_LINE_WIDTH - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0] * 320;
 	ASSERT(dsc_sink_caps->branch_max_line_width == 0 || dsc_sink_caps->branch_max_line_width >= 5120);
 
+	dsc_sink_caps->is_dp = true;
 	return true;
 }
 
@@ -838,7 +903,8 @@ bool dc_dsc_compute_bandwidth_range(
 				dsc_min_slice_height_override, max_bpp_x16, &config);
 
 	if (is_dsc_possible)
-		get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, &dsc_common_caps, timing, range);
+		get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16,
+				config.num_slices_h, &dsc_common_caps, timing, range);
 
 	return is_dsc_possible;
 }
@@ -864,13 +930,20 @@ bool dc_dsc_compute_config(
 	return is_dsc_possible;
 }
 
-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16)
+uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
+		uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp)
 {
-	struct fixed31_32 link_bw_kbps;
-	link_bw_kbps = dc_fixpt_from_int(pix_clk_100hz);
-	link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
-	link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, bpp_x16);
-	return dc_fixpt_ceil(link_bw_kbps);
+	struct fixed31_32 overhead_in_kbps;
+	struct fixed31_32 bpp;
+	struct fixed31_32 actual_bandwidth_in_kbps;
+
+	overhead_in_kbps = compute_dsc_max_bandwidth_overhead(
+			timing, num_slices_h, is_dp);
+	bpp = dc_fixpt_from_fraction(bpp_x16, 16);
+	actual_bandwidth_in_kbps = dc_fixpt_from_fraction(timing->pix_clk_100hz, 10);
+	actual_bandwidth_in_kbps = dc_fixpt_mul(actual_bandwidth_in_kbps, bpp);
+	actual_bandwidth_in_kbps = dc_fixpt_add(actual_bandwidth_in_kbps, overhead_in_kbps);
+	return dc_fixpt_ceil(actual_bandwidth_in_kbps);
 }
 
 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy)
@@ -954,3 +1027,8 @@ void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable)
 {
 	dsc_policy_enable_dsc_when_not_needed = enable;
 }
+
+void dc_dsc_policy_set_disable_dsc_stream_overhead(bool disable)
+{
+	dsc_policy_disable_dsc_stream_overhead = disable;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index c6a1cd80aeae..7b294f637881 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -284,26 +284,6 @@ static u32 _do_bytes_per_pixel_calc(int slice_width, u16 drm_bpp,
 	return bytes_per_pixel;
 }
 
-static u32 _do_calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
-				u32 bpp_increment_div)
-{
-	u32 dsc_target_bpp_x16;
-	float f_dsc_target_bpp;
-	float f_stream_bandwidth_100bps;
-	// bpp_increment_div is actually precision
-	u32 precision = bpp_increment_div;
-
-	f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f;
-	f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz;
-
-	// Round down to the nearest precision stop to bring it into DSC spec
-	// range
-	dsc_target_bpp_x16 = (u32)(f_dsc_target_bpp * precision);
-	dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision;
-
-	return dsc_target_bpp_x16;
-}
-
 /**
  * calc_rc_params - reads the user's cmdline mode
  * @rc: DC internal DSC parameters
@@ -367,26 +347,3 @@ u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps)
 	DC_FP_END();
 	return ret;
 }
-
-/**
- * calc_dsc_bpp_x16 - retrieve the dsc bits per pixel
- * @stream_bandwidth_kbps:
- * @pix_clk_100hz:
- * @bpp_increment_div:
- *
- * Calculate the total of bits per pixel for DSC configuration.
- *
- * @note This calculation requires float point operation, most of it executes
- * under kernel_fpu_{begin,end}.
- */
-u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
-		     u32 bpp_increment_div)
-{
-	u32 dsc_bpp;
-
-	DC_FP_START();
-	dsc_bpp =  _do_calc_dsc_bpp_x16(stream_bandwidth_kbps, pix_clk_100hz,
-					bpp_increment_div);
-	DC_FP_END();
-	return dsc_bpp;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
index 8123827840c5..262f06afcbf9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
@@ -79,8 +79,6 @@ typedef struct qp_entry qp_table[];
 
 void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps);
 u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps);
-u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
-		     u32 bpp_increment_div);
 
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
index 92280cc05e2d..dae8e489c8cf 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
@@ -53,8 +53,8 @@
  */
 
 struct gpio_service *dal_gpio_service_create(
-	enum dce_version dce_version_major,
-	enum dce_version dce_version_minor,
+	enum dce_version dce_version,
+	enum dce_environment dce_environment,
 	struct dc_context *ctx)
 {
 	struct gpio_service *service;
@@ -67,14 +67,14 @@ struct gpio_service *dal_gpio_service_create(
 		return NULL;
 	}
 
-	if (!dal_hw_translate_init(&service->translate, dce_version_major,
-			dce_version_minor)) {
+	if (!dal_hw_translate_init(&service->translate, dce_version,
+			dce_environment)) {
 		BREAK_TO_DEBUGGER();
 		goto failure_1;
 	}
 
-	if (!dal_hw_factory_init(&service->factory, dce_version_major,
-			dce_version_minor)) {
+	if (!dal_hw_factory_init(&service->factory, dce_version,
+			dce_environment)) {
 		BREAK_TO_DEBUGGER();
 		goto failure_1;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 92c65d2fa7d7..c5c840a06050 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -111,6 +111,8 @@ bool dal_hw_factory_init(
 	case DCN_VERSION_3_0:
 	case DCN_VERSION_3_01:
 	case DCN_VERSION_3_02:
+	case DCN_VERSION_3_03:
+	case DCN_VERSION_3_1:
 		dal_hw_factory_dcn30_init(factory);
 		return true;
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index da9499c09a11..4a9848308766 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -106,6 +106,8 @@ bool dal_hw_translate_init(
 	case DCN_VERSION_3_0:
 	case DCN_VERSION_3_01:
 	case DCN_VERSION_3_02:
+	case DCN_VERSION_3_03:
+	case DCN_VERSION_3_1:
 		dal_hw_translate_dcn30_init(translate);
 		return true;
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
index 51855a2624cf..4233955e3c47 100644
--- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
@@ -33,6 +33,7 @@
 #include "core_types.h"
 #include "dc_link_ddc.h"
 #include "link_hwss.h"
+#include "inc/link_dpcd.h"
 
 #define DC_LOGGER \
 	link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 81b92f20d5b6..45a6216dfa2a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -338,6 +338,7 @@ union pipe_update_flags {
 		uint32_t scaler : 1;
 		uint32_t viewport : 1;
 		uint32_t plane_changed : 1;
+		uint32_t det_size : 1;
 	} bits;
 	uint32_t raw;
 };
@@ -365,6 +366,8 @@ struct pipe_ctx {
 	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
 	struct _vcs_dpi_display_rq_regs_st rq_regs;
 	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
+	int det_buffer_size_kb;
+	bool unbounded_req;
 #endif
 	union pipe_update_flags update_flags;
 	struct dwbc *dwbc;
@@ -415,6 +418,7 @@ struct dcn_bw_output {
 	struct dc_clocks clk;
 	struct dcn_watermark_set watermarks;
 	struct dcn_bw_writeback bw_writeback;
+	int compbuf_size_kb;
 };
 
 union bw_output {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index 3ae05c96d557..e2b58ec9912d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -30,11 +30,29 @@
 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
 #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
+#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
+#define TRAINING_AUX_RD_INTERVAL 100 //us
 
 struct dc_link;
 struct dc_stream_state;
 struct dc_link_settings;
 
+enum {
+	LINK_TRAINING_MAX_RETRY_COUNT = 5,
+	/* to avoid infinite loop where-in the receiver
+	 * switches between different VS
+	 */
+	LINK_TRAINING_MAX_CR_RETRY = 100,
+	/*
+	 * Some receivers fail to train on first try and are good
+	 * on subsequent tries. 2 retries should be plenty. If we
+	 * don't have a successful training then we don't expect to
+	 * ever get one.
+	 */
+	LINK_TRAINING_MAX_VERIFY_RETRY = 2,
+	PEAK_FACTOR_X1000 = 1006,
+};
+
 bool dp_verify_link_cap(
 	struct dc_link *link,
 	struct dc_link_settings *known_limit_link_setting,
@@ -65,7 +83,12 @@ bool perform_link_training_with_retries(
 	bool skip_video_pattern,
 	int attempts,
 	struct pipe_ctx *pipe_ctx,
-	enum signal_type signal);
+	enum signal_type signal,
+	bool do_fallback);
+
+bool hpd_rx_irq_check_link_loss_status(
+	struct dc_link *link,
+	union hpd_irq_data *hpd_irq_dpcd_data);
 
 bool is_mst_supported(struct dc_link *link);
 
@@ -75,6 +98,8 @@ void detect_edp_sink_caps(struct dc_link *link);
 
 bool is_dp_active_dongle(const struct dc_link *link);
 
+bool is_dp_branch_device(const struct dc_link *link);
+
 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing);
 
 void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
@@ -85,8 +110,59 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
 bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
 
 void dpcd_set_source_specific_data(struct dc_link *link);
+/* Write DPCD link configuration data. */
+enum dc_status dpcd_set_link_settings(
+	struct dc_link *link,
+	const struct link_training_settings *lt_settings);
+/* Write DPCD drive settings. */
+enum dc_status dpcd_set_lane_settings(
+	struct dc_link *link,
+	const struct link_training_settings *link_training_setting,
+	uint32_t offset);
+/* Read training status and adjustment requests from DPCD. */
+enum dc_status dp_get_lane_status_and_drive_settings(
+	struct dc_link *link,
+	const struct link_training_settings *link_training_setting,
+	union lane_status *ln_status,
+	union lane_align_status_updated *ln_status_updated,
+	struct link_training_settings *req_settings,
+	uint32_t offset);
+
+void dp_wait_for_training_aux_rd_interval(
+	struct dc_link *link,
+	uint32_t wait_in_micro_secs);
+
+bool dp_is_cr_done(enum dc_lane_count ln_count,
+	union lane_status *dpcd_lane_status);
+
+enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
+	union lane_status *dpcd_lane_status);
+
+bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
+	union lane_status *dpcd_lane_status);
+bool dp_is_symbol_locked(enum dc_lane_count ln_count,
+	union lane_status *dpcd_lane_status);
+bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
 
-void dp_set_fec_ready(struct dc_link *link, bool ready);
+bool dp_is_max_vs_reached(
+	const struct link_training_settings *lt_settings);
+
+void dp_update_drive_settings(
+	struct link_training_settings *dest,
+	struct link_training_settings src);
+
+uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);
+
+enum dpcd_training_patterns
+	dc_dp_training_pattern_to_dpcd_training_pattern(
+	struct dc_link *link,
+	enum dc_dp_training_pattern pattern);
+
+uint8_t dc_dp_initialize_scrambling_data_symbols(
+	struct dc_link *link,
+	enum dc_dp_training_pattern pattern);
+
+enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready);
 void dp_set_fec_enable(struct dc_link *link, bool enable);
 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
@@ -94,5 +170,25 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
 bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
 
+/* Initialize output parameter lt_settings. */
+void dp_decide_training_settings(
+	struct dc_link *link,
+	const struct dc_link_settings *link_setting,
+	const struct dc_link_training_overrides *overrides,
+	struct link_training_settings *lt_settings);
+
+/* Convert PHY repeater count read from DPCD uint8_t. */
+uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);
+
+/* Check DPCD training status registers to detect link loss. */
+enum link_training_result dp_check_link_loss_status(
+		struct dc_link *link,
+		const struct link_training_settings *link_training_setting);
+
+enum dc_status dpcd_configure_lttpr_mode(
+		struct dc_link *link,
+		struct link_training_settings *lt_settings);
 
+enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
+bool dp_retrieve_lttpr_cap(struct dc_link *link);
 #endif /* __DC_LINK_DP_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
index e8ce8c85adf1..142753644377 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
@@ -52,7 +52,8 @@ struct abm_funcs {
 	unsigned int (*get_target_backlight)(struct abm *abm);
 	bool (*init_abm_config)(struct abm *abm,
 			const char *src,
-			unsigned int bytes);
+			unsigned int bytes,
+			unsigned int inst);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 5dc8d02b40c3..a17e5de3b100 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -91,6 +91,7 @@ struct clk_limit_table_entry {
 	unsigned int dispclk_mhz;
 	unsigned int dppclk_mhz;
 	unsigned int phyclk_mhz;
+	unsigned int wck_ratio;
 };
 
 /* This table is contiguous */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 336c80a18175..0afa2364a986 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -29,11 +29,40 @@
 #include "dc_types.h"
 #include "hw_shared.h"
 
+enum phyd32clk_clock_source {
+	PHYD32CLKA,
+	PHYD32CLKB,
+	PHYD32CLKC,
+	PHYD32CLKD,
+	PHYD32CLKE,
+	PHYD32CLKF,
+	PHYD32CLKG,
+};
+
+enum physymclk_clock_source {
+	PHYSYMCLK_FORCE_SRC_SYMCLK,    // Select symclk as source of clock which is output to PHY through DCIO.
+	PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
+	PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
+};
+
+enum hdmistreamclk_source {
+	REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
+	DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
+};
+
+enum dentist_dispclk_change_mode {
+	DISPCLK_CHANGE_MODE_IMMEDIATE,
+	DISPCLK_CHANGE_MODE_RAMPING,
+};
+
 struct dccg {
 	struct dc_context *ctx;
 	const struct dccg_funcs *funcs;
 	int pipe_dppclk_khz[MAX_PIPES];
 	int ref_dppclk;
+	int dtbclk_khz[MAX_PIPES];
+	int audio_dtbclk_khz;
+	int ref_dtbclk_khz;
 };
 
 struct dccg_funcs {
@@ -43,7 +72,34 @@ struct dccg_funcs {
 	void (*get_dccg_ref_freq)(struct dccg *dccg,
 			unsigned int xtalin_freq_inKhz,
 			unsigned int *dccg_ref_freq_inKhz);
+	void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
+			bool en);
+	void (*otg_add_pixel)(struct dccg *dccg,
+			uint32_t otg_inst);
+	void (*otg_drop_pixel)(struct dccg *dccg,
+			uint32_t otg_inst);
 	void (*dccg_init)(struct dccg *dccg);
+
+	void (*set_physymclk)(
+			struct dccg *dccg,
+			int phy_inst,
+			enum physymclk_clock_source clk_src,
+			bool force_enable);
+
+	void (*set_dtbclk_dto)(
+			struct dccg *dccg,
+			int dtbclk_inst,
+			int req_dtbclk_khz,
+			int num_odm_segments,
+			const struct dc_crtc_timing *timing);
+
+	void (*set_audio_dtbclk_dto)(
+			struct dccg *dccg,
+			uint32_t req_audio_dtbclk_khz);
+
+	void (*set_dispclk_change_mode)(
+			struct dccg *dccg,
+			enum dentist_dispclk_change_mode change_mode);
 };
 
 #endif //__DAL_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index d9fd28b34f2a..0638b337f143 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -152,6 +152,9 @@ struct hubbub_funcs {
 	void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
 
 	void (*init_watermarks)(struct hubbub *hubbub);
+	void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte);
+	void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
+	void (*init_crb)(struct hubbub *hubbub);
 };
 
 struct hubbub {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index ddbe4bb52724..00fc81431b43 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -32,6 +32,12 @@
 struct dpp {
 	const struct dpp_funcs *funcs;
 	struct dc_context *ctx;
+	/**
+	 * @inst:
+	 *
+	 * inst stands for "instance," and it is an id number that references a
+	 * specific DPP.
+	 */
 	int inst;
 	struct dpp_caps *caps;
 	struct pwl_params regamma_params;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
index f520e13aee4c..f94135c6e3c2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
@@ -88,6 +88,7 @@ struct dsc_enc_caps {
 	int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
 	int32_t max_slice_width;
 	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
+	bool is_dp;
 };
 
 struct dsc_funcs {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 80bc99500645..9eaf345aa2a1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -127,6 +127,12 @@ struct link_enc_state {
 
 };
 
+enum encoder_type_select {
+	ENCODER_TYPE_DIG = 0,
+	ENCODER_TYPE_HDMI_FRL = 1,
+	ENCODER_TYPE_DP_128B132B = 2
+};
+
 struct link_encoder_funcs {
 	void (*read_state)(
 			struct link_encoder *enc, struct link_enc_state *s);
@@ -185,6 +191,10 @@ struct link_encoder_funcs {
 
 	enum signal_type (*get_dig_mode)(
 		struct link_encoder *enc);
+	void (*set_dio_phy_mux)(
+		struct link_encoder *enc,
+		enum encoder_type_select sel,
+		uint32_t hpo_inst);
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 2e2310f1901a..8798cfa11a4d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -33,6 +33,8 @@
 struct dchub_init_data;
 struct cstate_pstate_watermarks_st {
 	uint32_t cstate_exit_ns;
+	uint32_t cstate_exit_z8_ns;
+	uint32_t cstate_enter_plus_exit_z8_ns;
 	uint32_t cstate_enter_plus_exit_ns;
 	uint32_t pstate_change_ns;
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 75c77ad9cbfe..640bb432bd6a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -363,6 +363,9 @@ struct mpc_funcs {
 			struct mpc *mpc,
 			int opp_id);
 
+	void (*set_bg_color)(struct mpc *mpc,
+			struct tg_color *bg_color,
+			int mpcc_id);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 47c7e4c3a51b..564ea6a727b0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -237,6 +237,9 @@ struct stream_encoder_funcs {
 	void (*dp_set_odm_combine)(
 		struct stream_encoder *enc,
 		bool odm_combine);
+
+	uint32_t (*get_fifo_cal_average_level)(
+		struct stream_encoder *enc);
 };
 
 #endif /* STREAM_ENCODER_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 9ff68b67780c..03f47f23fb65 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -173,6 +173,7 @@ struct timing_generator_funcs {
 
 	bool (*enable_crtc)(struct timing_generator *tg);
 	bool (*disable_crtc)(struct timing_generator *tg);
+	bool (*immediate_disable_crtc)(struct timing_generator *tg);
 	bool (*is_counter_moving)(struct timing_generator *tg);
 	void (*get_position)(struct timing_generator *tg,
 				struct crtc_position *position);
@@ -223,6 +224,8 @@ struct timing_generator_funcs {
 	void (*enable_advanced_request)(struct timing_generator *tg,
 					bool enable, const struct dc_crtc_timing *timing);
 	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
+	void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
+	void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
 	void (*set_static_screen_control)(struct timing_generator *tg,
 						uint32_t event_triggers,
 						uint32_t num_frames);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index 2947d1b15512..2a0db2b03047 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -162,9 +162,7 @@ struct scl_inits {
 	struct fixed31_32 h;
 	struct fixed31_32 h_c;
 	struct fixed31_32 v;
-	struct fixed31_32 v_bot;
 	struct fixed31_32 v_c;
-	struct fixed31_32 v_c_bot;
 };
 
 struct scaler_data {
@@ -173,8 +171,6 @@ struct scaler_data {
 	struct scaling_taps taps;
 	struct rect viewport;
 	struct rect viewport_c;
-	struct rect viewport_unadjusted;
-	struct rect viewport_c_unadjusted;
 	struct rect recout;
 	struct scaling_ratios ratios;
 	struct scl_inits inits;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 1d5853c95448..5ab008e62b82 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -235,6 +235,13 @@ struct hw_sequencer_funcs {
 			enum dc_color_depth color_depth,
 			const struct tg_color *solid_color,
 			int width, int height, int offset);
+
+	void (*z10_restore)(struct dc *dc);
+
+	void (*update_visual_confirm_color)(struct dc *dc,
+			struct pipe_ctx *pipe_ctx,
+			struct tg_color *color,
+			int mpcc_id);
 };
 
 void color_space_to_black_color(
@@ -249,4 +256,17 @@ const uint16_t *find_color_matrix(
 		enum dc_color_space color_space,
 		uint32_t *array_size);
 
+void get_surface_visual_confirm_color(
+		const struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
+
+void get_hdr_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
+void get_mpctree_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
+void get_surface_tile_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
 #endif /* __DC_HW_SEQUENCER_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index 36e906bb6bfc..f7f7e4fff0c2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -127,11 +127,6 @@ struct hwseq_private_funcs {
 			const struct dc_stream_state *stream,
 			struct dc_state *context);
 	bool (*s0i3_golden_init_wa)(struct dc *dc);
-	void (*get_surface_visual_confirm_color)(
-			const struct pipe_ctx *pipe_ctx,
-			struct tg_color *color);
-	void (*get_hdr_visual_confirm_color)(struct pipe_ctx *pipe_ctx,
-			struct tg_color *color);
 	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
 	void (*verify_allow_pstate_change_high)(struct dc *dc);
 	void (*program_pipe)(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h b/drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h
new file mode 100644
index 000000000000..d4d52ef1b165
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h
@@ -0,0 +1,18 @@
+#ifndef __LINK_DPCD_H__
+#define __LINK_DPCD_H__
+#include <inc/core_status.h>
+#include <dc_link.h>
+#include <inc/link_hwss.h>
+
+enum dc_status core_link_read_dpcd(
+		struct dc_link *link,
+		uint32_t address,
+		uint8_t *data,
+		uint32_t size);
+
+enum dc_status core_link_write_dpcd(
+		struct dc_link *link,
+		uint32_t address,
+		const uint8_t *data,
+		uint32_t size);
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
index 7d36e55f3097..883dd8733ea4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -81,6 +81,11 @@ struct dc_link *link_enc_cfg_get_link_using_link_enc(
 /* Return DIG link encoder used by link. NULL if unused. */
 struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(
 		struct dc_state *state,
-		struct dc_link *link);
+		const struct dc_link *link);
+
+/* Return next available DIG link encoder. NULL if none available. */
+struct link_encoder *link_enc_cfg_get_next_avail_link_enc(
+	const struct dc *dc,
+	const struct dc_state *state);
 
 #endif /* DC_INC_LINK_ENC_CFG_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 33590a728fc5..fc1d289bb9fe 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -26,20 +26,6 @@
 #ifndef __DC_LINK_HWSS_H__
 #define __DC_LINK_HWSS_H__
 
-#include "inc/core_status.h"
-
-enum dc_status core_link_read_dpcd(
-	struct dc_link *link,
-	uint32_t address,
-	uint8_t *data,
-	uint32_t size);
-
-enum dc_status core_link_write_dpcd(
-	struct dc_link *link,
-	uint32_t address,
-	const uint8_t *data,
-	uint32_t size);
-
 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 		struct graphics_object_id link_id,
 		struct gpio_service *gpio_service);
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index ca8168726324..0d09181227c5 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -109,4 +109,21 @@ IRQ_DCN3_02 = irq_service_dcn302.o
 AMD_DAL_IRQ_DCN3_02 = $(addprefix $(AMDDALPATH)/dc/irq/dcn302/,$(IRQ_DCN3_02))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_02)
+###############################################################################
+# DCN 3_03
+###############################################################################
+IRQ_DCN3_03 = irq_service_dcn303.o
+
+AMD_DAL_IRQ_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/irq/dcn303/,$(IRQ_DCN3_03))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_03)
+
+###############################################################################
+# DCN 31
+###############################################################################
+IRQ_DCN31 = irq_service_dcn31.o
+
+AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31)
 endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
index 1a5be2792055..ed54e1c819be 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
@@ -58,8 +58,8 @@ enum dc_irq_source to_dal_irq_source_dcn21(
 		return DC_IRQ_SOURCE_VBLANK5;
 	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
 		return DC_IRQ_SOURCE_VBLANK6;
-	case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
-		return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
+	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
+		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
 	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
 		return DC_IRQ_SOURCE_DC1_VLINE0;
 	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
@@ -187,7 +187,7 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
 	.ack = NULL
 };
 
-static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
+static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
 	.set = NULL,
 	.ack = NULL
 };
@@ -301,11 +301,11 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
 		.funcs = &vline0_irq_info_funcs\
 	}
 
-#define dmub_trace_int_entry()\
-	[DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
-		IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
-			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
-		.funcs = &dmub_trace_irq_info_funcs\
+#define dmub_outbox_int_entry()\
+	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
+		IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
+			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
+		.funcs = &dmub_outbox_irq_info_funcs\
 	}
 
 #define dummy_irq_entry() \
@@ -426,7 +426,7 @@ irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
 	vline0_int_entry(3),
 	vline0_int_entry(4),
 	vline0_int_entry(5),
-	dmub_trace_int_entry(),
+	dmub_outbox_int_entry(),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn21 = {
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
new file mode 100644
index 000000000000..66e60762388e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#include "dm_services.h"
+#include "irq_service_dcn303.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "sienna_cichlid_ip_offset.h"
+#include "dcn/dcn_3_0_3_offset.h"
+#include "dcn/dcn_3_0_3_sh_mask.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_service,
+						   uint32_t src_id,
+						   uint32_t ext_id)
+{
+	switch (src_id) {
+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK1;
+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK2;
+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP1;
+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP2;
+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE1;
+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE2;
+
+	case DCN_1_0__SRCID__DC_HPD1_INT:
+		/* generic src_id for all HPD and HPDRX interrupts */
+		switch (ext_id) {
+		case DCN_1_0__CTXID__DC_HPD1_INT:
+			return DC_IRQ_SOURCE_HPD1;
+		case DCN_1_0__CTXID__DC_HPD2_INT:
+			return DC_IRQ_SOURCE_HPD2;
+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
+			return DC_IRQ_SOURCE_HPD1RX;
+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
+			return DC_IRQ_SOURCE_HPD2RX;
+		default:
+			return DC_IRQ_SOURCE_INVALID;
+		}
+		break;
+
+	default:
+		return DC_IRQ_SOURCE_INVALID;
+	}
+}
+
+static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)
+{
+	uint32_t addr = info->status_reg;
+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
+	uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);
+
+	dal_irq_service_ack_generic(irq_service, info);
+
+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+	set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);
+
+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+	return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+		.set = NULL,
+		.ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+		.set = NULL,
+		.ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+		.set = NULL,
+		.ack = NULL
+};
+
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+		.set = NULL,
+		.ack = NULL
+};
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+		BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+		.enable_reg = SRI(reg1, block, reg_num),\
+		.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+		.enable_value = {\
+				block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+				~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+		},\
+		.ack_reg = SRI(reg2, block, reg_num),\
+		.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+		.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+
+
+#define hpd_int_entry(reg_num)\
+		[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+				IRQ_REG_ENTRY(HPD, reg_num,\
+						DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+						DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+						.funcs = &hpd_irq_info_funcs\
+}
+
+#define hpd_rx_int_entry(reg_num)\
+		[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+				IRQ_REG_ENTRY(HPD, reg_num,\
+						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
+						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+						.funcs = &hpd_rx_irq_info_funcs\
+}
+#define pflip_int_entry(reg_num)\
+		[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+				IRQ_REG_ENTRY(HUBPREQ, reg_num,\
+						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
+						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
+						.funcs = &pflip_irq_info_funcs\
+}
+
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+		.funcs = &vupdate_no_lock_irq_info_funcs\
+	}
+
+#define vblank_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+		.funcs = &vblank_irq_info_funcs\
+	}
+
+#define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
+
+#define i2c_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+		.set = dal_irq_service_dummy_set,
+		.ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info irq_source_info_dcn303[DAL_IRQ_SOURCES_NUMBER] = {
+		[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+		hpd_int_entry(0),
+		hpd_int_entry(1),
+		hpd_rx_int_entry(0),
+		hpd_rx_int_entry(1),
+		i2c_int_entry(1),
+		i2c_int_entry(2),
+		dp_sink_int_entry(1),
+		dp_sink_int_entry(2),
+		[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+		pflip_int_entry(0),
+		pflip_int_entry(1),
+		[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+		gpio_pad_int_entry(0),
+		gpio_pad_int_entry(1),
+		gpio_pad_int_entry(2),
+		gpio_pad_int_entry(3),
+		gpio_pad_int_entry(4),
+		gpio_pad_int_entry(5),
+		gpio_pad_int_entry(6),
+		gpio_pad_int_entry(7),
+		gpio_pad_int_entry(8),
+		gpio_pad_int_entry(9),
+		gpio_pad_int_entry(10),
+		gpio_pad_int_entry(11),
+		gpio_pad_int_entry(12),
+		gpio_pad_int_entry(13),
+		gpio_pad_int_entry(14),
+		gpio_pad_int_entry(15),
+		gpio_pad_int_entry(16),
+		gpio_pad_int_entry(17),
+		gpio_pad_int_entry(18),
+		gpio_pad_int_entry(19),
+		gpio_pad_int_entry(20),
+		gpio_pad_int_entry(21),
+		gpio_pad_int_entry(22),
+		gpio_pad_int_entry(23),
+		gpio_pad_int_entry(24),
+		gpio_pad_int_entry(25),
+		gpio_pad_int_entry(26),
+		gpio_pad_int_entry(27),
+		gpio_pad_int_entry(28),
+		gpio_pad_int_entry(29),
+		gpio_pad_int_entry(30),
+		dc_underflow_int_entry(1),
+		dc_underflow_int_entry(2),
+		[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+		[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+		vupdate_no_lock_int_entry(0),
+		vupdate_no_lock_int_entry(1),
+		vblank_int_entry(0),
+		vblank_int_entry(1),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dcn303 = {
+		.to_dal_irq_source = to_dal_irq_source_dcn303
+};
+
+static void dcn303_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
+{
+	dal_irq_service_construct(irq_service, init_data);
+
+	irq_service->info = irq_source_info_dcn303;
+	irq_service->funcs = &irq_service_funcs_dcn303;
+}
+
+struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data)
+{
+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
+
+	if (!irq_service)
+		return NULL;
+
+	dcn303_irq_construct(irq_service, init_data);
+	return irq_service;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.h b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.h
new file mode 100644
index 000000000000..fd64e3848ff3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef __DAL_IRQ_SERVICE_DCN303_H__
+#define __DAL_IRQ_SERVICE_DCN303_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data);
+
+#endif /* __DAL_IRQ_SERVICE_DCN303_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
new file mode 100644
index 000000000000..38e0ade60c7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+#include "../dce110/irq_service_dce110.h"
+
+
+#include "yellow_carp_offset.h"
+#include "dcn/dcn_3_1_2_offset.h"
+#include "dcn/dcn_3_1_2_sh_mask.h"
+
+#include "irq_service_dcn31.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+enum dc_irq_source to_dal_irq_source_dcn31(
+		struct irq_service *irq_service,
+		uint32_t src_id,
+		uint32_t ext_id)
+{
+	switch (src_id) {
+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK1;
+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK2;
+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK3;
+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK4;
+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK5;
+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK6;
+	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC1_VLINE0;
+	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC2_VLINE0;
+	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC3_VLINE0;
+	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC4_VLINE0;
+	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC5_VLINE0;
+	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC6_VLINE0;
+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP1;
+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP2;
+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP3;
+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP4;
+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP5;
+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP6;
+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE1;
+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE2;
+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE3;
+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE4;
+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE5;
+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE6;
+	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
+		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
+	case DCN_1_0__SRCID__DC_HPD1_INT:
+		/* generic src_id for all HPD and HPDRX interrupts */
+		switch (ext_id) {
+		case DCN_1_0__CTXID__DC_HPD1_INT:
+			return DC_IRQ_SOURCE_HPD1;
+		case DCN_1_0__CTXID__DC_HPD2_INT:
+			return DC_IRQ_SOURCE_HPD2;
+		case DCN_1_0__CTXID__DC_HPD3_INT:
+			return DC_IRQ_SOURCE_HPD3;
+		case DCN_1_0__CTXID__DC_HPD4_INT:
+			return DC_IRQ_SOURCE_HPD4;
+		case DCN_1_0__CTXID__DC_HPD5_INT:
+			return DC_IRQ_SOURCE_HPD5;
+		case DCN_1_0__CTXID__DC_HPD6_INT:
+			return DC_IRQ_SOURCE_HPD6;
+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
+			return DC_IRQ_SOURCE_HPD1RX;
+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
+			return DC_IRQ_SOURCE_HPD2RX;
+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
+			return DC_IRQ_SOURCE_HPD3RX;
+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
+			return DC_IRQ_SOURCE_HPD4RX;
+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
+			return DC_IRQ_SOURCE_HPD5RX;
+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
+			return DC_IRQ_SOURCE_HPD6RX;
+		default:
+			return DC_IRQ_SOURCE_INVALID;
+		}
+		break;
+
+	default:
+		return DC_IRQ_SOURCE_INVALID;
+	}
+}
+
+static bool hpd_ack(
+	struct irq_service *irq_service,
+	const struct irq_source_info *info)
+{
+	uint32_t addr = info->status_reg;
+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
+	uint32_t current_status =
+		get_reg_field_value(
+			value,
+			HPD0_DC_HPD_INT_STATUS,
+			DC_HPD_SENSE_DELAYED);
+
+	dal_irq_service_ack_generic(irq_service, info);
+
+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+	set_reg_field_value(
+		value,
+		current_status ? 0 : 1,
+		HPD0_DC_HPD_INT_CONTROL,
+		DC_HPD_INT_POLARITY);
+
+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+	return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+	.set = NULL,
+	.ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs outbox_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+			reg ## block ## id ## _ ## reg_name
+
+#define SRI_DMUB(reg_name)\
+	BASE(reg ## reg_name ## _BASE_IDX) + \
+			reg ## reg_name
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI(reg1, block, reg_num),\
+	.enable_mask = \
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI(reg2, block, reg_num),\
+	.ack_mask = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI_DMUB(reg1),\
+	.enable_mask = \
+		reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		reg1 ## __ ## mask1 ## _MASK,\
+		~reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI_DMUB(reg2),\
+	.ack_mask = \
+		reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		reg2 ## __ ## mask2 ## _MASK \
+
+#define hpd_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_irq_info_funcs\
+	}
+
+#define hpd_rx_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_rx_irq_info_funcs\
+	}
+#define pflip_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
+		.funcs = &pflip_irq_info_funcs\
+	}
+
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+		.funcs = &vupdate_no_lock_irq_info_funcs\
+	}
+
+#define vblank_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+		.funcs = &vblank_irq_info_funcs\
+	}
+
+#define vline0_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+		.funcs = &vline0_irq_info_funcs\
+	}
+#define dmub_outbox_int_entry()\
+	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
+		IRQ_REG_ENTRY_DMUB(\
+			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
+			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
+		.funcs = &outbox_irq_info_funcs\
+	}
+
+#define dummy_irq_entry() \
+	{\
+		.funcs = &dummy_irq_info_funcs\
+	}
+
+#define i2c_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+	.set = dal_irq_service_dummy_set,
+	.ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info
+irq_source_info_dcn31[DAL_IRQ_SOURCES_NUMBER] = {
+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+	hpd_int_entry(0),
+	hpd_int_entry(1),
+	hpd_int_entry(2),
+	hpd_int_entry(3),
+	hpd_int_entry(4),
+	hpd_rx_int_entry(0),
+	hpd_rx_int_entry(1),
+	hpd_rx_int_entry(2),
+	hpd_rx_int_entry(3),
+	hpd_rx_int_entry(4),
+	i2c_int_entry(1),
+	i2c_int_entry(2),
+	i2c_int_entry(3),
+	i2c_int_entry(4),
+	i2c_int_entry(5),
+	i2c_int_entry(6),
+	dp_sink_int_entry(1),
+	dp_sink_int_entry(2),
+	dp_sink_int_entry(3),
+	dp_sink_int_entry(4),
+	dp_sink_int_entry(5),
+	dp_sink_int_entry(6),
+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+	pflip_int_entry(0),
+	pflip_int_entry(1),
+	pflip_int_entry(2),
+	pflip_int_entry(3),
+	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+	gpio_pad_int_entry(0),
+	gpio_pad_int_entry(1),
+	gpio_pad_int_entry(2),
+	gpio_pad_int_entry(3),
+	gpio_pad_int_entry(4),
+	gpio_pad_int_entry(5),
+	gpio_pad_int_entry(6),
+	gpio_pad_int_entry(7),
+	gpio_pad_int_entry(8),
+	gpio_pad_int_entry(9),
+	gpio_pad_int_entry(10),
+	gpio_pad_int_entry(11),
+	gpio_pad_int_entry(12),
+	gpio_pad_int_entry(13),
+	gpio_pad_int_entry(14),
+	gpio_pad_int_entry(15),
+	gpio_pad_int_entry(16),
+	gpio_pad_int_entry(17),
+	gpio_pad_int_entry(18),
+	gpio_pad_int_entry(19),
+	gpio_pad_int_entry(20),
+	gpio_pad_int_entry(21),
+	gpio_pad_int_entry(22),
+	gpio_pad_int_entry(23),
+	gpio_pad_int_entry(24),
+	gpio_pad_int_entry(25),
+	gpio_pad_int_entry(26),
+	gpio_pad_int_entry(27),
+	gpio_pad_int_entry(28),
+	gpio_pad_int_entry(29),
+	gpio_pad_int_entry(30),
+	dc_underflow_int_entry(1),
+	dc_underflow_int_entry(2),
+	dc_underflow_int_entry(3),
+	dc_underflow_int_entry(4),
+	dc_underflow_int_entry(5),
+	dc_underflow_int_entry(6),
+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+	vupdate_no_lock_int_entry(0),
+	vupdate_no_lock_int_entry(1),
+	vupdate_no_lock_int_entry(2),
+	vupdate_no_lock_int_entry(3),
+	vblank_int_entry(0),
+	vblank_int_entry(1),
+	vblank_int_entry(2),
+	vblank_int_entry(3),
+	vline0_int_entry(0),
+	vline0_int_entry(1),
+	vline0_int_entry(2),
+	vline0_int_entry(3),
+	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
+	dmub_outbox_int_entry(),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dcn31 = {
+		.to_dal_irq_source = to_dal_irq_source_dcn31
+};
+
+static void dcn31_irq_construct(
+	struct irq_service *irq_service,
+	struct irq_service_init_data *init_data)
+{
+	dal_irq_service_construct(irq_service, init_data);
+
+	irq_service->info = irq_source_info_dcn31;
+	irq_service->funcs = &irq_service_funcs_dcn31;
+}
+
+struct irq_service *dal_irq_service_dcn31_create(
+	struct irq_service_init_data *init_data)
+{
+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
+						  GFP_KERNEL);
+
+	if (!irq_service)
+		return NULL;
+
+	dcn31_irq_construct(irq_service, init_data);
+	return irq_service;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h
new file mode 100644
index 000000000000..67efbfe9b7aa
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_IRQ_SERVICE_DCN31_H__
+#define __DAL_IRQ_SERVICE_DCN31_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dcn31_create(
+	struct irq_service_init_data *init_data);
+
+#endif /* __DAL_IRQ_SERVICE_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h
index ae8f47ec0f8c..5f9346622301 100644
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -150,7 +150,7 @@ enum dc_irq_source {
 	DC_IRQ_SOURCE_DC4_VLINE1,
 	DC_IRQ_SOURCE_DC5_VLINE1,
 	DC_IRQ_SOURCE_DC6_VLINE1,
-	DC_IRQ_DMCUB_OUTBOX1,
+	DC_IRQ_SOURCE_DMCUB_OUTBOX,
 	DC_IRQ_SOURCE_DMCUB_OUTBOX0,
 
 	DAL_IRQ_SOURCES_NUMBER
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index b4e14960b164..abbf7ae584c9 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -73,6 +73,7 @@ extern "C" {
 /* Forward declarations */
 struct dmub_srv;
 struct dmub_srv_common_regs;
+struct dmub_srv_dcn31_regs;
 
 struct dmcub_trace_buf_entry;
 
@@ -93,6 +94,8 @@ enum dmub_asic {
 	DMUB_ASIC_DCN30,
 	DMUB_ASIC_DCN301,
 	DMUB_ASIC_DCN302,
+	DMUB_ASIC_DCN303,
+	DMUB_ASIC_DCN31,
 	DMUB_ASIC_MAX,
 };
 
@@ -216,6 +219,49 @@ struct dmub_srv_fb_info {
 	struct dmub_fb fb[DMUB_WINDOW_TOTAL];
 };
 
+/*
+ * struct dmub_srv_hw_params - params for dmub hardware initialization
+ * @fb: framebuffer info for each region
+ * @fb_base: base of the framebuffer aperture
+ * @fb_offset: offset of the framebuffer aperture
+ * @psp_version: psp version to pass for DMCU init
+ * @load_inst_const: true if DMUB should load inst const fw
+ */
+struct dmub_srv_hw_params {
+	struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
+	uint64_t fb_base;
+	uint64_t fb_offset;
+	uint32_t psp_version;
+	bool load_inst_const;
+	bool skip_panel_power_sequence;
+	bool disable_z10;
+};
+
+/**
+ * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for
+ * debugging purposes, including logging, crash analysis, etc.
+ */
+struct dmub_diagnostic_data {
+	uint32_t dmcub_version;
+	uint32_t scratch[16];
+	uint32_t pc;
+	uint32_t undefined_address_fault_addr;
+	uint32_t inst_fetch_fault_addr;
+	uint32_t data_write_fault_addr;
+	uint32_t inbox1_rptr;
+	uint32_t inbox1_wptr;
+	uint32_t inbox1_size;
+	uint32_t inbox0_rptr;
+	uint32_t inbox0_wptr;
+	uint32_t inbox0_size;
+	uint8_t is_dmcub_enabled : 1;
+	uint8_t is_dmcub_soft_reset : 1;
+	uint8_t is_dmcub_secure_reset : 1;
+	uint8_t is_traceport_en : 1;
+	uint8_t is_cw0_enabled : 1;
+	uint8_t is_cw6_enabled : 1;
+};
+
 /**
  * struct dmub_srv_base_funcs - Driver specific base callbacks
  */
@@ -290,7 +336,8 @@ struct dmub_srv_hw_funcs {
 	bool (*is_hw_init)(struct dmub_srv *dmub);
 
 	bool (*is_phy_init)(struct dmub_srv *dmub);
-	void (*enable_dmub_boot_options)(struct dmub_srv *dmub);
+	void (*enable_dmub_boot_options)(struct dmub_srv *dmub,
+				const struct dmub_srv_hw_params *params);
 
 	void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);
 
@@ -305,6 +352,10 @@ struct dmub_srv_hw_funcs {
 
 	uint32_t (*get_gpint_response)(struct dmub_srv *dmub);
 
+	void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
+	uint32_t (*get_current_time)(struct dmub_srv *dmub);
+
+	void (*get_diagnostic_data)(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca);
 };
 
 /**
@@ -325,23 +376,6 @@ struct dmub_srv_create_params {
 	bool is_virtual;
 };
 
-/*
- * struct dmub_srv_hw_params - params for dmub hardware initialization
- * @fb: framebuffer info for each region
- * @fb_base: base of the framebuffer aperture
- * @fb_offset: offset of the framebuffer aperture
- * @psp_version: psp version to pass for DMCU init
- * @load_inst_const: true if DMUB should load inst const fw
- */
-struct dmub_srv_hw_params {
-	struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
-	uint64_t fb_base;
-	uint64_t fb_offset;
-	uint32_t psp_version;
-	bool load_inst_const;
-	bool skip_panel_power_sequence;
-};
-
 /**
  * struct dmub_srv - software state for dmcub
  * @asic: dmub asic identifier
@@ -360,6 +394,7 @@ struct dmub_srv {
 
 	/* private: internal use only */
 	const struct dmub_srv_common_regs *regs;
+	const struct dmub_srv_dcn31_regs *regs_dcn31;
 
 	struct dmub_srv_base_funcs funcs;
 	struct dmub_srv_hw_funcs hw_funcs;
@@ -669,6 +704,8 @@ enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
 
 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry);
 
+bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 4195ff10c514..7c4734f905d9 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x23db9b126
+#define DMUB_FW_VERSION_GIT_HASH 0xf3da2b656
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 62
+#define DMUB_FW_VERSION_REVISION 71
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -121,14 +121,25 @@
 #define TRACE_BUFFER_ENTRY_OFFSET  16
 
 /**
- * ABM backlight control version legacy
+ *
+ * PSR control version legacy
+ */
+#define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
+/**
+ * PSR control version with multi edp support
  */
-#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_UNKNOWN 0x0
+#define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
+
 
 /**
- * ABM backlight control version with multi edp support
+ * ABM control version legacy
  */
-#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1 0x1
+#define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
+
+/**
+ * ABM control version with multi edp support
+ */
+#define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
 
 /**
  * Physical framebuffer address location, 64-bit.
@@ -163,6 +174,13 @@ extern "C" {
 #endif
 
 /**
+ * Number of nanoseconds per DMUB tick.
+ * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default.
+ * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true.
+ */
+#define NS_PER_DMUB_TICK 10
+
+/**
  * union dmub_addr - DMUB physical/virtual 64-bit address.
  */
 union dmub_addr {
@@ -291,6 +309,7 @@ struct dmcub_trace_buf_entry {
  * Current scratch register usage is as follows:
  *
  * SCRATCH0: FW Boot Status register
+ * SCRATCH5: LVTMA Status Register
  * SCRATCH15: FW Boot Options register
  */
 
@@ -317,6 +336,21 @@ enum dmub_fw_boot_status_bit {
 	DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
 };
 
+/* Register bit definition for SCRATCH5 */
+union dmub_lvtma_status {
+	struct {
+		uint32_t psp_ok : 1;
+		uint32_t edp_on : 1;
+		uint32_t reserved : 30;
+	} bits;
+	uint32_t all;
+};
+
+enum dmub_lvtma_status_bit {
+	DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
+	DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
+};
+
 /**
  * union dmub_fw_boot_options - Boot option definitions for SCRATCH15
  */
@@ -328,7 +362,8 @@ union dmub_fw_boot_options {
 		uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
 		uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
 		uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
-		uint32_t reserved : 26; /**< reserved */
+		uint32_t z10_disable: 1; /**< 1 to disable z10 */
+		uint32_t reserved : 25; /**< reserved */
 	} bits; /**< boot bits */
 	uint32_t all; /**< 32-bit access to bits */
 };
@@ -452,6 +487,61 @@ enum dmub_gpint_command {
 	DMUB_GPINT__PSR_RESIDENCY = 9,
 };
 
+/**
+ * INBOX0 generic command definition
+ */
+union dmub_inbox0_cmd_common {
+	struct {
+		uint32_t command_code: 8; /**< INBOX0 command code */
+		uint32_t param: 24; /**< 24-bit parameter */
+	} bits;
+	uint32_t all;
+};
+
+/**
+ * INBOX0 hw_lock command definition
+ */
+union dmub_inbox0_cmd_lock_hw {
+	struct {
+		uint32_t command_code: 8;
+
+		/* NOTE: Must be have enough bits to match: enum hw_lock_client */
+		uint32_t hw_lock_client: 1;
+
+		/* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
+		uint32_t otg_inst: 3;
+		uint32_t opp_inst: 3;
+		uint32_t dig_inst: 3;
+
+		/* NOTE: Below fields must match with: union dmub_hw_lock_flags */
+		uint32_t lock_pipe: 1;
+		uint32_t lock_cursor: 1;
+		uint32_t lock_dig: 1;
+		uint32_t triple_buffer_lock: 1;
+
+		uint32_t lock: 1;				/**< Lock */
+		uint32_t should_release: 1;		/**< Release */
+		uint32_t reserved: 8; 			/**< Reserved for extending more clients, HW, etc. */
+	} bits;
+	uint32_t all;
+};
+
+union dmub_inbox0_data_register {
+	union dmub_inbox0_cmd_common inbox0_cmd_common;
+	union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
+};
+
+enum dmub_inbox0_command {
+	/**
+	 * DESC: Invalid command, ignored.
+	 */
+	DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
+	/**
+	 * DESC: Notification to acquire/release HW lock
+	 * ARGS:
+	 */
+	DMUB_INBOX0_CMD__HW_LOCK = 1,
+};
 //==============================================================================
 //</DMUB_GPINT>=================================================================
 //==============================================================================
@@ -538,6 +628,22 @@ enum dmub_cmd_type {
 	 */
 	DMUB_CMD__OUTBOX1_ENABLE = 71,
 	/**
+	 * Command type used for all idle optimization commands.
+	 */
+	DMUB_CMD__IDLE_OPT = 72,
+	/**
+	 * Command type used for all clock manager commands.
+	 */
+	DMUB_CMD__CLK_MGR = 73,
+	/**
+	 * Command type used for all panel control commands.
+	 */
+	DMUB_CMD__PANEL_CNTL = 74,
+	/**
+	 * Command type used for EDID CEA parsing
+	 */
+	DMUB_CMD__EDID_CEA = 79,
+	/**
 	 * Command type used for all VBIOS interface commands.
 	 */
 	DMUB_CMD__VBIOS = 128,
@@ -555,10 +661,6 @@ enum dmub_out_cmd_type {
 	 * Command type used for DP AUX Reply data notification
 	 */
 	DMUB_OUT_CMD__DP_AUX_REPLY = 1,
-	/**
-	 * Command type used for DP HPD event notification
-	 */
-	DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
 };
 
 #pragma pack(push, 1)
@@ -570,7 +672,8 @@ struct dmub_cmd_header {
 	unsigned int type : 8; /**< command type */
 	unsigned int sub_type : 8; /**< command sub type */
 	unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
-	unsigned int reserved0 : 7; /**< reserved bits */
+	unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
+	unsigned int reserved0 : 6; /**< reserved bits */
 	unsigned int payload_bytes : 6;  /* payload excluding header - up to 60 bytes */
 	unsigned int reserved1 : 2; /**< reserved bits */
 };
@@ -746,6 +849,51 @@ struct dmub_rb_cmd_mall {
 };
 
 /**
+ * enum dmub_cmd_idle_opt_type - Idle optimization command type.
+ */
+enum dmub_cmd_idle_opt_type {
+	/**
+	 * DCN hardware restore.
+	 */
+	DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
+};
+
+/**
+ * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
+ */
+struct dmub_rb_cmd_idle_opt_dcn_restore {
+	struct dmub_cmd_header header; /**< header */
+};
+
+/**
+ * struct dmub_clocks - Clock update notification.
+ */
+struct dmub_clocks {
+	uint32_t dispclk_khz; /**< dispclk kHz */
+	uint32_t dppclk_khz; /**< dppclk kHz */
+	uint32_t dcfclk_khz; /**< dcfclk kHz */
+	uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
+};
+
+/**
+ * enum dmub_cmd_clk_mgr_type - Clock manager commands.
+ */
+enum dmub_cmd_clk_mgr_type {
+	/**
+	 * Notify DMCUB of clock update.
+	 */
+	DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
+};
+
+/**
+ * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
+ */
+struct dmub_rb_cmd_clk_mgr_notify_clocks {
+	struct dmub_cmd_header header; /**< header */
+	struct dmub_clocks clocks; /**< clock data */
+};
+
+/**
  * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
  */
 struct dmub_cmd_digx_encoder_control_data {
@@ -1249,9 +1397,15 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint8_t fec_enable_delay_in100us;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
 	 */
-	uint8_t pad3[2];
+	uint8_t panel_inst;
 };
 
 /**
@@ -1276,10 +1430,16 @@ struct dmub_cmd_psr_set_level_data {
 	 * 16-bit value dicated by driver that will enable/disable different functionality.
 	 */
 	uint16_t psr_level;
+		/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
 	 */
-	uint8_t pad[2];
+	uint8_t panel_inst;
 };
 
 /**
@@ -1296,6 +1456,23 @@ struct dmub_rb_cmd_psr_set_level {
 	struct dmub_cmd_psr_set_level_data psr_set_level_data;
 };
 
+struct dmub_rb_cmd_psr_enable_data {
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
+};
+
 /**
  * Definition of a DMUB_CMD__PSR_ENABLE command.
  * PSR enable/disable is controlled using the sub_type.
@@ -1305,6 +1482,8 @@ struct dmub_rb_cmd_psr_enable {
 	 * Command header.
 	 */
 	struct dmub_cmd_header header;
+
+	struct dmub_rb_cmd_psr_enable_data data;
 };
 
 /**
@@ -1315,6 +1494,20 @@ struct dmub_cmd_psr_set_version_data {
 	 * PSR version that FW should implement.
 	 */
 	enum psr_version version;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
 };
 
 /**
@@ -1331,6 +1524,23 @@ struct dmub_rb_cmd_psr_set_version {
 	struct dmub_cmd_psr_set_version_data psr_set_version_data;
 };
 
+struct dmub_cmd_psr_force_static_data {
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
+};
+
 /**
  * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
  */
@@ -1339,10 +1549,17 @@ struct dmub_rb_cmd_psr_force_static {
 	 * Command header.
 	 */
 	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
+	 */
+	struct dmub_cmd_psr_force_static_data psr_force_static_data;
 };
 
 /**
  * Set of HW components that can be locked.
+ *
+ * Note: If updating with more HW components, fields
+ * in dmub_inbox0_cmd_lock_hw must be updated to match.
  */
 union dmub_hw_lock_flags {
 	/**
@@ -1375,6 +1592,9 @@ union dmub_hw_lock_flags {
 
 /**
  * Instances of HW to be locked.
+ *
+ * Note: If updating with more HW components, fields
+ * in dmub_inbox0_cmd_lock_hw must be updated to match.
  */
 struct dmub_hw_lock_inst_flags {
 	/**
@@ -1398,6 +1618,9 @@ struct dmub_hw_lock_inst_flags {
 
 /**
  * Clients that can acquire the HW Lock Manager.
+ *
+ * Note: If updating with more clients, fields in
+ * dmub_inbox0_cmd_lock_hw must be updated to match.
  */
 enum hw_lock_client {
 	/**
@@ -1405,10 +1628,6 @@ enum hw_lock_client {
 	 */
 	HW_LOCK_CLIENT_DRIVER = 0,
 	/**
-	 * FW is the client of HW Lock Manager.
-	 */
-	HW_LOCK_CLIENT_FW,
-	/**
 	 * Invalid client.
 	 */
 	HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
@@ -1637,7 +1856,7 @@ struct dmub_cmd_abm_set_backlight_data {
 	uint32_t backlight_user_level;
 
 	/**
-	 * Backlight data version.
+	 * ABM control version.
 	 */
 	uint8_t version;
 
@@ -1677,6 +1896,23 @@ struct dmub_cmd_abm_set_level_data {
 	 * Set current ABM operating/aggression level.
 	 */
 	uint32_t level;
+
+	/**
+	 * ABM control version.
+	 */
+	uint8_t version;
+
+	/**
+	 * Panel Control HW instance mask.
+	 * Bit 0 is Panel Control HW instance 0.
+	 * Bit 1 is Panel Control HW instance 1.
+	 */
+	uint8_t panel_mask;
+
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
 };
 
 /**
@@ -1702,6 +1938,23 @@ struct dmub_cmd_abm_set_ambient_level_data {
 	 * Ambient light sensor reading from OS.
 	 */
 	uint32_t ambient_lux;
+
+	/**
+	 * ABM control version.
+	 */
+	uint8_t version;
+
+	/**
+	 * Panel Control HW instance mask.
+	 * Bit 0 is Panel Control HW instance 0.
+	 * Bit 1 is Panel Control HW instance 1.
+	 */
+	uint8_t panel_mask;
+
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
 };
 
 /**
@@ -1728,6 +1981,23 @@ struct dmub_cmd_abm_set_pwm_frac_data {
 	 * TODO: Convert to uint8_t.
 	 */
 	uint32_t fractional_pwm;
+
+	/**
+	 * ABM control version.
+	 */
+	uint8_t version;
+
+	/**
+	 * Panel Control HW instance mask.
+	 * Bit 0 is Panel Control HW instance 0.
+	 * Bit 1 is Panel Control HW instance 1.
+	 */
+	uint8_t panel_mask;
+
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
 };
 
 /**
@@ -1758,6 +2028,24 @@ struct dmub_cmd_abm_init_config_data {
 	 * Indirect buffer length.
 	 */
 	uint16_t bytes;
+
+
+	/**
+	 * ABM control version.
+	 */
+	uint8_t version;
+
+	/**
+	 * Panel Control HW instance mask.
+	 * Bit 0 is Panel Control HW instance 0.
+	 * Bit 1 is Panel Control HW instance 1.
+	 */
+	uint8_t panel_mask;
+
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
 };
 
 /**
@@ -1816,6 +2104,41 @@ struct dmub_rb_cmd_drr_update {
 };
 
 /**
+ * enum dmub_cmd_panel_cntl_type - Panel control command.
+ */
+enum dmub_cmd_panel_cntl_type {
+	/**
+	 * Initializes embedded panel hardware blocks.
+	 */
+	DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
+	/**
+	 * Queries backlight info for the embedded panel.
+	 */
+	DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
+};
+
+/**
+ * struct dmub_cmd_panel_cntl_data - Panel control data.
+ */
+struct dmub_cmd_panel_cntl_data {
+	uint32_t inst; /**< panel instance */
+	uint32_t current_backlight; /* in/out */
+	uint32_t bl_pwm_cntl; /* in/out */
+	uint32_t bl_pwm_period_cntl; /* in/out */
+	uint32_t bl_pwm_ref_div1; /* in/out */
+	uint8_t is_backlight_on : 1; /* in/out */
+	uint8_t is_powered_on : 1; /* in/out */
+};
+
+/**
+ * struct dmub_rb_cmd_panel_cntl - Panel control command.
+ */
+struct dmub_rb_cmd_panel_cntl {
+	struct dmub_cmd_header header; /**< header */
+	struct dmub_cmd_panel_cntl_data data; /**< payload */
+};
+
+/**
  * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
  */
 struct dmub_cmd_lvtma_control_data {
@@ -1840,6 +2163,68 @@ struct dmub_rb_cmd_lvtma_control {
 };
 
 /**
+ * Maximum number of bytes a chunk sent to DMUB for parsing
+ */
+#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
+
+/**
+ *  Represent a chunk of CEA blocks sent to DMUB for parsing
+ */
+struct dmub_cmd_send_edid_cea {
+	uint16_t offset;	/**< offset into the CEA block */
+	uint8_t length;	/**< number of bytes in payload to copy as part of CEA block */
+	uint16_t total_length;  /**< total length of the CEA block */
+	uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
+	uint8_t pad[3]; /**< padding and for future expansion */
+};
+
+/**
+ * Result of VSDB parsing from CEA block
+ */
+struct dmub_cmd_edid_cea_amd_vsdb {
+	uint8_t vsdb_found;		/**< 1 if parsing has found valid AMD VSDB */
+	uint8_t freesync_supported;	/**< 1 if Freesync is supported */
+	uint16_t amd_vsdb_version;	/**< AMD VSDB version */
+	uint16_t min_frame_rate;	/**< Maximum frame rate */
+	uint16_t max_frame_rate;	/**< Minimum frame rate */
+};
+
+/**
+ * Result of sending a CEA chunk
+ */
+struct dmub_cmd_edid_cea_ack {
+	uint16_t offset;	/**< offset of the chunk into the CEA block */
+	uint8_t success;	/**< 1 if this sending of chunk succeeded */
+	uint8_t pad;		/**< padding and for future expansion */
+};
+
+/**
+ * Specify whether the result is an ACK/NACK or the parsing has finished
+ */
+enum dmub_cmd_edid_cea_reply_type {
+	DMUB_CMD__EDID_CEA_AMD_VSDB	= 1, /**< VSDB parsing has finished */
+	DMUB_CMD__EDID_CEA_ACK		= 2, /**< acknowledges the CEA sending is OK or failing */
+};
+
+/**
+ * Definition of a DMUB_CMD__EDID_CEA command.
+ */
+struct dmub_rb_cmd_edid_cea {
+	struct dmub_cmd_header header;	/**< Command header */
+	union dmub_cmd_edid_cea_data {
+		struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
+		struct dmub_cmd_edid_cea_output { /**< output with results */
+			uint8_t type;	/**< dmub_cmd_edid_cea_reply_type */
+			union {
+				struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
+				struct dmub_cmd_edid_cea_ack ack;
+			};
+		} output;	/**< output to retrieve ACK/NACK or VSDB parsing results */
+	} data;	/**< Command data */
+
+};
+
+/**
  * union dmub_rb_cmd - DMUB inbox command.
  */
 union dmub_rb_cmd {
@@ -1913,6 +2298,20 @@ union dmub_rb_cmd {
 	 */
 	struct dmub_rb_cmd_mall mall;
 	/**
+	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
+	 */
+	struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
+
+	/**
+	 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
+	 */
+	struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
+
+	/**
+	 * Definition of DMUB_CMD__PANEL_CNTL commands.
+	 */
+	struct dmub_rb_cmd_panel_cntl panel_cntl;
+	/**
 	 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
 	 */
 	struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
@@ -1961,6 +2360,10 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
 	 */
 	struct dmub_rb_cmd_lvtma_control lvtma_control;
+	/**
+	 * Definition of a DMUB_CMD__EDID_CEA command.
+	 */
+	struct dmub_rb_cmd_edid_cea edid_cea;
 };
 
 /**
@@ -2127,6 +2530,46 @@ static inline bool dmub_rb_front(struct dmub_rb *rb,
 }
 
 /**
+ * @brief Determines the next ringbuffer offset.
+ *
+ * @param rb DMUB inbox ringbuffer
+ * @param num_cmds Number of commands
+ * @param next_rptr The next offset in the ringbuffer
+ */
+static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
+				  uint32_t num_cmds,
+				  uint32_t *next_rptr)
+{
+	*next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
+
+	if (*next_rptr >= rb->capacity)
+		*next_rptr %= rb->capacity;
+}
+
+/**
+ * @brief Returns a pointer to a command in the inbox.
+ *
+ * @param rb DMUB inbox ringbuffer
+ * @param cmd The inbox command to return
+ * @param rptr The ringbuffer offset
+ * @return true if not empty
+ * @return false otherwise
+ */
+static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
+				 union dmub_rb_cmd  **cmd,
+				 uint32_t rptr)
+{
+	uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
+
+	if (dmub_rb_empty(rb))
+		return false;
+
+	*cmd = (union dmub_rb_cmd *)rb_cmd;
+
+	return true;
+}
+
+/**
  * @brief Returns the next unprocessed command in the outbox.
  *
  * @param rb DMUB outbox ringbuffer
diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index 7495c23c73a9..0495bcdd3463 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -21,8 +21,8 @@
 #
 
 DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
-DMUB += dmub_dcn30.o dmub_dcn301.o
-DMUB += dmub_dcn302.o
+DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o
+DMUB += dmub_dcn31.o
 
 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
 
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 6934906c665e..a6540e27044d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -40,7 +40,10 @@
 
 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 
 #define DMUB_SF(reg, field) FD_MASK(reg, field),
@@ -385,7 +388,7 @@ union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
 	return status;
 }
 
-void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub)
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
 {
 	union dmub_fw_boot_options boot_options = {0};
 
@@ -399,3 +402,68 @@ void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
 	boot_options.bits.skip_phy_init_panel_sequence = skip;
 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
 }
+
+uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_TIMER_CURRENT);
+}
+
+void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
+{
+	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
+	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
+
+	if (!dmub || !diag_data)
+		return;
+
+	memset(diag_data, 0, sizeof(*diag_data));
+
+	diag_data->dmcub_version = dmub->fw_version;
+
+	diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
+	diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
+	diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
+	diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
+	diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
+	diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
+	diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
+	diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
+	diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
+	diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
+	diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
+	diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
+	diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
+	diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
+	diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
+	diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
+
+	diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
+	diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
+	diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
+
+	diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
+	diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
+	diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
+
+	diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
+	diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
+	diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
+
+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
+	diag_data->is_dmcub_enabled = is_dmub_enabled;
+
+	REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
+	diag_data->is_dmcub_soft_reset = is_soft_reset;
+
+	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
+	diag_data->is_dmcub_secure_reset = is_sec_reset;
+
+	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
+	diag_data->is_traceport_en  = is_traceport_enabled;
+
+	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
+	diag_data->is_cw0_enabled = is_cw0_enabled;
+
+	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
+	diag_data->is_cw6_enabled = is_cw6_enabled;
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index de5351cd5abc..c2e5831ac52c 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -36,6 +36,9 @@ struct dmub_srv;
 	DMUB_SR(DMCUB_CNTL) \
 	DMUB_SR(DMCUB_MEM_CNTL) \
 	DMUB_SR(DMCUB_SEC_CNTL) \
+	DMUB_SR(DMCUB_INBOX0_SIZE) \
+	DMUB_SR(DMCUB_INBOX0_RPTR) \
+	DMUB_SR(DMCUB_INBOX0_WPTR) \
 	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
 	DMUB_SR(DMCUB_INBOX1_SIZE) \
 	DMUB_SR(DMCUB_INBOX1_RPTR) \
@@ -107,7 +110,13 @@ struct dmub_srv;
 	DMUB_SR(MMHUBBUB_SOFT_RESET) \
 	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
 	DMUB_SR(DCN_VM_FB_OFFSET) \
-	DMUB_SR(DMCUB_INTERRUPT_ACK)
+	DMUB_SR(DMCUB_INTERRUPT_ACK) \
+	DMUB_SR(DMCUB_TIMER_CURRENT) \
+	DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
+	DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
+	DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR)
+
+#define DMCUB_INTERNAL_REGS()
 
 #define DMUB_COMMON_FIELDS() \
 	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
@@ -117,6 +126,7 @@ struct dmub_srv;
 	DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_WRITE_SPACE) \
 	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
 	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
 	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
 	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
 	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
@@ -146,6 +156,7 @@ struct dmub_srv;
 struct dmub_srv_common_reg_offset {
 #define DMUB_SR(reg) uint32_t reg;
 	DMUB_COMMON_REGS()
+	DMCUB_INTERNAL_REGS()
 #undef DMUB_SR
 };
 
@@ -221,7 +232,7 @@ bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
 
 uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);
 
-void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub);
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
 
 void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
 
@@ -231,4 +242,8 @@ bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);
 
 bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);
 
+uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);
+
+void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca);
+
 #endif /* _DMUB_DCN20_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
index 1cf67b3e4771..51bb9bceb1b1 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
@@ -39,7 +39,10 @@
 
 const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 
 #define DMUB_SF(reg, field) FD_MASK(reg, field),
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
index fb11c8d39208..81dae75e9ff8 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
@@ -40,7 +40,10 @@
 
 const struct dmub_srv_common_regs dmub_srv_dcn30_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 
 #define DMUB_SF(reg, field) FD_MASK(reg, field),
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
index 197398257692..84c3ab3becc5 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
@@ -39,7 +39,10 @@
 
 const struct dmub_srv_common_regs dmub_srv_dcn301_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 
 #define DMUB_SF(reg, field) FD_MASK(reg, field),
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c
index f5db4437a882..8c02575e168d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c
@@ -39,7 +39,10 @@
 
 const struct dmub_srv_common_regs dmub_srv_dcn302_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 
 #define DMUB_SF(reg, field) FD_MASK(reg, field),
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c
new file mode 100644
index 000000000000..b42369984473
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn303.h"
+
+#include "sienna_cichlid_ip_offset.h"
+#include "dcn/dcn_3_0_3_offset.h"
+#include "dcn/dcn_3_0_3_sh_mask.h"
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs
+
+/* Registers. */
+
+const struct dmub_srv_common_regs dmub_srv_dcn303_regs = {
+#define DMUB_SR(reg) REG_OFFSET(reg),
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+	{ DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+	{ DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+};
+
+/* Shared functions. */
+
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h
new file mode 100644
index 000000000000..84141d450256
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef _DMUB_DCN303_H_
+#define _DMUB_DCN303_H_
+
+#include "dmub_dcn20.h"
+
+/* Registers. */
+
+extern const struct dmub_srv_common_regs dmub_srv_dcn303_regs;
+
+/* Hardware functions. */
+
+#endif /* _DMUB_DCN303_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
new file mode 100644
index 000000000000..8c886ece71f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn31.h"
+
+#include "yellow_carp_offset.h"
+#include "dcn/dcn_3_1_2_offset.h"
+#include "dcn/dcn_3_1_2_sh_mask.h"
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs_dcn31
+#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
+
+const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = {
+#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
+	{ DMUB_DCN31_REGS() },
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+	{ DMUB_DCN31_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+	{ DMUB_DCN31_FIELDS() },
+#undef DMUB_SF
+};
+
+static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,
+					  uint64_t *fb_base,
+					  uint64_t *fb_offset)
+{
+	uint32_t tmp;
+
+	if (dmub->fb_base || dmub->fb_offset) {
+		*fb_base = dmub->fb_base;
+		*fb_offset = dmub->fb_offset;
+		return;
+	}
+
+	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+	*fb_base = (uint64_t)tmp << 24;
+
+	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+	*fb_offset = (uint64_t)tmp << 24;
+}
+
+static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,
+					     uint64_t fb_base,
+					     uint64_t fb_offset,
+					     union dmub_addr *addr_out)
+{
+	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
+}
+
+void dmub_dcn31_reset(struct dmub_srv *dmub)
+{
+	union dmub_gpint_data_register cmd;
+	const uint32_t timeout = 30;
+	uint32_t in_reset, scratch, i;
+
+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
+
+	if (in_reset == 0) {
+		cmd.bits.status = 1;
+		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
+		cmd.bits.param = 0;
+
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/**
+		 * Timeout covers both the ACK and the wait
+		 * for remaining work to finish.
+		 *
+		 * This is mostly bound by the PHY disable sequence.
+		 * Each register check will be greater than 1us, so
+		 * don't bother using udelay.
+		 */
+
+		for (i = 0; i < timeout; ++i) {
+			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
+				break;
+		}
+
+		for (i = 0; i < timeout; ++i) {
+			scratch = dmub->hw_funcs.get_gpint_response(dmub);
+			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
+				break;
+		}
+
+		/* Clear the GPINT command manually so we don't reset again. */
+		cmd.all = 0;
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/* Force reset in case we timed out, DMCUB is likely hung. */
+	}
+
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
+	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_SCRATCH0, 0);
+}
+
+void dmub_dcn31_reset_release(struct dmub_srv *dmub)
+{
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
+	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
+	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
+}
+
+void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1)
+{
+	union dmub_addr offset;
+	uint64_t fb_base, fb_offset;
+
+	dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset);
+
+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
+
+	dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+		  DMCUB_REGION3_CW0_ENABLE, 1);
+
+	dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+		  DMCUB_REGION3_CW1_ENABLE, 1);
+
+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
+		     0x20);
+}
+
+void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
+			      const struct dmub_window *cw2,
+			      const struct dmub_window *cw3,
+			      const struct dmub_window *cw4,
+			      const struct dmub_window *cw5,
+			      const struct dmub_window *cw6)
+{
+	union dmub_addr offset;
+
+	offset = cw3->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
+	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
+		  DMCUB_REGION3_CW3_ENABLE, 1);
+
+	offset = cw4->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
+	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
+		  DMCUB_REGION3_CW4_ENABLE, 1);
+
+	offset = cw5->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
+	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+		  DMCUB_REGION3_CW5_ENABLE, 1);
+
+	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
+	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
+		  DMCUB_REGION5_TOP_ADDRESS,
+		  cw5->region.top - cw5->region.base - 1,
+		  DMCUB_REGION5_ENABLE, 1);
+
+	offset = cw6->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
+	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
+		  DMCUB_REGION3_CW6_ENABLE, 1);
+}
+
+void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *inbox1)
+{
+	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
+	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
+}
+
+uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_INBOX1_RPTR);
+}
+
+void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
+{
+	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
+}
+
+void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox1)
+{
+	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
+	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
+}
+
+uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)
+{
+	/**
+	 * outbox1 wptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	return REG_READ(DMCUB_OUTBOX1_WPTR);
+}
+
+void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	/**
+	 * outbox1 rptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
+}
+
+bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)
+{
+	uint32_t is_hw_init;
+
+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
+
+	return is_hw_init != 0;
+}
+
+bool dmub_dcn31_is_supported(struct dmub_srv *dmub)
+{
+	uint32_t supported = 0;
+
+	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
+
+	return supported;
+}
+
+void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
+			  union dmub_gpint_data_register reg)
+{
+	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
+}
+
+bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
+			       union dmub_gpint_data_register reg)
+{
+	union dmub_gpint_data_register test;
+
+	reg.bits.status = 0;
+	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
+
+	return test.all == reg.all;
+}
+
+uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_SCRATCH7);
+}
+
+union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)
+{
+	union dmub_fw_boot_status status;
+
+	status.all = REG_READ(DMCUB_SCRATCH0);
+	return status;
+}
+
+void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
+{
+	union dmub_fw_boot_options boot_options = {0};
+
+	boot_options.bits.z10_disable = params->disable_z10;
+
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
+{
+	union dmub_fw_boot_options boot_options;
+	boot_options.all = REG_READ(DMCUB_SCRATCH14);
+	boot_options.bits.skip_phy_init_panel_sequence = skip;
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox0)
+{
+	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
+
+	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
+}
+
+uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_OUTBOX0_WPTR);
+}
+
+void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
+}
+
+uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_TIMER_CURRENT);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
new file mode 100644
index 000000000000..2829c3e9a310
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_DCN31_H_
+#define _DMUB_DCN31_H_
+
+#include "dmub_dcn20.h"
+
+struct dmub_srv;
+
+/* DCN31 register definitions. */
+
+#define DMUB_DCN31_REGS() \
+	DMUB_SR(DMCUB_CNTL) \
+	DMUB_SR(DMCUB_CNTL2) \
+	DMUB_SR(DMCUB_SEC_CNTL) \
+	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_INBOX1_SIZE) \
+	DMUB_SR(DMCUB_INBOX1_RPTR) \
+	DMUB_SR(DMCUB_INBOX1_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX0_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX0_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX1_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX1_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_WPTR) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION4_OFFSET) \
+	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION5_OFFSET) \
+	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_SCRATCH0) \
+	DMUB_SR(DMCUB_SCRATCH1) \
+	DMUB_SR(DMCUB_SCRATCH2) \
+	DMUB_SR(DMCUB_SCRATCH3) \
+	DMUB_SR(DMCUB_SCRATCH4) \
+	DMUB_SR(DMCUB_SCRATCH5) \
+	DMUB_SR(DMCUB_SCRATCH6) \
+	DMUB_SR(DMCUB_SCRATCH7) \
+	DMUB_SR(DMCUB_SCRATCH8) \
+	DMUB_SR(DMCUB_SCRATCH9) \
+	DMUB_SR(DMCUB_SCRATCH10) \
+	DMUB_SR(DMCUB_SCRATCH11) \
+	DMUB_SR(DMCUB_SCRATCH12) \
+	DMUB_SR(DMCUB_SCRATCH13) \
+	DMUB_SR(DMCUB_SCRATCH14) \
+	DMUB_SR(DMCUB_SCRATCH15) \
+	DMUB_SR(DMCUB_GPINT_DATAIN1) \
+	DMUB_SR(CC_DC_PIPE_DIS) \
+	DMUB_SR(MMHUBBUB_SOFT_RESET) \
+	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+	DMUB_SR(DCN_VM_FB_OFFSET) \
+	DMUB_SR(DMCUB_TIMER_CURRENT)
+
+#define DMUB_DCN31_FIELDS() \
+	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
+	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
+	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
+	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
+	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET)
+
+struct dmub_srv_dcn31_reg_offset {
+#define DMUB_SR(reg) uint32_t reg;
+	DMUB_DCN31_REGS()
+#undef DMUB_SR
+};
+
+struct dmub_srv_dcn31_reg_shift {
+#define DMUB_SF(reg, field) uint8_t reg##__##field;
+	DMUB_DCN31_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn31_reg_mask {
+#define DMUB_SF(reg, field) uint32_t reg##__##field;
+	DMUB_DCN31_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn31_regs {
+	const struct dmub_srv_dcn31_reg_offset offset;
+	const struct dmub_srv_dcn31_reg_mask mask;
+	const struct dmub_srv_dcn31_reg_shift shift;
+};
+
+extern const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs;
+
+/* Hardware functions. */
+
+
+void dmub_dcn31_init(struct dmub_srv *dmub);
+
+void dmub_dcn31_reset(struct dmub_srv *dmub);
+
+void dmub_dcn31_reset_release(struct dmub_srv *dmub);
+
+void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1);
+
+void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
+			      const struct dmub_window *cw2,
+			      const struct dmub_window *cw3,
+			      const struct dmub_window *cw4,
+			      const struct dmub_window *cw5,
+			      const struct dmub_window *cw6);
+
+void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *inbox1);
+
+uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
+
+void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox1);
+
+uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);
+
+bool dmub_dcn31_is_supported(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
+			  union dmub_gpint_data_register reg);
+
+bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
+			       union dmub_gpint_data_register reg);
+
+uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);
+
+void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
+
+void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
+
+union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);
+
+void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox0);
+
+uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);
+
+#endif /* _DMUB_DCN31_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 1cbb125b4063..fd7e996ab1d7 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -30,6 +30,8 @@
 #include "dmub_dcn30.h"
 #include "dmub_dcn301.h"
 #include "dmub_dcn302.h"
+#include "dmub_dcn303.h"
+#include "dmub_dcn31.h"
 #include "os_types.h"
 /*
  * Note: the DMUB service is standalone. No additional headers should be
@@ -142,6 +144,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 	case DMUB_ASIC_DCN30:
 	case DMUB_ASIC_DCN301:
 	case DMUB_ASIC_DCN302:
+	case DMUB_ASIC_DCN303:
 		dmub->regs = &dmub_srv_dcn20_regs;
 
 		funcs->reset = dmub_dcn20_reset;
@@ -159,6 +162,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 		funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
 		funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
 		funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
+		funcs->get_current_time = dmub_dcn20_get_current_time;
 
 		// Out mailbox register access functions for RN and above
 		funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
@@ -170,6 +174,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 		funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
 		funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
 
+		funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
+
 		if (asic == DMUB_ASIC_DCN21) {
 			dmub->regs = &dmub_srv_dcn21_regs;
 
@@ -193,6 +199,44 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 			funcs->backdoor_load = dmub_dcn30_backdoor_load;
 			funcs->setup_windows = dmub_dcn30_setup_windows;
 		}
+		if (asic == DMUB_ASIC_DCN303) {
+			dmub->regs = &dmub_srv_dcn303_regs;
+
+			funcs->backdoor_load = dmub_dcn30_backdoor_load;
+			funcs->setup_windows = dmub_dcn30_setup_windows;
+		}
+		break;
+
+	case DMUB_ASIC_DCN31:
+		funcs->reset = dmub_dcn31_reset;
+		funcs->reset_release = dmub_dcn31_reset_release;
+		funcs->backdoor_load = dmub_dcn31_backdoor_load;
+		funcs->setup_windows = dmub_dcn31_setup_windows;
+		funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
+		funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
+		funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
+		funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
+		funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
+		funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
+		funcs->is_supported = dmub_dcn31_is_supported;
+		funcs->is_hw_init = dmub_dcn31_is_hw_init;
+		funcs->set_gpint = dmub_dcn31_set_gpint;
+		funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
+		funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
+		funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
+		funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
+		funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
+		//outbox0 call stacks
+		funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
+		funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
+		funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
+
+		if (asic == DMUB_ASIC_DCN31) {
+			dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
+		}
+
+		funcs->get_current_time = dmub_dcn31_get_current_time;
+
 		break;
 
 	default:
@@ -514,6 +558,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
 	dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
 
+	/* Report to DMUB what features are supported by current driver */
+	if (dmub->hw_funcs.enable_dmub_boot_options)
+		dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
+
 	if (dmub->hw_funcs.reset_release)
 		dmub->hw_funcs.reset_release(dmub);
 
@@ -744,3 +792,11 @@ bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entr
 
 	return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
 }
+
+bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
+{
+	if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
+		return false;
+	dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c
index e6f3bfab33d3..70766d534c9c 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c
@@ -35,20 +35,13 @@
  */
 
 /**
- *****************************************************************************
- *  Function: dmub_srv_stat_get_notification
+ * dmub_srv_stat_get_notification - Retrieves a dmub outbox notification, set up dmub notification
+ *                                  structure with message information. Also a pending bit if queue
+ *                                  is having more notifications
+ *  @dmub: dmub srv structure
+ *  @notify: dmub notification structure to be filled up
  *
- *  @brief
- *		Retrieves a dmub outbox notification, set up dmub notification
- *		structure with message information. Also a pending bit if queue
- *		is having more notifications
- *
- *  @param [in] dmub: dmub srv structure
- *  @param [out] pnotify: dmub notification structure to be filled up
- *
- *  @return
- *     dmub_status
- *****************************************************************************
+ *  Returns: dmub_status
  */
 enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,
 						struct dmub_notification *notify)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 24346f1d7dd0..381c17caace1 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -196,6 +196,7 @@ enum {
 	NV_NAVI14_M_A0      = 20,
 	NV_SIENNA_CICHLID_P_A0      = 40,
 	NV_DIMGREY_CAVEFISH_P_A0      = 60,
+	NV_BEIGE_GOBY_P_A0  = 70,
 	NV_UNKNOWN          = 0xFF
 };
 
@@ -204,7 +205,8 @@ enum {
 #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
 #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
 #define ASICREV_IS_SIENNA_CICHLID_P(eChipRev)        ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0))
-#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev)        ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN))
+#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev)        ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_BEIGE_GOBY_P_A0))
+#define ASICREV_IS_BEIGE_GOBY_P(eChipRev)        ((eChipRev >= NV_BEIGE_GOBY_P_A0) && (eChipRev < NV_UNKNOWN))
 #define GREEN_SARDINE_A0 0xA1
 #ifndef ASICREV_IS_GREEN_SARDINE
 #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
@@ -222,6 +224,17 @@ enum {
 #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
 #endif
 
+#define FAMILY_YELLOW_CARP                     146
+
+#define YELLOW_CARP_A0 0x01
+#define YELLOW_CARP_B0 0x02		// TODO: DCN31 - update with correct B0 ID
+#define YELLOW_CARP_UNKNOWN 0xFF
+
+#ifndef ASICREV_IS_YELLOW_CARP
+#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN))
+#endif
+
+
 /*
  * ASIC chip ID
  */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 0d485802a2d0..fe75ec834892 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -54,6 +54,8 @@ enum dce_version {
 	DCN_VERSION_3_0,
 	DCN_VERSION_3_01,
 	DCN_VERSION_3_02,
+	DCN_VERSION_3_03,
+	DCN_VERSION_3_1,
 	DCN_VERSION_MAX
 };
 
diff --git a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
index 9c55d247227e..7e3240e73c1f 100644
--- a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
+++ b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
@@ -42,8 +42,8 @@ void dal_gpio_destroy(
 	struct gpio **ptr);
 
 struct gpio_service *dal_gpio_service_create(
-	enum dce_version dce_version_major,
-	enum dce_version dce_version_minor,
+	enum dce_version dce_version,
+	enum dce_environment dce_environment,
 	struct dc_context *ctx);
 
 struct gpio *dal_gpio_service_create_irq(
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 7392a89e771f..32f5274ed34e 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -68,6 +68,14 @@ enum link_training_result {
 	LINK_TRAINING_LQA_FAIL,
 	/* one of the CR,EQ or symbol lock is dropped */
 	LINK_TRAINING_LINK_LOSS,
+	/* Abort link training (because sink unplugged) */
+	LINK_TRAINING_ABORT,
+};
+
+enum lttpr_mode {
+	LTTPR_MODE_NON_LTTPR,
+	LTTPR_MODE_TRANSPARENT,
+	LTTPR_MODE_NON_TRANSPARENT,
 };
 
 struct link_training_settings {
@@ -77,6 +85,7 @@ struct link_training_settings {
 	enum dc_voltage_swing *voltage_swing;
 	enum dc_pre_emphasis *pre_emphasis;
 	enum dc_post_cursor2 *post_cursor2;
+	bool should_set_fec_ready;
 
 	uint16_t cr_pattern_time;
 	uint16_t eq_pattern_time;
@@ -85,6 +94,7 @@ struct link_training_settings {
 
 	bool enhanced_framing;
 	bool allow_invalid_msa_timing_param;
+	enum lttpr_mode lttpr_mode;
 };
 
 /*TODO: Move this enum test harness*/
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 3f4f44b44e6a..b99aa232bd8b 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -516,7 +516,8 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
 }
 
 static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
-		struct dc_info_packet *infopacket)
+		struct dc_info_packet *infopacket,
+		bool freesync_on_desktop)
 {
 	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
 	infopacket->sb[1] = 0x1A;
@@ -542,10 +543,16 @@ static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
 			vrr->state != VRR_STATE_UNSUPPORTED)
 		infopacket->sb[6] |= 0x02;
 
-	/* PB6 = [Bit 2 = FreeSync Active] */
-	if (vrr->state != VRR_STATE_DISABLED &&
+	if (freesync_on_desktop) {
+		/* PB6 = [Bit 2 = FreeSync Active] */
+		if (vrr->state != VRR_STATE_DISABLED &&
 			vrr->state != VRR_STATE_UNSUPPORTED)
-		infopacket->sb[6] |= 0x04;
+			infopacket->sb[6] |= 0x04;
+	} else {
+		if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+			vrr->state == VRR_STATE_ACTIVE_FIXED)
+			infopacket->sb[6] |= 0x04;
+	}
 
 	// For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range
 	/* PB7 = FreeSync Minimum refresh rate (Hz) */
@@ -824,13 +831,14 @@ static void build_vrr_infopacket_checksum(unsigned int *payload_size,
 
 static void build_vrr_infopacket_v1(enum signal_type signal,
 		const struct mod_vrr_params *vrr,
-		struct dc_info_packet *infopacket)
+		struct dc_info_packet *infopacket,
+		bool freesync_on_desktop)
 {
 	/* SPD info packet for FreeSync */
 	unsigned int payload_size = 0;
 
 	build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
-	build_vrr_infopacket_data_v1(vrr, infopacket);
+	build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
 	build_vrr_infopacket_checksum(&payload_size, infopacket);
 
 	infopacket->valid = true;
@@ -839,12 +847,13 @@ static void build_vrr_infopacket_v1(enum signal_type signal,
 static void build_vrr_infopacket_v2(enum signal_type signal,
 		const struct mod_vrr_params *vrr,
 		enum color_transfer_func app_tf,
-		struct dc_info_packet *infopacket)
+		struct dc_info_packet *infopacket,
+		bool freesync_on_desktop)
 {
 	unsigned int payload_size = 0;
 
 	build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
-	build_vrr_infopacket_data_v1(vrr, infopacket);
+	build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
 
 	build_vrr_infopacket_fs2_data(app_tf, infopacket);
 
@@ -953,12 +962,12 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
 #endif
 		break;
 	case PACKET_TYPE_FS_V2:
-		build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket);
+		build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
 		break;
 	case PACKET_TYPE_VRR:
 	case PACKET_TYPE_FS_V1:
 	default:
-		build_vrr_infopacket_v1(stream->signal, vrr, infopacket);
+		build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);
 	}
 
 	if (true == pack_sdp_v1_3 &&
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index 68a6481d7f8f..b963226e8af4 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -260,7 +260,6 @@ enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp,
 	struct mod_hdcp_output output;
 	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
 
-	memset(hdcp, 0, sizeof(struct mod_hdcp));
 	memset(&output, 0, sizeof(output));
 	hdcp->config = *config;
 	HDCP_TOP_INTERFACE_TRACE(hdcp);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
index 2cbd931363bd..de872e7958b0 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
@@ -29,8 +29,10 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)
 {
 	uint64_t n = 0;
 	uint8_t count = 0;
+	u8 bksv[sizeof(n)] = { };
 
-	memcpy(&n, hdcp->auth.msg.hdcp1.bksv, sizeof(uint64_t));
+	memcpy(bksv, hdcp->auth.msg.hdcp1.bksv, sizeof(hdcp->auth.msg.hdcp1.bksv));
+	n = *(uint64_t *)bksv;
 
 	while (n) {
 		count++;
@@ -128,6 +130,11 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
 
 static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
 {
+	/* Avoid device count == 0 to do authentication */
+	if (0 == get_device_count(hdcp)) {
+		return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;
+	}
+
 	/* Some MST display may choose to report the internal panel as an HDCP RX.
 	 * To update this condition with 1(because the immediate repeater's internal
 	 * panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp).
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
index c1331facdcb4..117c6b45f718 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
@@ -207,6 +207,11 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
 
 static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
 {
+	/* Avoid device count == 0 to do authentication */
+	if (0 == get_device_count(hdcp)) {
+		return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;
+	}
+
 	/* Some MST display may choose to report the internal panel as an HDCP RX.   */
 	/* To update this condition with 1(because the immediate repeater's internal */
 	/* panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp). */
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
index b0306ed6d6b4..70cb230d8f56 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
@@ -564,7 +564,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
 	case D2_A5_AUTHENTICATED:
 		if (input->rxstatus_read == FAIL ||
 				input->reauth_request_check == FAIL) {
-			fail_and_restart_in_ms(0, &status, output);
+			fail_and_restart_in_ms(100, &status, output);
 			break;
 		} else if (input->link_integrity_check_dp == FAIL) {
 			if (hdcp->connection.hdcp2_retry_count >= 1)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
index ee5230ccf3c4..1a0f7c3dc964 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
@@ -172,6 +172,8 @@ char *mod_hdcp_status_to_str(int32_t status)
 		return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE";
 	case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE:
 		return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE";
+	case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE:
+		return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE";
 	default:
 		return "MOD_HDCP_STATUS_UNKNOWN";
 	}
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 26f96c05e0ec..1b02056bc8bd 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -44,11 +44,12 @@ static void hdcp2_message_init(struct mod_hdcp *hdcp,
 	in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
 	in->process.msg3_desc.msg_size = 0;
 }
-enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
+
+static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v2(
 		struct mod_hdcp *hdcp, uint8_t index)
- {
- 	struct psp_context *psp = hdcp->config.psp.handle;
- 	struct ta_dtm_shared_memory *dtm_cmd;
+{
+	struct psp_context *psp = hdcp->config.psp.handle;
+	struct ta_dtm_shared_memory *dtm_cmd;
 	struct mod_hdcp_display *display =
 			get_active_display_at_index(hdcp, index);
 	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
@@ -79,8 +80,61 @@ enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
 	mutex_unlock(&psp->dtm_context.mutex);
 	return status;
 }
-enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
-					       struct mod_hdcp_display *display)
+
+static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v3(
+		struct mod_hdcp *hdcp, uint8_t index)
+{
+	struct psp_context *psp = hdcp->config.psp.handle;
+	struct ta_dtm_shared_memory *dtm_cmd;
+	struct mod_hdcp_display *display =
+		get_active_display_at_index(hdcp, index);
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
+	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
+
+	if (!display || !is_display_active(display))
+		return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
+
+	mutex_lock(&psp->dtm_context.mutex);
+
+	memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
+
+	dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3;
+	dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;
+	dtm_cmd->dtm_in_message.topology_update_v3.is_active = 0;
+	dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
+
+	psp_dtm_invoke(psp, dtm_cmd->cmd_id);
+
+	if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) {
+		status = mod_hdcp_remove_display_from_topology_v2(hdcp, index);
+		if (status != MOD_HDCP_STATUS_SUCCESS)
+			display->state = MOD_HDCP_DISPLAY_INACTIVE;
+	} else {
+		display->state = MOD_HDCP_DISPLAY_ACTIVE;
+		HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);
+	}
+
+	mutex_unlock(&psp->dtm_context.mutex);
+
+	return status;
+}
+
+enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
+		struct mod_hdcp *hdcp, uint8_t index)
+{
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE;
+
+	if (hdcp->config.psp.caps.dtm_v3_supported)
+		status = mod_hdcp_remove_display_from_topology_v3(hdcp, index);
+	else
+		status = mod_hdcp_remove_display_from_topology_v2(hdcp, index);
+
+	return status;
+}
+
+static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v2(
+		struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
 {
 	struct psp_context *psp = hdcp->config.psp.handle;
 	struct ta_dtm_shared_memory *dtm_cmd;
@@ -126,6 +180,71 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
 	return status;
 }
 
+static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v3(
+		struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
+{
+	struct psp_context *psp = hdcp->config.psp.handle;
+	struct ta_dtm_shared_memory *dtm_cmd;
+	struct mod_hdcp_link *link = &hdcp->connection.link;
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
+	if (!psp->dtm_context.dtm_initialized) {
+		DRM_INFO("Failed to add display topology, DTM TA is not initialized.");
+		display->state = MOD_HDCP_DISPLAY_INACTIVE;
+		return MOD_HDCP_STATUS_FAILURE;
+	}
+
+	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
+
+	mutex_lock(&psp->dtm_context.mutex);
+	memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
+
+	dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3;
+	dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;
+	dtm_cmd->dtm_in_message.topology_update_v3.is_active = 1;
+	dtm_cmd->dtm_in_message.topology_update_v3.controller = display->controller;
+	dtm_cmd->dtm_in_message.topology_update_v3.ddc_line = link->ddc_line;
+	dtm_cmd->dtm_in_message.topology_update_v3.link_enc = link->link_enc_idx;
+	dtm_cmd->dtm_in_message.topology_update_v3.stream_enc = display->stream_enc_idx;
+	if (is_dp_hdcp(hdcp))
+		dtm_cmd->dtm_in_message.topology_update_v3.is_assr = link->dp.assr_enabled;
+
+	dtm_cmd->dtm_in_message.topology_update_v3.dp_mst_vcid = display->vc_id;
+	dtm_cmd->dtm_in_message.topology_update_v3.max_hdcp_supported_version =
+			TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_3;
+	dtm_cmd->dtm_in_message.topology_update_v3.encoder_type = TA_DTM_ENCODER_TYPE__DIG;
+	dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
+	dtm_cmd->dtm_in_message.topology_update_v3.phy_id = link->phy_idx;
+	dtm_cmd->dtm_in_message.topology_update_v3.link_hdcp_cap = link->hdcp_supported_informational;
+
+	psp_dtm_invoke(psp, dtm_cmd->cmd_id);
+
+	if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) {
+		status = mod_hdcp_add_display_to_topology_v2(hdcp, display);
+		if (status != MOD_HDCP_STATUS_SUCCESS)
+			display->state = MOD_HDCP_DISPLAY_INACTIVE;
+	} else {
+		HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);
+	}
+
+	mutex_unlock(&psp->dtm_context.mutex);
+
+	return status;
+}
+
+enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
+					       struct mod_hdcp_display *display)
+{
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
+	if (hdcp->config.psp.caps.dtm_v3_supported)
+		status = mod_hdcp_add_display_to_topology_v3(hdcp, display);
+	else
+		status = mod_hdcp_add_display_to_topology_v2(hdcp, display);
+
+	return status;
+}
+
 enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp)
 {
 
@@ -371,19 +490,6 @@ enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp)
 	return status;
 }
 
-enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *hdcp,
-							       enum mod_hdcp_encryption_status *encryption_status)
-{
-	*encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
-
-	if (mod_hdcp_hdcp1_link_maintenance(hdcp) != MOD_HDCP_STATUS_SUCCESS)
-		return MOD_HDCP_STATUS_FAILURE;
-
-	*encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON;
-
-	return MOD_HDCP_STATUS_SUCCESS;
-}
-
 enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)
 {
 	struct psp_context *psp = hdcp->config.psp.handle;
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
index 1a663dbbf810..2937b4b61461 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
@@ -44,7 +44,8 @@ enum bgd_security_hdcp2_content_type {
 enum ta_dtm_command {
 	TA_DTM_COMMAND__UNUSED_1 = 1,
 	TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2,
-	TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE
+	TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE,
+	TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3
 };
 
 /* DTM related enumerations */
@@ -86,6 +87,32 @@ struct ta_dtm_topology_update_input_v2 {
 	uint32_t max_hdcp_supported_version;
 };
 
+/* For security reason/HW may change value, these encoder type enum values are not HW register values */
+/* Security code will check real HW register values and these SW enum values */
+enum ta_dtm_encoder_type {
+	TA_DTM_ENCODER_TYPE__INVALID    = 0,
+	TA_DTM_ENCODER_TYPE__DIG        = 0x10
+};
+
+struct ta_dtm_topology_update_input_v3 {
+	/* display handle is unique across the driver and is used to identify a display */
+	/* for all security interfaces which reference displays such as HDCP */
+	/* link_hdcp_cap means link is HDCP-capable for audio HDCP capable property(informational), not for other logic(e.g. Crossbar) */
+	uint32_t display_handle;
+	uint32_t is_active;
+	uint32_t is_miracast;
+	uint32_t controller;
+	uint32_t ddc_line;
+	uint32_t link_enc;
+	uint32_t stream_enc;
+	uint32_t dp_mst_vcid;
+	uint32_t is_assr;
+	uint32_t max_hdcp_supported_version;
+	enum ta_dtm_encoder_type encoder_type;
+	uint32_t phy_id;
+	uint32_t link_hdcp_cap;
+};
+
 struct ta_dtm_topology_assr_enable {
 	uint32_t display_topology_dig_be_index;
 };
@@ -99,6 +126,7 @@ struct ta_dtm_topology_assr_enable {
 union ta_dtm_cmd_input {
 	struct ta_dtm_topology_update_input_v2 topology_update_v2;
 	struct ta_dtm_topology_assr_enable topology_assr_enable;
+	struct ta_dtm_topology_update_input_v3 topology_update_v3;
 };
 
 union ta_dtm_cmd_output {
@@ -278,7 +306,8 @@ enum ta_hdcp2_version {
 	TA_HDCP2_VERSION_UNKNOWN = 0,
 	TA_HDCP2_VERSION_2_0 = 20,
 	TA_HDCP2_VERSION_2_1 = 21,
-	TA_HDCP2_VERSION_2_2 = 22
+	TA_HDCP2_VERSION_2_2 = 22,
+	TA_HDCP2_VERSION_2_3 = 23,
 };
 
 /* input/output structures for HDCP commands */
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index acbeada5215b..c590493fd293 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -97,6 +97,7 @@ enum mod_hdcp_status {
 	MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST,
 	MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE,
 	MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE,
+	MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE,
 };
 
 struct mod_hdcp_displayport {
@@ -120,6 +121,11 @@ enum mod_hdcp_display_state {
 	MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED
 };
 
+struct mod_hdcp_psp_caps {
+	uint8_t dtm_v3_supported;
+	uint8_t opm_state_query_supported;
+};
+
 enum mod_hdcp_display_disable_option {
 	MOD_HDCP_DISPLAY_NOT_DISABLE = 0,
 	MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION,
@@ -152,6 +158,7 @@ struct mod_hdcp_ddc {
 struct mod_hdcp_psp {
 	void *handle;
 	void *funcs;
+	struct mod_hdcp_psp_caps caps;
 };
 
 struct mod_hdcp_display_adjustment {
@@ -227,6 +234,7 @@ struct mod_hdcp_display {
 	uint8_t index;
 	uint8_t controller;
 	uint8_t dig_fe;
+	uint8_t stream_enc_idx;
 	union {
 		uint8_t vc_id;
 	};
@@ -239,6 +247,9 @@ struct mod_hdcp_link {
 	enum mod_hdcp_operation_mode mode;
 	uint8_t dig_be;
 	uint8_t ddc_line;
+	uint8_t link_enc_idx;
+	uint8_t phy_idx;
+	uint8_t hdcp_supported_informational;
 	union {
 		struct mod_hdcp_displayport dp;
 		struct mod_hdcp_hdmi hdmi;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 6270ecbd2438..2b00f334e93d 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -87,19 +87,19 @@ struct abm_parameters {
 };
 
 static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
-//  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   min_knee  max_knee  blStart  blRed
-	{0xff,   0xbf,    0x20,   0x00,     0xff,        0x99,     0xb3, 0x40,     0xe0,     0xCCCC,  0xCCCC},
-	{0xde,   0x85,    0x20,   0x00,     0xff,        0x90,     0xa8, 0x40,     0xdf,     0xCCCC,  0xCCCC},
-	{0xb0,   0x50,    0x20,   0x00,     0xc0,        0x88,     0x78, 0x70,     0xa0,     0xCCCC,  0xCCCC},
-	{0x82,   0x40,    0x20,   0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xCCCC,  0xCCCC},
+//  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   min_knee  max_knee  blRed    blStart
+	{0xff,   0xbf,    0x20,       0x00,     0xff,        0x99,     0xb3, 0x40,     0xe0,     0xf777,  0xcccc},
+	{0xde,   0x85,    0x20,       0x00,     0xe0,        0x90,     0xa8, 0x40,     0xc8,     0xf777,  0xcccc},
+	{0xb0,   0x50,    0x20,       0x00,     0xc0,        0x88,     0x78, 0x70,     0xa0,     0xeeee,  0x9999},
+	{0x82,   0x40,    0x20,       0x00,     0x00,        0xb8,     0xb3, 0x70,     0x70,     0xe333,  0xb333},
 };
 
 static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
-//  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   min_knee  max_knee  blStart  blRed
-	{0xf0,   0xd9,    0x20,   0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xCCCC,  0xCCCC},
-	{0xcd,   0xa5,    0x20,   0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xCCCC,  0xCCCC},
-	{0x99,   0x65,    0x20,   0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xCCCC,  0xCCCC},
-	{0x82,   0x4d,    0x20,   0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xCCCC,  0xCCCC},
+//  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   min_knee  max_knee  blRed  blStart
+	{0xf0,   0xd9,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
+	{0xcd,   0xa5,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
+	{0x99,   0x65,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
+	{0x82,   0x4d,    0x20,       0x00,     0x00,        0xff,     0xb3, 0x70,     0x70,     0xcccc,  0xcccc},
 };
 
 static const struct abm_parameters * const abm_settings[] = {
@@ -660,7 +660,8 @@ static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram
 }
 
 bool dmub_init_abm_config(struct resource_pool *res_pool,
-	struct dmcu_iram_parameters params)
+	struct dmcu_iram_parameters params,
+	unsigned int inst)
 {
 	struct iram_table_v_2_2 ram_table;
 	struct abm_config_table config;
@@ -669,7 +670,7 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 	uint32_t i, j = 0;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-	if (res_pool->abm == NULL && res_pool->multiple_abms[0] == NULL)
+	if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
 		return false;
 #else
 	if (res_pool->abm == NULL)
@@ -728,13 +729,13 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 	config.min_abm_backlight = ram_table.min_abm_backlight;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-	if (res_pool->multiple_abms[0])
-		result = res_pool->multiple_abms[0]->funcs->init_abm_config(
-			res_pool->multiple_abms[0], (char *)(&config), sizeof(struct abm_config_table));
-	else
+	if (res_pool->multiple_abms[inst]) {
+		result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
+			res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
+	} else
 #endif
 		result = res_pool->abm->funcs->init_abm_config(
-			res_pool->abm, (char *)(&config), sizeof(struct abm_config_table));
+			res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);
 
 	return result;
 }
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 6f2eecce6baa..2a9f8e2d8080 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -49,6 +49,7 @@ struct dmcu_iram_parameters {
 bool dmcu_load_iram(struct dmcu *dmcu,
 		struct dmcu_iram_parameters params);
 bool dmub_init_abm_config(struct resource_pool *res_pool,
-		struct dmcu_iram_parameters params);
+		struct dmcu_iram_parameters params,
+		unsigned int inst);
 
 #endif /* MODULES_POWER_POWER_HELPERS_H_ */
diff --git a/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
index 644ffec2b0ce..cdd426b41c20 100644
--- a/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
+++ b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
@@ -30,7 +30,7 @@ struct IP_BASE_INSTANCE {
 
 struct IP_BASE {
     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
-};
+} __maybe_unused;
 
 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },
                                         { { 0, 0, 0, 0, 0, 0 } },
diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h
index c72cbfe8f684..2d089d30518f 100644
--- a/drivers/gpu/drm/amd/include/amd_acpi.h
+++ b/drivers/gpu/drm/amd/include/amd_acpi.h
@@ -103,6 +103,13 @@ struct atcs_pref_req_output {
 	u8 ret_val;		/* return value */
 } __packed;
 
+struct atcs_pwr_shift_input {
+	u16 size;		/* structure size in bytes (includes size field) */
+	u16 dgpu_id;		/* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
+	u8 dev_acpi_state;	/* D0 = 0, D3 hot = 3 */
+	u8 drv_state;	/* 0 = operational, 1 = not operational */
+} __packed;
+
 /* AMD hw uses four ACPI control methods:
  * 1. ATIF
  * ARG0: (ACPI_INTEGER) function code
@@ -418,6 +425,7 @@ struct atcs_pref_req_output {
 #       define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED             (1 << 1)
 #       define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED       (1 << 2)
 #       define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED                   (1 << 3)
+#       define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED		   (1 << 7)
 #define ATCS_FUNCTION_GET_EXTERNAL_STATE                           0x1
 /* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
  * ARG1: none
@@ -472,4 +480,14 @@ struct atcs_pref_req_output {
  * BYTE  - number of active lanes
  */
 
+#define ATCS_FUNCTION_POWER_SHIFT_CONTROL                          0x8
+/* ARG0: ATCS_FUNCTION_POWER_SHIFT_CONTROL
+ * ARG1:
+ * WORD  - structure size in bytes (includes size field)
+ * WORD  - dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
+ * BYTE  - Device ACPI state
+ * BYTE  - Driver state
+ * OUTPUT: none
+ */
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 9ab706cd07ff..332b0df53e52 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -246,6 +246,7 @@ enum amd_dpm_forced_level;
  * @late_init: sets up late driver/hw state (post hw_init) - Optional
  * @sw_init: sets up driver state, does not configure hw
  * @sw_fini: tears down driver state, does not configure hw
+ * @early_fini: tears down stuff before dev detached from driver
  * @hw_init: sets up the hw state
  * @hw_fini: tears down the hw state
  * @late_fini: final cleanup
@@ -274,6 +275,7 @@ struct amd_ip_funcs {
 	int (*late_init)(void *handle);
 	int (*sw_init)(void *handle);
 	int (*sw_fini)(void *handle);
+	int (*early_fini)(void *handle);
 	int (*hw_init)(void *handle);
 	int (*hw_fini)(void *handle);
 	void (*late_fini)(void *handle);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
index 2a622c13817b..59155007c186 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
@@ -29292,6 +29292,7 @@
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
@@ -34431,6 +34432,7 @@
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h
new file mode 100644
index 000000000000..daa8130636f0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h
@@ -0,0 +1,8427 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef _dcn_3_0_3_OFFSET_HEADER
+#define _dcn_3_0_3_OFFSET_HEADER
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+#define mmVGA_RENDER_CONTROL                                                                           0x0000
+#define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define mmVGA_MODE_CONTROL                                                                             0x0002
+#define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define mmVGA_HDP_CONTROL                                                                              0x000a
+#define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define mmVGA_CACHE_CONTROL                                                                            0x000b
+#define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define mmD1VGA_CONTROL                                                                                0x000c
+#define mmD1VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD2VGA_CONTROL                                                                                0x000e
+#define mmD2VGA_CONTROL_BASE_IDX                                                                       1
+#define mmVGA_STATUS                                                                                   0x0010
+#define mmVGA_STATUS_BASE_IDX                                                                          1
+#define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define mmVGA_STATUS_CLEAR                                                                             0x0012
+#define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define mmVGA_INTERRUPT_STATUS                                                                         0x0013
+#define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define mmVGA_MAIN_CONTROL                                                                             0x0014
+#define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define mmVGA_TEST_CONTROL                                                                             0x0015
+#define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define mmVGA_QOS_CTRL                                                                                 0x0018
+#define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define mmCRTC8_IDX                                                                                    0x002d
+#define mmCRTC8_IDX_BASE_IDX                                                                           1
+#define mmCRTC8_DATA                                                                                   0x002d
+#define mmCRTC8_DATA_BASE_IDX                                                                          1
+#define mmGENFC_WT                                                                                     0x002e
+#define mmGENFC_WT_BASE_IDX                                                                            1
+#define mmGENS1                                                                                        0x002e
+#define mmGENS1_BASE_IDX                                                                               1
+#define mmATTRDW                                                                                       0x0030
+#define mmATTRDW_BASE_IDX                                                                              1
+#define mmATTRX                                                                                        0x0030
+#define mmATTRX_BASE_IDX                                                                               1
+#define mmATTRDR                                                                                       0x0030
+#define mmATTRDR_BASE_IDX                                                                              1
+#define mmGENMO_WT                                                                                     0x0030
+#define mmGENMO_WT_BASE_IDX                                                                            1
+#define mmGENS0                                                                                        0x0030
+#define mmGENS0_BASE_IDX                                                                               1
+#define mmGENENB                                                                                       0x0030
+#define mmGENENB_BASE_IDX                                                                              1
+#define mmSEQ8_IDX                                                                                     0x0031
+#define mmSEQ8_IDX_BASE_IDX                                                                            1
+#define mmSEQ8_DATA                                                                                    0x0031
+#define mmSEQ8_DATA_BASE_IDX                                                                           1
+#define mmDAC_MASK                                                                                     0x0031
+#define mmDAC_MASK_BASE_IDX                                                                            1
+#define mmDAC_R_INDEX                                                                                  0x0031
+#define mmDAC_R_INDEX_BASE_IDX                                                                         1
+#define mmDAC_W_INDEX                                                                                  0x0032
+#define mmDAC_W_INDEX_BASE_IDX                                                                         1
+#define mmDAC_DATA                                                                                     0x0032
+#define mmDAC_DATA_BASE_IDX                                                                            1
+#define mmGENFC_RD                                                                                     0x0032
+#define mmGENFC_RD_BASE_IDX                                                                            1
+#define mmGENMO_RD                                                                                     0x0033
+#define mmGENMO_RD_BASE_IDX                                                                            1
+#define mmGRPH8_IDX                                                                                    0x0033
+#define mmGRPH8_IDX_BASE_IDX                                                                           1
+#define mmGRPH8_DATA                                                                                   0x0033
+#define mmGRPH8_DATA_BASE_IDX                                                                          1
+#define mmCRTC8_IDX_1                                                                                  0x0035
+#define mmCRTC8_IDX_1_BASE_IDX                                                                         1
+#define mmCRTC8_DATA_1                                                                                 0x0035
+#define mmCRTC8_DATA_1_BASE_IDX                                                                        1
+#define mmGENFC_WT_1                                                                                   0x0036
+#define mmGENFC_WT_1_BASE_IDX                                                                          1
+#define mmGENS1_1                                                                                      0x0036
+#define mmGENS1_1_BASE_IDX                                                                             1
+#define mmD3VGA_CONTROL                                                                                0x0038
+#define mmD3VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD4VGA_CONTROL                                                                                0x0039
+#define mmD4VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD5VGA_CONTROL                                                                                0x003a
+#define mmD5VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD6VGA_CONTROL                                                                                0x003b
+#define mmD6VGA_CONTROL_BASE_IDX                                                                       1
+#define mmVGA_SOURCE_SELECT                                                                            0x003c
+#define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define mmDP_DTO_DBUF_EN                                                                               0x0044
+#define mmDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define mmREFCLK_CNTL                                                                                  0x0049
+#define mmREFCLK_CNTL_BASE_IDX                                                                         1
+#define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDCCG_PERFMON_CNTL2                                                                           0x004e
+#define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
+#define mmDCCG_DS_DTO_INCR                                                                             0x0053
+#define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define mmDCCG_DS_DTO_MODULO                                                                           0x0054
+#define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define mmDCCG_DS_CNTL                                                                                 0x0055
+#define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define mmDPREFCLK_CNTL                                                                                0x0058
+#define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define mmDCE_VERSION                                                                                  0x005e
+#define mmDCE_VERSION_BASE_IDX                                                                         1
+#define mmDCCG_GTC_CNTL                                                                                0x0060
+#define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define mmDCCG_GTC_DTO_INCR                                                                            0x0061
+#define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define mmDCCG_GTC_CURRENT                                                                             0x0063
+#define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define mmDSCCLK0_DTO_PARAM                                                                            0x006c
+#define mmDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDSCCLK1_DTO_PARAM                                                                            0x006d
+#define mmDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define mmDCCG_PERFMON_CNTL                                                                            0x0073
+#define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
+#define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define mmSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDCCG_CAC_STATUS                                                                              0x0077
+#define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDCCG_DISP_CNTL_REG                                                                           0x007f
+#define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define mmOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define mmDP_DTO0_PHASE                                                                                0x0081
+#define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define mmDP_DTO0_MODULO                                                                               0x0082
+#define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define mmOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define mmDP_DTO1_PHASE                                                                                0x0085
+#define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define mmDP_DTO1_MODULO                                                                               0x0086
+#define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define mmDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDPPCLK0_DTO_PARAM                                                                            0x0099
+#define mmDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDPPCLK1_DTO_PARAM                                                                            0x009a
+#define mmDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDCCG_CAC_STATUS2                                                                             0x009f
+#define mmDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define mmDCCG_SOFT_RESET                                                                              0x00a6
+#define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define mmDSCCLK_DTO_CTRL                                                                              0x00a7
+#define mmDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDPPCLK_DTO_CTRL                                                                              0x00b6
+#define mmDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define mmDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define mmDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define mmFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define mmFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define mmPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define mmPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+// base address: 0x0
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
+#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
+#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
+#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON0_PERFMON_HI                                                                       0x0007
+#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0008
+#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2f8
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x00be
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x00bf
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x00c0
+#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x00c1
+#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x00c2
+#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x00c3
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x00c4
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON1_PERFMON_HI                                                                       0x00c5
+#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON1_PERFMON_LOW                                                                      0x00c6
+#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define mmCC_DC_PIPE_DIS                                                                               0x00ca
+#define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define mmDMU_CLK_CNTL                                                                                 0x00cb
+#define mmDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
+#define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
+#define mmDMCU_SMU_INTERRUPT_CNTL                                                                      0x00cd
+#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
+#define mmSMU_INTERRUPT_CONTROL                                                                        0x00ce
+#define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
+#define mmDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+// base address: 0x0
+#define mmDMCU_CTRL                                                                                    0x00da
+#define mmDMCU_CTRL_BASE_IDX                                                                           2
+#define mmDMCU_STATUS                                                                                  0x00db
+#define mmDMCU_STATUS_BASE_IDX                                                                         2
+#define mmDMCU_PC_START_ADDR                                                                           0x00dc
+#define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
+#define mmDMCU_FW_START_ADDR                                                                           0x00dd
+#define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
+#define mmDMCU_FW_END_ADDR                                                                             0x00de
+#define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
+#define mmDMCU_FW_ISR_START_ADDR                                                                       0x00df
+#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
+#define mmDMCU_FW_CS_HI                                                                                0x00e0
+#define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
+#define mmDMCU_FW_CS_LO                                                                                0x00e1
+#define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
+#define mmDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
+#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
+#define mmDMCU_ERAM_WR_CTRL                                                                            0x00e3
+#define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_ERAM_WR_DATA                                                                            0x00e4
+#define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
+#define mmDMCU_ERAM_RD_CTRL                                                                            0x00e5
+#define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_ERAM_RD_DATA                                                                            0x00e6
+#define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_WR_CTRL                                                                            0x00e7
+#define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_WR_DATA                                                                            0x00e8
+#define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_RD_CTRL                                                                            0x00e9
+#define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_RD_DATA                                                                            0x00ea
+#define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
+#define mmDMCU_EVENT_TRIGGER                                                                           0x00eb
+#define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
+#define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
+#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
+#define mmDMCU_INTERRUPT_STATUS                                                                        0x00ee
+#define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define mmDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
+#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
+#define mmDC_DMCU_SCRATCH                                                                              0x00f5
+#define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
+#define mmDMCU_INT_CNT                                                                                 0x00f6
+#define mmDMCU_INT_CNT_BASE_IDX                                                                        2
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
+#define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
+#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
+#define mmMASTER_COMM_DATA_REG1                                                                        0x00f9
+#define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
+#define mmMASTER_COMM_DATA_REG2                                                                        0x00fa
+#define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
+#define mmMASTER_COMM_DATA_REG3                                                                        0x00fb
+#define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
+#define mmMASTER_COMM_CMD_REG                                                                          0x00fc
+#define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
+#define mmMASTER_COMM_CNTL_REG                                                                         0x00fd
+#define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
+#define mmSLAVE_COMM_DATA_REG1                                                                         0x00fe
+#define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
+#define mmSLAVE_COMM_DATA_REG2                                                                         0x00ff
+#define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
+#define mmSLAVE_COMM_DATA_REG3                                                                         0x0100
+#define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
+#define mmSLAVE_COMM_CMD_REG                                                                           0x0101
+#define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
+#define mmSLAVE_COMM_CNTL_REG                                                                          0x0102
+#define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
+#define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
+#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
+#define mmDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
+#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
+#define mmDMCU_INT_CNT_CONTINUE                                                                        0x011c
+#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
+#define mmDMCU_INTERRUPT_STATUS_2                                                                      0x011e
+#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define mmDC_GPU_TIMER_READ                                                                            0x0128
+#define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define mmDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define mmDISP_INTERRUPT_STATUS                                                                        0x012a
+#define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define mmDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define mmDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define mmDCCG_INTERRUPT_DEST                                                                          0x0148
+#define mmDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmDMU_INTERRUPT_DEST                                                                           0x0149
+#define mmDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmDMU_INTERRUPT_DEST2                                                                          0x014a
+#define mmDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define mmDCPG_INTERRUPT_DEST                                                                          0x014b
+#define mmDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define mmDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define mmMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define mmWB_INTERRUPT_DEST                                                                            0x014e
+#define mmWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define mmDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define mmDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define mmDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define mmMPC_INTERRUPT_DEST                                                                           0x0153
+#define mmMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmOPP_INTERRUPT_DEST                                                                           0x0154
+#define mmOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmOPTC_INTERRUPT_DEST                                                                          0x0155
+#define mmOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG0_INTERRUPT_DEST                                                                          0x0156
+#define mmOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG1_INTERRUPT_DEST                                                                          0x0157
+#define mmOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG2_INTERRUPT_DEST                                                                          0x0158
+#define mmOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG3_INTERRUPT_DEST                                                                          0x0159
+#define mmOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG4_INTERRUPT_DEST                                                                          0x015a
+#define mmOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG5_INTERRUPT_DEST                                                                          0x015b
+#define mmOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmDIG_INTERRUPT_DEST                                                                           0x015c
+#define mmDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define mmDIO_INTERRUPT_DEST                                                                           0x015f
+#define mmDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmDCIO_INTERRUPT_DEST                                                                          0x0160
+#define mmDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmHPD_INTERRUPT_DEST                                                                           0x0161
+#define mmHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmAZ_INTERRUPT_DEST                                                                            0x0162
+#define mmAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define mmAUX_INTERRUPT_DEST                                                                           0x0163
+#define mmAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmDSC_INTERRUPT_DEST                                                                           0x0164
+#define mmDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_fgsec_dispdec
+// base address: 0x0
+#define mmDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a
+#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define mmRBBMIF_TIMEOUT                                                                               0x017f
+#define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define mmRBBMIF_STATUS                                                                                0x0180
+#define mmRBBMIF_STATUS_BASE_IDX                                                                       2
+#define mmRBBMIF_STATUS_2                                                                              0x0181
+#define mmRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define mmRBBMIF_INT_STATUS                                                                            0x0182
+#define mmRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define mmRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define mmRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define mmRBBMIF_STATUS_FLAG                                                                           0x0185
+#define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define mmDMCUB_REGION0_OFFSET                                                                         0x018e
+#define mmDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION1_OFFSET                                                                         0x0190
+#define mmDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION2_OFFSET                                                                         0x0192
+#define mmDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION4_OFFSET                                                                         0x0196
+#define mmDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION5_OFFSET                                                                         0x0198
+#define mmDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION6_OFFSET                                                                         0x019a
+#define mmDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION7_OFFSET                                                                         0x019c
+#define mmDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define mmDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define mmDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define mmDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define mmDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define mmDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define mmDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define mmDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define mmDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define mmDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define mmDMCUB_SEC_CNTL                                                                               0x01ce
+#define mmDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define mmDMCUB_MEM_CNTL                                                                               0x01cf
+#define mmDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define mmDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define mmDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define mmDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define mmDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define mmDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define mmDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define mmDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define mmDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define mmDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define mmDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define mmDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define mmDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define mmDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define mmDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define mmDMCUB_SCRATCH0                                                                               0x01e3
+#define mmDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH1                                                                               0x01e4
+#define mmDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH2                                                                               0x01e5
+#define mmDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH3                                                                               0x01e6
+#define mmDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH4                                                                               0x01e7
+#define mmDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH5                                                                               0x01e8
+#define mmDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH6                                                                               0x01e9
+#define mmDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH7                                                                               0x01ea
+#define mmDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH8                                                                               0x01eb
+#define mmDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH9                                                                               0x01ec
+#define mmDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH10                                                                              0x01ed
+#define mmDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH11                                                                              0x01ee
+#define mmDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH12                                                                              0x01ef
+#define mmDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH13                                                                              0x01f0
+#define mmDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH14                                                                              0x01f1
+#define mmDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH15                                                                              0x01f2
+#define mmDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define mmDMCUB_CNTL                                                                                   0x01f6
+#define mmDMCUB_CNTL_BASE_IDX                                                                          2
+#define mmDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define mmDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define mmDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define mmDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define mmDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define mmDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define mmDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define mmDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define mmDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define mmDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define mmDMCUB_PROC_ID                                                                                0x01ff
+#define mmDMCUB_PROC_ID_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define mmMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define mmMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_PITCH                                                                            0x0275
+#define mmMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define mmMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define mmMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define mmMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define mmMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define mmMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define mmMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define mmMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI                                                       0x02a7
+#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX                                              2
+#define mmMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define mmMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define mmMCIF_WB_MIN_TTO                                                                              0x02a9
+#define mmMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define mmMCIF_WB_WATERMARK                                                                            0x02ab
+#define mmMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define mmMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define mmMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define mmMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define mmMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define mmMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define mmWBIF_SMU_WM_CONTROL                                                                          0x0333
+#define mmWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
+#define mmWBIF0_MISC_CTRL                                                                              0x0334
+#define mmWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0335
+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0336
+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define mmVGA_SRC_SPLIT_CNTL                                                                           0x033d
+#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define mmMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e
+#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define mmMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f
+#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define mmMMHUBBUB_CLOCK_CNTL                                                                          0x0340
+#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define mmMMHUBBUB_SOFT_RESET                                                                          0x0341
+#define mmMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define mmDMU_IF_ERR_STATUS                                                                            0x0345
+#define mmDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define mmMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346
+#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define mmMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348
+#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define mmMCIF_CONTROL                                                                                 0x034a
+#define mmMCIF_CONTROL_BASE_IDX                                                                        2
+#define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0xd48
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x0352
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x0353
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x0354
+#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x0355
+#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x0356
+#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x0357
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x0358
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON2_PERFMON_HI                                                                       0x0359
+#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON2_PERFMON_LOW                                                                      0x035a
+#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define mmAZ_CLOCK_CNTL                                                                                0x0372
+#define mmAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+// base address: 0xde8
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x037a
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x037b
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x037c
+#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x037d
+#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x037e
+#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x037f
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0380
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON3_PERFMON_HI                                                                       0x0381
+#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON3_PERFMON_LOW                                                                      0x0382
+#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define mmAZALIA_AUDIO_DTO                                                                             0x03c3
+#define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define mmAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define mmAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define mmAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define mmAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define mmAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_RESULT                                                                           0x03e7
+#define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define mmAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_RESULT                                                                           0x03ec
+#define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define mmAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_SDPIF_CFG0                                                                          0x048f
+#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define mmVM_REQUEST_PHYSICAL                                                                          0x0490
+#define mmVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define mmDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0491
+#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define mmDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0492
+#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define mmDCN_VM_FB_LOCATION_BASE                                                                      0x0493
+#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define mmDCN_VM_FB_LOCATION_TOP                                                                       0x0494
+#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define mmDCN_VM_FB_OFFSET                                                                             0x0495
+#define mmDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define mmDCN_VM_AGP_BOT                                                                               0x0496
+#define mmDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define mmDCN_VM_AGP_TOP                                                                               0x0497
+#define mmDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define mmDCN_VM_AGP_BASE                                                                              0x0498
+#define mmDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x0499
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x049a
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x049b
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x04ba
+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x04bb
+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+#define mmDCHUBBUB_SDPIF_CFG1                                                                          0x04bf
+#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define mmDCHUBBUB_SDPIF_CFG2                                                                          0x04c0
+#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04cf
+#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04d0
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04d1
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04d2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04d3
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04d4
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04d5
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04d6
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04d7
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04ef
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04f0
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define mmDCHUBBUB_CRC_CTRL                                                                            0x04f1
+#define mmDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define mmDCHUBBUB_CRC0_VAL_R_G                                                                        0x04f2
+#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define mmDCHUBBUB_CRC0_VAL_B_A                                                                        0x04f3
+#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define mmDCHUBBUB_CRC1_VAL_R_G                                                                        0x04f4
+#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define mmDCHUBBUB_CRC1_VAL_B_A                                                                        0x04f5
+#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x0505
+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define mmDCHUBBUB_ARB_SAT_LEVEL                                                                       0x0506
+#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define mmDCHUBBUB_ARB_QOS_FORCE                                                                       0x0507
+#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x0508
+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x0509
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x050a
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x050b
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x050c
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x050d
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x050e
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050f
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0510
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0511
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x0512
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0513
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0514
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0515
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0516
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0517
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051b
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051c
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x051d
+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x051e
+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x051f
+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define mmSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0520
+#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0521
+#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0522
+#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0523
+#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0524
+#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0525
+#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0526
+#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0527
+#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmVTG0_CONTROL                                                                                 0x0528
+#define mmVTG0_CONTROL_BASE_IDX                                                                        2
+#define mmVTG1_CONTROL                                                                                 0x0529
+#define mmVTG1_CONTROL_BASE_IDX                                                                        2
+#define mmDCHUBBUB_SOFT_RESET                                                                          0x052e
+#define mmDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define mmDCHUBBUB_CLOCK_CNTL                                                                          0x052f
+#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define mmDCFCLK_CNTL                                                                                  0x0530
+#define mmDCFCLK_CNTL_BASE_IDX                                                                         2
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0531
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0532
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define mmDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0533
+#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define mmDCHUBBUB_CTRL_STATUS                                                                         0x0534
+#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053a
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053b
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053c
+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053d
+#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
+#define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053e
+#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x053f
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0540
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0541
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0542
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0543
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0544
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0545
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0546
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define mmFMON_CTRL                                                                                    0x0548
+#define mmFMON_CTRL_BASE_IDX                                                                           2
+#define mmFMON_CTRL_1                                                                                  0x0548
+#define mmFMON_CTRL_1_BASE_IDX                                                                         2
+
+
+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1534
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x054d
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x054e
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x054f
+#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x0550
+#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x0551
+#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0552
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0553
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON4_PERFMON_HI                                                                       0x0554
+#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON4_PERFMON_LOW                                                                      0x0555
+#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define mmDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define mmDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define mmDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define mmDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define mmDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define mmDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define mmDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define mmDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define mmHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define mmHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define mmHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define mmHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define mmHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define mmHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define mmHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define mmHUBP0_HUBPREQ_DEBUG_DB 								       0x05f6
+#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX							       2
+#define mmHUBP0_HUBPREQ_DEBUG 									       0x05f7
+#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX								       2
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define mmHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define mmHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0629
+#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062a
+#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062b
+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062c
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062d
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062e
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062f
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0630
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0631
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0632
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0633
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0634
+#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0635
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0636
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0643
+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define mmHUBPREQ0_BLANK_OFFSET_0                                                                      0x0644
+#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define mmHUBPREQ0_BLANK_OFFSET_1                                                                      0x0645
+#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define mmHUBPREQ0_DST_DIMENSIONS                                                                      0x0646
+#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define mmHUBPREQ0_DST_AFTER_SCALER                                                                    0x0647
+#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define mmHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0648
+#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define mmHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0649
+#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064a
+#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064b
+#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064c
+#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064d
+#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064e
+#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define mmHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064f
+#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0650
+#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0651
+#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define mmHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0652
+#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0653
+#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0654
+#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0655
+#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0656
+#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0657
+#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0658
+#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0659
+#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065a
+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define mmHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065b
+#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define mmHUBPREQ0_CURSOR_SETTINGS                                                                     0x065c
+#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065d
+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065e
+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065f
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0660
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0663
+#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0664
+#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define mmHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0665
+#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0666
+#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0667
+#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0668
+#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define mmHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define mmHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define mmHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define mmHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define mmCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define mmCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define mmCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define mmCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define mmCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define mmCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define mmCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define mmCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define mmCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define mmCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a74
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x069d
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x069e
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x069f
+#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x06a0
+#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x06a1
+#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x06a2
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x06a3
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON5_PERFMON_HI                                                                       0x06a4
+#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON5_PERFMON_LOW                                                                      0x06a5
+#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define mmHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define mmHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define mmHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define mmHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define mmHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define mmHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define mmHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define mmHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
+#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define mmHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
+#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define mmHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define mmHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0705
+#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0706
+#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0707
+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0708
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0709
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070a
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070b
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070c
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070d
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070e
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070f
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x0710
+#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0711
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0712
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071f
+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define mmHUBPREQ1_BLANK_OFFSET_0                                                                      0x0720
+#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define mmHUBPREQ1_BLANK_OFFSET_1                                                                      0x0721
+#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define mmHUBPREQ1_DST_DIMENSIONS                                                                      0x0722
+#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define mmHUBPREQ1_DST_AFTER_SCALER                                                                    0x0723
+#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define mmHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0724
+#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define mmHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0725
+#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0726
+#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0727
+#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0728
+#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0729
+#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072a
+#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define mmHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072b
+#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072c
+#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072d
+#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define mmHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072e
+#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072f
+#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0730
+#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0731
+#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0732
+#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0733
+#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0734
+#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0735
+#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0736
+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define mmHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0737
+#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define mmHUBPREQ1_CURSOR_SETTINGS                                                                     0x0738
+#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0739
+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073a
+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073b
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073c
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073f
+#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0740
+#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define mmHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0741
+#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0742
+#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0743
+#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0744
+#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define mmHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define mmHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define mmHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define mmHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define mmCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define mmCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define mmCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define mmCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define mmCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define mmCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define mmCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define mmCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define mmCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define mmCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1de4
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x0779
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x077a
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x077b
+#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x077c
+#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x077d
+#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x077e
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x077f
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON6_PERFMON_HI                                                                       0x0780
+#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON6_PERFMON_LOW                                                                      0x0781
+#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define mmDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define mmDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define mmDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define mmCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define mmCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define mmCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define mmCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define mmCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define mmCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define mmCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define mmCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define mmCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define mmCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define mmCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define mmCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define mmCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define mmCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define mmDSCL0_SCL_MODE                                                                               0x0cfb
+#define mmDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define mmDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define mmDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define mmDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define mmDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define mmDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define mmDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define mmDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define mmDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define mmDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define mmDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define mmDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define mmDSCL0_RECOUT_START                                                                           0x0d11
+#define mmDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define mmDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define mmDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define mmDSCL0_MPC_SIZE                                                                               0x0d13
+#define mmDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define mmDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define mmDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define mmDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define mmDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define mmDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define mmDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define mmDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define mmCM0_CM_CONTROL                                                                               0x0d20
+#define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define mmCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define mmCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define mmCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define mmCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define mmCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define mmCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define mmCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define mmCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_CONTROL                                                                       0x0d87
+#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define mmCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d88
+#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define mmCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d89
+#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define mmCM0_CM_BLNDGAM_LUT_CONTROL                                                                   0x0d8a
+#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d8b
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d8c
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d8d
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0d8e
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0d8f
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0d90
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0d91
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0d92
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0d93
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d94
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d95
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d96
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d97
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d98
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d99
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0d9a
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0d9b
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0d9c
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d9d
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d9e
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d9f
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0da0
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0da1
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0da2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0da3
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0da4
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0da5
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0da6
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0da7
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0da8
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0da9
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0daa
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0dab
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0dac
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0dad
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0dae
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0daf
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0db0
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0db1
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0db2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0db3
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0db4
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0db5
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0db6
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0db7
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0db8
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0db9
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0dba
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0dbb
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0dbc
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0dbd
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0dbe
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0dbf
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0dc0
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0dc1
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0dc2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0dc3
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0dc4
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0dc5
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0dc6
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0dc7
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0dc8
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0dc9
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0dca
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0dcb
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0dcc
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0dcd
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0dce
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0dcf
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0dd0
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define mmCM0_CM_HDR_MULT_COEF                                                                         0x0dd1
+#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0dd2
+#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0dd3
+#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define mmCM0_CM_DEALPHA                                                                               0x0dd5
+#define mmCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define mmCM0_CM_COEF_FORMAT                                                                           0x0dd6
+#define mmCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define mmCM0_CM_SHAPER_CONTROL                                                                        0x0dd7
+#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define mmCM0_CM_SHAPER_OFFSET_R                                                                       0x0dd8
+#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_OFFSET_G                                                                       0x0dd9
+#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_OFFSET_B                                                                       0x0dda
+#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_SCALE_R                                                                        0x0ddb
+#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define mmCM0_CM_SHAPER_SCALE_G_B                                                                      0x0ddc
+#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define mmCM0_CM_SHAPER_LUT_INDEX                                                                      0x0ddd
+#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM0_CM_SHAPER_LUT_DATA                                                                       0x0dde
+#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0ddf
+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0de0
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0de1
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0de2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0de3
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0de4
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0de5
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0de6
+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0de7
+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0de8
+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0de9
+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dea
+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0deb
+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dec
+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0ded
+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dee
+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0def
+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0df0
+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0df1
+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0df2
+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0df3
+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0df4
+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0df5
+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0df6
+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0df7
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0df8
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0df9
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dfa
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dfb
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dfc
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dfd
+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dfe
+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dff
+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0e00
+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0e01
+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0e02
+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0e03
+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0e04
+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0e05
+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0e06
+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0e07
+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0e08
+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0e09
+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0e0a
+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0e0b
+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0e0c
+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0e0d
+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_MEM_PWR_CTRL2                                                                         0x0e0e
+#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define mmCM0_CM_MEM_PWR_STATUS2                                                                       0x0e0f
+#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define mmCM0_CM_3DLUT_MODE                                                                            0x0e10
+#define mmCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define mmCM0_CM_3DLUT_INDEX                                                                           0x0e11
+#define mmCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define mmCM0_CM_3DLUT_DATA                                                                            0x0e12
+#define mmCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define mmCM0_CM_3DLUT_DATA_30BIT                                                                      0x0e13
+#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0e14
+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0e15
+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0e16
+#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0e17
+#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18
+#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3890
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x0e24
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x0e25
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x0e26
+#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x0e27
+#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x0e28
+#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x0e29
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x0e2a
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON7_PERFMON_HI                                                                       0x0e2b
+#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON7_PERFMON_LOW                                                                      0x0e2c
+#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define mmDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define mmDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define mmCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define mmCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define mmCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define mmCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define mmCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define mmCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define mmCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define mmCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define mmCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define mmCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define mmCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define mmCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define mmCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define mmDSCL1_SCL_MODE                                                                               0x0e66
+#define mmDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define mmDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define mmDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define mmDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define mmDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define mmDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define mmDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define mmDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define mmDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define mmDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define mmDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define mmDSCL1_RECOUT_START                                                                           0x0e7c
+#define mmDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define mmDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define mmDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define mmDSCL1_MPC_SIZE                                                                               0x0e7e
+#define mmDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define mmDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define mmDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define mmDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define mmDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define mmDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define mmDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define mmCM1_CM_CONTROL                                                                               0x0e8b
+#define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define mmCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define mmCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define mmCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define mmCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define mmCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define mmCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define mmCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define mmCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_CONTROL                                                                       0x0ef2
+#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define mmCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ef3
+#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define mmCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ef4
+#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define mmCM1_CM_BLNDGAM_LUT_CONTROL                                                                   0x0ef5
+#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ef6
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ef7
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ef8
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0ef9
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0efa
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0efb
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0efc
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0efd
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0efe
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0eff
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0f00
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0f01
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0f02
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0f03
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0f04
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0f05
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0f06
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0f07
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0f08
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0f09
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0f0a
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0f0b
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0f0c
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0f0d
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0f0e
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0f0f
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0f10
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0f11
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0f12
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0f13
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0f14
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0f15
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0f16
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0f17
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0f18
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0f19
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0f1a
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0f1b
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0f1c
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0f1d
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0f1e
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0f1f
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0f20
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0f21
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0f22
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0f23
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0f24
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0f25
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0f26
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0f27
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0f28
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0f29
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0f2a
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0f2b
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0f2c
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0f2d
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0f2e
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0f2f
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f30
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f31
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f32
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f33
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f34
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f35
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f36
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f37
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f38
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f39
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f3a
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f3b
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define mmCM1_CM_HDR_MULT_COEF                                                                         0x0f3c
+#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define mmCM1_CM_MEM_PWR_CTRL                                                                          0x0f3d
+#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f3e
+#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define mmCM1_CM_DEALPHA                                                                               0x0f40
+#define mmCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define mmCM1_CM_COEF_FORMAT                                                                           0x0f41
+#define mmCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define mmCM1_CM_SHAPER_CONTROL                                                                        0x0f42
+#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define mmCM1_CM_SHAPER_OFFSET_R                                                                       0x0f43
+#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_OFFSET_G                                                                       0x0f44
+#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_OFFSET_B                                                                       0x0f45
+#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_SCALE_R                                                                        0x0f46
+#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define mmCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f47
+#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define mmCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f48
+#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM1_CM_SHAPER_LUT_DATA                                                                       0x0f49
+#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f4a
+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f4b
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f4c
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f4d
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f4e
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f4f
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f50
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f51
+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f52
+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f53
+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f54
+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f55
+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f56
+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f57
+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f58
+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f59
+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f5a
+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f5b
+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f5c
+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f5d
+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f5e
+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f5f
+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f60
+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f61
+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f62
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f63
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f64
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f65
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f66
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f67
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f68
+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f69
+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f6a
+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f6b
+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f6c
+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f6d
+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f6e
+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f6f
+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f70
+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f71
+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f72
+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f73
+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f74
+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f75
+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f76
+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f77
+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f78
+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_MEM_PWR_CTRL2                                                                         0x0f79
+#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f7a
+#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define mmCM1_CM_3DLUT_MODE                                                                            0x0f7b
+#define mmCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define mmCM1_CM_3DLUT_INDEX                                                                           0x0f7c
+#define mmCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define mmCM1_CM_3DLUT_DATA                                                                            0x0f7d
+#define mmCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define mmCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f7e
+#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f7f
+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f80
+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f81
+#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f82
+#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83
+#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3e3c
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0f8f
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x0f90
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x0f91
+#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x0f92
+#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x0f93
+#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x0f94
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x0f95
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON8_PERFMON_HI                                                                       0x0f96
+#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON8_PERFMON_LOW                                                                      0x0f97
+#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define mmFMT0_FMT_CONTROL                                                                             0x1840
+#define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define mmFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define mmFMT0_FMT_422_CONTROL                                                                         0x1849
+#define mmFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define mmDPG0_DPG_CONTROL                                                                             0x1854
+#define mmDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define mmDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define mmDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define mmDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define mmDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define mmDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define mmDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define mmDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define mmDPG0_DPG_STATUS                                                                              0x185b
+#define mmDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define mmOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define mmOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define mmOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define mmFMT1_FMT_CONTROL                                                                             0x189a
+#define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define mmFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define mmFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define mmFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define mmDPG1_DPG_CONTROL                                                                             0x18ae
+#define mmDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define mmDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define mmDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define mmDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define mmDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define mmDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define mmDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define mmDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define mmDPG1_DPG_STATUS                                                                              0x18b5
+#define mmDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define mmOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define mmOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define mmOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define mmOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define mmOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define mmOPP_ABM_CONTROL                                                                              0x1a60
+#define mmOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x6af8
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x1abe
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x1abf
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x1ac0
+#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x1ac1
+#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x1ac2
+#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x1ac3
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x1ac4
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON9_PERFMON_HI                                                                       0x1ac5
+#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON9_PERFMON_LOW                                                                      0x1ac6
+#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+// base address: 0x0
+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define mmODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define mmODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define mmODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define mmODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define mmODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define mmODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+// base address: 0x40
+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define mmODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define mmODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define mmODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define mmODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define mmODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define mmODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+// base address: 0x0
+#define mmOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define mmOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define mmOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define mmOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define mmOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define mmOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define mmOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define mmOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define mmOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define mmOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define mmOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define mmOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define mmOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define mmOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define mmOTG0_OTG_CONTROL                                                                             0x1b41
+#define mmOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define mmOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define mmOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define mmOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define mmOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define mmOTG0_OTG_STATUS                                                                              0x1b49
+#define mmOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define mmOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define mmOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define mmOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define mmOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define mmOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define mmOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define mmOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define mmOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define mmOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define mmOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define mmOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define mmOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define mmOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define mmOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define mmOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define mmOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define mmOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define mmOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define mmOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define mmOTG0_OTG_BLANK_DATA_COLOR                                                                    0x1b5e
+#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT                                                                0x1b5f
+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define mmOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define mmOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define mmOTG0_OTG_CRC_CNTL2                                                                           0x1b69
+#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
+#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
+#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
+#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
+#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
+#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
+#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
+#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
+#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define mmOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
+#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define mmOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
+#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define mmOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
+#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define mmOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
+#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define mmOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
+#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define mmOTG0_OTG_VREADY_PARAM                                                                        0x1b89
+#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define mmOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
+#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define mmOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
+#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define mmOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
+#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define mmOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
+#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define mmOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
+#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
+#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
+#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
+#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
+#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b94
+#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b95
+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b96
+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define mmOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b97
+#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b98
+#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b99
+#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define mmOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b9a
+#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define mmOTG0_OTG_DRR_CONTROL                                                                         0x1b9b
+#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define mmOTG0_OTG_M_CONST_DTO0                                                                        0x1b9c
+#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define mmOTG0_OTG_M_CONST_DTO1                                                                        0x1b9d
+#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define mmOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9e
+#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define mmOTG0_OTG_DSC_START_POSITION                                                                  0x1b9f
+#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define mmOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1ba0
+#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define mmOTG0_OTG_SPARE_REGISTER                                                                      0x1ba2
+#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+// base address: 0x200
+#define mmOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define mmOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define mmOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define mmOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define mmOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define mmOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define mmOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define mmOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define mmOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define mmOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define mmOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define mmOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define mmOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define mmOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define mmOTG1_OTG_CONTROL                                                                             0x1bc1
+#define mmOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define mmOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define mmOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define mmOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define mmOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define mmOTG1_OTG_STATUS                                                                              0x1bc9
+#define mmOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define mmOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define mmOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define mmOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define mmOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define mmOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define mmOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define mmOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define mmOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define mmOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define mmOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define mmOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define mmOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define mmOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define mmOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define mmOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define mmOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define mmOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define mmOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define mmOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define mmOTG1_OTG_BLANK_DATA_COLOR                                                                    0x1bde
+#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT                                                                0x1bdf
+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define mmOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define mmOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define mmOTG1_OTG_CRC_CNTL2                                                                           0x1be9
+#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
+#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
+#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
+#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
+#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
+#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
+#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
+#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
+#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define mmOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
+#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define mmOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
+#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define mmOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
+#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define mmOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
+#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define mmOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
+#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define mmOTG1_OTG_VREADY_PARAM                                                                        0x1c09
+#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define mmOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
+#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define mmOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
+#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define mmOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
+#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define mmOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
+#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define mmOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
+#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
+#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
+#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
+#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
+#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c14
+#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c15
+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c16
+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define mmOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c17
+#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c18
+#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c19
+#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define mmOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c1a
+#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define mmOTG1_OTG_DRR_CONTROL                                                                         0x1c1b
+#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define mmOTG1_OTG_M_CONST_DTO0                                                                        0x1c1c
+#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define mmOTG1_OTG_M_CONST_DTO1                                                                        0x1c1d
+#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define mmOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1e
+#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define mmOTG1_OTG_DSC_START_POSITION                                                                  0x1c1f
+#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define mmOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c20
+#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define mmOTG1_OTG_SPARE_REGISTER                                                                      0x1c22
+#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define mmDWB_SOURCE_SELECT                                                                            0x1e2a
+#define mmDWB_SOURCE_SELECT_BASE_IDX                                                                   2
+#define mmGSL_SOURCE_SELECT                                                                            0x1e2b
+#define mmGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define mmOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define mmOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define mmODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define mmODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define mmODM_MEM_PWR_CTRL2                                                                            0x1e2e
+#define mmODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define mmODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define mmODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define mmODM_MEM_PWR_STATUS                                                                           0x1e30
+#define mmODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define mmOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x79a8
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x1e6a
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x1e6b
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x1e6c
+#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x1e6d
+#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x1e6e
+#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x1e70
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON10_PERFMON_HI                                                                      0x1e71
+#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON10_PERFMON_LOW                                                                     0x1e72
+#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define mmDC_I2C_CONTROL                                                                               0x1e98
+#define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define mmDC_I2C_ARBITRATION                                                                           0x1e99
+#define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define mmDC_I2C_SW_STATUS                                                                             0x1e9b
+#define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define mmDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define mmDC_I2C_TRANSACTION0                                                                          0x1eae
+#define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define mmDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define mmDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define mmDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define mmDC_I2C_DATA                                                                                  0x1eb2
+#define mmDC_I2C_DATA_BASE_IDX                                                                         2
+#define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define mmDIO_SCRATCH0                                                                                 0x1eca
+#define mmDIO_SCRATCH0_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH1                                                                                 0x1ecb
+#define mmDIO_SCRATCH1_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH2                                                                                 0x1ecc
+#define mmDIO_SCRATCH2_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH3                                                                                 0x1ecd
+#define mmDIO_SCRATCH3_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH4                                                                                 0x1ece
+#define mmDIO_SCRATCH4_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH5                                                                                 0x1ecf
+#define mmDIO_SCRATCH5_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH6                                                                                 0x1ed0
+#define mmDIO_SCRATCH6_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH7                                                                                 0x1ed1
+#define mmDIO_SCRATCH7_BASE_IDX                                                                        2
+#define mmDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define mmDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define mmDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define mmDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define mmDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define mmDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define mmDIO_CLK_CNTL                                                                                 0x1ee0
+#define mmDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define mmDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define mmDIG_SOFT_RESET                                                                               0x1eee
+#define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define mmDIO_CLK_CNTL2                                                                                0x1ef2
+#define mmDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define mmDIO_CLK_CNTL3                                                                                0x1ef3
+#define mmDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define mmDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
+#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
+#define mmDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
+#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define mmHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define mmHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+// base address: 0x7d10
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x1f44
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x1f45
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x1f46
+#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x1f47
+#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x1f48
+#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x1f49
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x1f4a
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON11_PERFMON_HI                                                                      0x1f4b
+#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON11_PERFMON_LOW                                                                     0x1f4c
+#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define mmDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define mmDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define mmDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define mmVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define mmVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define mmVPG0_VPG_MEM_PWR                                                                             0x206d
+#define mmVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define mmVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define mmVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define mmVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define mmAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define mmAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define mmAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define mmAFMT0_AFMT_60958_0                                                                           0x2078
+#define mmAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define mmAFMT0_AFMT_60958_1                                                                           0x2079
+#define mmAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_60958_2                                                                           0x207f
+#define mmAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define mmAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define mmAFMT0_AFMT_STATUS                                                                            0x2081
+#define mmAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define mmAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define mmAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define mmDME0_DME_CONTROL                                                                             0x2089
+#define mmDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define mmDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+// base address: 0x0
+#define mmDIG0_DIG_FE_CNTL                                                                             0x208b
+#define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define mmDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define mmDIG0_DIG_FIFO_STATUS                                                                         0x2091
+#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2092
+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define mmDIG0_HDMI_CONTROL                                                                            0x2093
+#define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define mmDIG0_HDMI_STATUS                                                                             0x2094
+#define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2095
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2096
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2097
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2098
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2099
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209a
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209b
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209c
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GC                                                                                 0x209d
+#define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209e
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x209f
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a0
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a1
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a3
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a4
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a5
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define mmDIG0_HDMI_DB_CONTROL                                                                         0x20a6
+#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define mmDIG0_HDMI_ACR_32_0                                                                           0x20a7
+#define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_32_1                                                                           0x20a8
+#define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_44_0                                                                           0x20a9
+#define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_44_1                                                                           0x20aa
+#define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_48_0                                                                           0x20ab
+#define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_48_1                                                                           0x20ac
+#define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x20ad
+#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x20ae
+#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define mmDIG0_AFMT_CNTL                                                                               0x20af
+#define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define mmDIG0_DIG_BE_CNTL                                                                             0x20b0
+#define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define mmDIG0_DIG_BE_EN_CNTL                                                                          0x20b1
+#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define mmDIG0_TMDS_CNTL                                                                               0x20d7
+#define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d8
+#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d9
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20da
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20db
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dc
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define mmDIG0_TMDS_CTL_BITS                                                                           0x20de
+#define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20df
+#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e0
+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e1
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e2
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define mmDIG0_DIG_VERSION                                                                             0x20e4
+#define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define mmDIG0_DIG_LANE_ENABLE                                                                         0x20e5
+#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
+#define mmDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
+#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+// base address: 0x0
+#define mmDP0_DP_LINK_CNTL                                                                             0x2108
+#define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define mmDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define mmDP0_DP_CONFIG                                                                                0x210b
+#define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define mmDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_STEER_FIFO                                                                            0x210d
+#define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define mmDP0_DP_MSA_MISC                                                                              0x210e
+#define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define mmDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define mmDP0_DP_VID_TIMING                                                                            0x2110
+#define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define mmDP0_DP_VID_N                                                                                 0x2111
+#define mmDP0_DP_VID_N_BASE_IDX                                                                        2
+#define mmDP0_DP_VID_M                                                                                 0x2112
+#define mmDP0_DP_VID_M_BASE_IDX                                                                        2
+#define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define mmDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define mmDP0_DP_DPHY_CNTL                                                                             0x2117
+#define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define mmDP0_DP_DPHY_SYM0                                                                             0x2119
+#define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_SYM1                                                                             0x211a
+#define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_SYM2                                                                             0x211b
+#define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define mmDP0_DP_SEC_CNTL                                                                              0x212b
+#define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define mmDP0_DP_SEC_CNTL1                                                                             0x212c
+#define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_AUD_N                                                                             0x2131
+#define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define mmDP0_DP_SEC_AUD_M                                                                             0x2133
+#define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define mmDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_SAT0                                                                              0x213a
+#define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define mmDP0_DP_MSE_SAT1                                                                              0x213b
+#define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define mmDP0_DP_MSE_SAT2                                                                              0x213c
+#define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define mmDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define mmDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define mmDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define mmDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define mmDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define mmDP0_DP_MSO_CNTL                                                                              0x2150
+#define mmDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define mmDP0_DP_MSO_CNTL1                                                                             0x2151
+#define mmDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define mmDP0_DP_DSC_CNTL                                                                              0x2152
+#define mmDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define mmDP0_DP_SEC_CNTL2                                                                             0x2153
+#define mmDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL3                                                                             0x2154
+#define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL4                                                                             0x2155
+#define mmDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL5                                                                             0x2156
+#define mmDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL6                                                                             0x2157
+#define mmDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL7                                                                             0x2158
+#define mmDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define mmDP0_DP_DB_CNTL                                                                               0x2159
+#define mmDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define mmDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define mmDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define mmDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
+#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define mmDP0_DP_ALPM_CNTL                                                                             0x215d
+#define mmDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_GSP8_CNTL                                                                             0x215e
+#define mmDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_GSP9_CNTL                                                                             0x215f
+#define mmDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_GSP10_CNTL                                                                            0x2160
+#define mmDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define mmDP0_DP_GSP11_CNTL                                                                            0x2161
+#define mmDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define mmDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define mmVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define mmVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define mmVPG1_VPG_MEM_PWR                                                                             0x216d
+#define mmVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define mmVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define mmVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define mmVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define mmAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define mmAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define mmAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define mmAFMT1_AFMT_60958_0                                                                           0x2178
+#define mmAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define mmAFMT1_AFMT_60958_1                                                                           0x2179
+#define mmAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_60958_2                                                                           0x217f
+#define mmAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define mmAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define mmAFMT1_AFMT_STATUS                                                                            0x2181
+#define mmAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define mmAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define mmAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define mmDME1_DME_CONTROL                                                                             0x2189
+#define mmDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define mmDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+// base address: 0x400
+#define mmDIG1_DIG_FE_CNTL                                                                             0x218b
+#define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define mmDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define mmDIG1_DIG_FIFO_STATUS                                                                         0x2191
+#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2192
+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define mmDIG1_HDMI_CONTROL                                                                            0x2193
+#define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define mmDIG1_HDMI_STATUS                                                                             0x2194
+#define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2195
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2196
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2197
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2198
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2199
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219a
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219b
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219c
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GC                                                                                 0x219d
+#define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219e
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x219f
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a0
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a1
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a3
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a4
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a5
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define mmDIG1_HDMI_DB_CONTROL                                                                         0x21a6
+#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define mmDIG1_HDMI_ACR_32_0                                                                           0x21a7
+#define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_32_1                                                                           0x21a8
+#define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_44_0                                                                           0x21a9
+#define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_44_1                                                                           0x21aa
+#define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_48_0                                                                           0x21ab
+#define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_48_1                                                                           0x21ac
+#define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x21ad
+#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x21ae
+#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define mmDIG1_AFMT_CNTL                                                                               0x21af
+#define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define mmDIG1_DIG_BE_CNTL                                                                             0x21b0
+#define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define mmDIG1_DIG_BE_EN_CNTL                                                                          0x21b1
+#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define mmDIG1_TMDS_CNTL                                                                               0x21d7
+#define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x21d8
+#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d9
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21da
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21db
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dc
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define mmDIG1_TMDS_CTL_BITS                                                                           0x21de
+#define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21df
+#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e0
+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e1
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e2
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define mmDIG1_DIG_VERSION                                                                             0x21e4
+#define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define mmDIG1_DIG_LANE_ENABLE                                                                         0x21e5
+#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
+#define mmDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
+#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+// base address: 0x400
+#define mmDP1_DP_LINK_CNTL                                                                             0x2208
+#define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define mmDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define mmDP1_DP_CONFIG                                                                                0x220b
+#define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define mmDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_STEER_FIFO                                                                            0x220d
+#define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define mmDP1_DP_MSA_MISC                                                                              0x220e
+#define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define mmDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define mmDP1_DP_VID_TIMING                                                                            0x2210
+#define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define mmDP1_DP_VID_N                                                                                 0x2211
+#define mmDP1_DP_VID_N_BASE_IDX                                                                        2
+#define mmDP1_DP_VID_M                                                                                 0x2212
+#define mmDP1_DP_VID_M_BASE_IDX                                                                        2
+#define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define mmDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define mmDP1_DP_DPHY_CNTL                                                                             0x2217
+#define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define mmDP1_DP_DPHY_SYM0                                                                             0x2219
+#define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_SYM1                                                                             0x221a
+#define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_SYM2                                                                             0x221b
+#define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define mmDP1_DP_SEC_CNTL                                                                              0x222b
+#define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define mmDP1_DP_SEC_CNTL1                                                                             0x222c
+#define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_AUD_N                                                                             0x2231
+#define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define mmDP1_DP_SEC_AUD_M                                                                             0x2233
+#define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define mmDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_SAT0                                                                              0x223a
+#define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define mmDP1_DP_MSE_SAT1                                                                              0x223b
+#define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define mmDP1_DP_MSE_SAT2                                                                              0x223c
+#define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define mmDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define mmDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define mmDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define mmDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define mmDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define mmDP1_DP_MSO_CNTL                                                                              0x2250
+#define mmDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define mmDP1_DP_MSO_CNTL1                                                                             0x2251
+#define mmDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define mmDP1_DP_DSC_CNTL                                                                              0x2252
+#define mmDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define mmDP1_DP_SEC_CNTL2                                                                             0x2253
+#define mmDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL3                                                                             0x2254
+#define mmDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL4                                                                             0x2255
+#define mmDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL5                                                                             0x2256
+#define mmDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL6                                                                             0x2257
+#define mmDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL7                                                                             0x2258
+#define mmDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define mmDP1_DP_DB_CNTL                                                                               0x2259
+#define mmDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define mmDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define mmDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define mmDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
+#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define mmDP1_DP_ALPM_CNTL                                                                             0x225d
+#define mmDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_GSP8_CNTL                                                                             0x225e
+#define mmDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_GSP9_CNTL                                                                             0x225f
+#define mmDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_GSP10_CNTL                                                                            0x2260
+#define mmDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define mmDP1_DP_GSP11_CNTL                                                                            0x2261
+#define mmDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define mmDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define mmDC_GENERICA                                                                                  0x2868
+#define mmDC_GENERICA_BASE_IDX                                                                         2
+#define mmDC_GENERICB                                                                                  0x2869
+#define mmDC_GENERICB_BASE_IDX                                                                         2
+#define mmDCIO_CLOCK_CNTL                                                                              0x286a
+#define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define mmDC_REF_CLK_CNTL                                                                              0x286b
+#define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define mmUNIPHYA_LINK_CNTL                                                                            0x286d
+#define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define mmUNIPHYB_LINK_CNTL                                                                            0x286f
+#define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define mmDCIO_WRCMD_DELAY                                                                             0x287e
+#define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define mmDC_PINSTRAPS                                                                                 0x2880
+#define mmDC_PINSTRAPS_BASE_IDX                                                                        2
+#define mmLVTMA_PWRSEQ_CNTL                                                                            0x2883
+#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX                                                                   2
+#define mmLVTMA_PWRSEQ_STATE                                                                           0x2884
+#define mmLVTMA_PWRSEQ_STATE_BASE_IDX                                                                  2
+#define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885
+#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
+#define mmLVTMA_PWRSEQ_DELAY1                                                                          0x2886
+#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
+#define mmLVTMA_PWRSEQ_DELAY2                                                                          0x2887
+#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX                                                                 2
+#define mmBL_PWM_CNTL                                                                                  0x2888
+#define mmBL_PWM_CNTL_BASE_IDX                                                                         2
+#define mmBL_PWM_CNTL2                                                                                 0x2889
+#define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
+#define mmBL_PWM_PERIOD_CNTL                                                                           0x288a
+#define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
+#define mmBL_PWM_GRP1_REG_LOCK                                                                         0x288b
+#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
+#define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define mmDCIO_SOFT_RESET                                                                              0x289e
+#define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define mmDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define mmDC_GPIO_GENERIC_A                                                                            0x28c9
+#define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define mmDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define mmDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC1_A                                                                               0x28d1
+#define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC1_EN                                                                              0x28d2
+#define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_DDC1_Y                                                                               0x28d3
+#define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC2_A                                                                               0x28d5
+#define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC2_EN                                                                              0x28d6
+#define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_DDC2_Y                                                                               0x28d7
+#define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define mmDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define mmDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define mmDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define mmDC_GPIO_GENLK_A                                                                              0x28f1
+#define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define mmDC_GPIO_GENLK_EN                                                                             0x28f2
+#define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define mmDC_GPIO_GENLK_Y                                                                              0x28f3
+#define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define mmDC_GPIO_HPD_MASK                                                                             0x28f4
+#define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define mmDC_GPIO_HPD_A                                                                                0x28f5
+#define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define mmDC_GPIO_HPD_EN                                                                               0x28f6
+#define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define mmDC_GPIO_HPD_Y                                                                                0x28f7
+#define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define mmDC_GPIO_PWRSEQ_MASK                                                                          0x28f8
+#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
+#define mmDC_GPIO_PWRSEQ_A                                                                             0x28f9
+#define mmDC_GPIO_PWRSEQ_A_BASE_IDX                                                                    2
+#define mmDC_GPIO_PWRSEQ_EN                                                                            0x28fa
+#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
+#define mmDC_GPIO_PWRSEQ_Y                                                                             0x28fb
+#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX                                                                    2
+#define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define mmPHY_AUX_CNTL                                                                                 0x28ff
+#define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define mmDC_GPIO_TX12_EN                                                                              0x2915
+#define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define mmDC_GPIO_RXEN                                                                                 0x2919
+#define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define mmDC_GPIO_PULLUPEN                                                                             0x291a
+#define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define mmDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define mmDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define mmDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define mmDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define mmDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define mmDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define mmDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define mmDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define mmDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define mmDSCC0_DSCC_STATUS                                                                            0x300c
+#define mmDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define mmDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc140
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x3050
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x3051
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x3052
+#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x3053
+#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x3054
+#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x3055
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x3056
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON12_PERFMON_HI                                                                      0x3057
+#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON12_PERFMON_LOW                                                                     0x3058
+#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define mmDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define mmDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define mmDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define mmDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define mmDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define mmDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define mmDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define mmDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define mmDSCC1_DSCC_STATUS                                                                            0x3068
+#define mmDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define mmDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc2b0
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x30ac
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x30ad
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x30ae
+#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x30af
+#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x30b0
+#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x30b1
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x30b2
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON13_PERFMON_HI                                                                      0x30b3
+#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON13_PERFMON_LOW                                                                     0x30b4
+#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define mmDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define mmDWB_MEM_PWR_CTRL                                                                             0x3229
+#define mmDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define mmFC_MODE_CTRL                                                                                 0x322a
+#define mmFC_MODE_CTRL_BASE_IDX                                                                        2
+#define mmFC_FLOW_CTRL                                                                                 0x322b
+#define mmFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define mmFC_WINDOW_START                                                                              0x322c
+#define mmFC_WINDOW_START_BASE_IDX                                                                     2
+#define mmFC_WINDOW_SIZE                                                                               0x322d
+#define mmFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define mmFC_SOURCE_SIZE                                                                               0x322e
+#define mmFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define mmDWB_UPDATE_CTRL                                                                              0x322f
+#define mmDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define mmDWB_CRC_CTRL                                                                                 0x3230
+#define mmDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define mmDWB_CRC_MASK_R_G                                                                             0x3231
+#define mmDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define mmDWB_CRC_MASK_B_A                                                                             0x3232
+#define mmDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define mmDWB_CRC_VAL_R_G                                                                              0x3233
+#define mmDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define mmDWB_CRC_VAL_B_A                                                                              0x3234
+#define mmDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define mmDWB_OUT_CTRL                                                                                 0x3235
+#define mmDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define mmDWB_HOST_READ_CONTROL                                                                        0x3238
+#define mmDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define mmDWB_OVERFLOW_STATUS                                                                          0x3239
+#define mmDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define mmDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define mmDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define mmDWB_SOFT_RESET                                                                               0x323b
+#define mmDWB_SOFT_RESET_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+// base address: 0xca20
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x3288
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x3289
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON14_PERFCOUNTER_STATE                                                               0x328a
+#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON14_PERFMON_CNTL                                                                    0x328b
+#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON14_PERFMON_CNTL2                                                                   0x328c
+#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x328d
+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x328e
+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON14_PERFMON_HI                                                                      0x328f
+#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON14_PERFMON_LOW                                                                     0x3290
+#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define mmDWB_HDR_MULT_COEF                                                                            0x3294
+#define mmDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define mmDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define mmDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define mmDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define mmDWB_OGAM_CONTROL                                                                             0x32a3
+#define mmDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define mmDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define mmDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define mmDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define mmDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define mmDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define mmDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define mmMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define mmMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define mmMPCC0_MPCC_CONTROL                                                                           0x0003
+#define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define mmMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define mmMPCC0_MPCC_BG_R_CR                                                                           0x0009
+#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_BG_G_Y                                                                            0x000a
+#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define mmMPCC0_MPCC_BG_B_CB                                                                           0x000b
+#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000c
+#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define mmMPCC0_MPCC_STATUS                                                                            0x000d
+#define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+// base address: 0x80
+#define mmMPCC1_MPCC_TOP_SEL                                                                           0x0020
+#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_BOT_SEL                                                                           0x0021
+#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_OPP_ID                                                                            0x0022
+#define mmMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define mmMPCC1_MPCC_CONTROL                                                                           0x0023
+#define mmMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_SM_CONTROL                                                                        0x0024
+#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x0025
+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define mmMPCC1_MPCC_TOP_GAIN                                                                          0x0026
+#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x0027
+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0028
+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define mmMPCC1_MPCC_BG_R_CR                                                                           0x0029
+#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_BG_G_Y                                                                            0x002a
+#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define mmMPCC1_MPCC_BG_B_CB                                                                           0x002b
+#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x002c
+#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define mmMPCC1_MPCC_STATUS                                                                            0x002d
+#define mmMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x0100
+#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x0101
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x0102
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x0103
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0104
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0105
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0106
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0107
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0108
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0109
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x010a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x010b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x010c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x010d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x010e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x010f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0110
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0111
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0112
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0113
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0114
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0115
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0116
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0117
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0118
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0119
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x011a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x011b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x011c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x011d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x011e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x011f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0120
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0121
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0122
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0123
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0124
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0125
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0126
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0127
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0128
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0129
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x012a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x012b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x012c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x012d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x012e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x012f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0130
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0131
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0132
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0133
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0134
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0135
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0136
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0137
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0138
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0139
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x013a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x013b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x013c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x013d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x013e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x013f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0140
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0141
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0142
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0143
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0144
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0145
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0146
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0147
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0148
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0149
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x014a
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x014b
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x014c
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x014d
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x014e
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x014f
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0150
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0151
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0152
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0153
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0154
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0155
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0156
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0157
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x200
+#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0180
+#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0181
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0182
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0183
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0184
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0185
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0186
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0187
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0188
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0189
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x018a
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x018b
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x018c
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x018d
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x018e
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x018f
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0190
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0191
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0192
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0193
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0194
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0195
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0196
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0197
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0198
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0199
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x019a
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x019b
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x019c
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x019d
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x019e
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x019f
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01a0
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01a1
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01a2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01a3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01a4
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01a5
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01a6
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01a7
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01a8
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01a9
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01aa
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ab
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ac
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ad
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01ae
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01af
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01b0
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01b1
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01b2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01b3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01b4
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01b5
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01b6
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01b7
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01b8
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01b9
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01ba
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01bb
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01bc
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01bd
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01be
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01bf
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01c0
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01c1
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01c2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01c3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01c4
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01c5
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01c6
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01c7
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01c8
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01c9
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ca
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x01cb
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01cc
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01cd
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01ce
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01cf
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01d0
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01d1
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01d2
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01d3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01d4
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01d5
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01d6
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01d7
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define mmMPC_CLOCK_CONTROL                                                                            0x0500
+#define mmMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define mmMPC_SOFT_RESET                                                                               0x0501
+#define mmMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define mmMPC_CRC_CTRL                                                                                 0x0502
+#define mmMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define mmMPC_CRC_SEL_CONTROL                                                                          0x0503
+#define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define mmMPC_CRC_RESULT_AR                                                                            0x0504
+#define mmMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define mmMPC_CRC_RESULT_GB                                                                            0x0505
+#define mmMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define mmMPC_CRC_RESULT_C                                                                             0x0506
+#define mmMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define mmMPC_PERFMON_EVENT_CTRL                                                                       0x0509
+#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3
+#define mmMPC_BYPASS_BG_AR                                                                             0x050a
+#define mmMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define mmMPC_BYPASS_BG_GB                                                                             0x050b
+#define mmMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define mmMPC_HOST_READ_CONTROL                                                                        0x050c
+#define mmMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define mmMPC_DPP_PENDING_STATUS                                                                       0x050d
+#define mmMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define mmMPC_PENDING_STATUS_MISC                                                                      0x050e
+#define mmMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x050f
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define mmADR_CFG_VUPDATE_LOCK_SET0                                                                    0x0510
+#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define mmADR_VUPDATE_LOCK_SET0                                                                        0x0511
+#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define mmCFG_VUPDATE_LOCK_SET0                                                                        0x0512
+#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define mmCUR_VUPDATE_LOCK_SET0                                                                        0x0513
+#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x0514
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define mmADR_CFG_VUPDATE_LOCK_SET1                                                                    0x0515
+#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define mmADR_VUPDATE_LOCK_SET1                                                                        0x0516
+#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define mmCFG_VUPDATE_LOCK_SET1                                                                        0x0517
+#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define mmCUR_VUPDATE_LOCK_SET1                                                                        0x0518
+#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define mmMPC_DWB0_MUX                                                                                 0x055c
+#define mmMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define mmMPC_OUT0_MUX                                                                                 0x0580
+#define mmMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define mmMPC_OUT0_DENORM_CONTROL                                                                      0x0581
+#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define mmMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x0582
+#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define mmMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x0583
+#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define mmMPC_OUT1_MUX                                                                                 0x0584
+#define mmMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define mmMPC_OUT1_DENORM_CONTROL                                                                      0x0585
+#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define mmMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x0586
+#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define mmMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x0587
+#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define mmMPC_OUT_CSC_COEF_FORMAT                                                                      0x0598
+#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define mmMPC_OUT0_CSC_MODE                                                                            0x0599
+#define mmMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define mmMPC_OUT0_CSC_C11_C12_A                                                                       0x059a
+#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C13_C14_A                                                                       0x059b
+#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C21_C22_A                                                                       0x059c
+#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C23_C24_A                                                                       0x059d
+#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C31_C32_A                                                                       0x059e
+#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C33_C34_A                                                                       0x059f
+#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C11_C12_B                                                                       0x05a0
+#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C13_C14_B                                                                       0x05a1
+#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C21_C22_B                                                                       0x05a2
+#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C23_C24_B                                                                       0x05a3
+#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C31_C32_B                                                                       0x05a4
+#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C33_C34_B                                                                       0x05a5
+#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_MODE                                                                            0x05a6
+#define mmMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define mmMPC_OUT1_CSC_C11_C12_A                                                                       0x05a7
+#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C13_C14_A                                                                       0x05a8
+#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C21_C22_A                                                                       0x05a9
+#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C23_C24_A                                                                       0x05aa
+#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C31_C32_A                                                                       0x05ab
+#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C33_C34_A                                                                       0x05ac
+#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C11_C12_B                                                                       0x05ad
+#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C13_C14_B                                                                       0x05ae
+#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C21_C22_B                                                                       0x05af
+#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C23_C24_B                                                                       0x05b0
+#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C31_C32_B                                                                       0x05b1
+#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C33_C34_B                                                                       0x05b2
+#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+// base address: 0x0
+#define mmMPC_RMU_CONTROL                                                                              0x0680
+#define mmMPC_RMU_CONTROL_BASE_IDX                                                                     3
+#define mmMPC_RMU_MEM_PWR_CTRL                                                                         0x0681
+#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX                                                                3
+#define mmMPC_RMU0_SHAPER_CONTROL                                                                      0x0682
+#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX                                                             3
+#define mmMPC_RMU0_SHAPER_OFFSET_R                                                                     0x0683
+#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_OFFSET_G                                                                     0x0684
+#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_OFFSET_B                                                                     0x0685
+#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_SCALE_R                                                                      0x0686
+#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX                                                             3
+#define mmMPC_RMU0_SHAPER_SCALE_G_B                                                                    0x0687
+#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX                                                           3
+#define mmMPC_RMU0_SHAPER_LUT_INDEX                                                                    0x0688
+#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX                                                           3
+#define mmMPC_RMU0_SHAPER_LUT_DATA                                                                     0x0689
+#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK                                                            0x068a
+#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B                                                            0x068b
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G                                                            0x068c
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R                                                            0x068d
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B                                                              0x068e
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G                                                              0x068f
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R                                                              0x0690
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1                                                              0x0691
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3                                                              0x0692
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5                                                              0x0693
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7                                                              0x0694
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9                                                              0x0695
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11                                                            0x0696
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13                                                            0x0697
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15                                                            0x0698
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17                                                            0x0699
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19                                                            0x069a
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21                                                            0x069b
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23                                                            0x069c
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25                                                            0x069d
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27                                                            0x069e
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29                                                            0x069f
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31                                                            0x06a0
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33                                                            0x06a1
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B                                                            0x06a2
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G                                                            0x06a3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R                                                            0x06a4
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B                                                              0x06a5
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G                                                              0x06a6
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R                                                              0x06a7
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1                                                              0x06a8
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3                                                              0x06a9
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5                                                              0x06aa
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7                                                              0x06ab
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9                                                              0x06ac
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11                                                            0x06ad
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13                                                            0x06ae
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15                                                            0x06af
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17                                                            0x06b0
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19                                                            0x06b1
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21                                                            0x06b2
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23                                                            0x06b3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25                                                            0x06b4
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27                                                            0x06b5
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29                                                            0x06b6
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31                                                            0x06b7
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33                                                            0x06b8
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
+#define mmMPC_RMU0_3DLUT_MODE                                                                          0x06b9
+#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX                                                                 3
+#define mmMPC_RMU0_3DLUT_INDEX                                                                         0x06ba
+#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX                                                                3
+#define mmMPC_RMU0_3DLUT_DATA                                                                          0x06bb
+#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX                                                                 3
+#define mmMPC_RMU0_3DLUT_DATA_30BIT                                                                    0x06bc
+#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX                                                           3
+#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL                                                            0x06bd
+#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
+#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR                                                               0x06be
+#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R                                                                  0x06bf
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G                                                                  0x06c0
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B                                                                  0x06c1
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1901c
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x08c7
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       3
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x08c8
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
+#define mmDC_PERFMON15_PERFCOUNTER_STATE                                                               0x08c9
+#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      3
+#define mmDC_PERFMON15_PERFMON_CNTL                                                                    0x08ca
+#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           3
+#define mmDC_PERFMON15_PERFMON_CNTL2                                                                   0x08cb
+#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          3
+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x08cc
+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x08cd
+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
+#define mmDC_PERFMON15_PERFMON_HI                                                                      0x08ce
+#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             3
+#define mmDC_PERFMON15_PERFMON_LOW                                                                     0x08cf
+#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+// base address: 0x2646c
+#define mmAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x091c
+#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
+#define mmAFMT2_AFMT_60958_0                                                                           0x0920
+#define mmAFMT2_AFMT_60958_0_BASE_IDX                                                                  3
+#define mmAFMT2_AFMT_60958_1                                                                           0x0921
+#define mmAFMT2_AFMT_60958_1_BASE_IDX                                                                  3
+#define mmAFMT2_AFMT_60958_2                                                                           0x0927
+#define mmAFMT2_AFMT_60958_2_BASE_IDX                                                                  3
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
+#define mmAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x092b
+#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
+#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
+#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
+#define mmAFMT2_AFMT_MEM_PWR                                                                           0x092f
+#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+// base address: 0x264c4
+#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
+#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
+#define mmVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x0932
+#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
+#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
+#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
+#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
+#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
+#define mmVPG2_VPG_GENERIC_STATUS                                                                      0x0935
+#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+// base address: 0x264f0
+#define mmDME2_DME_CONTROL                                                                             0x093c
+#define mmDME2_DME_CONTROL_BASE_IDX                                                                    3
+#define mmDME2_DME_MEMORY_CONTROL                                                                      0x093d
+#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             3
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+// base address: 0x0
+#define mmHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+
+
+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a698
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x0e66
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       3
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x0e67
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
+#define mmDC_PERFMON16_PERFCOUNTER_STATE                                                               0x0e68
+#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      3
+#define mmDC_PERFMON16_PERFMON_CNTL                                                                    0x0e69
+#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           3
+#define mmDC_PERFMON16_PERFMON_CNTL2                                                                   0x0e6a
+#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          3
+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x0e6b
+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x0e6c
+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
+#define mmDC_PERFMON16_PERFMON_HI                                                                      0x0e6d
+#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             3
+#define mmDC_PERFMON16_PERFMON_LOW                                                                     0x0e6e
+#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            3
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+// base address: 0x0
+#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define mmABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define mmABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define mmABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define mmABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define mmABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
+#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define mmABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
+#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
+#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
+#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define mmABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+// base address: 0x104
+#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define mmABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define mmABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define mmABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define mmABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define mmABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
+#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define mmABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
+#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
+#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
+#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define mmABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define mmCORB_WRITE_POINTER                                                                           0x0000
+#define mmCORB_WRITE_POINTER_BASE_IDX                                                                  0
+#define mmCORB_READ_POINTER                                                                            0x0000
+#define mmCORB_READ_POINTER_BASE_IDX                                                                   0
+#define mmCORB_CONTROL                                                                                 0x0001
+#define mmCORB_CONTROL_BASE_IDX                                                                        0
+#define mmCORB_STATUS                                                                                  0x0001
+#define mmCORB_STATUS_BASE_IDX                                                                         0
+#define mmCORB_SIZE                                                                                    0x0001
+#define mmCORB_SIZE_BASE_IDX                                                                           0
+#define mmRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
+#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
+#define mmRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
+#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
+#define mmRIRB_WRITE_POINTER                                                                           0x0004
+#define mmRIRB_WRITE_POINTER_BASE_IDX                                                                  0
+#define mmRESPONSE_INTERRUPT_COUNT                                                                     0x0004
+#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
+#define mmRIRB_CONTROL                                                                                 0x0005
+#define mmRIRB_CONTROL_BASE_IDX                                                                        0
+#define mmRIRB_STATUS                                                                                  0x0005
+#define mmRIRB_STATUS_BASE_IDX                                                                         0
+#define mmRIRB_SIZE                                                                                    0x0005
+#define mmRIRB_SIZE_BASE_IDX                                                                           0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
+#define mmIMMEDIATE_COMMAND_STATUS                                                                     0x0008
+#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
+#define mmWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
+#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
+
+
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h
new file mode 100644
index 000000000000..e8f4ad05932b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h
@@ -0,0 +1,35330 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef _dcn_3_0_3_SH_MASK_HEADER
+#define _dcn_3_0_3_SH_MASK_HEADER
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT                                           0x19
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK                                             0x02000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT                                                                           0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK                                                                             0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT                                                                         0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK                                                                           0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT                                                                          0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK                                                                            0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT                                                                              0x0
+#define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT                                                                         0x4
+#define GENS1__NO_DISPLAY_MASK                                                                                0x01L
+#define GENS1__VGA_VSTATUS_MASK                                                                               0x08L
+#define GENS1__PIXEL_READ_BACK_MASK                                                                           0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDW__ATTR_DATA_MASK                                                                                0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT                                                                                0x0
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT                                                                         0x5
+#define ATTRX__ATTR_IDX_MASK                                                                                  0x1FL
+#define ATTRX__ATTR_PAL_RW_ENB_MASK                                                                           0x20L
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDR__ATTR_DATA_MASK                                                                                0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_WT__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT                                                                            0x4
+#define GENS0__CRT_INTR__SHIFT                                                                                0x7
+#define GENS0__SENSE_SWITCH_MASK                                                                              0x10L
+#define GENS0__CRT_INTR_MASK                                                                                  0x80L
+//GENENB
+#define GENENB__BLK_IO_BASE__SHIFT                                                                            0x0
+#define GENENB__BLK_IO_BASE_MASK                                                                              0xFFL
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT                                                                              0x0
+#define SEQ8_IDX__SEQ_IDX_MASK                                                                                0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT                                                                            0x0
+#define SEQ8_DATA__SEQ_DATA_MASK                                                                              0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT                                                                             0x0
+#define DAC_MASK__DAC_MASK_MASK                                                                               0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT                                                                       0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK                                                                         0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT                                                                       0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK                                                                         0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT                                                                             0x0
+#define DAC_DATA__DAC_DATA_MASK                                                                               0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT                                                                          0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK                                                                            0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_RD__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT                                                                            0x0
+#define GRPH8_IDX__GRPH_IDX_MASK                                                                              0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT                                                                          0x0
+#define GRPH8_DATA__GRPH_DATA_MASK                                                                            0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT                                                                         0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK                                                                           0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT                                                                       0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK                                                                         0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT                                                                        0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK                                                                          0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT                                                                            0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT                                                                           0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT                                                                       0x4
+#define GENS1_1__NO_DISPLAY_MASK                                                                              0x01L
+#define GENS1_1__VGA_VSTATUS_MASK                                                                             0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK                                                                         0x30L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
+//REFCLK_CNTL
+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT                                                                   0x0
+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT                                                                    0x1
+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK                                                                     0x00000001L
+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK                                                                      0x00000002L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_PERFMON_CNTL2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
+//DCCG_PERFMON_CNTL
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT                                               0x18
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT                                               0x19
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT                                               0x1a
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT                                               0x1b
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT                                               0x1c
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE__SHIFT                                               0x1d
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK                                                 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK                                                 0x02000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK                                                 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK                                                 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK                                                 0x10000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE_MASK                                                 0x20000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x00001FFFL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT                                                        0x1
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK                                                          0x00000002L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000030L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT                                                 0x1
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK                                                   0x00000002L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
+//PHYASYMCLK_CLOCK_CNTL
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L
+//PHYBSYMCLK_CLOCK_CNTL
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+//DC_PERFMON0_PERFCOUNTER_CNTL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_CNTL2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_STATE
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON0_PERFMON_CNTL
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON0_PERFMON_CNTL2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON0_PERFMON_CVALUE_LOW
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON0_PERFMON_HI
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON0_PERFMON_LOW
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON1_PERFCOUNTER_CNTL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_CNTL2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_STATE
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON1_PERFMON_CNTL
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON1_PERFMON_CNTL2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON1_PERFMON_CVALUE_LOW
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON1_PERFMON_HI
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON1_PERFMON_LOW
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT                                                          0x5
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT                                                          0x9
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK                                                            0x00000020L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK                                                            0x00000200L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
+//DMU_MEM_PWR_CNTL
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT                                                   0x0
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT                                                      0x1
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT                                                        0x3
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT                                                      0x4
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT                                                      0x8
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT                                                        0x9
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT                                                      0xa
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK                                                     0x00000001L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK                                                        0x00000006L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK                                                          0x00000008L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK                                                        0x00000100L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK                                                          0x00000200L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK                                                        0x00000400L
+//DMCU_SMU_INTERRUPT_CNTL
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT                                            0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT                                         0x10
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK                                              0x00000001L
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK                                           0xFFFF0000L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+//DMCU_CTRL
+#define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT                                                                       0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT                                                                   0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT                                                                  0x3
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT                                                                         0x4
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT                                                              0x8
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT                                                                   0x10
+#define DMCU_CTRL__RESET_UC_MASK                                                                              0x00000001L
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK                                                                         0x00000002L
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK                                                                     0x00000004L
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK                                                                    0x00000008L
+#define DMCU_CTRL__DMCU_ENABLE_MASK                                                                           0x00000010L
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK                                                                0x00000100L
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK                                                                     0xFFFF0000L
+//DMCU_STATUS
+#define DMCU_STATUS__UC_IN_RESET__SHIFT                                                                       0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT                                                                   0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT                                                                   0x2
+#define DMCU_STATUS__UC_IN_RESET_MASK                                                                         0x00000001L
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK                                                                     0x00000002L
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK                                                                     0x00000004L
+//DMCU_PC_START_ADDR
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_START_ADDR
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_END_ADDR
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT                                                              0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT                                                              0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK                                                                0x000000FFL
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK                                                                0x0000FF00L
+//DMCU_FW_ISR_START_ADDR
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT                                                  0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT                                                  0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK                                                    0x000000FFL
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK                                                    0x0000FF00L
+//DMCU_FW_CS_HI
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT                                                                  0x0
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK                                                                    0xFFFFFFFFL
+//DMCU_FW_CS_LO
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT                                                                  0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK                                                                    0xFFFFFFFFL
+//DMCU_RAM_ACCESS_CTRL
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT                                                      0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT                                                      0x5
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000001L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000002L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000004L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000008L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK                                                        0x00000010L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK                                                        0x00000020L
+//DMCU_ERAM_WR_CTRL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_WR_DATA
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_ERAM_RD_CTRL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_RD_DATA
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_IRAM_WR_CTRL
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_WR_DATA
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK                                                                  0x000000FFL
+//DMCU_IRAM_RD_CTRL
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_RD_DATA
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK                                                                  0x000000FFL
+//DMCU_EVENT_TRIGGER
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT                                                           0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT                                                       0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT                                                0x17
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK                                                             0x00000001L
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK                                                         0x007F0000L
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK                                                  0x00800000L
+//DMCU_UC_INTERNAL_INT_STATUS
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT                                                  0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT                                                 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT                                         0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT                                        0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT                                     0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT                                     0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT                                     0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT                                     0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT                                             0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT                                        0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT                     0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT                                      0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT                                      0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT                                      0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT                               0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT                                 0xf
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK                                                    0x00000001L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK                                                   0x00000002L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK                                           0x00000004L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK                                          0x00000008L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK                                       0x00000010L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK                                       0x00000020L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK                                       0x00000040L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK                                       0x00000080L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK                                               0x00000100L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK                                          0x00000200L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK                       0x00000400L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK                                        0x00000800L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK                                        0x00001000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK                                        0x00002000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK                                 0x00004000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK                                   0x00008000L
+//DMCU_SS_INTERRUPT_CNTL_STATUS
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT                                       0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT                                     0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT                                        0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT                                       0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT                                     0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT                                        0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT                                       0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT                                     0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT                                        0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT                                       0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT                                     0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT                                        0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT                                       0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT                                     0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT                                        0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT                                       0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT                                     0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT                                        0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK                                         0x00002000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK                                       0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK                                          0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK                                         0x00008000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK                                       0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK                                          0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK                                         0x00020000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK                                       0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK                                          0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK                                         0x00080000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK                                       0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK                                          0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK                                         0x00200000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK                                       0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK                                          0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK                                         0x00800000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK                                       0x01000000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK                                          0x01000000L
+//DMCU_INTERRUPT_STATUS
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT                                              0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT                                                 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT                                              0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT                                                 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT                                             0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT                                                0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT                                                        0x3
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT                                                0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT                                                   0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT                                                        0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT                                                0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT                                                   0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT                                          0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT                                             0xb
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT                                                    0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT                                                       0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT                                                    0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT                                                       0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT                                                    0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT                                                       0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT                                                    0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT                                                       0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT                                                    0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT                                                       0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT                                                    0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT                                                       0x1d
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK                                                0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK                                                   0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK                                                0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK                                                   0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK                                               0x00000004L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK                                                  0x00000004L
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK                                                          0x00000008L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK                                                  0x00000100L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK                                                     0x00000100L
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK                                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK                                                  0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK                                                     0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK                                            0x00000800L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK                                               0x00000800L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK                                                      0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK                                                         0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK                                                      0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK                                                         0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK                                                      0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK                                                         0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK                                                      0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK                                                         0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK                                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK                                                         0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK                                                      0x20000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK                                                         0x20000000L
+//DMCU_INTERRUPT_STATUS_1
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xb
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xb
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT                                       0xd
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT                                          0xd
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK                                         0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK                                            0x00002000L
+//DMCU_INTERRUPT_TO_HOST_EN_MASK
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT                                         0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT                                         0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT                                        0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT                                         0x3
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT                                         0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT                                        0x5
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT                                                   0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT                                           0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT                                     0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK                                           0x00000001L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK                                           0x00000002L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK                                          0x00000004L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK                                           0x00000008L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK                                           0x00000010L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK                                          0x00000020L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK                                                     0x00000200L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK                                             0x00000400L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK                                       0x00000800L
+//DMCU_INTERRUPT_TO_UC_EN_MASK
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT                                       0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT                                       0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT                                      0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT                                                 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT                                      0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT                                      0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT                                         0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT                                      0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT                                      0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT                                      0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT                                             0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT                                             0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT                                             0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT                                             0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT                                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT                                             0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT                                      0x1e
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK                                         0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK                                         0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK                                        0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK                                                   0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK                                        0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK                                        0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK                                           0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK                                        0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK                                        0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK                                        0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK                                               0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK                                               0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK                                               0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK                                               0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK                                               0x10000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK                                               0x20000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK                                        0x40000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT                                      0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK                                        0x00002000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                             0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT                                        0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT                             0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT                             0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT                                0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT                             0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT                             0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT                             0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT                                    0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT                                    0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT                             0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                               0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK                                          0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK                               0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK                               0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK                                  0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK                               0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK                               0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK                               0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK                                      0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK                                      0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK                                      0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK                                      0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK                                      0x20000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK                               0x40000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT                             0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK                               0x00002000L
+//DC_DMCU_SCRATCH
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT                                                                  0x0
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK                                                                    0xFFFFFFFFL
+//DMCU_INT_CNT
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT                                                       0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT                                                       0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT                                                      0x10
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK                                                         0x000000FFL
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK                                                         0x0000FF00L
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK                                                        0x00FF0000L
+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT                              0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT                              0x2
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK                                0x00000003L
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK                                0x0000000CL
+//DMCU_UC_CLK_GATING_CNTL
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT                                                      0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT                                                      0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT                                              0x10
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK                                                        0x00000007L
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK                                                        0x00000700L
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK                                                0x00010000L
+//MASTER_COMM_DATA_REG1
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG2
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG3
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_CMD_REG
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT                                                 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT                                                 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT                                                 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT                                                 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK                                                   0x000000FFL
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK                                                   0x0000FF00L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK                                                   0x00FF0000L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK                                                   0xFF000000L
+//MASTER_COMM_CNTL_REG
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT                                                    0x0
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK                                                      0x00000001L
+//SLAVE_COMM_DATA_REG1
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG2
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG3
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_CMD_REG
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT                                                   0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT                                                   0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT                                                   0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT                                                   0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK                                                     0x000000FFL
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK                                                     0x0000FF00L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK                                                     0x00FF0000L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK                                                     0xFF000000L
+//SLAVE_COMM_CNTL_REG
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT                                                      0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT                                         0x8
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK                                                        0x00000001L
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK                                           0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+//DMCU_PERFMON_INTERRUPT_STATUS2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                            0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                               0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                              0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                                 0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+//DMCU_PERFMON_INTERRUPT_STATUS4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                          0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000010L
+//DMCU_PERFMON_INTERRUPT_STATUS5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                     0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                       0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                   0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                     0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT            0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK              0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT          0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+//DMCU_DPRX_INTERRUPT_STATUS1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT            0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT               0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT         0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT            0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT          0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT             0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT      0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT         0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT               0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT                  0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT                          0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT                             0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT                           0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT                              0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT                          0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT                             0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT                         0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT                            0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT                    0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT                       0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT                                      0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT                                         0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT                                      0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT                                         0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT                                      0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT                                         0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT                             0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT                                0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT                             0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT                                0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT                             0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT                                0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT                             0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT                                0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK              0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK           0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK              0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK            0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK               0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK        0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK           0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK                 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                    0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK                            0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK                               0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK                             0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK                                0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK                            0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK                               0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK                           0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK                              0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK                      0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK                         0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK                                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK                                           0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK                                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK                                           0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK                                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK                                           0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK                               0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK                                  0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK                               0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK                                  0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK                               0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK                                  0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK                               0x10000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK                                  0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT     0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT   0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT        0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT                   0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT                    0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT                   0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT                  0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT             0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT                               0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT                               0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT                               0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK       0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK    0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK     0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK          0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK                     0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK                      0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK                     0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK                    0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK               0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK                                 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK                                 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK                                 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK                        0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK                        0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK                        0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK                        0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT          0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT           0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT          0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT         0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT    0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT                      0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT                      0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT                      0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK            0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK             0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK            0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK           0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK      0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x10000000L
+//DMCU_INTERRUPT_STATUS_CONTINUE
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT                          0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT                             0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT                          0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT                             0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT                          0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT                             0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT                          0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT                             0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT                          0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT                             0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT                          0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT                             0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT                                     0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT                                        0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT                                     0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT                                        0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT                                       0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK                            0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK                               0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK                            0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK                               0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK                            0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK                               0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK                            0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK                               0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK                            0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK                               0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK                            0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK                               0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK                                       0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK                                          0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK                                       0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK                                          0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK                                         0x10000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT                   0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT                   0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT                   0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT                   0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT                   0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT                   0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT                              0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT                              0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK                     0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK                     0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK                     0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK                     0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK                     0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK                     0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK                                0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK                                0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK                               0x10000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT          0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT          0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT          0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT          0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT          0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT          0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK            0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK            0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK            0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK            0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK            0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK            0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK                       0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK                       0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                      0x10000000L
+//DMCU_INT_CNT_CONTINUE
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT                                              0x0
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT                                              0x8
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT                                             0x10
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK                                                0x000000FFL
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK                                                0x0000FF00L
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK                                               0x00FF0000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT                        0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT                        0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT                        0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT                        0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT                        0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT                        0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT                        0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK                          0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK                          0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK                          0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK                          0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK                          0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK                          0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK                          0x00400000L
+//DMCU_INTERRUPT_STATUS_2
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT                                            0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT                                               0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT                                            0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT                                               0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT                                            0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT                                               0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT                                            0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT                                               0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT                                            0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT                                               0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT                                            0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT                                               0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT                                            0x16
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT                                               0x16
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK                                              0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK                                                 0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK                                              0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK                                                 0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK                                              0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK                                                 0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK                                              0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK                                                 0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK                                              0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK                                                 0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK                                              0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK                                                 0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK                                              0x00400000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK                                                 0x00400000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT                                     0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT                                     0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT                                     0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT                                     0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT                                     0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT                                     0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT                                     0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK                                       0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK                                       0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK                                       0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK                                       0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK                                       0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK                                       0x00400000L
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT                                                    0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT                                                            0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT                                                       0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT                                                       0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT                                                      0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK                                                      0x04000000L
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK                                                              0x08000000L
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK                                                         0x10000000L
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK                                                         0x20000000L
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK                                                        0x40000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT                        0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK                          0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT                         0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT                         0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT                        0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT                        0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT                       0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT                       0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT                       0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT                                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT                                            0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK                           0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK                           0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK                          0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK                          0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK                         0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK                         0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK                         0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK                                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK                                              0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE25
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT__SHIFT                                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT__SHIFT                                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT__SHIFT                                           0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT__SHIFT                                            0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT__SHIFT                                            0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT__SHIFT                                           0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT__SHIFT                                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT__SHIFT                                            0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT__SHIFT                                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT__SHIFT                                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT__SHIFT                                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT_MASK                                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT_MASK                                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT_MASK                                             0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT_MASK                                              0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT_MASK                                              0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT_MASK                                             0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT_MASK                                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT_MASK                                              0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT_MASK                                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT_MASK                                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT_MASK                                             0x00000800L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0xb
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT                                      0xe
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x10
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT                                      0x11
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT                                      0x12
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x13
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x18
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x19
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT                                      0x1b
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT                                                0x1c
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00000800L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK                                        0x00004000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00010000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK                                        0x00020000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK                                        0x00040000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00080000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x01000000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x02000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK                                        0x08000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK                                                  0x10000000L
+//DMU_INTERRUPT_DEST2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST__SHIFT                                     0x0
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST__SHIFT                                     0x1
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST__SHIFT                                     0x3
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST__SHIFT                                     0x4
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x5
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST__SHIFT                                     0x6
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST__SHIFT                                     0x7
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x8
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST__SHIFT                                     0x9
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST__SHIFT                                     0xa
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0xb
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST_MASK                                       0x00000001L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST_MASK                                       0x00000002L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST_MASK                                       0x00000008L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST_MASK                                       0x00000010L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST_MASK                                       0x00000040L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST_MASK                                       0x00000080L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST_MASK                                       0x00000200L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST_MASK                                       0x00000400L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000800L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x8
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x9
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xa
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xb
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xc
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xd
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xe
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xf
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x18
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x19
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1a
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1b
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1c
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1d
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1e
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1f
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000100L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000200L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000400L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000800L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK                                   0x00001000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK                                   0x00002000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK                                   0x00004000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK                                   0x00008000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x01000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x02000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x04000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x08000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x10000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x20000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x40000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x80000000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPP_INTERRUPT_DEST
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT                        0x17
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK                          0x00800000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00002000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00002000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00008000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00002000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT                                                          0x8
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT                                                           0xc
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK                                                            0x00000700L
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK                                                             0x00007000L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
+#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT                                                                   0x11
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
+#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK                                                                     0x00020000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L
+//MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                           0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                             0x00000001L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000004L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L
+//MCIF_WB_BUF_PITCH
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L
+//MCIF_WB_BUF_1_STATUS
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_2_STATUS
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_3_STATUS
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_4_STATUS
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L
+//MCIF_WB_SCLK_CHANGE
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L
+//MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                          0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                         0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                                    0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                            0x00000010L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                           0x00000020L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                                      0x00000040L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L
+//MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                              0x0
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                          0x2
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                                0x00000001L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                            0x00000004L
+//MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L
+//MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                         0x0
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                           0x00000001L
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L
+//MULTI_LEVEL_QOS_CTRL
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL
+//MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL
+//MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL
+//MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__SHIFT                 0x0
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_MASK                   0x0000FFFFL
+//MCIF_WB_VMID_CONTROL
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL
+//MCIF_WB_MIN_TTO
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L
+//MCIF_WB_WATERMARK
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L
+//MMHUBBUB_WARMUP_CONFIG
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L
+//MMHUBBUB_WARMUP_CONTROL_STATUS
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L
+//MMHUBBUB_WARMUP_BASE_ADDR_LOW
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL
+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL
+//MMHUBBUB_WARMUP_ADDR_REGION
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL
+//MMHUBBUB_MIN_TTO
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL
+//WBIF_SMU_WM_CONTROL
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
+//MMHUBBUB_WARMUP_VMID_CONTROL
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON3_PERFCOUNTER_CNTL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_CNTL2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_STATE
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON3_PERFMON_CNTL
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON3_PERFMON_CNTL2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON3_PERFMON_CVALUE_LOW
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON3_PERFMON_HI
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON3_PERFMON_LOW
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK                                 0x00000038L
+//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK                                 0x00000038L
+//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT                                   0x0
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT                                   0x3
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK                                     0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK                                     0x00000038L
+//DCHUBBUB_SDPIF_PIPE_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x3
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x00000038L
+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x3
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x00000038L
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
+//DCHUBBUB_SDPIF_CFG2
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000700L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_DCC_CFG
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK                                                   0x00000001L
+//DCHUBBUB_RET_PATH_DCC_CFG0_0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG0_1
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_1
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_1
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_1
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xc
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x001FF000L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT  0x8
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT  0x9
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK  0x00000100L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK  0x00000200L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
+//FMON_CTRL_1
+#define FMON_CTRL_1__FMON_START__SHIFT                                                                        0x0
+#define FMON_CTRL_1__FMON_MODE__SHIFT                                                                         0x1
+#define FMON_CTRL_1__FMON_PSTATE_IGNORE__SHIFT                                                                0x4
+#define FMON_CTRL_1__FMON_STATUS_IGNORE__SHIFT                                                                0x5
+#define FMON_CTRL_1__FMON_URG_MODE_GREATER__SHIFT                                                             0x6
+#define FMON_CTRL_1__FMON_FILTER_UID_EN__SHIFT                                                                0x7
+#define FMON_CTRL_1__FMON_STATE__SHIFT                                                                        0x9
+#define FMON_CTRL_1__FMON_URG_FILTER__SHIFT                                                                   0xc
+#define FMON_CTRL_1__FMON_URG_THRESHOLD__SHIFT                                                                0xd
+#define FMON_CTRL_1__FMON_FILTER_UID_1__SHIFT                                                                 0x11
+#define FMON_CTRL_1__FMON_FILTER_UID_2__SHIFT                                                                 0x16
+#define FMON_CTRL_1__FMON_SOF_SEL__SHIFT                                                                      0x1b
+#define FMON_CTRL_1__FMON_START_MASK                                                                          0x00000001L
+#define FMON_CTRL_1__FMON_MODE_MASK                                                                           0x00000006L
+#define FMON_CTRL_1__FMON_PSTATE_IGNORE_MASK                                                                  0x00000010L
+#define FMON_CTRL_1__FMON_STATUS_IGNORE_MASK                                                                  0x00000020L
+#define FMON_CTRL_1__FMON_URG_MODE_GREATER_MASK                                                               0x00000040L
+#define FMON_CTRL_1__FMON_FILTER_UID_EN_MASK                                                                  0x00000180L
+#define FMON_CTRL_1__FMON_STATE_MASK                                                                          0x00000600L
+#define FMON_CTRL_1__FMON_URG_FILTER_MASK                                                                     0x00001000L
+#define FMON_CTRL_1__FMON_URG_THRESHOLD_MASK                                                                  0x0001E000L
+#define FMON_CTRL_1__FMON_FILTER_UID_1_MASK                                                                   0x003E0000L
+#define FMON_CTRL_1__FMON_FILTER_UID_2_MASK                                                                   0x07C00000L
+#define FMON_CTRL_1__FMON_SOF_SEL_MASK                                                                        0x38000000L
+
+
+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON4_PERFCOUNTER_CNTL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_CNTL2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_STATE
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON4_PERFMON_CNTL
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON4_PERFMON_CNTL2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON4_PERFMON_CVALUE_LOW
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON4_PERFMON_HI
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON4_PERFMON_LOW
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_DEFAULT_ADDR_MSB
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
+//DCN_VM_DEFAULT_ADDR_LSB
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_DMDATA_VM_CNTL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ0_VBLANK_PARAMETERS_5
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_6
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_3
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_4
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_5
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_6
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON5_PERFCOUNTER_CNTL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_CNTL2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_STATE
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON5_PERFMON_CNTL
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON5_PERFMON_CNTL2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON5_PERFMON_CVALUE_LOW
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON5_PERFMON_HI
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON5_PERFMON_LOW
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_DMDATA_VM_CNTL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ1_VBLANK_PARAMETERS_5
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_6
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_3
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_4
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_5
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_6
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON6_PERFCOUNTER_CNTL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_CNTL2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_STATE
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON6_PERFMON_CNTL
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON6_PERFMON_CNTL2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON6_PERFMON_CVALUE_LOW
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON6_PERFMON_HI
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON6_PERFMON_LOW
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG0_PRE_DEALPHA
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG0_PRE_CSC_MODE
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG0_PRE_CSC_C11_C12
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C13_C14
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C21_C22
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C23_C24
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C31_C32
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C33_C34
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C11_C12
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C13_C14
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C21_C22
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C23_C24
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C31_C32
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C33_C34
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_CNVC_COEF_FORMAT
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG0_PRE_DEGAM
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG0_PRE_REALPHA
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL0_SCL_BLACK_COLOR
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM0_CM_POST_CSC_CONTROL
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM0_CM_POST_CSC_C11_C12
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C13_C14
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C21_C22
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C23_C24
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C31_C32
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C33_C34
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_B_C11_C12
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C13_C14
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C21_C22
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C23_C24
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C31_C32
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C33_C34
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM0_CM_GAMCOR_CONTROL
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM0_CM_GAMCOR_LUT_INDEX
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM0_CM_GAMCOR_LUT_DATA
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM0_CM_GAMCOR_LUT_CONTROL
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_OFFSET_B
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_G
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_R
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_REGION_0_1
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_2_3
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_4_5
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_6_7
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_8_9
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_10_11
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_12_13
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_14_15
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_16_17
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_18_19
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_20_21
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_22_23
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_24_25
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_26_27
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_28_29
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_30_31
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_32_33
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_OFFSET_B
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_G
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_R
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_REGION_0_1
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_2_3
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_4_5
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_6_7
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_8_9
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_10_11
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_12_13
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_14_15
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_16_17
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_18_19
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_20_21
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_22_23
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_24_25
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_26_27
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_28_29
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_30_31
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_32_33
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_BLNDGAM_CONTROL
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM0_CM_BLNDGAM_LUT_INDEX
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM0_CM_BLNDGAM_LUT_DATA
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM0_CM_BLNDGAM_LUT_CONTROL
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG__SHIFT                                            0x5
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG_MASK                                              0x00000020L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM0_CM_SHAPER_CONTROL
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM0_CM_SHAPER_OFFSET_R
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_G
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_B
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_SCALE_R
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM0_CM_SHAPER_SCALE_G_B
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM0_CM_SHAPER_LUT_INDEX
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM0_CM_SHAPER_LUT_DATA
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM0_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM0_CM_SHAPER_RAMA_START_CNTL_B
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_G
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_R
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_B
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_G
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_R
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_REGION_0_1
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_2_3
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_4_5
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_6_7
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_8_9
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_10_11
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_12_13
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_14_15
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_16_17
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_18_19
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_20_21
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_22_23
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_24_25
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_26_27
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_28_29
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_30_31
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_32_33
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_B
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_G
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_R
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_B
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_G
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_R
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_REGION_0_1
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_2_3
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_4_5
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_6_7
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_8_9
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_10_11
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_12_13
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_14_15
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_16_17
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_18_19
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_20_21
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_22_23
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_24_25
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_26_27
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_28_29
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_30_31
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_32_33
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_MEM_PWR_CTRL2
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM0_CM_MEM_PWR_STATUS2
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM0_CM_3DLUT_MODE
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM0_CM_3DLUT_INDEX
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM0_CM_3DLUT_DATA
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM0_CM_3DLUT_DATA_30BIT
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM0_CM_3DLUT_READ_WRITE_CONTROL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM0_CM_3DLUT_OUT_NORM_FACTOR
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM0_CM_3DLUT_OUT_OFFSET_R
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_G
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_B
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON7_PERFCOUNTER_CNTL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_CNTL2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_STATE
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON7_PERFMON_CNTL
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON7_PERFMON_CNTL2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON7_PERFMON_CVALUE_LOW
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON7_PERFMON_HI
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON7_PERFMON_LOW
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG1_PRE_DEALPHA
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG1_PRE_CSC_MODE
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG1_PRE_CSC_C11_C12
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C13_C14
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C21_C22
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C23_C24
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C31_C32
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C33_C34
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C11_C12
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C13_C14
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C21_C22
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C23_C24
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C31_C32
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C33_C34
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_CNVC_COEF_FORMAT
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG1_PRE_DEGAM
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG1_PRE_REALPHA
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL1_SCL_BLACK_COLOR
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM1_CM_POST_CSC_CONTROL
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM1_CM_POST_CSC_C11_C12
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C13_C14
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C21_C22
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C23_C24
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C31_C32
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C33_C34
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_B_C11_C12
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C13_C14
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C21_C22
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C23_C24
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C31_C32
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C33_C34
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM1_CM_GAMCOR_CONTROL
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM1_CM_GAMCOR_LUT_INDEX
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM1_CM_GAMCOR_LUT_DATA
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM1_CM_GAMCOR_LUT_CONTROL
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_OFFSET_B
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_G
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_R
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_REGION_0_1
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_2_3
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_4_5
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_6_7
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_8_9
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_10_11
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_12_13
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_14_15
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_16_17
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_18_19
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_20_21
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_22_23
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_24_25
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_26_27
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_28_29
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_30_31
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_32_33
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_OFFSET_B
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_G
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_R
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_REGION_0_1
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_2_3
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_4_5
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_6_7
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_8_9
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_10_11
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_12_13
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_14_15
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_16_17
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_18_19
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_20_21
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_22_23
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_24_25
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_26_27
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_28_29
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_30_31
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_32_33
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_BLNDGAM_CONTROL
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM1_CM_BLNDGAM_LUT_INDEX
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM1_CM_BLNDGAM_LUT_DATA
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM1_CM_BLNDGAM_LUT_CONTROL
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG__SHIFT                                            0x5
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_DBG_MASK                                              0x00000020L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM1_CM_SHAPER_CONTROL
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM1_CM_SHAPER_OFFSET_R
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_G
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_B
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_SCALE_R
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM1_CM_SHAPER_SCALE_G_B
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM1_CM_SHAPER_LUT_INDEX
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM1_CM_SHAPER_LUT_DATA
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM1_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM1_CM_SHAPER_RAMA_START_CNTL_B
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_G
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_R
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_B
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_G
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_R
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_REGION_0_1
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_2_3
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_4_5
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_6_7
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_8_9
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_10_11
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_12_13
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_14_15
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_16_17
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_18_19
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_20_21
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_22_23
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_24_25
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_26_27
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_28_29
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_30_31
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_32_33
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_B
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_G
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_R
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_B
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_G
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_R
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_REGION_0_1
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_2_3
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_4_5
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_6_7
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_8_9
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_10_11
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_12_13
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_14_15
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_16_17
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_18_19
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_20_21
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_22_23
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_24_25
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_26_27
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_28_29
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_30_31
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_32_33
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_MEM_PWR_CTRL2
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM1_CM_MEM_PWR_STATUS2
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM1_CM_3DLUT_MODE
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM1_CM_3DLUT_INDEX
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM1_CM_3DLUT_DATA
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM1_CM_3DLUT_DATA_30BIT
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM1_CM_3DLUT_READ_WRITE_CONTROL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM1_CM_3DLUT_OUT_NORM_FACTOR
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM1_CM_3DLUT_OUT_OFFSET_R
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_G
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_B
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON8_PERFCOUNTER_CNTL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_CNTL2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_STATE
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON8_PERFMON_CNTL
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON8_PERFMON_CNTL2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON8_PERFMON_CVALUE_LOW
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON8_PERFMON_HI
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON8_PERFMON_LOW
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
+//OPP_ABM_CONTROL
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON9_PERFCOUNTER_CNTL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_CNTL2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_STATE
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON9_PERFMON_CNTL
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON9_PERFMON_CNTL2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON9_PERFMON_CVALUE_LOW
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON9_PERFMON_HI
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON9_PERFMON_LOW
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x10
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x14
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0x00F00000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x10
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x14
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0x00F00000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00100000L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG0_OTG_BLANK_DATA_COLOR
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
+//OTG0_OTG_BLANK_DATA_COLOR_EXT
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG0_OTG_CRC_CNTL2
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG0_OTG_GLOBAL_CONTROL4
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_DRR_TIMING_INT_STATUS
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG0_OTG_DRR_V_TOTAL_CHANGE
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG0_OTG_DRR_TRIGGER_WINDOW
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG0_OTG_M_CONST_DTO0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG0_OTG_M_CONST_DTO1
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00100000L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG1_OTG_BLANK_DATA_COLOR
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
+//OTG1_OTG_BLANK_DATA_COLOR_EXT
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG1_OTG_CRC_CNTL2
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG1_OTG_GLOBAL_CONTROL4
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_DRR_TIMING_INT_STATUS
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG1_OTG_DRR_V_TOTAL_CHANGE
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG1_OTG_DRR_TRIGGER_WINDOW
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG1_OTG_M_CONST_DTO0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG1_OTG_M_CONST_DTO1
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+//DWB_SOURCE_SELECT
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT                                                     0x0
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT                                                     0x3
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT                                                     0x6
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK                                                       0x00000007L
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK                                                       0x00000038L
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK                                                       0x000001C0L
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
+//ODM_MEM_PWR_CTRL2
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON10_PERFCOUNTER_CNTL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_CNTL2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_STATE
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON10_PERFMON_CNTL
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON10_PERFMON_CNTL2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON10_PERFMON_CVALUE_LOW
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON10_PERFMON_HI
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON10_PERFMON_LOW
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT                                                             0x1f
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK                                                               0x80000000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
+
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT                                                           0x5
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT                                                            0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT                                                          0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT                                                          0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT                                                          0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT                                                          0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT                                                          0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT                                                          0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT                                                          0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK                                                             0x00000020L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK                                                              0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK                                                            0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK                                                            0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK                                                            0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK                                                            0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK                                                            0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK                                                            0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK                                                            0x40000000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT                                                           0x18
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT                                                           0x19
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT                                                           0x1a
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT                                                           0x1b
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT                                                           0x1c
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT                                                           0x1d
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT                                                           0x1e
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK                                                             0x01000000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK                                                             0x02000000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK                                                             0x04000000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK                                                             0x08000000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK                                                             0x10000000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK                                                             0x20000000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK                                                             0x40000000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
+//DIO_GENERIC_INTERRUPT_MESSAGE
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT                                    0x0
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT                                   0x1
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK                                      0x00000001L
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK                                     0xFFFFFFFEL
+//DIO_GENERIC_INTERRUPT_CLEAR
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT                                       0x0
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK                                         0x00000001L
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON11_PERFCOUNTER_CNTL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_CNTL2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_STATE
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON11_PERFMON_CNTL
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON11_PERFMON_CNTL2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON11_PERFMON_CVALUE_LOW
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON11_PERFMON_HI
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON11_PERFMON_LOW
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG0_VPG_GENERIC_PACKET_DATA
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG0_VPG_GENERIC_STATUS
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG0_VPG_MEM_PWR
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG0_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG0_VPG_ISRC1_2_DATA
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG0_VPG_MPEG_INFO0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG0_VPG_MPEG_INFO1
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+//AFMT0_AFMT_VBI_PACKET_CONTROL
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT0_AFMT_AUDIO_INFO0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT0_AFMT_AUDIO_INFO1
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT0_AFMT_60958_0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT0_AFMT_60958_1
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_CONTROL
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT0_AFMT_RAMP_CONTROL0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT0_AFMT_RAMP_CONTROL1
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT0_AFMT_RAMP_CONTROL2
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_RAMP_CONTROL3
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_60958_2
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_RESULT
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT0_AFMT_STATUS
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT0_AFMT_INFOFRAME_CONTROL0
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT0_AFMT_AUDIO_SRC_CONTROL
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT0_AFMT_MEM_PWR
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+//DME0_DME_CONTROL
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+//DME0_DME_MEMORY_CONTROL
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG0_DIG_FIFO_STATUS
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG0_DIG_LANE_ENABLE
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP0_DP_DSC_BYTES_PER_PIXEL
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_GSP8_CNTL
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP9_CNTL
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP10_CNTL
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP11_CNTL
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP_EN_DB_STATUS
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG1_VPG_GENERIC_PACKET_DATA
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG1_VPG_GENERIC_STATUS
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG1_VPG_MEM_PWR
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG1_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG1_VPG_ISRC1_2_DATA
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG1_VPG_MPEG_INFO0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG1_VPG_MPEG_INFO1
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+//AFMT1_AFMT_VBI_PACKET_CONTROL
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT1_AFMT_AUDIO_INFO0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT1_AFMT_AUDIO_INFO1
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT1_AFMT_60958_0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT1_AFMT_60958_1
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_CONTROL
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT1_AFMT_RAMP_CONTROL0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT1_AFMT_RAMP_CONTROL1
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT1_AFMT_RAMP_CONTROL2
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_RAMP_CONTROL3
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_60958_2
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_RESULT
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT1_AFMT_STATUS
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT1_AFMT_INFOFRAME_CONTROL0
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT1_AFMT_AUDIO_SRC_CONTROL
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT1_AFMT_MEM_PWR
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+//DME1_DME_CONTROL
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+//DME1_DME_MEMORY_CONTROL
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG1_DIG_FIFO_STATUS
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG1_DIG_LANE_ENABLE
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP1_DP_DSC_BYTES_PER_PIXEL
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_GSP8_CNTL
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP9_CNTL
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP10_CNTL
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP11_CNTL
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP_EN_DB_STATUS
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT                                                                0xc
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT                                                                   0x10
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK                                                                  0x0000F000L
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK                                                                     0x000F0000L
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//LVTMA_PWRSEQ_CNTL
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT                                                             0x0
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT                                0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT                                                   0x4
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT                                                                0x8
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT                                                           0x9
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT                                                            0xa
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT                                                                 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT                                                            0x11
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT                                                             0x12
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT                                                                  0x18
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT                                                             0x19
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT                                                              0x1a
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK                                                               0x00000001L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK                                  0x00000002L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK                                                     0x00000010L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK                                                                  0x00000100L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK                                                             0x00000200L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK                                                              0x00000400L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK                                                                   0x00010000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK                                                              0x00020000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK                                                               0x00040000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK                                                                    0x01000000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK                                                               0x02000000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK                                                                0x04000000L
+//LVTMA_PWRSEQ_STATE
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT                                                0x0
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT                                                         0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT                                                        0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT                                                          0x3
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT                                                          0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT                                                         0x8
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK                                                  0x00000001L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK                                                           0x00000002L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK                                                          0x00000004L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK                                                            0x00000008L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK                                                            0x00000010L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK                                                           0x00000F00L
+//LVTMA_PWRSEQ_REF_DIV
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT                                                     0x0
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT                                                           0x10
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK                                                       0x00000FFFL
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK                                                             0xFFFF0000L
+//LVTMA_PWRSEQ_DELAY1
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT                                                        0x0
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT                                                        0x8
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT                                                        0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT                                                        0x18
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK                                                          0x000000FFL
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK                                                          0x0000FF00L
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK                                                          0x00FF0000L
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK                                                          0xFF000000L
+//LVTMA_PWRSEQ_DELAY2
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT                                                    0x0
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT                                                        0x8
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT                                                        0x10
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT                                                 0x18
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK                                                      0x000000FFL
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK                                                          0x0000FF00L
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK                                                          0x00FF0000L
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK                                                   0x01000000L
+//BL_PWM_CNTL
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                            0x0
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                              0x1e
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                         0x1f
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                              0x0000FFFFL
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                                0x40000000L
+#define BL_PWM_CNTL__BL_PWM_EN_MASK                                                                           0x80000000L
+//BL_PWM_CNTL2
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                      0x0
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT                                                   0x1c
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                    0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT                                                  0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                        0x0000FFFFL
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK                                                     0x30000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                      0x40000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK                                                    0x80000000L
+//BL_PWM_PERIOD_CNTL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                              0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                       0x10
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                                0x0000FFFFL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                         0x000F0000L
+//BL_PWM_GRP1_REG_LOCK
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                     0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                           0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                        0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT                                         0x11
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                     0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                        0x1f
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                       0x00000001L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                             0x00000100L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                          0x00010000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK                                           0x000E0000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                       0x01000000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                          0x80000000L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT                                                            0x14
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT                                                               0x1a
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK                                                              0x00100000L
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK                                                                 0x04000000L
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT                                                          0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT                                                        0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT                                                        0x3
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK                                                            0x00000002L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK                                                          0x00000004L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK                                                          0x00000008L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT                                                               0x3
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT                                                               0x4
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT                                                                    0x7
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK                                                                 0x00000008L
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK                                                                 0x00000010L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK                                                                      0x00000080L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_PWRSEQ_MASK
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                         0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                       0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                         0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                        0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                      0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                        0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT                                                       0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT                                                     0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT                                                       0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT                                                     0x18
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT                                                   0x19
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT                                                     0x1a
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT                                                     0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT                                                   0x1d
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT                                                     0x1e
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                           0x00000001L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                         0x00000010L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                           0x000000C0L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                          0x00000100L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                        0x00001000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                          0x0000C000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK                                                         0x00010000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK                                                       0x00100000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK                                                         0x00C00000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK                                                       0x01000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK                                                     0x02000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK                                                       0x04000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK                                                       0x10000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK                                                     0x20000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK                                                       0x40000000L
+//DC_GPIO_PWRSEQ_A
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT                                                               0x0
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT                                                              0x8
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT                                                           0x18
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT                                                           0x1f
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK                                                                 0x00000001L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK                                                                0x00000100L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK                                                               0x00010000L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK                                                             0x01000000L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK                                                             0x80000000L
+//DC_GPIO_PWRSEQ_EN
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                             0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                            0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT                                                           0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT                                                         0x18
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT                                                         0x1f
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                               0x00000001L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                   0x00000002L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                              0x00000100L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK                                                           0x01000000L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK                                                           0x80000000L
+//DC_GPIO_PWRSEQ_Y
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT                                                               0x0
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT                                                              0x8
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT                                                             0x18
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT                                                             0x1f
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK                                                                 0x00000001L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK                                                                0x00000100L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK                                                               0x00010000L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK                                                               0x01000000L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK                                                               0x80000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT                                                     0x8
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK                                                       0x00000F00L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK                                                       0x0000F000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT                                                               0x0
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT                                                                0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT                                                               0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT                                                                0x3
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT                                                              0x4
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT                                                                 0x5
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT                                                               0x6
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT                                                                  0x7
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT                                                               0x8
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT                                                                0x17
+#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT                                                                    0x18
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT                                                                0x1c
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK                                                                 0x00000001L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK                                                                  0x00000002L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK                                                                 0x00000004L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK                                                                  0x00000008L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK                                                                0x00000010L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK                                                                   0x00000020L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK                                                                 0x00000040L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK                                                                    0x00000080L
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK                                                                 0x00000100L
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK                                                                  0x00800000L
+#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK                                                                      0x03000000L
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK                                                                  0x70000000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT                                                          0x0
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT                                                         0x1
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT                                                        0x2
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK                                                            0x00000001L
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK                                                           0x00000002L
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK                                                          0x00000004L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT                                                                0x14
+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT                                                               0x15
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT                                                              0x16
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK                                                                  0x00100000L
+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK                                                                 0x00200000L
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK                                                                0x00400000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT                                                           0x14
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT                                                          0x15
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT                                                         0x16
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK                                                             0x00100000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK                                                            0x00200000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK                                                           0x00400000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON12_PERFCOUNTER_CNTL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_CNTL2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_STATE
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON12_PERFMON_CNTL
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON12_PERFMON_CNTL2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON12_PERFMON_CVALUE_LOW
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON12_PERFMON_HI
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON12_PERFMON_LOW
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP1_DSC_DEBUG_CONTROL
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON13_PERFCOUNTER_CNTL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_CNTL2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_STATE
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON13_PERFMON_CNTL
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON13_PERFMON_CNTL2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON13_PERFMON_CVALUE_LOW
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON13_PERFMON_HI
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON13_PERFMON_LOW
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+//DWB_ENABLE_CLK_CTRL
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L
+//DWB_MEM_PWR_CTRL
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L
+//FC_MODE_CTRL
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L
+//FC_FLOW_CTRL
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL
+//FC_WINDOW_START
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L
+//FC_WINDOW_SIZE
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L
+//FC_SOURCE_SIZE
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L
+//DWB_UPDATE_CTRL
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L
+//DWB_CRC_CTRL
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L
+//DWB_CRC_MASK_R_G
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L
+//DWB_CRC_MASK_B_A
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L
+//DWB_CRC_VAL_R_G
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L
+//DWB_CRC_VAL_B_A
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L
+//DWB_OUT_CTRL
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL
+//DWB_HOST_READ_CONTROL
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL
+//DWB_OVERFLOW_STATUS
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L
+//DWB_OVERFLOW_COUNTER
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L
+//DWB_SOFT_RESET
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON14_PERFCOUNTER_CNTL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_CNTL2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_STATE
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON14_PERFMON_CNTL
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON14_PERFMON_CNTL2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON14_PERFMON_CVALUE_LOW
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON14_PERFMON_HI
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON14_PERFMON_LOW
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+//DWB_HDR_MULT_COEF
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL
+//DWB_GAMUT_REMAP_MODE
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L
+//DWB_GAMUT_REMAP_COEF_FORMAT
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L
+//DWB_GAMUT_REMAPA_C11_C12
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C13_C14
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C21_C22
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C23_C24
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C31_C32
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C33_C34
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C11_C12
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C13_C14
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C21_C22
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C23_C24
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C31_C32
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C33_C34
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L
+//DWB_OGAM_CONTROL
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L
+//DWB_OGAM_LUT_INDEX
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL
+//DWB_OGAM_LUT_DATA
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL
+//DWB_OGAM_LUT_CONTROL
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L
+//DWB_OGAM_RAMA_START_CNTL_B
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_G
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_R
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_BASE_CNTL_B
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_G
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_R
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL1_B
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_B
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_G
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_G
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_R
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_R
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_OFFSET_B
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_G
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_R
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_REGION_0_1
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_2_3
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_4_5
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_6_7
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_8_9
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_10_11
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_12_13
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_14_15
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_16_17
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_18_19
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_20_21
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_22_23
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_24_25
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_26_27
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_28_29
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_30_31
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_32_33
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_START_CNTL_B
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_G
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_R
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_BASE_CNTL_B
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_G
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_R
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL1_B
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_B
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_G
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_G
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_R
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_R
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_OFFSET_B
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_G
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_R
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_REGION_0_1
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_2_3
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_4_5
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_6_7
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_8_9
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_10_11
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_12_13
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_14_15
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_16_17
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_18_19
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_20_21
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_22_23
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_24_25
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_26_27
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_28_29
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_30_31
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_32_33
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
+//MPC_PERFMON_EVENT_CTRL
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
+//MPC_DPP_PENDING_STATUS
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L
+//MPC_PENDING_STATUS_MISC
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//MPC_DWB0_MUX
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+//MPC_RMU_CONTROL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX__SHIFT                                                                  0x0
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS__SHIFT                                                           0x4
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_MASK                                                                    0x0000000FL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS_MASK                                                             0x000000F0L
+//MPC_RMU_MEM_PWR_CTRL
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE__SHIFT                                                   0x0
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS__SHIFT                                                     0x2
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE__SHIFT                                            0x4
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE__SHIFT                                             0x6
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE__SHIFT                                                0x8
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE_MASK                                                     0x00000003L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS_MASK                                                       0x00000004L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE_MASK                                              0x00000030L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE_MASK                                               0x000000C0L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE_MASK                                                  0x00000300L
+//MPC_RMU0_SHAPER_CONTROL
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT                                               0x0
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT                                           0x8
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK                                                 0x00000003L
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK                                             0x00000300L
+//MPC_RMU0_SHAPER_OFFSET_R
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_G
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_B
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_SCALE_R
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT                                                0x0
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK                                                  0x0000FFFFL
+//MPC_RMU0_SHAPER_SCALE_G_B
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT                                              0x10
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK                                                0x0000FFFFL
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK                                                0xFFFF0000L
+//MPC_RMU0_SHAPER_LUT_INDEX
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT                                            0x0
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK                                              0x000000FFL
+//MPC_RMU0_SHAPER_LUT_DATA
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK                                                0x00FFFFFFL
+//MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT                            0x0
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT                                0x4
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK                              0x00000007L
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK                                  0x00000010L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_3DLUT_MODE
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT                                                        0x0
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT                                                        0x4
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT                                                0x8
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK                                                          0x00000003L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK                                                          0x00000010L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK                                                  0x00000300L
+//MPC_RMU0_3DLUT_INDEX
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT                                                      0x0
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK                                                        0x000007FFL
+//MPC_RMU0_3DLUT_DATA
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT                                                       0x0
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT                                                       0x10
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK                                                         0x0000FFFFL
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK                                                         0xFFFF0000L
+//MPC_RMU0_3DLUT_DATA_30BIT
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT                                            0x2
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK                                              0xFFFFFFFCL
+//MPC_RMU0_3DLUT_READ_WRITE_CONTROL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT                                 0x0
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT                                       0x4
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT                                      0x8
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT                                      0x10
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK                                   0x0000000FL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK                                         0x00000010L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK                                        0x00000100L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK                                        0x00030000L
+//MPC_RMU0_3DLUT_OUT_NORM_FACTOR
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT                                  0x0
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK                                    0x0000FFFFL
+//MPC_RMU0_3DLUT_OUT_OFFSET_R
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_G
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_B
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON15_PERFCOUNTER_CNTL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_CNTL2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_STATE
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON15_PERFMON_CNTL
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON15_PERFMON_CNTL2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON15_PERFMON_CVALUE_LOW
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON15_PERFMON_HI
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON15_PERFMON_LOW
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT                                              0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT                                                0xd
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x10
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK                                                0x00000200L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK                                                  0x00002000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0x003F0000L
+
+
+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON16_PERFCOUNTER_CNTL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_CNTL2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_STATE
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON16_PERFMON_CNTL
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON16_PERFMON_CNTL2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON16_PERFMON_CVALUE_LOW
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON16_PERFMON_HI
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON16_PERFMON_LOW
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM0_BL1_PWM_USER_LEVEL
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM0_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM0_BL1_PWM_ABM_CNTL
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM0_BL1_PWM_GRP2_REG_LOCK
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM0_DC_ABM1_CNTL
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM0_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_12
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_34
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_CNTL_MISC
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM0_DC_ABM1_HG_MISC_CTRL
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM0_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM0_DC_ABM1_LS_PIXEL_COUNT
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_HG_SAMPLE_RATE
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_LS_SAMPLE_RATE
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_1
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_2
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_3
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_4
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_5
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_6
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_7
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_8
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_9
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_10
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_11
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_12
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_13
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_14
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_15
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_16
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_17
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_18
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_19
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_20
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_21
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_22
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_23
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_24
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_BL_MASTER_LOCK
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM1_BL1_PWM_USER_LEVEL
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM1_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM1_BL1_PWM_ABM_CNTL
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM1_BL1_PWM_GRP2_REG_LOCK
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM1_DC_ABM1_CNTL
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM1_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_12
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_34
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_CNTL_MISC
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM1_DC_ABM1_HG_MISC_CTRL
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM1_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM1_DC_ABM1_LS_PIXEL_COUNT
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_HG_SAMPLE_RATE
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_LS_SAMPLE_RATE
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_1
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_2
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_3
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_4
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_5
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_6
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_7
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_8
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_9
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_10
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_11
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_12
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_13
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_14
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_15
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_16
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_17
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_18
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_19
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_20
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_21
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_22
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_23
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_24
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_BL_MASTER_LOCK
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//CORB_WRITE_POINTER
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                                         0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                                           0x00FFL
+//CORB_READ_POINTER
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                                           0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                                     0xf
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK                                                             0x00FFL
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                                       0x8000L
+//CORB_CONTROL
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                                           0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                                 0x01L
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                                             0x02L
+//CORB_STATUS
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                                      0x0
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                                        0x01L
+//CORB_SIZE
+#define CORB_SIZE__CORB_SIZE__SHIFT                                                                           0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define CORB_SIZE__CORB_SIZE_MASK                                                                             0x0003L
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//RIRB_LOWER_BASE_ADDRESS
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                               0x7
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L
+//RIRB_UPPER_BASE_ADDRESS
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                               0x0
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//RIRB_WRITE_POINTER
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                                         0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                                   0xf
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                                           0x00FFL
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                                     0x8000L
+//RESPONSE_INTERRUPT_COUNT
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                                           0x0
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                                             0x00FFL
+//RIRB_CONTROL
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                                       0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                               0x2
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                                         0x01L
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                                 0x04L
+//RIRB_STATUS
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                                 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                                  0x01L
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                                   0x04L
+//RIRB_SIZE
+#define RIRB_SIZE__RIRB_SIZE__SHIFT                                                                           0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define RIRB_SIZE__RIRB_SIZE_MASK                                                                             0x0003L
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT                   0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT                      0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK                     0x0FFFFFFFL
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK                        0xF0000000L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                               0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                                 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                              0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                                0x0000FFFFL
+//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                                    0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                                      0xFFFFFFFFL
+//IMMEDIATE_COMMAND_STATUS
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                               0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                               0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                                 0x00000001L
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                                 0x00000002L
+//DMA_POSITION_LOWER_BASE_ADDRESS
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                                    0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                    0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                               0x7
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                                      0x00000001L
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                      0x0000007EL
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                                 0xFFFFFF80L
+//DMA_POSITION_UPPER_BASE_ADDRESS
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                               0x0
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                                 0xFFFFFFFFL
+//WALL_CLOCK_COUNTER_ALIAS
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                                             0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                      0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                   0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                     0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                     0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                       0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                      0x0001FFFFL
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT                                                                              0x0
+#define CRT0C__DISP_START_MASK                                                                                0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT                                                                              0x0
+#define CRT0D__DISP_START_MASK                                                                                0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
+#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
+#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
+
+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
new file mode 100644
index 000000000000..312c50ea30f3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
@@ -0,0 +1,15083 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_1_2_OFFSET_HEADER
+#define _dcn_3_1_2_OFFSET_HEADER
+
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x1300000
+#define regAZCONTROLLER0_GLOBAL_CAPABILITIES                                                            0x4b7000
+#define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX                                                   3
+#define regAZCONTROLLER0_MINOR_VERSION                                                                  0x4b7000
+#define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX                                                         3
+#define regAZCONTROLLER0_MAJOR_VERSION                                                                  0x4b7000
+#define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX                                                         3
+#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY                                                      0x4b7001
+#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                             3
+#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY                                                       0x4b7001
+#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                              3
+#define regAZCONTROLLER0_GLOBAL_CONTROL                                                                 0x4b7002
+#define regAZCONTROLLER0_GLOBAL_CONTROL_BASE_IDX                                                        3
+#define regAZCONTROLLER0_WAKE_ENABLE                                                                    0x4b7003
+#define regAZCONTROLLER0_WAKE_ENABLE_BASE_IDX                                                           3
+#define regAZCONTROLLER0_STATE_CHANGE_STATUS                                                            0x4b7003
+#define regAZCONTROLLER0_STATE_CHANGE_STATUS_BASE_IDX                                                   3
+#define regAZCONTROLLER0_GLOBAL_STATUS                                                                  0x4b7004
+#define regAZCONTROLLER0_GLOBAL_STATUS_BASE_IDX                                                         3
+#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY                                               0x4b7006
+#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                      3
+#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY                                                0x4b7006
+#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                       3
+#define regAZCONTROLLER0_INTERRUPT_CONTROL                                                              0x4b7008
+#define regAZCONTROLLER0_INTERRUPT_CONTROL_BASE_IDX                                                     3
+#define regAZCONTROLLER0_INTERRUPT_STATUS                                                               0x4b7009
+#define regAZCONTROLLER0_INTERRUPT_STATUS_BASE_IDX                                                      3
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER                                                             0x4b700c
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_BASE_IDX                                                    3
+#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION                                                         0x4b700e
+#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION_BASE_IDX                                                3
+#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS                                                        0x4b7010
+#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS                                                        0x4b7011
+#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_CORB_WRITE_POINTER                                                             0x4b7012
+#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX                                                    3
+#define regAZCONTROLLER0_CORB_READ_POINTER                                                              0x4b7012
+#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX                                                     3
+#define regAZCONTROLLER0_CORB_CONTROL                                                                   0x4b7013
+#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX                                                          3
+#define regAZCONTROLLER0_CORB_STATUS                                                                    0x4b7013
+#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX                                                           3
+#define regAZCONTROLLER0_CORB_SIZE                                                                      0x4b7013
+#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX                                                             3
+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS                                                        0x4b7014
+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS                                                        0x4b7015
+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_RIRB_WRITE_POINTER                                                             0x4b7016
+#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX                                                    3
+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT                                                       0x4b7016
+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              3
+#define regAZCONTROLLER0_RIRB_CONTROL                                                                   0x4b7017
+#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX                                                          3
+#define regAZCONTROLLER0_RIRB_STATUS                                                                    0x4b7017
+#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX                                                           3
+#define regAZCONTROLLER0_RIRB_SIZE                                                                      0x4b7017
+#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX                                                             3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x4b7018
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x4b7018
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x4b7018
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              3
+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x4b7019
+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS                                                       0x4b701a
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              3
+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x4b701c
+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       3
+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x4b701d
+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       3
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS                                                       0x4b780c
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              3
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x1300000
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x4b7018
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      3
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x4b7018
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     3
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x1300000
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x4b7018
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  3
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x4b7018
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 3
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
+// base address: 0x48
+#define regVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define regVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
+// base address: 0x3b4
+#define regCRTC8_IDX                                                                                    0x002d
+#define regCRTC8_IDX_BASE_IDX                                                                           1
+#define regCRTC8_DATA                                                                                   0x002d
+#define regCRTC8_DATA_BASE_IDX                                                                          1
+#define regGENFC_WT                                                                                     0x002e
+#define regGENFC_WT_BASE_IDX                                                                            1
+#define regGENS1                                                                                        0x002e
+#define regGENS1_BASE_IDX                                                                               1
+#define regATTRDW                                                                                       0x0030
+#define regATTRDW_BASE_IDX                                                                              1
+#define regATTRX                                                                                        0x0030
+#define regATTRX_BASE_IDX                                                                               1
+#define regATTRDR                                                                                       0x0030
+#define regATTRDR_BASE_IDX                                                                              1
+#define regGENMO_WT                                                                                     0x0030
+#define regGENMO_WT_BASE_IDX                                                                            1
+#define regGENS0                                                                                        0x0030
+#define regGENS0_BASE_IDX                                                                               1
+#define regGENENB                                                                                       0x0030
+#define regSEQ8_IDX                                                                                     0x0031
+#define regSEQ8_IDX_BASE_IDX                                                                            1
+#define regSEQ8_DATA                                                                                    0x0031
+#define regSEQ8_DATA_BASE_IDX                                                                           1
+#define regDAC_MASK                                                                                     0x0031
+#define regDAC_MASK_BASE_IDX                                                                            1
+#define regDAC_R_INDEX                                                                                  0x0031
+#define regDAC_R_INDEX_BASE_IDX                                                                         1
+#define regDAC_W_INDEX                                                                                  0x0032
+#define regDAC_W_INDEX_BASE_IDX                                                                         1
+#define regDAC_DATA                                                                                     0x0032
+#define regDAC_DATA_BASE_IDX                                                                            1
+#define regGENFC_RD                                                                                     0x0032
+#define regGENFC_RD_BASE_IDX                                                                            1
+#define regGENMO_RD                                                                                     0x0033
+#define regGENMO_RD_BASE_IDX                                                                            1
+#define regGRPH8_IDX                                                                                    0x0033
+#define regGRPH8_IDX_BASE_IDX                                                                           1
+#define regGRPH8_DATA                                                                                   0x0033
+#define regGRPH8_DATA_BASE_IDX                                                                          1
+#define regCRTC8_IDX_1                                                                                  0x0035
+#define regCRTC8_IDX_1_BASE_IDX                                                                         1
+#define regCRTC8_DATA_1                                                                                 0x0035
+#define regCRTC8_DATA_1_BASE_IDX                                                                        1
+#define regGENFC_WT_1                                                                                   0x0036
+#define regGENFC_WT_1_BASE_IDX                                                                          1
+#define regGENS1_1                                                                                      0x0036
+#define regGENS1_1_BASE_IDX                                                                             1
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define regAZCONTROLLER1_CORB_WRITE_POINTER                                                             0x0000
+#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX                                                    0
+#define regAZCONTROLLER1_CORB_READ_POINTER                                                              0x0000
+#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX                                                     0
+#define regAZCONTROLLER1_CORB_CONTROL                                                                   0x0001
+#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX                                                          0
+#define regAZCONTROLLER1_CORB_STATUS                                                                    0x0001
+#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX                                                           0
+#define regAZCONTROLLER1_CORB_SIZE                                                                      0x0001
+#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX                                                             0
+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS                                                        0x0002
+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               0
+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS                                                        0x0003
+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               0
+#define regAZCONTROLLER1_RIRB_WRITE_POINTER                                                             0x0004
+#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX                                                    0
+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT                                                       0x0004
+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              0
+#define regAZCONTROLLER1_RIRB_CONTROL                                                                   0x0005
+#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX                                                          0
+#define regAZCONTROLLER1_RIRB_STATUS                                                                    0x0005
+#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX                                                           0
+#define regAZCONTROLLER1_RIRB_SIZE                                                                      0x0005
+#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX                                                             0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x0006
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x0006
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x0006
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              0
+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x0007
+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS                                                       0x0008
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              0
+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x000a
+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       0
+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x000b
+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       0
+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS                                                       0x074c
+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              1
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x0006
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      0
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x0006
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     0
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x0006
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  0
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x0006
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 0
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDP_DTO_DBUF_EN                                                                               0x0044
+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
+#define regDPSTREAMCLK_CNTL                                                                             0x004a
+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDCCG_PERFMON_CNTL2                                                                           0x004e
+#define regDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
+#define regDCCG_DS_DTO_INCR                                                                             0x0053
+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define regDCCG_DS_DTO_MODULO                                                                           0x0054
+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define regDCCG_DS_CNTL                                                                                 0x0055
+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define regDPREFCLK_CNTL                                                                                0x0058
+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define regDCE_VERSION                                                                                  0x005e
+#define regDCE_VERSION_BASE_IDX                                                                         1
+#define regDCCG_GTC_CNTL                                                                                0x0060
+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GTC_DTO_INCR                                                                            0x0061
+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define regDCCG_GTC_CURRENT                                                                             0x0063
+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define regSYMCLK32_SE_CNTL                                                                             0x0065
+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
+#define regSYMCLK32_LE_CNTL                                                                             0x0066
+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
+#define regDSCCLK0_DTO_PARAM                                                                            0x006c
+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK1_DTO_PARAM                                                                            0x006d
+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK2_DTO_PARAM                                                                            0x006e
+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define regDCCG_PERFMON_CNTL                                                                            0x0073
+#define regDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_CAC_STATUS                                                                              0x0077
+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_DISP_CNTL_REG                                                                           0x007f
+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO0_PHASE                                                                                0x0081
+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO0_MODULO                                                                               0x0082
+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO1_PHASE                                                                                0x0085
+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO1_MODULO                                                                               0x0086
+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO2_PHASE                                                                                0x0089
+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO2_MODULO                                                                               0x008a
+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO3_PHASE                                                                                0x008d
+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO3_MODULO                                                                               0x008e
+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDPPCLK0_DTO_PARAM                                                                            0x0099
+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK1_DTO_PARAM                                                                            0x009a
+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK2_DTO_PARAM                                                                            0x009b
+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK3_DTO_PARAM                                                                            0x009c
+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDCCG_CAC_STATUS2                                                                             0x009f
+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regDCCG_SOFT_RESET                                                                              0x00a6
+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define regDSCCLK_DTO_CTRL                                                                              0x00a7
+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define regDPPCLK_DTO_CTRL                                                                              0x00b6
+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define regDTBCLK_DTO0_PHASE                                                                            0x0018
+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO1_PHASE                                                                            0x0019
+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO2_PHASE                                                                            0x001a
+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO3_PHASE                                                                            0x001b
+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO0_MODULO                                                                           0x001f
+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO1_MODULO                                                                           0x0020
+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO2_MODULO                                                                           0x0021
+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO3_MODULO                                                                           0x0022
+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+// base address: 0x0
+#define regDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
+#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
+#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
+#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
+#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
+#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
+#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON0_PERFMON_HI                                                                       0x0007
+#define regDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON0_PERFMON_LOW                                                                      0x0008
+#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+// base address: 0x30
+#define regDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
+#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
+#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
+#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
+#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
+#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
+#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON1_PERFMON_HI                                                                       0x0013
+#define regDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON1_PERFMON_LOW                                                                      0x0014
+#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+// base address: 0x0
+#define regDMCU_CTRL                                                                                    0x00da
+#define regDMCU_CTRL_BASE_IDX                                                                           2
+#define regDMCU_STATUS                                                                                  0x00db
+#define regDMCU_STATUS_BASE_IDX                                                                         2
+#define regDMCU_PC_START_ADDR                                                                           0x00dc
+#define regDMCU_PC_START_ADDR_BASE_IDX                                                                  2
+#define regDMCU_FW_START_ADDR                                                                           0x00dd
+#define regDMCU_FW_START_ADDR_BASE_IDX                                                                  2
+#define regDMCU_FW_END_ADDR                                                                             0x00de
+#define regDMCU_FW_END_ADDR_BASE_IDX                                                                    2
+#define regDMCU_FW_ISR_START_ADDR                                                                       0x00df
+#define regDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
+#define regDMCU_FW_CS_HI                                                                                0x00e0
+#define regDMCU_FW_CS_HI_BASE_IDX                                                                       2
+#define regDMCU_FW_CS_LO                                                                                0x00e1
+#define regDMCU_FW_CS_LO_BASE_IDX                                                                       2
+#define regDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
+#define regDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
+#define regDMCU_ERAM_WR_CTRL                                                                            0x00e3
+#define regDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
+#define regDMCU_ERAM_WR_DATA                                                                            0x00e4
+#define regDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
+#define regDMCU_ERAM_RD_CTRL                                                                            0x00e5
+#define regDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
+#define regDMCU_ERAM_RD_DATA                                                                            0x00e6
+#define regDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
+#define regDMCU_IRAM_WR_CTRL                                                                            0x00e7
+#define regDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
+#define regDMCU_IRAM_WR_DATA                                                                            0x00e8
+#define regDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
+#define regDMCU_IRAM_RD_CTRL                                                                            0x00e9
+#define regDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
+#define regDMCU_IRAM_RD_DATA                                                                            0x00ea
+#define regDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
+#define regDMCU_EVENT_TRIGGER                                                                           0x00eb
+#define regDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
+#define regDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
+#define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
+#define regDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
+#define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
+#define regDMCU_INTERRUPT_STATUS                                                                        0x00ee
+#define regDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
+#define regDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
+#define regDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
+#define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
+#define regDC_DMCU_SCRATCH                                                                              0x00f5
+#define regDC_DMCU_SCRATCH_BASE_IDX                                                                     2
+#define regDMCU_INT_CNT                                                                                 0x00f6
+#define regDMCU_INT_CNT_BASE_IDX                                                                        2
+#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
+#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
+#define regDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
+#define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
+#define regMASTER_COMM_DATA_REG1                                                                        0x00f9
+#define regMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
+#define regMASTER_COMM_DATA_REG2                                                                        0x00fa
+#define regMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
+#define regMASTER_COMM_DATA_REG3                                                                        0x00fb
+#define regMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
+#define regMASTER_COMM_CMD_REG                                                                          0x00fc
+#define regMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
+#define regMASTER_COMM_CNTL_REG                                                                         0x00fd
+#define regMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
+#define regSLAVE_COMM_DATA_REG1                                                                         0x00fe
+#define regSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
+#define regSLAVE_COMM_DATA_REG2                                                                         0x00ff
+#define regSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
+#define regSLAVE_COMM_DATA_REG3                                                                         0x0100
+#define regSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
+#define regSLAVE_COMM_CMD_REG                                                                           0x0101
+#define regSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
+#define regSLAVE_COMM_CNTL_REG                                                                          0x0102
+#define regSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
+#define regDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
+#define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
+#define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
+#define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
+#define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
+#define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
+#define regDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
+#define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
+#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
+#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
+#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
+#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
+#define regDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
+#define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
+#define regDMCU_INT_CNT_CONTINUE                                                                        0x011c
+#define regDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
+#define regDMCU_INTERRUPT_STATUS_2                                                                      0x011e
+#define regDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
+#define regDMCU_INT_CNT_CONT2                                                                           0x0120
+#define regDMCU_INT_CNT_CONT2_BASE_IDX                                                                  2
+#define regDMCU_INT_CNT_CONT3                                                                           0x0121
+#define regDMCU_INT_CNT_CONT3_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_fgsec_dispdec
+// base address: 0x0
+#define regDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a
+#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define regRBBMIF_TIMEOUT                                                                               0x017f
+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define regRBBMIF_STATUS                                                                                0x0180
+#define regRBBMIF_STATUS_BASE_IDX                                                                       2
+#define regRBBMIF_STATUS_2                                                                              0x0181
+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define regRBBMIF_INT_STATUS                                                                            0x0182
+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define regRBBMIF_STATUS_FLAG                                                                           0x0185
+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2f8
+#define regDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
+#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
+#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
+#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
+#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
+#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
+#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON2_PERFMON_HI                                                                       0x00c5
+#define regDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
+#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define regDC_GPU_TIMER_READ                                                                            0x0128
+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define regDISP_INTERRUPT_STATUS                                                                        0x012a
+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define regDCCG_INTERRUPT_DEST                                                                          0x0148
+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDMU_INTERRUPT_DEST                                                                           0x0149
+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDMU_INTERRUPT_DEST2                                                                          0x014a
+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST                                                                          0x014b
+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define regWB_INTERRUPT_DEST                                                                            0x014e
+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define regMPC_INTERRUPT_DEST                                                                           0x0153
+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPP_INTERRUPT_DEST                                                                           0x0154
+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPTC_INTERRUPT_DEST                                                                          0x0155
+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG0_INTERRUPT_DEST                                                                          0x0156
+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG1_INTERRUPT_DEST                                                                          0x0157
+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG2_INTERRUPT_DEST                                                                          0x0158
+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG3_INTERRUPT_DEST                                                                          0x0159
+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG4_INTERRUPT_DEST                                                                          0x015a
+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG5_INTERRUPT_DEST                                                                          0x015b
+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDIG_INTERRUPT_DEST                                                                           0x015c
+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define regDIO_INTERRUPT_DEST                                                                           0x015f
+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDCIO_INTERRUPT_DEST                                                                          0x0160
+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regHPD_INTERRUPT_DEST                                                                           0x0161
+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regAZ_INTERRUPT_DEST                                                                            0x0162
+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regAUX_INTERRUPT_DEST                                                                           0x0163
+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDSC_INTERRUPT_DEST                                                                           0x0164
+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regHPO_INTERRUPT_DEST                                                                           0x0165
+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define regCC_DC_PIPE_DIS                                                                               0x00ca
+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define regDMU_CLK_CNTL                                                                                 0x00cb
+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define regDMU_MEM_PWR_CNTL                                                                             0x00cc
+#define regDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
+#define regDMCU_SMU_INTERRUPT_CNTL                                                                      0x00cd
+#define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
+#define regZSC_CNTL                                                                                     0x00cf
+#define regZSC_CNTL_BASE_IDX                                                                            2
+#define regZSC_CNTL2                                                                                    0x00d0
+#define regZSC_CNTL2_BASE_IDX                                                                           2
+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+#define regZSC_STATUS                                                                                   0x00d7
+#define regZSC_STATUS_BASE_IDX                                                                          2
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define regDOMAIN0_PG_CONFIG                                                                            0x0080
+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN0_PG_STATUS                                                                            0x0081
+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_CONFIG                                                                            0x0082
+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_STATUS                                                                            0x0083
+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_CONFIG                                                                            0x0084
+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_STATUS                                                                            0x0085
+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_CONFIG                                                                            0x0086
+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_STATUS                                                                            0x0087
+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN16_PG_CONFIG                                                                           0x0089
+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN16_PG_STATUS                                                                           0x008a
+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_CONFIG                                                                           0x008b
+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_STATUS                                                                           0x008c
+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_CONFIG                                                                           0x008d
+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_STATUS                                                                           0x008e
+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
+#define regDCPG_INTERRUPT_STATUS                                                                        0x008f
+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x0090
+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x0091
+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x0092
+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
+#define regDC_IP_REQUEST_CNTL                                                                           0x0093
+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define regDMCUB_REGION0_OFFSET                                                                         0x018e
+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION1_OFFSET                                                                         0x0190
+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION2_OFFSET                                                                         0x0192
+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION4_OFFSET                                                                         0x0196
+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION5_OFFSET                                                                         0x0198
+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION6_OFFSET                                                                         0x019a
+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION7_OFFSET                                                                         0x019c
+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_SEC_CNTL                                                                               0x01ce
+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_MEM_CNTL                                                                               0x01cf
+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define regDMCUB_SCRATCH0                                                                               0x01e3
+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH1                                                                               0x01e4
+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH2                                                                               0x01e5
+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH3                                                                               0x01e6
+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH4                                                                               0x01e7
+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH5                                                                               0x01e8
+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH6                                                                               0x01e9
+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH7                                                                               0x01ea
+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH8                                                                               0x01eb
+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH9                                                                               0x01ec
+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH10                                                                              0x01ed
+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH11                                                                              0x01ee
+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH12                                                                              0x01ef
+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH13                                                                              0x01f0
+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH14                                                                              0x01f1
+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH15                                                                              0x01f2
+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define regDMCUB_CNTL                                                                                   0x01f6
+#define regDMCUB_CNTL_BASE_IDX                                                                          2
+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define regDMCUB_PROC_ID                                                                                0x01ff
+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
+#define regDMCUB_CNTL2                                                                                  0x0200
+#define regDMCUB_CNTL2_BASE_IDX                                                                         2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define regDWB_MEM_PWR_CTRL                                                                             0x3229
+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regFC_MODE_CTRL                                                                                 0x322a
+#define regFC_MODE_CTRL_BASE_IDX                                                                        2
+#define regFC_FLOW_CTRL                                                                                 0x322b
+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define regFC_WINDOW_START                                                                              0x322c
+#define regFC_WINDOW_START_BASE_IDX                                                                     2
+#define regFC_WINDOW_SIZE                                                                               0x322d
+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define regFC_SOURCE_SIZE                                                                               0x322e
+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define regDWB_UPDATE_CTRL                                                                              0x322f
+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define regDWB_CRC_CTRL                                                                                 0x3230
+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define regDWB_CRC_MASK_R_G                                                                             0x3231
+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define regDWB_CRC_MASK_B_A                                                                             0x3232
+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define regDWB_CRC_VAL_R_G                                                                              0x3233
+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define regDWB_CRC_VAL_B_A                                                                              0x3234
+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define regDWB_OUT_CTRL                                                                                 0x3235
+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define regDWB_HOST_READ_CONTROL                                                                        0x3238
+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define regDWB_OVERFLOW_STATUS                                                                          0x3239
+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define regDWB_SOFT_RESET                                                                               0x323b
+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2
+#define regDWB_DEBUG_CTRL                                                                               0x323c
+#define regDWB_DEBUG_CTRL_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define regDWB_HDR_MULT_COEF                                                                            0x3294
+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define regDWB_OGAM_CONTROL                                                                             0x32a3
+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+// base address: 0xca20
+#define regDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x3288
+#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x3289
+#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON3_PERFCOUNTER_STATE                                                                0x328a
+#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON3_PERFMON_CNTL                                                                     0x328b
+#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON3_PERFMON_CNTL2                                                                    0x328c
+#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x328d
+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x328e
+#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON3_PERFMON_HI                                                                       0x328f
+#define regDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON3_PERFMON_LOW                                                                      0x3290
+#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define regVGA_RENDER_CONTROL                                                                           0x0000
+#define regVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define regVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define regVGA_MODE_CONTROL                                                                             0x0002
+#define regVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define regVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define regVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define regVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define regVGA_HDP_CONTROL                                                                              0x000a
+#define regVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define regVGA_CACHE_CONTROL                                                                            0x000b
+#define regVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define regD1VGA_CONTROL                                                                                0x000c
+#define regD1VGA_CONTROL_BASE_IDX                                                                       1
+#define regD2VGA_CONTROL                                                                                0x000e
+#define regD2VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_STATUS                                                                                   0x0010
+#define regVGA_STATUS_BASE_IDX                                                                          1
+#define regVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define regVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define regVGA_STATUS_CLEAR                                                                             0x0012
+#define regVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define regVGA_INTERRUPT_STATUS                                                                         0x0013
+#define regVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define regVGA_MAIN_CONTROL                                                                             0x0014
+#define regVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define regVGA_TEST_CONTROL                                                                             0x0015
+#define regVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define regVGA_QOS_CTRL                                                                                 0x0018
+#define regVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define regD3VGA_CONTROL                                                                                0x0038
+#define regD3VGA_CONTROL_BASE_IDX                                                                       1
+#define regD4VGA_CONTROL                                                                                0x0039
+#define regD4VGA_CONTROL_BASE_IDX                                                                       1
+#define regD5VGA_CONTROL                                                                                0x003a
+#define regD5VGA_CONTROL_BASE_IDX                                                                       1
+#define regD6VGA_CONTROL                                                                                0x003b
+#define regD6VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_SOURCE_SELECT                                                                            0x003c
+#define regVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define regMCIF_CONTROL                                                                                 0x034a
+#define regMCIF_CONTROL_BASE_IDX                                                                        2
+#define regMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_PITCH                                                                            0x0275
+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
+#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
+#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
+#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI                                                       0x02a7
+#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX                                              2
+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define regMCIF_WB_MIN_TTO                                                                              0x02a9
+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0xd48
+#define regDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352
+#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353
+#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354
+#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON4_PERFMON_CNTL                                                                     0x0355
+#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356
+#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357
+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358
+#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON4_PERFMON_HI                                                                       0x0359
+#define regDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON4_PERFMON_LOW                                                                      0x035a
+#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define regMCIF_WB_WATERMARK                                                                            0x02ab
+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define regMMHUBBUB_CTRL                                                                                0x0333
+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
+#define regWBIF0_MISC_CTRL                                                                              0x0335
+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regVGA_SRC_SPLIT_CNTL                                                                           0x033e
+#define regVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033f
+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x0340
+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0341
+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regMMHUBBUB_SOFT_RESET                                                                          0x0342
+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDMU_IF_ERR_STATUS                                                                            0x0346
+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0347
+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0349
+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define regAZALIA_AUDIO_DTO                                                                             0x03c3
+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define regAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC0_RESULT                                                                           0x03e7
+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC1_RESULT                                                                           0x03ec
+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define regAZ_CLOCK_CNTL                                                                                0x0372
+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+// base address: 0xde8
+#define regDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a
+#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b
+#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c
+#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON5_PERFMON_CNTL                                                                     0x037d
+#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e
+#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f
+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380
+#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON5_PERFMON_HI                                                                       0x0381
+#define regDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON5_PERFMON_LOW                                                                      0x0382
+#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
+// base address: 0x0
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fd
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x04fe
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x04ff
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A                                                   0x0500
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0501
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A                                                    0x0502
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x0503
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0504
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0505
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0506
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0507
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0508
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B                                                   0x0509
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050a
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B                                                    0x050b
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x050c
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x050d
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x050e
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x050f
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0510
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0511
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C                                                   0x0512
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0513
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C                                                    0x0514
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0515
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0516
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0517
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D                                                   0x051b
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051c
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D                                                    0x051d
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051e
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x051f
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0520
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x0521
+#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0522
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0523
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0524
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0525
+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0526
+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0527
+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0528
+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0529
+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052a
+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052b
+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052c
+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define regVTG0_CONTROL                                                                                 0x052d
+#define regVTG0_CONTROL_BASE_IDX                                                                        2
+#define regVTG1_CONTROL                                                                                 0x052e
+#define regVTG1_CONTROL_BASE_IDX                                                                        2
+#define regVTG2_CONTROL                                                                                 0x052f
+#define regVTG2_CONTROL_BASE_IDX                                                                        2
+#define regVTG3_CONTROL                                                                                 0x0530
+#define regVTG3_CONTROL_BASE_IDX                                                                        2
+#define regDCHUBBUB_SOFT_RESET                                                                          0x0531
+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0532
+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regDCFCLK_CNTL                                                                                  0x0533
+#define regDCFCLK_CNTL_BASE_IDX                                                                         2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0534
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0535
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0536
+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0537
+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053d
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053e
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053f
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define regFMON_CTRL                                                                                    0x0540
+#define regFMON_CTRL_BASE_IDX                                                                           2
+#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x0541
+#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
+#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x0542
+#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
+// base address: 0x0
+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+#define regVM_REQUEST_PHYSICAL                                                                          0x0472
+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define regDCN_VM_FB_OFFSET                                                                             0x0477
+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define regDCN_VM_AGP_BOT                                                                               0x0478
+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_TOP                                                                               0x0479
+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_BASE                                                                              0x047a
+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0483
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0484
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
+// base address: 0x0
+#define regDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04af
+#define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04b0
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04b1
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04b2
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04b3
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04b4
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04b5
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04b6
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04b7
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04b8
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04b9
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04ba
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04bb
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04bc
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04bd
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04be
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04bf
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04c0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04c1
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define regDCHUBBUB_CRC_CTRL                                                                            0x04c2
+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04c3
+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04c4
+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04c5
+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04c6
+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04c7
+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_DCC_STAT0                                                                           0x04c8
+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT1                                                                           0x04c9
+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT2                                                                           0x04ca
+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04cb
+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
+#define regDCHUBBUB_DET0_CTRL                                                                           0x04cc
+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET1_CTRL                                                                           0x04cd
+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET2_CTRL                                                                           0x04ce
+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET3_CTRL                                                                           0x04cf
+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04d1
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04d2
+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04d3
+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04d4
+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04d5
+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1534
+#define regDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d
+#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e
+#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f
+#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON6_PERFMON_CNTL                                                                     0x0550
+#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551
+#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552
+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553
+#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON6_PERFMON_HI                                                                       0x0554
+#define regDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON6_PERFMON_LOW                                                                      0x0555
+#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0629
+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062a
+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062b
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062c
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062d
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062e
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062f
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0630
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0631
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0632
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0633
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0634
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0635
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0636
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0643
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0644
+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0645
+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0646
+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0647
+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0648
+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0649
+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064a
+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064b
+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064c
+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064d
+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064e
+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064f
+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0650
+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0651
+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0652
+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0653
+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0654
+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0655
+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0656
+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0657
+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0658
+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0659
+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065a
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065b
+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065c
+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065d
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065e
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065f
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0660
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0663
+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0664
+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0665
+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0666
+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0667
+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0668
+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a74
+#define regDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d
+#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e
+#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f
+#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0
+#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1
+#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2
+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3
+#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON7_PERFMON_HI                                                                       0x06a4
+#define regDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON7_PERFMON_LOW                                                                      0x06a5
+#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0705
+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0706
+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0707
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0708
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0709
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070a
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070b
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070c
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070d
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070e
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070f
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x0710
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0711
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0712
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071f
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x0720
+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0721
+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0722
+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0723
+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0724
+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0725
+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0726
+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0727
+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0728
+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0729
+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072a
+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072b
+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072c
+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072d
+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072e
+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072f
+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0730
+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0731
+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0732
+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0733
+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0734
+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0735
+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0736
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0737
+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0738
+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0739
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073a
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073b
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073c
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073f
+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0740
+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0741
+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0742
+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0743
+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0744
+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1de4
+#define regDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779
+#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a
+#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b
+#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON8_PERFMON_CNTL                                                                     0x077c
+#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d
+#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e
+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f
+#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON8_PERFMON_HI                                                                       0x0780
+#define regDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON8_PERFMON_LOW                                                                      0x0781
+#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07af
+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e1
+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e2
+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e3
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e4
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e5
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e6
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e7
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e8
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e9
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ea
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07eb
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07ec
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ed
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ee
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fb
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fc
+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fd
+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fe
+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07ff
+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0800
+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0801
+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0802
+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0803
+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0804
+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0805
+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0806
+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0807
+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0808
+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0809
+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080a
+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080b
+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080c
+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080d
+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080e
+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080f
+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0810
+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0811
+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0812
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0813
+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0814
+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0815
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0816
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0817
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0818
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081b
+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081c
+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081d
+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081e
+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081f
+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0820
+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2154
+#define regDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855
+#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856
+#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857
+#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON9_PERFMON_CNTL                                                                     0x0858
+#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859
+#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a
+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b
+#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON9_PERFMON_HI                                                                       0x085c
+#define regDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON9_PERFMON_LOW                                                                      0x085d
+#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088b
+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bd
+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08be
+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08bf
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c0
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c1
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c3
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c4
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c5
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c6
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c7
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c8
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c9
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08ca
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d7
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d8
+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d9
+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08da
+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08db
+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08dc
+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dd
+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08de
+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08df
+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e0
+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e1
+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e3
+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e4
+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e5
+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e6
+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e7
+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e8
+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e9
+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ea
+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08eb
+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ec
+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ed
+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ee
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ef
+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f0
+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f1
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f3
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f4
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f7
+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f8
+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f9
+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fa
+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fb
+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fc
+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x24c4
+#define regDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931
+#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932
+#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933
+#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON10_PERFMON_CNTL                                                                    0x0934
+#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935
+#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936
+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937
+#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON10_PERFMON_HI                                                                      0x0938
+#define regDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON10_PERFMON_LOW                                                                     0x0939
+#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL0_SCL_MODE                                                                               0x0cfb
+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_RECOUT_START                                                                           0x0d11
+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL0_MPC_SIZE                                                                               0x0d13
+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define regCM0_CM_CONTROL                                                                               0x0d20
+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_CONTROL                                                                       0x0d87
+#define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d88
+#define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d89
+#define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM0_CM_BLNDGAM_LUT_CONTROL                                                                   0x0d8a
+#define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d8b
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d8c
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d8d
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0d8e
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0d8f
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0d90
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0d91
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0d92
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0d93
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d94
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d95
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d96
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d97
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d98
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d99
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0d9a
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0d9b
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0d9c
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d9d
+#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d9e
+#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d9f
+#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0da0
+#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0da1
+#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0da2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0da3
+#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0da4
+#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0da5
+#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0da6
+#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0da7
+#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0da8
+#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0da9
+#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0daa
+#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0dab
+#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0dac
+#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0dad
+#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0dae
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0daf
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0db0
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0db1
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0db2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0db3
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0db4
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0db5
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0db6
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0db7
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0db8
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0db9
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0dba
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0dbb
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0dbc
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0dbd
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0dbe
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0dbf
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0dc0
+#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0dc1
+#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0dc2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0dc3
+#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0dc4
+#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0dc5
+#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0dc6
+#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0dc7
+#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0dc8
+#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0dc9
+#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0dca
+#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0dcb
+#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0dcc
+#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0dcd
+#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0dce
+#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0dcf
+#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0dd0
+#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0dd1
+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0dd2
+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0dd3
+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM0_CM_DEALPHA                                                                               0x0dd5
+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM0_CM_COEF_FORMAT                                                                           0x0dd6
+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM0_CM_SHAPER_CONTROL                                                                        0x0dd7
+#define regCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_SHAPER_OFFSET_R                                                                       0x0dd8
+#define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_OFFSET_G                                                                       0x0dd9
+#define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_OFFSET_B                                                                       0x0dda
+#define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_SCALE_R                                                                        0x0ddb
+#define regCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM0_CM_SHAPER_SCALE_G_B                                                                      0x0ddc
+#define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM0_CM_SHAPER_LUT_INDEX                                                                      0x0ddd
+#define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_SHAPER_LUT_DATA                                                                       0x0dde
+#define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0ddf
+#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0de0
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0de1
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0de2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0de3
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0de4
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0de5
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0de6
+#define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0de7
+#define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0de8
+#define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0de9
+#define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dea
+#define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0deb
+#define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dec
+#define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0ded
+#define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dee
+#define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0def
+#define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0df0
+#define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0df1
+#define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0df2
+#define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0df3
+#define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0df4
+#define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0df5
+#define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0df6
+#define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0df7
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0df8
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0df9
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dfa
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dfb
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dfc
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dfd
+#define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dfe
+#define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dff
+#define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0e00
+#define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0e01
+#define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0e02
+#define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0e03
+#define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0e04
+#define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0e05
+#define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0e06
+#define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0e07
+#define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0e08
+#define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0e09
+#define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0e0a
+#define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0e0b
+#define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0e0c
+#define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0e0d
+#define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_MEM_PWR_CTRL2                                                                         0x0e0e
+#define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_STATUS2                                                                       0x0e0f
+#define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM0_CM_3DLUT_MODE                                                                            0x0e10
+#define regCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM0_CM_3DLUT_INDEX                                                                           0x0e11
+#define regCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM0_CM_3DLUT_DATA                                                                            0x0e12
+#define regCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM0_CM_3DLUT_DATA_30BIT                                                                      0x0e13
+#define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0e14
+#define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0e15
+#define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0e16
+#define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0e17
+#define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18
+#define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0e19
+#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0e1a
+#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3890
+#define regDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24
+#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25
+#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26
+#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27
+#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28
+#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29
+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a
+#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON11_PERFMON_HI                                                                      0x0e2b
+#define regDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c
+#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL1_SCL_MODE                                                                               0x0e66
+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_RECOUT_START                                                                           0x0e7c
+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL1_MPC_SIZE                                                                               0x0e7e
+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define regCM1_CM_CONTROL                                                                               0x0e8b
+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_CONTROL                                                                       0x0ef2
+#define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ef3
+#define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ef4
+#define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM1_CM_BLNDGAM_LUT_CONTROL                                                                   0x0ef5
+#define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ef6
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ef7
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ef8
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0ef9
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0efa
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0efb
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0efc
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0efd
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0efe
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0eff
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0f00
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0f01
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0f02
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0f03
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0f04
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0f05
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0f06
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0f07
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0f08
+#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0f09
+#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0f0a
+#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0f0b
+#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0f0c
+#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0f0d
+#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0f0e
+#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0f0f
+#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0f10
+#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0f11
+#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0f12
+#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0f13
+#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0f14
+#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0f15
+#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0f16
+#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0f17
+#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0f18
+#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0f19
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0f1a
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0f1b
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0f1c
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0f1d
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0f1e
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0f1f
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0f20
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0f21
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0f22
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0f23
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0f24
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0f25
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0f26
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0f27
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0f28
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0f29
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0f2a
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0f2b
+#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0f2c
+#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0f2d
+#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0f2e
+#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0f2f
+#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f30
+#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f31
+#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f32
+#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f33
+#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f34
+#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f35
+#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f36
+#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f37
+#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f38
+#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f39
+#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f3a
+#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f3b
+#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0f3c
+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0f3d
+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0f3e
+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM1_CM_DEALPHA                                                                               0x0f40
+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM1_CM_COEF_FORMAT                                                                           0x0f41
+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM1_CM_SHAPER_CONTROL                                                                        0x0f42
+#define regCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_SHAPER_OFFSET_R                                                                       0x0f43
+#define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_OFFSET_G                                                                       0x0f44
+#define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_OFFSET_B                                                                       0x0f45
+#define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_SCALE_R                                                                        0x0f46
+#define regCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f47
+#define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f48
+#define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_SHAPER_LUT_DATA                                                                       0x0f49
+#define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f4a
+#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f4b
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f4c
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f4d
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f4e
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f4f
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f50
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f51
+#define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f52
+#define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f53
+#define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f54
+#define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f55
+#define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f56
+#define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f57
+#define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f58
+#define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f59
+#define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f5a
+#define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f5b
+#define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f5c
+#define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f5d
+#define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f5e
+#define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f5f
+#define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f60
+#define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f61
+#define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f62
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f63
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f64
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f65
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f66
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f67
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f68
+#define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f69
+#define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f6a
+#define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f6b
+#define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f6c
+#define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f6d
+#define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f6e
+#define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f6f
+#define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f70
+#define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f71
+#define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f72
+#define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f73
+#define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f74
+#define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f75
+#define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f76
+#define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f77
+#define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f78
+#define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_MEM_PWR_CTRL2                                                                         0x0f79
+#define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_STATUS2                                                                       0x0f7a
+#define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM1_CM_3DLUT_MODE                                                                            0x0f7b
+#define regCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM1_CM_3DLUT_INDEX                                                                           0x0f7c
+#define regCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM1_CM_3DLUT_DATA                                                                            0x0f7d
+#define regCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f7e
+#define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f7f
+#define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f80
+#define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f81
+#define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f82
+#define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83
+#define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f84
+#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0f85
+#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3e3c
+#define regDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f
+#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90
+#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91
+#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92
+#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93
+#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94
+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95
+#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON12_PERFMON_HI                                                                      0x0f96
+#define regDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON12_PERFMON_LOW                                                                     0x0f97
+#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL2_SCL_MODE                                                                               0x0fd1
+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_RECOUT_START                                                                           0x0fe7
+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL2_MPC_SIZE                                                                               0x0fe9
+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define regCM2_CM_CONTROL                                                                               0x0ff6
+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM2_CM_BIAS_CR_R                                                                             0x1011
+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_CONTROL                                                                       0x105d
+#define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x105e
+#define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM2_CM_BLNDGAM_LUT_DATA                                                                      0x105f
+#define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM2_CM_BLNDGAM_LUT_CONTROL                                                                   0x1060
+#define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x1061
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x1062
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x1063
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x1064
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x1065
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x1066
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x1067
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x1068
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x1069
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x106a
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x106b
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x106c
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x106d
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x106e
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x106f
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x1070
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x1071
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x1072
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1073
+#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x1074
+#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x1075
+#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x1076
+#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x1077
+#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x1078
+#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x1079
+#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x107a
+#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x107b
+#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x107c
+#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x107d
+#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x107e
+#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x107f
+#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1080
+#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1081
+#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1082
+#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1083
+#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x1084
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x1085
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x1086
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x1087
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x1088
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x1089
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x108a
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x108b
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x108c
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x108d
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x108e
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x108f
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1090
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1091
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1092
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x1093
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x1094
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1095
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1096
+#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1097
+#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1098
+#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1099
+#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x109a
+#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x109b
+#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x109c
+#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x109d
+#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x109e
+#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x109f
+#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x10a0
+#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x10a1
+#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x10a2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x10a3
+#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x10a4
+#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x10a5
+#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x10a6
+#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM2_CM_HDR_MULT_COEF                                                                         0x10a7
+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x10a8
+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x10a9
+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM2_CM_DEALPHA                                                                               0x10ab
+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM2_CM_COEF_FORMAT                                                                           0x10ac
+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM2_CM_SHAPER_CONTROL                                                                        0x10ad
+#define regCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_SHAPER_OFFSET_R                                                                       0x10ae
+#define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_OFFSET_G                                                                       0x10af
+#define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_OFFSET_B                                                                       0x10b0
+#define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_SCALE_R                                                                        0x10b1
+#define regCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM2_CM_SHAPER_SCALE_G_B                                                                      0x10b2
+#define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM2_CM_SHAPER_LUT_INDEX                                                                      0x10b3
+#define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_SHAPER_LUT_DATA                                                                       0x10b4
+#define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x10b5
+#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x10b6
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x10b7
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x10b8
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x10b9
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x10ba
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x10bb
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x10bc
+#define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x10bd
+#define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x10be
+#define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x10bf
+#define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x10c0
+#define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x10c1
+#define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x10c2
+#define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x10c3
+#define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x10c4
+#define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x10c5
+#define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x10c6
+#define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x10c7
+#define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x10c8
+#define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x10c9
+#define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x10ca
+#define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x10cb
+#define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x10cc
+#define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x10cd
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x10ce
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x10cf
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10d0
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10d1
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10d2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10d3
+#define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10d4
+#define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10d5
+#define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10d6
+#define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10d7
+#define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10d8
+#define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10d9
+#define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10da
+#define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10db
+#define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10dc
+#define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10dd
+#define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10de
+#define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10df
+#define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10e0
+#define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10e1
+#define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10e2
+#define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10e3
+#define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_MEM_PWR_CTRL2                                                                         0x10e4
+#define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_STATUS2                                                                       0x10e5
+#define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM2_CM_3DLUT_MODE                                                                            0x10e6
+#define regCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM2_CM_3DLUT_INDEX                                                                           0x10e7
+#define regCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM2_CM_3DLUT_DATA                                                                            0x10e8
+#define regCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM2_CM_3DLUT_DATA_30BIT                                                                      0x10e9
+#define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ea
+#define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10eb
+#define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10ec
+#define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10ed
+#define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10ee
+#define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x10ef
+#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x10f0
+#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x43e8
+#define regDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa
+#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb
+#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc
+#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd
+#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe
+#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff
+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100
+#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON13_PERFMON_HI                                                                      0x1101
+#define regDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON13_PERFMON_LOW                                                                     0x1102
+#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL3_SCL_MODE                                                                               0x113c
+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL3_DSCL_CONTROL                                                                           0x113e
+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL3_DSCL_UPDATE                                                                            0x114c
+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL3_OTG_H_BLANK                                                                            0x1150
+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_OTG_V_BLANK                                                                            0x1151
+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_RECOUT_START                                                                           0x1152
+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL3_RECOUT_SIZE                                                                            0x1153
+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL3_MPC_SIZE                                                                               0x1154
+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL3_LB_V_COUNTER                                                                           0x1157
+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL3_OBUF_CONTROL                                                                           0x115a
+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define regCM3_CM_CONTROL                                                                               0x1161
+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM3_CM_BIAS_CR_R                                                                             0x117c
+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_CONTROL                                                                       0x11c8
+#define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11c9
+#define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11ca
+#define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM3_CM_BLNDGAM_LUT_CONTROL                                                                   0x11cb
+#define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11cc
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11cd
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11ce
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x11cf
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x11d0
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x11d1
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x11d2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x11d3
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x11d4
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11d5
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11d6
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11d7
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11d8
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11d9
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11da
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x11db
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x11dc
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x11dd
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11de
+#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11df
+#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11e0
+#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11e1
+#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11e2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11e3
+#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11e4
+#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11e5
+#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11e6
+#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11e7
+#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11e8
+#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11e9
+#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11ea
+#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11eb
+#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11ec
+#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11ed
+#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11ee
+#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11ef
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11f0
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11f1
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x11f2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x11f3
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x11f4
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x11f5
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x11f6
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x11f7
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11f8
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11f9
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11fa
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11fb
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11fc
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11fd
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x11fe
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x11ff
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1200
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1201
+#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1202
+#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1203
+#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1204
+#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x1205
+#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x1206
+#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x1207
+#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x1208
+#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x1209
+#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x120a
+#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x120b
+#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x120c
+#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x120d
+#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x120e
+#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x120f
+#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1210
+#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1211
+#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM3_CM_HDR_MULT_COEF                                                                         0x1212
+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x1213
+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x1214
+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM3_CM_DEALPHA                                                                               0x1216
+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM3_CM_COEF_FORMAT                                                                           0x1217
+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM3_CM_SHAPER_CONTROL                                                                        0x1218
+#define regCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_SHAPER_OFFSET_R                                                                       0x1219
+#define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_OFFSET_G                                                                       0x121a
+#define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_OFFSET_B                                                                       0x121b
+#define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_SCALE_R                                                                        0x121c
+#define regCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM3_CM_SHAPER_SCALE_G_B                                                                      0x121d
+#define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM3_CM_SHAPER_LUT_INDEX                                                                      0x121e
+#define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_SHAPER_LUT_DATA                                                                       0x121f
+#define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1220
+#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1221
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1222
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1223
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1224
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x1225
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x1226
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x1227
+#define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x1228
+#define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x1229
+#define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x122a
+#define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x122b
+#define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x122c
+#define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x122d
+#define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x122e
+#define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x122f
+#define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1230
+#define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1231
+#define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1232
+#define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1233
+#define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1234
+#define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1235
+#define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1236
+#define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1237
+#define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1238
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1239
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x123a
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x123b
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x123c
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x123d
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x123e
+#define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x123f
+#define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1240
+#define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1241
+#define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1242
+#define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1243
+#define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1244
+#define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1245
+#define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1246
+#define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1247
+#define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1248
+#define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1249
+#define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x124a
+#define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x124b
+#define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x124c
+#define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x124d
+#define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x124e
+#define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_MEM_PWR_CTRL2                                                                         0x124f
+#define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_STATUS2                                                                       0x1250
+#define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM3_CM_3DLUT_MODE                                                                            0x1251
+#define regCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM3_CM_3DLUT_INDEX                                                                           0x1252
+#define regCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM3_CM_3DLUT_DATA                                                                            0x1253
+#define regCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM3_CM_3DLUT_DATA_30BIT                                                                      0x1254
+#define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1255
+#define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1256
+#define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1257
+#define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1258
+#define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1259
+#define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x125a
+#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x125b
+#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x4994
+#define regDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265
+#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266
+#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267
+#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON14_PERFMON_CNTL                                                                    0x1268
+#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269
+#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a
+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b
+#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON14_PERFMON_HI                                                                      0x126c
+#define regDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON14_PERFMON_LOW                                                                     0x126d
+#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_CONTROL                                                                           0x0003
+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC0_MPCC_BG_R_CR                                                                           0x0009
+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000a
+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000b
+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000c
+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC0_MPCC_STATUS                                                                            0x000d
+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+// base address: 0x80
+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0020
+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0021
+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_OPP_ID                                                                            0x0022
+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_CONTROL                                                                           0x0023
+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0024
+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x0025
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x0026
+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x0027
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0028
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC1_MPCC_BG_R_CR                                                                           0x0029
+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BG_G_Y                                                                            0x002a
+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_BG_B_CB                                                                           0x002b
+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x002c
+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC1_MPCC_STATUS                                                                            0x002d
+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+// base address: 0x100
+#define regMPCC2_MPCC_TOP_SEL                                                                           0x0040
+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BOT_SEL                                                                           0x0041
+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_OPP_ID                                                                            0x0042
+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_CONTROL                                                                           0x0043
+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x0044
+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x0045
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0046
+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0047
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0048
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0049
+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BG_G_Y                                                                            0x004a
+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_BG_B_CB                                                                           0x004b
+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x004c
+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC2_MPCC_STATUS                                                                            0x004d
+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+// base address: 0x180
+#define regMPCC3_MPCC_TOP_SEL                                                                           0x0060
+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0061
+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_OPP_ID                                                                            0x0062
+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_CONTROL                                                                           0x0063
+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0064
+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0065
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0066
+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0067
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0068
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0069
+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BG_G_Y                                                                            0x006a
+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_BG_B_CB                                                                           0x006b
+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x006c
+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC3_MPCC_STATUS                                                                            0x006d
+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define regMPC_CLOCK_CONTROL                                                                            0x0500
+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define regMPC_SOFT_RESET                                                                               0x0501
+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define regMPC_CRC_CTRL                                                                                 0x0502
+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define regMPC_CRC_SEL_CONTROL                                                                          0x0503
+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define regMPC_CRC_RESULT_AR                                                                            0x0504
+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_GB                                                                            0x0505
+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_C                                                                             0x0506
+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define regMPC_PERFMON_EVENT_CTRL                                                                       0x0509
+#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3
+#define regMPC_BYPASS_BG_AR                                                                             0x050a
+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_GB                                                                             0x050b
+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define regMPC_HOST_READ_CONTROL                                                                        0x050c
+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define regMPC_DPP_PENDING_STATUS                                                                       0x050d
+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define regMPC_PENDING_STATUS_MISC                                                                      0x050e
+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x050f
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x0510
+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET0                                                                        0x0511
+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x0512
+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x0513
+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x0514
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x0515
+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET1                                                                        0x0516
+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x0517
+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x0518
+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x0519
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x051a
+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET2                                                                        0x051b
+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x051c
+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x051d
+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x051e
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x051f
+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET3                                                                        0x0520
+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x0521
+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x0522
+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regMPC_DWB0_MUX                                                                                 0x055c
+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1901c
+#define regDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x08c7
+#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       3
+#define regDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x08c8
+#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
+#define regDC_PERFMON15_PERFCOUNTER_STATE                                                               0x08c9
+#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      3
+#define regDC_PERFMON15_PERFMON_CNTL                                                                    0x08ca
+#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           3
+#define regDC_PERFMON15_PERFMON_CNTL2                                                                   0x08cb
+#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          3
+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x08cc
+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
+#define regDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x08cd
+#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
+#define regDC_PERFMON15_PERFMON_HI                                                                      0x08ce
+#define regDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             3
+#define regDC_PERFMON15_PERFMON_LOW                                                                     0x08cf
+#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x0100
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x0101
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x0102
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x0103
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0104
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0105
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0106
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0107
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0108
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0109
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x010a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x010b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x010c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x010d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x010e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x010f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0110
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0111
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0112
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0113
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0114
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0115
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0116
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0117
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0118
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0119
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x011a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x011b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x011c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x011d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x011e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x011f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0120
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0121
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0122
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0123
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0124
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0125
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0126
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0127
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0128
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0129
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x012a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x012b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x012c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x012d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x012e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x012f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0130
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0131
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0132
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0133
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0134
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0135
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0136
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0137
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0138
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0139
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x013a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x013b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x013c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x013d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x013e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x013f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0140
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0141
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0142
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0143
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0144
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0145
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0146
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0147
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0148
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0149
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x014a
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x014b
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x014c
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x014d
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x014e
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x014f
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0150
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0151
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0152
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0153
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0154
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0155
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0156
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0157
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x200
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0180
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0181
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0182
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0183
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0184
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0185
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0186
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0187
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0188
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0189
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x018a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x018b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x018c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x018d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x018e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x018f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0190
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0191
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0192
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0193
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0194
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0195
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0196
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0197
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0198
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0199
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x019a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x019b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x019c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x019d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x019e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x019f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01a0
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01a1
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01a2
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01a3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01a4
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01a5
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01a6
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01a7
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01a8
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01a9
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01aa
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ab
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ac
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ad
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01ae
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01af
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01b0
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01b1
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01b2
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01b3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01b4
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01b5
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01b6
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01b7
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01b8
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01b9
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01ba
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01bb
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01bc
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01bd
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01be
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01bf
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01c0
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01c1
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01c2
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01c3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01c4
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01c5
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01c6
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01c7
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01c8
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01c9
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ca
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x01cb
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01cc
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01cd
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01ce
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01cf
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01d0
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01d1
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01d2
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01d3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01d4
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01d5
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01d6
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01d7
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x400
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0200
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0201
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0202
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0203
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0204
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0205
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0206
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0207
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0208
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0209
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x020a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x020b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x020c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x020d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x020e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x020f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0210
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0211
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0212
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0213
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0214
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0215
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0216
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0217
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0218
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0219
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x021a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x021b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x021c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x021d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x021e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x021f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0220
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0221
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0222
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0223
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0224
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0225
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0226
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0227
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0228
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0229
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x022a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x022b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x022c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x022d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x022e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x022f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0230
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0231
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0232
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0233
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0234
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0235
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0236
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0237
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0238
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0239
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x023a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x023b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x023c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x023d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x023e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x023f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0240
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0241
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0242
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0243
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0244
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0245
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0246
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0247
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0248
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0249
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x024a
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x024b
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x024c
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x024d
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x024e
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x024f
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0250
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0251
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0252
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0253
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0254
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0255
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0256
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0257
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x600
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x0280
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x0281
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x0282
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x0283
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0284
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0285
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0286
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0287
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0288
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0289
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x028a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x028b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x028c
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x028d
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x028e
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x028f
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0290
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0291
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0292
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0293
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0294
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0295
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0296
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0297
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0298
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0299
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x029a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x029b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x029c
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x029d
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x029e
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x029f
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x02a0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x02a1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x02a2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x02a3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x02a4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x02a5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x02a6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x02a7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x02a8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x02a9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x02aa
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x02ab
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x02ac
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x02ad
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x02ae
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x02af
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x02b0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x02b1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x02b2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x02b3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x02b4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x02b5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x02b6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x02b7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x02b8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x02b9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x02ba
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x02bb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x02bc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x02bd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x02be
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x02bf
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x02c0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x02c1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x02c2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x02c3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x02c4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x02c5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x02c6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x02c7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x02c8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x02c9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x02ca
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x02cb
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x02cc
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x02cd
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x02ce
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x02cf
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x02d0
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x02d1
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x02d2
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x02d3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x02d4
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x02d5
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x02d6
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x02d7
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define regMPC_OUT0_MUX                                                                                 0x0580
+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x0581
+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x0582
+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x0583
+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT1_MUX                                                                                 0x0584
+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x0585
+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x0586
+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x0587
+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT2_MUX                                                                                 0x0588
+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x0589
+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x058a
+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x058b
+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT3_MUX                                                                                 0x058c
+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x058d
+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x058e
+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x058f
+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x05a0
+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define regMPC_OUT0_CSC_MODE                                                                            0x05a1
+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x05a2
+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x05a3
+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x05a4
+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x05a5
+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x05a6
+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x05a7
+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x05a8
+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x05a9
+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x05aa
+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x05ab
+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x05ac
+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x05ad
+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_MODE                                                                            0x05ae
+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x05af
+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x05b0
+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x05b1
+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x05b2
+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x05b3
+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x05b4
+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x05b5
+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x05b6
+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x05b7
+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x05b8
+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x05b9
+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x05ba
+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_MODE                                                                            0x05bb
+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x05bc
+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x05bd
+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x05be
+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x05bf
+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x05c0
+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x05c1
+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x05c2
+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x05c3
+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x05c4
+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x05c5
+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x05c6
+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x05c7
+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_MODE                                                                            0x05c8
+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x05c9
+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x05ca
+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x05cb
+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x05cc
+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x05cd
+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x05ce
+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x05cf
+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x05d0
+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x05d1
+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x05d2
+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x05d3
+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x05d4
+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+// base address: 0x0
+#define regMPC_RMU_CONTROL                                                                              0x0680
+#define regMPC_RMU_CONTROL_BASE_IDX                                                                     3
+#define regMPC_RMU_MEM_PWR_CTRL                                                                         0x0681
+#define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX                                                                3
+#define regMPC_RMU0_SHAPER_CONTROL                                                                      0x0682
+#define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX                                                             3
+#define regMPC_RMU0_SHAPER_OFFSET_R                                                                     0x0683
+#define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_OFFSET_G                                                                     0x0684
+#define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_OFFSET_B                                                                     0x0685
+#define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_SCALE_R                                                                      0x0686
+#define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX                                                             3
+#define regMPC_RMU0_SHAPER_SCALE_G_B                                                                    0x0687
+#define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX                                                           3
+#define regMPC_RMU0_SHAPER_LUT_INDEX                                                                    0x0688
+#define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX                                                           3
+#define regMPC_RMU0_SHAPER_LUT_DATA                                                                     0x0689
+#define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK                                                            0x068a
+#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B                                                            0x068b
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G                                                            0x068c
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R                                                            0x068d
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B                                                              0x068e
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G                                                              0x068f
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R                                                              0x0690
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1                                                              0x0691
+#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3                                                              0x0692
+#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5                                                              0x0693
+#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7                                                              0x0694
+#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9                                                              0x0695
+#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11                                                            0x0696
+#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13                                                            0x0697
+#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15                                                            0x0698
+#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17                                                            0x0699
+#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19                                                            0x069a
+#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21                                                            0x069b
+#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23                                                            0x069c
+#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25                                                            0x069d
+#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27                                                            0x069e
+#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29                                                            0x069f
+#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31                                                            0x06a0
+#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33                                                            0x06a1
+#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B                                                            0x06a2
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G                                                            0x06a3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R                                                            0x06a4
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B                                                              0x06a5
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G                                                              0x06a6
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R                                                              0x06a7
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1                                                              0x06a8
+#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3                                                              0x06a9
+#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5                                                              0x06aa
+#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7                                                              0x06ab
+#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9                                                              0x06ac
+#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11                                                            0x06ad
+#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13                                                            0x06ae
+#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15                                                            0x06af
+#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17                                                            0x06b0
+#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19                                                            0x06b1
+#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21                                                            0x06b2
+#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23                                                            0x06b3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25                                                            0x06b4
+#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27                                                            0x06b5
+#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29                                                            0x06b6
+#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31                                                            0x06b7
+#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33                                                            0x06b8
+#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU0_3DLUT_MODE                                                                          0x06b9
+#define regMPC_RMU0_3DLUT_MODE_BASE_IDX                                                                 3
+#define regMPC_RMU0_3DLUT_INDEX                                                                         0x06ba
+#define regMPC_RMU0_3DLUT_INDEX_BASE_IDX                                                                3
+#define regMPC_RMU0_3DLUT_DATA                                                                          0x06bb
+#define regMPC_RMU0_3DLUT_DATA_BASE_IDX                                                                 3
+#define regMPC_RMU0_3DLUT_DATA_30BIT                                                                    0x06bc
+#define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX                                                           3
+#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL                                                            0x06bd
+#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
+#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR                                                               0x06be
+#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_R                                                                  0x06bf
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_G                                                                  0x06c0
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_B                                                                  0x06c1
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
+#define regMPC_RMU1_SHAPER_CONTROL                                                                      0x06c2
+#define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX                                                             3
+#define regMPC_RMU1_SHAPER_OFFSET_R                                                                     0x06c3
+#define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_OFFSET_G                                                                     0x06c4
+#define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_OFFSET_B                                                                     0x06c5
+#define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_SCALE_R                                                                      0x06c6
+#define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX                                                             3
+#define regMPC_RMU1_SHAPER_SCALE_G_B                                                                    0x06c7
+#define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX                                                           3
+#define regMPC_RMU1_SHAPER_LUT_INDEX                                                                    0x06c8
+#define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX                                                           3
+#define regMPC_RMU1_SHAPER_LUT_DATA                                                                     0x06c9
+#define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK                                                            0x06ca
+#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B                                                            0x06cb
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G                                                            0x06cc
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R                                                            0x06cd
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B                                                              0x06ce
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G                                                              0x06cf
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R                                                              0x06d0
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1                                                              0x06d1
+#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3                                                              0x06d2
+#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5                                                              0x06d3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7                                                              0x06d4
+#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9                                                              0x06d5
+#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11                                                            0x06d6
+#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13                                                            0x06d7
+#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15                                                            0x06d8
+#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17                                                            0x06d9
+#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19                                                            0x06da
+#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21                                                            0x06db
+#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23                                                            0x06dc
+#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25                                                            0x06dd
+#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27                                                            0x06de
+#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29                                                            0x06df
+#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31                                                            0x06e0
+#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33                                                            0x06e1
+#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B                                                            0x06e2
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G                                                            0x06e3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R                                                            0x06e4
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B                                                              0x06e5
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G                                                              0x06e6
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R                                                              0x06e7
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1                                                              0x06e8
+#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3                                                              0x06e9
+#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5                                                              0x06ea
+#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7                                                              0x06eb
+#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9                                                              0x06ec
+#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11                                                            0x06ed
+#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13                                                            0x06ee
+#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15                                                            0x06ef
+#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17                                                            0x06f0
+#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19                                                            0x06f1
+#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21                                                            0x06f2
+#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23                                                            0x06f3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25                                                            0x06f4
+#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27                                                            0x06f5
+#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29                                                            0x06f6
+#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31                                                            0x06f7
+#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33                                                            0x06f8
+#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU1_3DLUT_MODE                                                                          0x06f9
+#define regMPC_RMU1_3DLUT_MODE_BASE_IDX                                                                 3
+#define regMPC_RMU1_3DLUT_INDEX                                                                         0x06fa
+#define regMPC_RMU1_3DLUT_INDEX_BASE_IDX                                                                3
+#define regMPC_RMU1_3DLUT_DATA                                                                          0x06fb
+#define regMPC_RMU1_3DLUT_DATA_BASE_IDX                                                                 3
+#define regMPC_RMU1_3DLUT_DATA_30BIT                                                                    0x06fc
+#define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX                                                           3
+#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL                                                            0x06fd
+#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
+#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR                                                               0x06fe
+#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_R                                                                  0x06ff
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_G                                                                  0x0700
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_B                                                                  0x0701
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+// base address: 0x0
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+// base address: 0x104
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+// base address: 0x208
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05
+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+// base address: 0x30c
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46
+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define regDPG0_DPG_CONTROL                                                                             0x1854
+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG0_DPG_STATUS                                                                              0x185b
+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT0_FMT_CONTROL                                                                             0x1840
+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT0_FMT_422_CONTROL                                                                         0x1849
+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define regDPG1_DPG_CONTROL                                                                             0x18ae
+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG1_DPG_STATUS                                                                              0x18b5
+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT1_FMT_CONTROL                                                                             0x189a
+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define regDPG2_DPG_CONTROL                                                                             0x1908
+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909
+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a
+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b
+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c
+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d
+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG2_DPG_STATUS                                                                              0x190f
+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT2_FMT_CONTROL                                                                             0x18f4
+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd
+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define regDPG3_DPG_CONTROL                                                                             0x1962
+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963
+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964
+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965
+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966
+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967
+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG3_DPG_STATUS                                                                              0x1969
+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT3_FMT_CONTROL                                                                             0x194e
+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953
+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT3_FMT_422_CONTROL                                                                         0x1957
+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define regOPP_ABM_CONTROL                                                                              0x1a60
+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x6af8
+#define regDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe
+#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf
+#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0
+#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1
+#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2
+#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4
+#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON16_PERFMON_HI                                                                      0x1ac5
+#define regDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6
+#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+// base address: 0x0
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+// base address: 0x40
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+// base address: 0x80
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+// base address: 0x0
+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG0_OTG_CONTROL                                                                             0x1b41
+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG0_OTG_STATUS                                                                              0x1b49
+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG0_OTG_CRC_CNTL2                                                                           0x1b69
+#define regOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b89
+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b94
+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b95
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b96
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b97
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b98
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b99
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b9a
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b9b
+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9c
+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9d
+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9e
+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9f
+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1ba0
+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba2
+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+// base address: 0x200
+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG1_OTG_CONTROL                                                                             0x1bc1
+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG1_OTG_STATUS                                                                              0x1bc9
+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG1_OTG_CRC_CNTL2                                                                           0x1be9
+#define regOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c09
+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c14
+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c15
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c16
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c17
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c18
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c19
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c1a
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c1b
+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1c
+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1d
+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1e
+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1f
+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c20
+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c22
+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+// base address: 0x400
+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a
+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c
+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f
+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c37
+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
+#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG2_OTG_CONTROL                                                                             0x1c41
+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG2_OTG_STATUS                                                                              0x1c49
+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c50
+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c53
+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5c
+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c68
+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG2_OTG_CRC_CNTL2                                                                           0x1c69
+#define regOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c89
+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c94
+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c95
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c96
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c97
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c98
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c99
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c9a
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c9b
+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9c
+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9d
+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9e
+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9f
+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1ca0
+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca2
+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+// base address: 0x600
+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa
+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac
+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf
+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb7
+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
+#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG3_OTG_CONTROL                                                                             0x1cc1
+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG3_OTG_STATUS                                                                              0x1cc9
+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca
+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd0
+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdc
+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce8
+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
+#define regOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d09
+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d14
+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d15
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d16
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d17
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d18
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d19
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d1a
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d1b
+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1c
+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1d
+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1e
+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1f
+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d20
+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d22
+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define regDWB_SOURCE_SELECT                                                                            0x1e2a
+#define regDWB_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regGSL_SOURCE_SELECT                                                                            0x1e2b
+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define regODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define regODM_MEM_PWR_STATUS                                                                           0x1e30
+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x79a8
+#define regDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a
+#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b
+#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c
+#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d
+#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e
+#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70
+#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON17_PERFMON_HI                                                                      0x1e71
+#define regDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON17_PERFMON_LOW                                                                     0x1e72
+#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26
+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e
+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+// base address: 0x80
+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36
+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+// base address: 0x0
+#define regDP0_DP_LINK_CNTL                                                                             0x2108
+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP0_DP_CONFIG                                                                                0x210b
+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_STEER_FIFO                                                                            0x210d
+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_MISC                                                                              0x210e
+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP0_DP_VID_TIMING                                                                            0x2110
+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP0_DP_VID_N                                                                                 0x2111
+#define regDP0_DP_VID_N_BASE_IDX                                                                        2
+#define regDP0_DP_VID_M                                                                                 0x2112
+#define regDP0_DP_VID_M_BASE_IDX                                                                        2
+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_CNTL                                                                             0x2117
+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP0_DP_DPHY_SYM0                                                                             0x2119
+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM1                                                                             0x211a
+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM2                                                                             0x211b
+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP0_DP_SEC_CNTL                                                                              0x212b
+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL1                                                                             0x212c
+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_AUD_N                                                                             0x2131
+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_AUD_M                                                                             0x2133
+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT0                                                                              0x213a
+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT1                                                                              0x213b
+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT2                                                                              0x213c
+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP0_DP_MSO_CNTL                                                                              0x2150
+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_MSO_CNTL1                                                                             0x2151
+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_DSC_CNTL                                                                              0x2152
+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL2                                                                             0x2153
+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL3                                                                             0x2154
+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL4                                                                             0x2155
+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL5                                                                             0x2156
+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL6                                                                             0x2157
+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL7                                                                             0x2158
+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP0_DP_DB_CNTL                                                                               0x2159
+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
+#define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP0_DP_ALPM_CNTL                                                                             0x215d
+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP8_CNTL                                                                             0x215e
+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP9_CNTL                                                                             0x215f
+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP10_CNTL                                                                            0x2160
+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP11_CNTL                                                                            0x2161
+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+// base address: 0x0
+#define regDIG0_DIG_FE_CNTL                                                                             0x208b
+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG0_DIG_FIFO_STATUS                                                                         0x2091
+#define regDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2092
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG0_HDMI_CONTROL                                                                            0x2093
+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG0_HDMI_STATUS                                                                             0x2094
+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2095
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2096
+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2097
+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2098
+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2099
+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209a
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209b
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209c
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG0_HDMI_GC                                                                                 0x209d
+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209e
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x209f
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a0
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a1
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a3
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a4
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a5
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20a6
+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG0_HDMI_ACR_32_0                                                                           0x20a7
+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_32_1                                                                           0x20a8
+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_0                                                                           0x20a9
+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_1                                                                           0x20aa
+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_0                                                                           0x20ab
+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_1                                                                           0x20ac
+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20ad
+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20ae
+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG0_AFMT_CNTL                                                                               0x20af
+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG0_DIG_BE_CNTL                                                                             0x20b0
+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20b1
+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG0_TMDS_CNTL                                                                               0x20d7
+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20d8
+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d9
+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20da
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20db
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dc
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG0_TMDS_CTL_BITS                                                                           0x20de
+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20df
+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e0
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e1
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_DIG_VERSION                                                                             0x20e4
+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG0_FORCE_DIG_DISABLE                                                                       0x20e5
+#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+// base address: 0x400
+#define regDP1_DP_LINK_CNTL                                                                             0x2208
+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP1_DP_CONFIG                                                                                0x220b
+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_STEER_FIFO                                                                            0x220d
+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_MISC                                                                              0x220e
+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP1_DP_VID_TIMING                                                                            0x2210
+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP1_DP_VID_N                                                                                 0x2211
+#define regDP1_DP_VID_N_BASE_IDX                                                                        2
+#define regDP1_DP_VID_M                                                                                 0x2212
+#define regDP1_DP_VID_M_BASE_IDX                                                                        2
+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_CNTL                                                                             0x2217
+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP1_DP_DPHY_SYM0                                                                             0x2219
+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM1                                                                             0x221a
+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM2                                                                             0x221b
+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP1_DP_SEC_CNTL                                                                              0x222b
+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL1                                                                             0x222c
+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_AUD_N                                                                             0x2231
+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_AUD_M                                                                             0x2233
+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT0                                                                              0x223a
+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT1                                                                              0x223b
+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT2                                                                              0x223c
+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP1_DP_MSO_CNTL                                                                              0x2250
+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_MSO_CNTL1                                                                             0x2251
+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_DSC_CNTL                                                                              0x2252
+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL2                                                                             0x2253
+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL3                                                                             0x2254
+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL4                                                                             0x2255
+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL5                                                                             0x2256
+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL6                                                                             0x2257
+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL7                                                                             0x2258
+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP1_DP_DB_CNTL                                                                               0x2259
+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
+#define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP1_DP_ALPM_CNTL                                                                             0x225d
+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP8_CNTL                                                                             0x225e
+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP9_CNTL                                                                             0x225f
+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP10_CNTL                                                                            0x2260
+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP11_CNTL                                                                            0x2261
+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+// base address: 0x400
+#define regDIG1_DIG_FE_CNTL                                                                             0x218b
+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG1_DIG_FIFO_STATUS                                                                         0x2191
+#define regDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2192
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG1_HDMI_CONTROL                                                                            0x2193
+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG1_HDMI_STATUS                                                                             0x2194
+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2195
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2196
+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2197
+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2198
+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2199
+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219a
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219b
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219c
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG1_HDMI_GC                                                                                 0x219d
+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219e
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x219f
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a0
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a1
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a3
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a4
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a5
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21a6
+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG1_HDMI_ACR_32_0                                                                           0x21a7
+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_32_1                                                                           0x21a8
+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_0                                                                           0x21a9
+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_1                                                                           0x21aa
+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_0                                                                           0x21ab
+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_1                                                                           0x21ac
+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21ad
+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21ae
+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG1_AFMT_CNTL                                                                               0x21af
+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG1_DIG_BE_CNTL                                                                             0x21b0
+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21b1
+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG1_TMDS_CNTL                                                                               0x21d7
+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x21d8
+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d9
+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21da
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21db
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dc
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG1_TMDS_CTL_BITS                                                                           0x21de
+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21df
+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e0
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e1
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_DIG_VERSION                                                                             0x21e4
+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG1_FORCE_DIG_DISABLE                                                                       0x21e5
+#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+// base address: 0x800
+#define regDP2_DP_LINK_CNTL                                                                             0x2308
+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2309
+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x230a
+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP2_DP_CONFIG                                                                                0x230b
+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x230c
+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_STEER_FIFO                                                                            0x230d
+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_MISC                                                                              0x230e
+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP2_DP_VID_TIMING                                                                            0x2310
+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP2_DP_VID_N                                                                                 0x2311
+#define regDP2_DP_VID_N_BASE_IDX                                                                        2
+#define regDP2_DP_VID_M                                                                                 0x2312
+#define regDP2_DP_VID_M_BASE_IDX                                                                        2
+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP2_DP_VID_MSA_VBID                                                                          0x2315
+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_CNTL                                                                             0x2317
+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP2_DP_DPHY_SYM0                                                                             0x2319
+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM1                                                                             0x231a
+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM2                                                                             0x231b
+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_EN                                                                           0x231f
+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP2_DP_SEC_CNTL                                                                              0x232b
+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL1                                                                             0x232c
+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_FRAMING1                                                                          0x232d
+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING2                                                                          0x232e
+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING3                                                                          0x232f
+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING4                                                                          0x2330
+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_AUD_N                                                                             0x2331
+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_AUD_M                                                                             0x2333
+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2335
+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2337
+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT0                                                                              0x233a
+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT1                                                                              0x233b
+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT2                                                                              0x233c
+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x233e
+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x233f
+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP2_DP_MSO_CNTL                                                                              0x2350
+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_MSO_CNTL1                                                                             0x2351
+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_DSC_CNTL                                                                              0x2352
+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL2                                                                             0x2353
+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL3                                                                             0x2354
+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL4                                                                             0x2355
+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL5                                                                             0x2356
+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL6                                                                             0x2357
+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL7                                                                             0x2358
+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP2_DP_DB_CNTL                                                                               0x2359
+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP2_DP_MSA_VBID_MISC                                                                         0x235a
+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
+#define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP2_DP_ALPM_CNTL                                                                             0x235d
+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP8_CNTL                                                                             0x235e
+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP9_CNTL                                                                             0x235f
+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP10_CNTL                                                                            0x2360
+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP11_CNTL                                                                            0x2361
+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+// base address: 0x800
+#define regDIG2_DIG_FE_CNTL                                                                             0x228b
+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG2_DIG_TEST_PATTERN                                                                        0x228f
+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG2_DIG_FIFO_STATUS                                                                         0x2291
+#define regDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2292
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG2_HDMI_CONTROL                                                                            0x2293
+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG2_HDMI_STATUS                                                                             0x2294
+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2295
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2296
+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2297
+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2298
+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2299
+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229a
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229b
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229c
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG2_HDMI_GC                                                                                 0x229d
+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229e
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x229f
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a0
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a1
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a3
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a4
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a5
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22a6
+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG2_HDMI_ACR_32_0                                                                           0x22a7
+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_32_1                                                                           0x22a8
+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_0                                                                           0x22a9
+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_1                                                                           0x22aa
+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_0                                                                           0x22ab
+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ac
+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x22ad
+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x22ae
+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG2_AFMT_CNTL                                                                               0x22af
+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG2_DIG_BE_CNTL                                                                             0x22b0
+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x22b1
+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG2_TMDS_CNTL                                                                               0x22d7
+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x22d8
+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d9
+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22da
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22db
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dc
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG2_TMDS_CTL_BITS                                                                           0x22de
+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22df
+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e0
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22e1
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22e2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_DIG_VERSION                                                                             0x22e4
+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG2_FORCE_DIG_DISABLE                                                                       0x22e5
+#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define regDP3_DP_LINK_CNTL                                                                             0x2408
+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_PIXEL_FORMAT                                                                          0x2409
+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x240a
+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP3_DP_CONFIG                                                                                0x240b
+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x240c
+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_STEER_FIFO                                                                            0x240d
+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_MISC                                                                              0x240e
+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP3_DP_VID_TIMING                                                                            0x2410
+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP3_DP_VID_N                                                                                 0x2411
+#define regDP3_DP_VID_N_BASE_IDX                                                                        2
+#define regDP3_DP_VID_M                                                                                 0x2412
+#define regDP3_DP_VID_M_BASE_IDX                                                                        2
+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP3_DP_VID_MSA_VBID                                                                          0x2415
+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_CNTL                                                                             0x2417
+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP3_DP_DPHY_SYM0                                                                             0x2419
+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM1                                                                             0x241a
+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM2                                                                             0x241b
+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_EN                                                                           0x241f
+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP3_DP_SEC_CNTL                                                                              0x242b
+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL1                                                                             0x242c
+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_FRAMING1                                                                          0x242d
+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING2                                                                          0x242e
+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING3                                                                          0x242f
+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING4                                                                          0x2430
+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_AUD_N                                                                             0x2431
+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_AUD_M                                                                             0x2433
+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x2435
+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x2437
+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT0                                                                              0x243a
+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT1                                                                              0x243b
+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT2                                                                              0x243c
+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x243e
+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x243f
+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP3_DP_MSO_CNTL                                                                              0x2450
+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_MSO_CNTL1                                                                             0x2451
+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_DSC_CNTL                                                                              0x2452
+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL2                                                                             0x2453
+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL3                                                                             0x2454
+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL4                                                                             0x2455
+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL5                                                                             0x2456
+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL6                                                                             0x2457
+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL7                                                                             0x2458
+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP3_DP_DB_CNTL                                                                               0x2459
+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP3_DP_MSA_VBID_MISC                                                                         0x245a
+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
+#define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP3_DP_ALPM_CNTL                                                                             0x245d
+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP8_CNTL                                                                             0x245e
+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP9_CNTL                                                                             0x245f
+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP10_CNTL                                                                            0x2460
+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP11_CNTL                                                                            0x2461
+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define regDIG3_DIG_FE_CNTL                                                                             0x238b
+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG3_DIG_TEST_PATTERN                                                                        0x238f
+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG3_DIG_FIFO_STATUS                                                                         0x2391
+#define regDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2392
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG3_HDMI_CONTROL                                                                            0x2393
+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG3_HDMI_STATUS                                                                             0x2394
+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2395
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2396
+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2397
+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2398
+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2399
+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239a
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239b
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239c
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG3_HDMI_GC                                                                                 0x239d
+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239e
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x239f
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a0
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a1
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a3
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a4
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a5
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG3_HDMI_DB_CONTROL                                                                         0x23a6
+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG3_HDMI_ACR_32_0                                                                           0x23a7
+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_32_1                                                                           0x23a8
+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_0                                                                           0x23a9
+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_1                                                                           0x23aa
+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_0                                                                           0x23ab
+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_1                                                                           0x23ac
+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x23ad
+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x23ae
+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG3_AFMT_CNTL                                                                               0x23af
+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG3_DIG_BE_CNTL                                                                             0x23b0
+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x23b1
+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG3_TMDS_CNTL                                                                               0x23d7
+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x23d8
+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d9
+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23da
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23db
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dc
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG3_TMDS_CTL_BITS                                                                           0x23de
+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23df
+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e0
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23e1
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23e2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_DIG_VERSION                                                                             0x23e4
+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG3_FORCE_DIG_DISABLE                                                                       0x23e5
+#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+// base address: 0x1000
+#define regDP4_DP_LINK_CNTL                                                                             0x2508
+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_PIXEL_FORMAT                                                                          0x2509
+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x250a
+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP4_DP_CONFIG                                                                                0x250b
+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x250c
+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_STEER_FIFO                                                                            0x250d
+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_MISC                                                                              0x250e
+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP4_DP_VID_TIMING                                                                            0x2510
+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP4_DP_VID_N                                                                                 0x2511
+#define regDP4_DP_VID_N_BASE_IDX                                                                        2
+#define regDP4_DP_VID_M                                                                                 0x2512
+#define regDP4_DP_VID_M_BASE_IDX                                                                        2
+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP4_DP_VID_MSA_VBID                                                                          0x2515
+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_CNTL                                                                             0x2517
+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP4_DP_DPHY_SYM0                                                                             0x2519
+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM1                                                                             0x251a
+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM2                                                                             0x251b
+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_EN                                                                           0x251f
+#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
+#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
+#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
+#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
+#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP4_DP_SEC_CNTL                                                                              0x252b
+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL1                                                                             0x252c
+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_FRAMING1                                                                          0x252d
+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING2                                                                          0x252e
+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING3                                                                          0x252f
+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING4                                                                          0x2530
+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_AUD_N                                                                             0x2531
+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_AUD_M                                                                             0x2533
+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x2535
+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x2537
+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT0                                                                              0x253a
+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT1                                                                              0x253b
+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT2                                                                              0x253c
+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x253e
+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x253f
+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP4_DP_MSO_CNTL                                                                              0x2550
+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_MSO_CNTL1                                                                             0x2551
+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_DSC_CNTL                                                                              0x2552
+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL2                                                                             0x2553
+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL3                                                                             0x2554
+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL4                                                                             0x2555
+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL5                                                                             0x2556
+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL6                                                                             0x2557
+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL7                                                                             0x2558
+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP4_DP_DB_CNTL                                                                               0x2559
+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP4_DP_MSA_VBID_MISC                                                                         0x255a
+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP4_DP_DSC_BYTES_PER_PIXEL                                                                   0x255c
+#define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP4_DP_ALPM_CNTL                                                                             0x255d
+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP8_CNTL                                                                             0x255e
+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP9_CNTL                                                                             0x255f
+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP10_CNTL                                                                            0x2560
+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP11_CNTL                                                                            0x2561
+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2562
+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+// base address: 0x1000
+#define regDIG4_DIG_FE_CNTL                                                                             0x248b
+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x248c
+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x248d
+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x248e
+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG4_DIG_TEST_PATTERN                                                                        0x248f
+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x2490
+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG4_DIG_FIFO_STATUS                                                                         0x2491
+#define regDIG4_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x2492
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG4_HDMI_CONTROL                                                                            0x2493
+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG4_HDMI_STATUS                                                                             0x2494
+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2495
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2496
+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2497
+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2498
+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2499
+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x249a
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x249b
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x249c
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG4_HDMI_GC                                                                                 0x249d
+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x249e
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x249f
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x24a0
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x24a1
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x24a2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x24a3
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x24a4
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x24a5
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG4_HDMI_DB_CONTROL                                                                         0x24a6
+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG4_HDMI_ACR_32_0                                                                           0x24a7
+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_32_1                                                                           0x24a8
+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_0                                                                           0x24a9
+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_1                                                                           0x24aa
+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_0                                                                           0x24ab
+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_1                                                                           0x24ac
+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x24ad
+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x24ae
+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG4_AFMT_CNTL                                                                               0x24af
+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG4_DIG_BE_CNTL                                                                             0x24b0
+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x24b1
+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG4_TMDS_CNTL                                                                               0x24d7
+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x24d8
+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24d9
+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24da
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24db
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24dc
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG4_TMDS_CTL_BITS                                                                           0x24de
+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24df
+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24e0
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24e1
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24e2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_DIG_VERSION                                                                             0x24e4
+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG4_FORCE_DIG_DISABLE                                                                       0x24e5
+#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT0_AFMT_60958_0                                                                           0x2078
+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_60958_1                                                                           0x2079
+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT0_AFMT_60958_2                                                                           0x207f
+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT0_AFMT_STATUS                                                                            0x2081
+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT1_AFMT_60958_0                                                                           0x2178
+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_60958_1                                                                           0x2179
+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT1_AFMT_60958_2                                                                           0x217f
+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT1_AFMT_STATUS                                                                            0x2181
+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+// base address: 0x15ccc
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT2_AFMT_60958_0                                                                           0x2278
+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_60958_1                                                                           0x2279
+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT2_AFMT_60958_2                                                                           0x227f
+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT2_AFMT_STATUS                                                                            0x2281
+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_MEM_PWR                                                                           0x2287
+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+// base address: 0x160cc
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT3_AFMT_60958_0                                                                           0x2378
+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_60958_1                                                                           0x2379
+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT3_AFMT_60958_2                                                                           0x237f
+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT3_AFMT_STATUS                                                                            0x2381
+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_MEM_PWR                                                                           0x2387
+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
+// base address: 0x164cc
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2474
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2475
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2476
+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2477
+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT4_AFMT_60958_0                                                                           0x2478
+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_60958_1                                                                           0x2479
+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x247a
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x247b
+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x247c
+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x247d
+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x247e
+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT4_AFMT_60958_2                                                                           0x247f
+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2480
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT4_AFMT_STATUS                                                                            0x2481
+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2482
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2483
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2484
+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2485
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2487
+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define regDME0_DME_CONTROL                                                                             0x2089
+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG0_VPG_MEM_PWR                                                                             0x206d
+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define regDME1_DME_CONTROL                                                                             0x2189
+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG1_VPG_MEM_PWR                                                                             0x216d
+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+// base address: 0x15d24
+#define regDME2_DME_CONTROL                                                                             0x2289
+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME2_DME_MEMORY_CONTROL                                                                      0x228a
+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+// base address: 0x15ca0
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x226c
+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG2_VPG_MEM_PWR                                                                             0x226d
+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG2_VPG_MPEG_INFO0                                                                          0x2270
+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG2_VPG_MPEG_INFO1                                                                          0x2271
+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+// base address: 0x16124
+#define regDME3_DME_CONTROL                                                                             0x2389
+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME3_DME_MEMORY_CONTROL                                                                      0x238a
+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+// base address: 0x160a0
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x236c
+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG3_VPG_MEM_PWR                                                                             0x236d
+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG3_VPG_MPEG_INFO0                                                                          0x2370
+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG3_VPG_MPEG_INFO1                                                                          0x2371
+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
+// base address: 0x16524
+#define regDME4_DME_CONTROL                                                                             0x2489
+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME4_DME_MEMORY_CONTROL                                                                      0x248a
+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
+// base address: 0x164a0
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2468
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x2469
+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x246a
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x246b
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x246c
+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG4_VPG_MEM_PWR                                                                             0x246d
+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x246e
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x246f
+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2470
+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2471
+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88
+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4
+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa
+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab
+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+// base address: 0x1c0
+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0
+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define regDC_I2C_CONTROL                                                                               0x1e98
+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define regDC_I2C_ARBITRATION                                                                           0x1e99
+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define regDC_I2C_SW_STATUS                                                                             0x1e9b
+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6
+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7
+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8
+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9
+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa
+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab
+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_TRANSACTION0                                                                          0x1eae
+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define regDC_I2C_DATA                                                                                  0x1eb2
+#define regDC_I2C_DATA_BASE_IDX                                                                         2
+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define regDIO_SCRATCH0                                                                                 0x1eca
+#define regDIO_SCRATCH0_BASE_IDX                                                                        2
+#define regDIO_SCRATCH1                                                                                 0x1ecb
+#define regDIO_SCRATCH1_BASE_IDX                                                                        2
+#define regDIO_SCRATCH2                                                                                 0x1ecc
+#define regDIO_SCRATCH2_BASE_IDX                                                                        2
+#define regDIO_SCRATCH3                                                                                 0x1ecd
+#define regDIO_SCRATCH3_BASE_IDX                                                                        2
+#define regDIO_SCRATCH4                                                                                 0x1ece
+#define regDIO_SCRATCH4_BASE_IDX                                                                        2
+#define regDIO_SCRATCH5                                                                                 0x1ecf
+#define regDIO_SCRATCH5_BASE_IDX                                                                        2
+#define regDIO_SCRATCH6                                                                                 0x1ed0
+#define regDIO_SCRATCH6_BASE_IDX                                                                        2
+#define regDIO_SCRATCH7                                                                                 0x1ed1
+#define regDIO_SCRATCH7_BASE_IDX                                                                        2
+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define regDIO_CLK_CNTL                                                                                 0x1ee0
+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define regDIG_SOFT_RESET                                                                               0x1eee
+#define regDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define regDIO_CLK_CNTL2                                                                                0x1ef2
+#define regDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define regDIO_CLK_CNTL3                                                                                0x1ef3
+#define regDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define regDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
+#define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
+#define regDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
+#define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
+#define regDIO_LINKA_CNTL                                                                               0x1f04
+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKB_CNTL                                                                               0x1f05
+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKC_CNTL                                                                               0x1f06
+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKD_CNTL                                                                               0x1f07
+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKE_CNTL                                                                               0x1f08
+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKF_CNTL                                                                               0x1f09
+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+// base address: 0x7d10
+#define regDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44
+#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45
+#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46
+#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47
+#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48
+#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49
+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a
+#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON18_PERFMON_HI                                                                      0x1f4b
+#define regDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c
+#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_LINK_CNTL                                                                            0x286d
+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_LINK_CNTL                                                                            0x286f
+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_LINK_CNTL                                                                            0x2871
+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_LINK_CNTL                                                                            0x2873
+#define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_LINK_CNTL                                                                            0x2875
+#define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902
+#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19
+#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a
+#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21
+#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec
+// base address: 0x1b0
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85
+#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86
+#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d
+#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_STATUS                                                                            0x300c
+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc140
+#define regDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050
+#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051
+#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052
+#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON19_PERFMON_CNTL                                                                    0x3053
+#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054
+#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055
+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056
+#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON19_PERFMON_HI                                                                      0x3057
+#define regDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON19_PERFMON_LOW                                                                     0x3058
+#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_STATUS                                                                            0x3068
+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc2b0
+#define regDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac
+#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad
+#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae
+#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON20_PERFMON_CNTL                                                                    0x30af
+#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0
+#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1
+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2
+#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON20_PERFMON_HI                                                                      0x30b3
+#define regDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON20_PERFMON_LOW                                                                     0x30b4
+#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2
+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3
+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_STATUS                                                                            0x30c4
+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc420
+#define regDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108
+#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109
+#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a
+#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON21_PERFMON_CNTL                                                                    0x310b
+#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c
+#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d
+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e
+#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON21_PERFMON_HI                                                                      0x310f
+#define regDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON21_PERFMON_LOW                                                                     0x3110
+#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+// base address: 0x2790c
+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a
+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
+// base address: 0x27958
+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56
+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57
+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58
+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59
+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3
+
+
+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a698
+#define regDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x0e66
+#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       3
+#define regDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x0e67
+#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
+#define regDC_PERFMON22_PERFCOUNTER_STATE                                                               0x0e68
+#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      3
+#define regDC_PERFMON22_PERFMON_CNTL                                                                    0x0e69
+#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           3
+#define regDC_PERFMON22_PERFMON_CNTL2                                                                   0x0e6a
+#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          3
+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x0e6b
+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
+#define regDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x0e6c
+#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
+#define regDC_PERFMON22_PERFMON_HI                                                                      0x0e6d
+#define regDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             3
+#define regDC_PERFMON22_PERFMON_LOW                                                                     0x0e6e
+#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+// base address: 0x2646c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e
+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3
+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f
+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3
+#define regAFMT5_AFMT_60958_0                                                                           0x0920
+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_60958_1                                                                           0x0921
+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923
+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924
+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925
+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926
+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3
+#define regAFMT5_AFMT_60958_2                                                                           0x0927
+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3
+#define regAFMT5_AFMT_STATUS                                                                            0x0929
+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c
+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f
+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+// base address: 0x264f0
+#define regDME5_DME_CONTROL                                                                             0x093c
+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3
+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d
+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+// base address: 0x264c4
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932
+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935
+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3
+#define regVPG5_VPG_MEM_PWR                                                                             0x0936
+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3
+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938
+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3
+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939
+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3
+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a
+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
+// base address: 0x1ab8c
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+// base address: 0x1abc0
+#define regAPG0_APG_CONTROL                                                                             0x3630
+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG0_APG_CONTROL2                                                                            0x3631
+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632
+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633
+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a
+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b
+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c
+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG0_APG_STATUS                                                                              0x3641
+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG0_APG_STATUS2                                                                             0x3642
+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG0_APG_MEM_PWR                                                                             0x3644
+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG0_APG_SPARE                                                                               0x3646
+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+// base address: 0x1ac38
+#define regDME6_DME_CONTROL                                                                             0x364e
+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f
+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+// base address: 0x1ac44
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652
+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655
+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG6_VPG_MEM_PWR                                                                             0x3656
+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658
+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659
+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a
+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
+// base address: 0x1ac74
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
+// base address: 0x1aedc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+// base address: 0x1af10
+#define regAPG1_APG_CONTROL                                                                             0x3704
+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG1_APG_CONTROL2                                                                            0x3705
+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706
+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e
+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f
+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710
+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG1_APG_STATUS                                                                              0x3715
+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG1_APG_STATUS2                                                                             0x3716
+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG1_APG_MEM_PWR                                                                             0x3718
+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG1_APG_SPARE                                                                               0x371a
+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+// base address: 0x1af88
+#define regDME7_DME_CONTROL                                                                             0x3722
+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723
+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+// base address: 0x1af94
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726
+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729
+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG7_VPG_MEM_PWR                                                                             0x372a
+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c
+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d
+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e
+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
+// base address: 0x1afc4
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x375f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3760
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
+// base address: 0x1b22c
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+// base address: 0x1b260
+#define regAPG2_APG_CONTROL                                                                             0x37d8
+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG2_APG_CONTROL2                                                                            0x37d9
+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da
+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db
+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2
+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3
+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4
+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG2_APG_STATUS                                                                              0x37e9
+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG2_APG_STATUS2                                                                             0x37ea
+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG2_APG_MEM_PWR                                                                             0x37ec
+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG2_APG_SPARE                                                                               0x37ee
+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+// base address: 0x1b2d8
+#define regDME8_DME_CONTROL                                                                             0x37f6
+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7
+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+// base address: 0x1b2e4
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa
+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd
+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe
+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800
+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801
+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802
+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
+// base address: 0x1b314
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3833
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3834
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
+// base address: 0x1b57c
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+// base address: 0x1b5b0
+#define regAPG3_APG_CONTROL                                                                             0x38ac
+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG3_APG_CONTROL2                                                                            0x38ad
+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae
+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af
+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6
+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7
+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8
+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG3_APG_STATUS                                                                              0x38bd
+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG3_APG_STATUS2                                                                             0x38be
+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG3_APG_MEM_PWR                                                                             0x38c0
+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG3_APG_SPARE                                                                               0x38c2
+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+// base address: 0x1b628
+#define regDME9_DME_CONTROL                                                                             0x38ca
+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb
+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+// base address: 0x1b634
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce
+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1
+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2
+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4
+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5
+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6
+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
+// base address: 0x1b664
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3907
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x3908
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
+// base address: 0x1ad5c
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
+// base address: 0x1ae00
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36eb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ec
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36ed
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36ee
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
+// base address: 0x1b0ac
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
+// base address: 0x1b150
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37bf
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_dchvm_hvm_dispdec
+// base address: 0x0
+#define regDCHVM_CTRL0                                                                                  0x3603
+#define regDCHVM_CTRL0_BASE_IDX                                                                         2
+#define regDCHVM_CTRL1                                                                                  0x3604
+#define regDCHVM_CTRL1_BASE_IDX                                                                         2
+#define regDCHVM_CLK_CTRL                                                                               0x3605
+#define regDCHVM_CLK_CTRL_BASE_IDX                                                                      2
+#define regDCHVM_MEM_CTRL                                                                               0x3606
+#define regDCHVM_MEM_CTRL_BASE_IDX                                                                      2
+#define regDCHVM_RIOMMU_CTRL0                                                                           0x3607
+#define regDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  2
+#define regDCHVM_RIOMMU_STAT0                                                                           0x3608
+#define regDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  2
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
new file mode 100644
index 000000000000..e5fd0121ceff
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
@@ -0,0 +1,60749 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_1_2_SH_MASK_HEADER
+#define _dcn_3_1_2_SH_MASK_HEADER
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//AZCONTROLLER0_GLOBAL_CAPABILITIES
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT                            0x0
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                        0x1
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT                   0x3
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT                           0x8
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT                          0xc
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK                              0x0001L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                          0x0006L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK                     0x00F8L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK                             0x0F00L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK                            0xF000L
+//AZCONTROLLER0_MINOR_VERSION
+#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION__SHIFT                                                     0x0
+#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION_MASK                                                       0xFFL
+//AZCONTROLLER0_MAJOR_VERSION
+#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION__SHIFT                                                     0x0
+#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION_MASK                                                       0xFFL
+//AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                             0x0
+#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                               0xFFFFL
+//AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                               0x0
+#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                 0xFFFFL
+//AZCONTROLLER0_GLOBAL_CONTROL
+#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT                                                 0x0
+#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT                                                    0x1
+#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT                               0x8
+#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET_MASK                                                   0x00000001L
+#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL_MASK                                                      0x00000002L
+#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK                                 0x00000100L
+//AZCONTROLLER0_WAKE_ENABLE
+#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT                                               0x0
+#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK                                                 0x0001L
+//AZCONTROLLER0_STATE_CHANGE_STATUS
+#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT                                         0x0
+#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK                                           0x0001L
+//AZCONTROLLER0_GLOBAL_STATUS
+#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS__SHIFT                                                      0x1
+#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS_MASK                                                        0x00000002L
+//AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                     0x0
+#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                       0xFFFFL
+//AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                       0x0
+#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                         0xFFFFL
+//AZCONTROLLER0_INTERRUPT_CONTROL
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT                                     0x0
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT                                     0x1
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT                                     0x2
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT                                     0x3
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT                                     0x4
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT                                     0x5
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT                                     0x6
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT                                     0x7
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT                                     0x8
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT                                     0x9
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT                                    0xa
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT                                    0xb
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT                                    0xc
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT                                    0xd
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT                                    0xe
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT                                    0xf
+#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT                                   0x1e
+#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT                                       0x1f
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK                                       0x00000001L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK                                       0x00000002L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK                                       0x00000004L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK                                       0x00000008L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK                                       0x00000010L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK                                       0x00000020L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK                                       0x00000040L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK                                       0x00000080L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK                                       0x00000100L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK                                       0x00000200L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK                                      0x00000400L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK                                      0x00000800L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK                                      0x00001000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK                                      0x00002000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK                                      0x00004000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK                                      0x00008000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK                                     0x40000000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK                                         0x80000000L
+//AZCONTROLLER0_INTERRUPT_STATUS
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT                                      0x0
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT                                      0x1
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT                                      0x2
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT                                      0x3
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT                                      0x4
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT                                      0x5
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT                                      0x6
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT                                      0x7
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT                                      0x8
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT                                      0x9
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT                                     0xa
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT                                     0xb
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT                                     0xc
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT                                     0xd
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT                                     0xe
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT                                     0xf
+#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT                                    0x1e
+#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT                                        0x1f
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK                                        0x00000001L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK                                        0x00000002L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK                                        0x00000004L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK                                        0x00000008L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK                                        0x00000010L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK                                        0x00000020L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK                                        0x00000040L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK                                        0x00000080L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK                                        0x00000100L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK                                        0x00000200L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK                                       0x00000400L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK                                       0x00000800L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK                                       0x00001000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK                                       0x00002000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK                                       0x00004000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK                                       0x00008000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK                                      0x40000000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK                                          0x80000000L
+//AZCONTROLLER0_WALL_CLOCK_COUNTER
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT                                           0x0
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK                                             0xFFFFFFFFL
+//AZCONTROLLER0_STREAM_SYNCHRONIZATION
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT                                 0x0
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT                                 0x1
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT                                 0x2
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT                                 0x3
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT                                 0x4
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT                                 0x5
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT                                 0x6
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT                                 0x7
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT                                 0x8
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT                                 0x9
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT                                0xa
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT                                0xb
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT                                0xc
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT                                0xd
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT                                0xe
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT                                0xf
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK                                   0x00000001L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK                                   0x00000002L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK                                   0x00000004L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK                                   0x00000008L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK                                   0x00000010L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK                                   0x00000020L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK                                   0x00000040L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK                                   0x00000080L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK                                   0x00000100L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK                                   0x00000200L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK                                  0x00000400L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK                                  0x00000800L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK                                  0x00001000L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK                                  0x00002000L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK                                  0x00004000L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK                                  0x00008000L
+//AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT                                 0x7
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L
+//AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS
+#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT                                 0x0
+#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL
+//AZCONTROLLER0_CORB_WRITE_POINTER
+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL
+//AZCONTROLLER0_CORB_READ_POINTER
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L
+//AZCONTROLLER0_CORB_CONTROL
+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0
+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1
+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L
+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L
+//AZCONTROLLER0_CORB_STATUS
+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0
+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L
+//AZCONTROLLER0_CORB_SIZE
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L
+//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS
+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0
+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL
+//AZCONTROLLER0_RIRB_WRITE_POINTER
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L
+//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT
+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0
+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL
+//AZCONTROLLER0_RIRB_CONTROL
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0
+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L
+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L
+//AZCONTROLLER0_RIRB_STATUS
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L
+//AZCONTROLLER0_RIRB_SIZE
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L
+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL
+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL
+//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0
+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL
+//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L
+//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L
+//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS
+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0
+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL
+//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL
+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL
+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT                                                                           0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK                                                                             0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT                                                                         0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK                                                                           0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT                                                                          0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK                                                                            0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT                                                                              0x0
+#define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT                                                                         0x4
+#define GENS1__NO_DISPLAY_MASK                                                                                0x01L
+#define GENS1__VGA_VSTATUS_MASK                                                                               0x08L
+#define GENS1__PIXEL_READ_BACK_MASK                                                                           0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDW__ATTR_DATA_MASK                                                                                0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT                                                                                0x0
+#define ATTRX__ATTR_IDX_MASK                                                                                  0x1FL
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDR__ATTR_DATA_MASK                                                                                0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_WT__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT                                                                            0x4
+#define GENS0__CRT_INTR__SHIFT                                                                                0x7
+#define GENS0__SENSE_SWITCH_MASK                                                                              0x10L
+#define GENS0__CRT_INTR_MASK                                                                                  0x80L
+//GENENB
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT                                                                              0x0
+#define SEQ8_IDX__SEQ_IDX_MASK                                                                                0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT                                                                            0x0
+#define SEQ8_DATA__SEQ_DATA_MASK                                                                              0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT                                                                             0x0
+#define DAC_MASK__DAC_MASK_MASK                                                                               0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT                                                                       0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK                                                                         0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT                                                                       0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK                                                                         0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT                                                                             0x0
+#define DAC_DATA__DAC_DATA_MASK                                                                               0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT                                                                          0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK                                                                            0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_RD__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT                                                                            0x0
+#define GRPH8_IDX__GRPH_IDX_MASK                                                                              0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT                                                                          0x0
+#define GRPH8_DATA__GRPH_DATA_MASK                                                                            0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT                                                                         0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK                                                                           0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT                                                                       0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK                                                                         0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT                                                                        0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK                                                                          0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT                                                                            0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT                                                                           0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT                                                                       0x4
+#define GENS1_1__NO_DISPLAY_MASK                                                                              0x01L
+#define GENS1_1__VGA_VSTATUS_MASK                                                                             0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK                                                                         0x30L
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//AZCONTROLLER1_CORB_WRITE_POINTER
+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL
+//AZCONTROLLER1_CORB_READ_POINTER
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L
+//AZCONTROLLER1_CORB_CONTROL
+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0
+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1
+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L
+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L
+//AZCONTROLLER1_CORB_STATUS
+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0
+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L
+//AZCONTROLLER1_CORB_SIZE
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L
+//AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS
+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0
+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL
+//AZCONTROLLER1_RIRB_WRITE_POINTER
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L
+//AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT
+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0
+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL
+//AZCONTROLLER1_RIRB_CONTROL
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0
+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L
+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L
+//AZCONTROLLER1_RIRB_STATUS
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L
+//AZCONTROLLER1_RIRB_SIZE
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L
+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL
+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL
+//AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0
+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL
+//AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L
+//AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L
+//AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS
+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0
+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL
+//AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS
+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0
+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL
+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL
+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
+//DCCG_GATE_DISABLE_CNTL4
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L
+//DPSTREAMCLK_CNTL
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE0_EN__SHIFT                                                         0x1
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE1_EN__SHIFT                                                         0x2
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE2_EN__SHIFT                                                         0x3
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE3_EN__SHIFT                                                         0x4
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE0_EN_MASK                                                           0x00000002L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE1_EN_MASK                                                           0x00000004L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE2_EN_MASK                                                           0x00000008L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE3_EN_MASK                                                           0x00000010L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//PHYPLLE_PIXCLK_RESYNC_CNTL
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//DCCG_PERFMON_CNTL2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE__SHIFT                                                   0x9
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE_MASK                                                     0x00000200L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
+//SYMCLK32_SE_CNTL
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L
+//SYMCLK32_LE_CNTL
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK2_DTO_PARAM
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
+//DCCG_PERFMON_CNTL
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT                                               0x18
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT                                               0x19
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT                                               0x1a
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT                                               0x1b
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT                                               0x1c
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE__SHIFT                                               0x1d
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK                                                 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK                                                 0x02000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK                                                 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK                                                 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK                                                 0x10000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE_MASK                                                 0x20000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT                                                       0x3
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_DIV__SHIFT                                                          0x1c
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK                                                         0x00000008L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_DIV_MASK                                                            0xF0000000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT                                                       0x3
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_DIV__SHIFT                                                          0x1c
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK                                                         0x00000008L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_DIV_MASK                                                            0xF0000000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG2_PIXEL_RATE_CNTL
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT                                                       0x3
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_DIV__SHIFT                                                          0x1c
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK                                                         0x00000008L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_DIV_MASK                                                            0xF0000000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG2_PHYPLL_PIXEL_RATE_CNTL
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG3_PIXEL_RATE_CNTL
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT                                                       0x3
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_DIV__SHIFT                                                          0x1c
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK                                                         0x00000008L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_DIV_MASK                                                            0xF0000000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG3_PHYPLL_PIXEL_RATE_CNTL
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK2_DTO_PARAM
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK3_DTO_PARAM
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKE_CLOCK_ENABLE
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK                                                       0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT                                    0x1d
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000070L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK                                      0x20000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
+//DTBCLK_DTO0_PHASE
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO1_PHASE
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO2_PHASE
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO3_PHASE
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO0_MODULO
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO1_MODULO
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO2_MODULO
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO3_MODULO
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL
+//PHYASYMCLK_CLOCK_CNTL
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYBSYMCLK_CLOCK_CNTL
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYCSYMCLK_CLOCK_CNTL
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYDSYMCLK_CLOCK_CNTL
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYESYMCLK_CLOCK_CNTL
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//DCCG_GATE_DISABLE_CNTL3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_ROOT_GATE_DISABLE__SHIFT                                         0x6
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_GATE_DISABLE__SHIFT                                              0x7
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_ROOT_GATE_DISABLE_MASK                                           0x00000040L
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_GATE_DISABLE_MASK                                                0x00000080L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L
+//DCCG_AUDIO_DTBCLK_DTO_PHASE
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL
+//DCCG_AUDIO_DTBCLK_DTO_MODULO
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT                                     0x0
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK                                       0xFFFFFFFFL
+//DTBCLK_DTO_DBUF_EN
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT                                                        0x0
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT                                                        0x1
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT                                                        0x2
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT                                                        0x3
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK                                                          0x00000001L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK                                                          0x00000002L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK                                                          0x00000004L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK                                                          0x00000008L
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+//DC_PERFMON0_PERFCOUNTER_CNTL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_CNTL2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_STATE
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON0_PERFMON_CNTL
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON0_PERFMON_CNTL2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON0_PERFMON_CVALUE_LOW
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON0_PERFMON_HI
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON0_PERFMON_LOW
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+//DC_PERFMON1_PERFCOUNTER_CNTL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_CNTL2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_STATE
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON1_PERFMON_CNTL
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON1_PERFMON_CNTL2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON1_PERFMON_CVALUE_LOW
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON1_PERFMON_HI
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON1_PERFMON_LOW
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+//DMCU_CTRL
+#define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT                                                                       0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT                                                                   0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT                                                                  0x3
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT                                                                         0x4
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT                                                              0x8
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT                                                                   0x10
+#define DMCU_CTRL__RESET_UC_MASK                                                                              0x00000001L
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK                                                                         0x00000002L
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK                                                                     0x00000004L
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK                                                                    0x00000008L
+#define DMCU_CTRL__DMCU_ENABLE_MASK                                                                           0x00000010L
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK                                                                0x00000100L
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK                                                                     0xFFFF0000L
+//DMCU_STATUS
+#define DMCU_STATUS__UC_IN_RESET__SHIFT                                                                       0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT                                                                   0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT                                                                   0x2
+#define DMCU_STATUS__UC_IN_RESET_MASK                                                                         0x00000001L
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK                                                                     0x00000002L
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK                                                                     0x00000004L
+//DMCU_PC_START_ADDR
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_START_ADDR
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_END_ADDR
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT                                                              0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT                                                              0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK                                                                0x000000FFL
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK                                                                0x0000FF00L
+//DMCU_FW_ISR_START_ADDR
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT                                                  0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT                                                  0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK                                                    0x000000FFL
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK                                                    0x0000FF00L
+//DMCU_FW_CS_HI
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT                                                                  0x0
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK                                                                    0xFFFFFFFFL
+//DMCU_FW_CS_LO
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT                                                                  0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK                                                                    0xFFFFFFFFL
+//DMCU_RAM_ACCESS_CTRL
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT                                                      0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT                                                      0x5
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000001L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000002L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000004L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000008L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK                                                        0x00000010L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK                                                        0x00000020L
+//DMCU_ERAM_WR_CTRL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_WR_DATA
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_ERAM_RD_CTRL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_RD_DATA
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_IRAM_WR_CTRL
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_WR_DATA
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK                                                                  0x000000FFL
+//DMCU_IRAM_RD_CTRL
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_RD_DATA
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK                                                                  0x000000FFL
+//DMCU_EVENT_TRIGGER
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT                                                           0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT                                                       0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT                                                0x17
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK                                                             0x00000001L
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK                                                         0x007F0000L
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK                                                  0x00800000L
+//DMCU_UC_INTERNAL_INT_STATUS
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT                                                  0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT                                                 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT                                         0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT                                        0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT                                     0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT                                     0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT                                     0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT                                     0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT                                             0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT                                        0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT                     0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT                                      0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT                                      0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT                                      0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT                               0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT                                 0xf
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK                                                    0x00000001L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK                                                   0x00000002L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK                                           0x00000004L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK                                          0x00000008L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK                                       0x00000010L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK                                       0x00000020L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK                                       0x00000040L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK                                       0x00000080L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK                                               0x00000100L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK                                          0x00000200L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK                       0x00000400L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK                                        0x00000800L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK                                        0x00001000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK                                        0x00002000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK                                 0x00004000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK                                   0x00008000L
+//DMCU_SS_INTERRUPT_CNTL_STATUS
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT                                       0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT                                     0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT                                        0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT                                       0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT                                     0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT                                        0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT                                       0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT                                     0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT                                        0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT                                       0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT                                     0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT                                        0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT                                       0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT                                     0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT                                        0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT                                       0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT                                     0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT                                        0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK                                         0x00002000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK                                       0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK                                          0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK                                         0x00008000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK                                       0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK                                          0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK                                         0x00020000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK                                       0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK                                          0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK                                         0x00080000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK                                       0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK                                          0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK                                         0x00200000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK                                       0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK                                          0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK                                         0x00800000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK                                       0x01000000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK                                          0x01000000L
+//DMCU_INTERRUPT_STATUS
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT                                              0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT                                                 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT                                              0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT                                                 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT                                             0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT                                                0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT                                                        0x3
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT                                                0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT                                                   0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT                                                        0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT                                                0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT                                                   0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT                                          0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT                                             0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                  0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                     0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                  0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                     0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                  0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                     0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                  0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                     0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                  0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                     0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                  0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                     0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                   0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                   0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                   0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                   0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                   0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                   0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT                                                    0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT                                                       0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT                                                    0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT                                                       0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT                                                    0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT                                                       0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT                                                    0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT                                                       0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT                                                    0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT                                                       0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT                                                    0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT                                                       0x1d
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK                                                0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK                                                   0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK                                                0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK                                                   0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK                                               0x00000004L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK                                                  0x00000004L
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK                                                          0x00000008L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK                                                  0x00000100L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK                                                     0x00000100L
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK                                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK                                                  0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK                                                     0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK                                            0x00000800L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK                                               0x00000800L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                    0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK                                       0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                    0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK                                       0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                    0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK                                       0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                    0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK                                       0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                    0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK                                       0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                    0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                  0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                     0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                  0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                     0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                  0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                     0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                  0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                     0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                  0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                     0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                  0x00800000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                     0x00800000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK                                                      0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK                                                         0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK                                                      0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK                                                         0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK                                                      0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK                                                         0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK                                                      0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK                                                         0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK                                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK                                                         0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK                                                      0x20000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK                                                         0x20000000L
+//DMCU_INTERRUPT_STATUS_1
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xb
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xb
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT                                       0xd
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT                                          0xd
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED__SHIFT                                            0xe
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR__SHIFT                                               0xe
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED__SHIFT                                            0xf
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR__SHIFT                                               0xf
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED__SHIFT                                           0x10
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR__SHIFT                                              0x10
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED__SHIFT                                            0x11
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR__SHIFT                                               0x11
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED__SHIFT                                            0x12
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR__SHIFT                                               0x12
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED__SHIFT                                           0x13
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR__SHIFT                                              0x13
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK                                         0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK                                            0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED_MASK                                              0x00004000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR_MASK                                                 0x00004000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED_MASK                                              0x00008000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR_MASK                                                 0x00008000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED_MASK                                             0x00010000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR_MASK                                                0x00010000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED_MASK                                              0x00020000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR_MASK                                                 0x00020000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED_MASK                                              0x00040000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR_MASK                                                 0x00040000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED_MASK                                             0x00080000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR_MASK                                                0x00080000L
+//DMCU_INTERRUPT_TO_HOST_EN_MASK
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT                                         0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT                                         0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT                                        0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT                                         0x3
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT                                         0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT                                        0x5
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT                                                   0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT                                           0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT                                     0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK__SHIFT                                         0xc
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK__SHIFT                                         0xd
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK__SHIFT                                        0xe
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK__SHIFT                                         0xf
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK__SHIFT                                         0x10
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK__SHIFT                                        0x11
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK                                           0x00000001L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK                                           0x00000002L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK                                          0x00000004L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK                                           0x00000008L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK                                           0x00000010L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK                                          0x00000020L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK                                                     0x00000200L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK                                             0x00000400L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK                                       0x00000800L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK_MASK                                           0x00001000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK_MASK                                           0x00002000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK_MASK                                          0x00004000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK_MASK                                           0x00008000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK_MASK                                           0x00010000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK_MASK                                          0x00020000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT                                       0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT                                       0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT                                      0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT                                                 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT                                      0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT                                      0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT                                         0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT                                      0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT                                      0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT                                      0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT                           0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT                           0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT                           0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT                           0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT                           0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT                           0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT                                             0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT                                             0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT                                             0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT                                             0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT                                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT                                             0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT                                      0x1e
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK                                         0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK                                         0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK                                        0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK                                                   0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK                                        0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK                                        0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK                                           0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK                                        0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK                                        0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK                                        0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK                             0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK                             0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK                             0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK                             0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK                             0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK                             0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK                                               0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK                                               0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK                                               0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK                                               0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK                                               0x10000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK                                               0x20000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK                                        0x40000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT                                      0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN__SHIFT                                     0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN__SHIFT                                     0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN__SHIFT                                    0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN__SHIFT                                     0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN__SHIFT                                     0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN__SHIFT                                    0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK                                        0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN_MASK                                       0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN_MASK                                       0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN_MASK                                      0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN_MASK                                       0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN_MASK                                      0x00080000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                             0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT                                        0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT                             0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT                             0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT                                0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT                             0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT                             0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT                             0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT                                    0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT                                    0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT                             0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                               0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK                                          0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK                               0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK                               0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK                                  0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK                               0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK                               0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK                               0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK                                      0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK                                      0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK                                      0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK                                      0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK                                      0x20000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK                               0x40000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT                             0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                           0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                           0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK                               0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                             0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                             0x00080000L
+//DC_DMCU_SCRATCH
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT                                                                  0x0
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK                                                                    0xFFFFFFFFL
+//DMCU_INT_CNT
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT                                                       0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT                                                       0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT                                                      0x10
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK                                                         0x000000FFL
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK                                                         0x0000FF00L
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK                                                        0x00FF0000L
+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT                              0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT                              0x2
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK                                0x00000003L
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK                                0x0000000CL
+//DMCU_UC_CLK_GATING_CNTL
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT                                                      0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT                                                      0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT                                              0x10
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK                                                        0x00000007L
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK                                                        0x00000700L
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK                                                0x00010000L
+//MASTER_COMM_DATA_REG1
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG2
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG3
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_CMD_REG
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT                                                 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT                                                 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT                                                 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT                                                 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK                                                   0x000000FFL
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK                                                   0x0000FF00L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK                                                   0x00FF0000L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK                                                   0xFF000000L
+//MASTER_COMM_CNTL_REG
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT                                                    0x0
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK                                                      0x00000001L
+//SLAVE_COMM_DATA_REG1
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG2
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG3
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_CMD_REG
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT                                                   0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT                                                   0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT                                                   0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT                                                   0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK                                                     0x000000FFL
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK                                                     0x0000FF00L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK                                                     0x00FF0000L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK                                                     0xFF000000L
+//SLAVE_COMM_CNTL_REG
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT                                                      0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT                                         0x8
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK                                                        0x00000001L
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK                                           0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
+//DMCU_PERFMON_INTERRUPT_STATUS2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                            0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                               0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                              0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                                 0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+//DMCU_PERFMON_INTERRUPT_STATUS4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                          0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000010L
+//DMCU_PERFMON_INTERRUPT_STATUS5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__HPO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__HPO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                     0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                       0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                   0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                     0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__HPO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__HPO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT            0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK              0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT          0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+//DMCU_DPRX_INTERRUPT_STATUS1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT            0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT               0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT         0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT            0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT          0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT             0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT      0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT         0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT               0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT                  0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT                          0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT                             0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT                           0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT                              0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT                          0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT                             0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT                         0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT                            0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT                    0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT                       0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT                                      0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT                                         0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT                                      0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT                                         0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT                                      0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT                                         0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT                             0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT                                0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT                             0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT                                0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT                             0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT                                0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT                             0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT                                0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK              0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK           0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK              0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK            0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK               0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK        0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK           0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK                 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                    0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK                            0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK                               0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK                             0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK                                0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK                            0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK                               0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK                           0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK                              0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK                      0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK                         0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK                                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK                                           0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK                                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK                                           0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK                                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK                                           0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK                               0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK                                  0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK                               0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK                                  0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK                               0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK                                  0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK                               0x10000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK                                  0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT     0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT   0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT        0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT                   0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT                    0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT                   0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT                  0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT             0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT                               0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT                               0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT                               0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK       0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK    0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK     0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK          0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK                     0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK                      0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK                     0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK                    0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK               0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK                                 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK                                 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK                                 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK                        0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK                        0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK                        0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK                        0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT          0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT           0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT          0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT         0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT    0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT                      0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT                      0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT                      0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK            0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK             0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK            0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK           0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK      0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x10000000L
+//DMCU_INTERRUPT_STATUS_CONTINUE
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                         0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                            0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                         0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                            0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                         0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                            0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                         0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                            0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                        0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                           0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                        0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                           0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                        0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                           0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                        0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                           0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                        0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                           0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                        0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                           0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                       0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                          0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                       0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                          0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                       0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                          0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                       0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                          0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                      0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                         0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                      0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                         0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                      0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                         0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                      0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                         0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                      0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                         0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                      0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                         0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT                          0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT                             0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT                          0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT                             0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT                          0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT                             0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT                          0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT                             0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT                          0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT                             0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT                          0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT                             0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT                                     0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT                                        0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT                                     0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT                                        0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT                                       0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK                           0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK                              0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK                           0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK                              0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK                           0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK                              0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK                           0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK                              0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK                          0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK                             0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK                          0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK                             0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK                          0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK                             0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK                          0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK                             0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK                          0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK                             0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK                          0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK                             0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                         0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                            0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                         0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                            0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                         0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                            0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                         0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                            0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                        0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                           0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                        0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                           0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                        0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                           0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                        0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                           0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                        0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                           0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                        0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                           0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK                            0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK                               0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK                            0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK                               0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK                            0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK                               0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK                            0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK                               0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK                            0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK                               0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK                            0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK                               0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK                                       0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK                                          0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK                                       0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK                                          0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK                                         0x10000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT                  0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT                  0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT                  0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT                  0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT                 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT                 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT                 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT                 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT                 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT                 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT                   0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT                   0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT                   0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT                   0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT                   0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT                   0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT                              0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT                              0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK                    0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK                    0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK                    0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK                    0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK                   0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK                   0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK                   0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK                   0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK                   0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK                   0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK                     0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK                     0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK                     0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK                     0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK                     0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK                     0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK                                0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK                                0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK                               0x10000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT          0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT          0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT          0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT          0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT          0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT          0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK            0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK            0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK            0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK            0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK            0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK            0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK                       0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK                       0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                      0x10000000L
+//DMCU_INT_CNT_CONTINUE
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT                                              0x0
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT                                              0x8
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT                                             0x10
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK                                                0x000000FFL
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK                                                0x0000FF00L
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK                                               0x00FF0000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT                        0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT                        0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT                        0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT                        0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT                        0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT                        0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT                        0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK                          0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK                          0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK                          0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK                          0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK                          0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK                          0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK                          0x00400000L
+//DMCU_INTERRUPT_STATUS_2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                               0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                  0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                               0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                  0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                               0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                  0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                             0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                             0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                             0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                             0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                             0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                             0xb
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                0xb
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT                                            0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT                                               0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT                                            0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT                                               0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT                                            0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT                                               0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT                                            0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT                                               0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT                                            0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT                                               0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT                                            0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT                                               0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT                                            0x16
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT                                               0x16
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                 0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK                                    0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK                                    0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                 0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK                                    0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                 0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK                                    0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                               0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                  0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                               0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                  0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                               0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                  0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                               0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                  0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                               0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                  0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                               0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                  0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK                                              0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK                                                 0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK                                              0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK                                                 0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK                                              0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK                                                 0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK                                              0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK                                                 0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK                                              0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK                                                 0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK                                              0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK                                                 0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK                                              0x00400000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK                                                 0x00400000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT                        0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT                        0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT                        0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT                                     0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT                                     0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT                                     0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT                                     0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT                                     0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT                                     0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT                                     0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK                          0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK                          0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK                          0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK                          0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK                                       0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK                                       0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK                                       0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK                                       0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK                                       0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK                                       0x00400000L
+//DMCU_INT_CNT_CONT2
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT__SHIFT                                                 0x0
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT__SHIFT                                                 0x8
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT__SHIFT                                                0x10
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT_MASK                                                   0x000000FFL
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT_MASK                                                   0x0000FF00L
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT_MASK                                                  0x00FF0000L
+//DMCU_INT_CNT_CONT3
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT__SHIFT                                                 0x0
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT__SHIFT                                                 0x8
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT__SHIFT                                                0x10
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT_MASK                                                   0x000000FFL
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT_MASK                                                   0x0000FF00L
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT_MASK                                                  0x00FF0000L
+
+
+// addressBlock: dce_dc_dmu_fgsec_dispdec
+//DMCUB_RBBMIF_SEC_CNTL
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT                                                  0x4
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT                                                  0x8
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK                                                    0x00000070L
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK                                                    0x01FFFF00L
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
+//RBBMIF_STATUS_2
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL
+//RBBMIF_INT_STATUS
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
+//RBBMIF_TIMEOUT_DIS_2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON2_PERFCOUNTER_CNTL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_CNTL2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_STATE
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON2_PERFMON_CNTL
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON2_PERFMON_CNTL2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON2_PERFMON_CVALUE_LOW
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON2_PERFMON_HI
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON2_PERFMON_LOW
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT                                                    0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT                                                            0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT                                                       0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT                                                       0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT                                                      0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK                                                      0x04000000L
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK                                                              0x08000000L
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK                                                         0x10000000L
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK                                                         0x20000000L
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK                                                        0x40000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT                                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT                                            0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK                                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK                                              0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE25
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT__SHIFT                                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT__SHIFT                                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT__SHIFT                                           0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT__SHIFT                                            0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT__SHIFT                                            0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT__SHIFT                                           0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT__SHIFT                                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT__SHIFT                                            0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT__SHIFT                                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT__SHIFT                                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT__SHIFT                                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT_MASK                                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT_MASK                                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT_MASK                                             0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT_MASK                                              0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT_MASK                                              0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT_MASK                                             0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT_MASK                                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT_MASK                                              0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT_MASK                                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT_MASK                                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT_MASK                                             0x00000800L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0xb
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT                                      0xe
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x10
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT                                      0x11
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT                                      0x12
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x13
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x18
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x19
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT                                      0x1b
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT                                                0x1c
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00000800L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK                                        0x00004000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00010000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK                                        0x00020000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK                                        0x00040000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00080000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x01000000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x02000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK                                        0x08000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK                                                  0x10000000L
+//DMU_INTERRUPT_DEST2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST__SHIFT                                     0x0
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST__SHIFT                                     0x1
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST__SHIFT                                     0x3
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST__SHIFT                                     0x4
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x5
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST__SHIFT                                     0x6
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST__SHIFT                                     0x7
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x8
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST__SHIFT                                     0x9
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST__SHIFT                                     0xa
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0xb
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST_MASK                                       0x00000001L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST_MASK                                       0x00000002L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST_MASK                                       0x00000008L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST_MASK                                       0x00000010L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST_MASK                                       0x00000040L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST_MASK                                       0x00000080L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST_MASK                                       0x00000200L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST_MASK                                       0x00000400L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000800L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPP_INTERRUPT_DEST
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L
+//HPO_INTERRUPT_DEST
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0x2
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0x3
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00000004L
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00000008L
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT                                                          0x5
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT                                                          0x9
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK                                                            0x00000020L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK                                                            0x00000200L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
+//DMU_MEM_PWR_CNTL
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT                                                   0x0
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT                                                      0x1
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT                                                        0x3
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT                                                      0x4
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT                                                      0x8
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT                                                        0x9
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT                                                      0xa
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK                                                     0x00000001L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK                                                        0x00000006L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK                                                          0x00000008L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK                                                        0x00000100L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK                                                          0x00000200L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK                                                        0x00000400L
+//DMCU_SMU_INTERRUPT_CNTL
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_INT__SHIFT                                                      0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG__SHIFT                                                          0x10
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_INT_MASK                                                        0x00000001L
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_MASK                                                            0xFFFF0000L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
+//ZSC_CNTL
+#define ZSC_CNTL__FORCE_SOC_ACCESS__SHIFT                                                                     0x0
+#define ZSC_CNTL__FORCE_SOC_ACCESS_MASK                                                                       0x00000003L
+//ZSC_CNTL2
+#define ZSC_CNTL2__ALLOW_Z10__SHIFT                                                                           0x0
+#define ZSC_CNTL2__ALLOW_Z10_MASK                                                                             0x00000001L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
+//ZSC_STATUS
+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT                                                          0x0
+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS__SHIFT                                                   0x4
+#define ZSC_STATUS__FENCE_REQ_STATUS__SHIFT                                                                   0x8
+#define ZSC_STATUS__FENCE_ACK_STATUS__SHIFT                                                                   0x9
+#define ZSC_STATUS__FENCE_STATUS__SHIFT                                                                       0xa
+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS_MASK                                                            0x00000003L
+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS_MASK                                                     0x00000030L
+#define ZSC_STATUS__FENCE_REQ_STATUS_MASK                                                                     0x00000100L
+#define ZSC_STATUS__FENCE_ACK_STATUS_MASK                                                                     0x00000200L
+#define ZSC_STATUS__FENCE_STATUS_MASK                                                                         0x00000C00L
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+//DOMAIN0_PG_CONFIG
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN0_PG_STATUS
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN1_PG_CONFIG
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN1_PG_STATUS
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN2_PG_CONFIG
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN2_PG_STATUS
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN3_PG_CONFIG
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN3_PG_STATUS
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN16_PG_CONFIG
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN16_PG_STATUS
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN17_PG_CONFIG
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN17_PG_STATUS
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN18_PG_CONFIG
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN18_PG_STATUS
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
+//DCPG_INTERRUPT_STATUS_2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
+//DCPG_INTERRUPT_CONTROL_1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
+//DCPG_INTERRUPT_CONTROL_3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00002000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00002000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00008000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00002000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
+//DMCUB_CNTL2
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+//DWB_ENABLE_CLK_CTRL
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L
+//DWB_MEM_PWR_CTRL
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L
+//FC_MODE_CTRL
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L
+//FC_FLOW_CTRL
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL
+//FC_WINDOW_START
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L
+//FC_WINDOW_SIZE
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L
+//FC_SOURCE_SIZE
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L
+//DWB_UPDATE_CTRL
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L
+//DWB_CRC_CTRL
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L
+//DWB_CRC_MASK_R_G
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L
+//DWB_CRC_MASK_B_A
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L
+//DWB_CRC_VAL_R_G
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L
+//DWB_CRC_VAL_B_A
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L
+//DWB_OUT_CTRL
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL
+//DWB_HOST_READ_CONTROL
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL
+//DWB_OVERFLOW_STATUS
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L
+//DWB_OVERFLOW_COUNTER
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L
+//DWB_SOFT_RESET
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L
+//DWB_DEBUG_CTRL
+#define DWB_DEBUG_CTRL__DWB_DEBUG_EN__SHIFT                                                                   0x0
+#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL__SHIFT                                                                  0x6
+#define DWB_DEBUG_CTRL__DWB_DEBUG_EN_MASK                                                                     0x00000001L
+#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL_MASK                                                                    0x000000C0L
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+//DWB_HDR_MULT_COEF
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL
+//DWB_GAMUT_REMAP_MODE
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L
+//DWB_GAMUT_REMAP_COEF_FORMAT
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L
+//DWB_GAMUT_REMAPA_C11_C12
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C13_C14
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C21_C22
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C23_C24
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C31_C32
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C33_C34
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C11_C12
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C13_C14
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C21_C22
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C23_C24
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C31_C32
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C33_C34
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L
+//DWB_OGAM_CONTROL
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L
+//DWB_OGAM_LUT_INDEX
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL
+//DWB_OGAM_LUT_DATA
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL
+//DWB_OGAM_LUT_CONTROL
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L
+//DWB_OGAM_RAMA_START_CNTL_B
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_G
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_R
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_BASE_CNTL_B
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_G
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_R
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL1_B
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_B
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_G
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_G
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_R
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_R
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_OFFSET_B
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_G
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_R
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_REGION_0_1
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_2_3
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_4_5
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_6_7
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_8_9
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_10_11
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_12_13
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_14_15
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_16_17
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_18_19
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_20_21
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_22_23
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_24_25
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_26_27
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_28_29
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_30_31
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_32_33
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_START_CNTL_B
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_G
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_R
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_BASE_CNTL_B
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_G
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_R
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL1_B
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_B
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_G
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_G
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_R
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_R
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_OFFSET_B
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_G
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_R
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_REGION_0_1
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_2_3
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_4_5
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_6_7
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_8_9
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_10_11
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_12_13
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_14_15
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_16_17
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_18_19
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_20_21
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_22_23
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_24_25
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_26_27
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_28_29
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_30_31
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_32_33
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON3_PERFCOUNTER_CNTL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_CNTL2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_STATE
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON3_PERFMON_CNTL
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON3_PERFMON_CNTL2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON3_PERFMON_CVALUE_LOW
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON3_PERFMON_HI
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON3_PERFMON_LOW
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L
+//MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                           0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                             0x00000001L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000004L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L
+//MCIF_WB_BUF_PITCH
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L
+//MCIF_WB_BUF_1_STATUS
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_2_STATUS
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_3_STATUS
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_4_STATUS
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L
+//MCIF_WB_SCLK_CHANGE
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L
+//MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                             0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                          0x8
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                               0x000000FFL
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                            0x00000100L
+//MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                               0x0
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                                 0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                          0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                         0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                                    0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                            0x00000010L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                           0x00000020L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                                      0x00000040L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L
+//MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                              0x0
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                          0x2
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                                0x00000001L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                            0x00000004L
+//MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L
+//MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                         0x0
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                           0x00000001L
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L
+//MULTI_LEVEL_QOS_CTRL
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL
+//MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL
+//MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL
+//MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__SHIFT                 0x0
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_MASK                   0x0000FFFFL
+//MCIF_WB_VMID_CONTROL
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL
+//MCIF_WB_MIN_TTO
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON4_PERFCOUNTER_CNTL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_CNTL2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_STATE
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON4_PERFMON_CNTL
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON4_PERFMON_CNTL2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON4_PERFMON_CVALUE_LOW
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON4_PERFMON_HI
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON4_PERFMON_LOW
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L
+//MCIF_WB_WATERMARK
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L
+//MMHUBBUB_WARMUP_CONFIG
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L
+//MMHUBBUB_WARMUP_CONTROL_STATUS
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L
+//MMHUBBUB_WARMUP_BASE_ADDR_LOW
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL
+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL
+//MMHUBBUB_WARMUP_ADDR_REGION
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL
+//MMHUBBUB_MIN_TTO
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL
+//MMHUBBUB_CTRL
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L
+//WBIF_SMU_WM_CONTROL
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
+//MMHUBBUB_WARMUP_VMID_CONTROL
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+//AZ_CLOCK_CNTL
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON5_PERFCOUNTER_CNTL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_CNTL2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_STATE
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON5_PERFMON_CNTL
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON5_PERFMON_CNTL2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON5_PERFMON_CVALUE_LOW
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON5_PERFMON_HI
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON5_PERFMON_LOW
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xc
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT                   0x17
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x001FF000L
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK                     0xFF800000L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT                                          0xc
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK                                            0x0000F000L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT  0x8
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT  0x9
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK  0x00000100L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK  0x00000200L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_HOSTVM_CNTL
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT                                          0x0
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT                                    0x1
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT                                                       0x2
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT                                                  0x3
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT                                                  0x4
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT                                           0x5
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT                                         0x6
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT                                          0x8
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT                                           0x10
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT                                                           0x18
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT                                0x1c
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK                                            0x00000001L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK                                      0x00000002L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK                                                         0x00000004L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK                                                    0x00000008L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK                                                    0x00000010L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK                                             0x00000020L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK                                           0x00000040L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK                                            0x00003F00L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK                                             0x00FF0000L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK                                                             0x0F000000L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK                                  0xF0000000L
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8__SHIFT                    0x10
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8_MASK                      0x00010000L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
+//VTG2_CONTROL
+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
+//VTG3_CONTROL
+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x003FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x3FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
+//DCHUBBUB_TEST_DEBUG_INDEX
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT                                           0x0
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK                                             0x000000FFL
+//DCHUBBUB_TEST_DEBUG_DATA
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT                                             0x0
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
+//DCHUBBUB_SDPIF_CFG2
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_DCC_CFG
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK                                                   0x00000001L
+//DCHUBBUB_RET_PATH_DCC_CFG0_0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG0_1
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_1
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_1
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_1
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_1
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_1
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_1
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_1
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_DCC_STAT_CNTL
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L
+//DCHUBBUB_DCC_STAT0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT1
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT2
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL
+//DCHUBBUB_COMPBUF_CTRL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L
+//DCHUBBUB_DET0_CTRL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_DET1_CTRL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_DET2_CTRL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_DET3_CTRL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_MEM_PWR_MODE_CTRL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT                                             0x8
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT                                               0x1a
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK                                                 0x04000000L
+//COMPBUF_MEM_PWR_CTRL_1
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L
+//COMPBUF_MEM_PWR_CTRL_2
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL
+//DCHUBBUB_MEM_PWR_STATUS
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT                                                0x6
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK                                                  0x000000C0L
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L
+//COMPBUF_RESERVED_SPACE
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT                                              0x10
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_DEFAULT_ADDR_MSB
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
+//DCN_VM_DEFAULT_ADDR_LSB
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON6_PERFCOUNTER_CNTL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_CNTL2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_STATE
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON6_PERFMON_CNTL
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON6_PERFMON_CNTL2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON6_PERFMON_CVALUE_LOW
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON6_PERFMON_HI
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON6_PERFMON_LOW
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP0_HUBPREQ_DEBUG_DB
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP0_HUBPREQ_DEBUG
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_DMDATA_VM_CNTL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ0_VBLANK_PARAMETERS_5
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_6
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_3
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_4
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_5
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_6
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON7_PERFCOUNTER_CNTL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_CNTL2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_STATE
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON7_PERFMON_CNTL
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON7_PERFMON_CNTL2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON7_PERFMON_CVALUE_LOW
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON7_PERFMON_HI
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON7_PERFMON_LOW
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP1_HUBPREQ_DEBUG_DB
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP1_HUBPREQ_DEBUG
+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ1_VBLANK_PARAMETERS_5
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_6
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_3
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_4
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_5
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_6
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON8_PERFCOUNTER_CNTL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_CNTL2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_STATE
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON8_PERFMON_CNTL
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON8_PERFMON_CNTL2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON8_PERFMON_CVALUE_LOW
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON8_PERFMON_HI
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON8_PERFMON_LOW
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+//HUBP2_DCSURF_SURFACE_CONFIG
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP2_DCSURF_ADDR_CONFIG
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP2_DCSURF_TILING_CONFIG
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP2_DCSURF_PRI_VIEWPORT_START
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP2_DCHUBP_CNTL
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP2_HUBP_CLK_CNTL
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP2_DCHUBP_VMPG_CONFIG
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP2_HUBPREQ_DEBUG_DB
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP2_HUBPREQ_DEBUG
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+//HUBPREQ2_DCSURF_SURFACE_PITCH
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ2_VMID_SETTINGS_0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_CONTROL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL2
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ2_DCN_EXPANSION_MODE
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ2_DCN_TTU_QOS_WM
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ2_BLANK_OFFSET_0
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ2_BLANK_OFFSET_1
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ2_DST_DIMENSIONS
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ2_DST_AFTER_SCALER
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ2_PREFETCH_SETTINGS
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ2_PREFETCH_SETTINGS_C
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ2_VBLANK_PARAMETERS_1
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_2
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_3
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_4
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ2_FLIP_PARAMETERS_1
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_2
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_1
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_2
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_3
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_4
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_5
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_6
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_7
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ2_PER_LINE_DELIVERY_PRE
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ2_PER_LINE_DELIVERY
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ2_CURSOR_SETTINGS
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ2_VBLANK_PARAMETERS_5
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_6
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_3
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_4
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_5
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_6
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+//HUBPRET2_HUBPRET_CONTROL
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET2_HUBPRET_READ_LINE0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE1
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_INTERRUPT
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET2_HUBPRET_READ_LINE_VALUE
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_STATUS
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+//CURSOR0_2_CURSOR_CONTROL
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_2_CURSOR_SIZE
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_2_CURSOR_POSITION
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_2_CURSOR_HOT_SPOT
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_2_CURSOR_STEREO_CONTROL
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_2_CURSOR_DST_OFFSET
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_2_DMDATA_ADDRESS_HIGH
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_2_DMDATA_ADDRESS_LOW
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_2_DMDATA_CNTL
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_2_DMDATA_QOS_CNTL
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_2_DMDATA_STATUS
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_2_DMDATA_SW_CNTL
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_2_DMDATA_SW_DATA
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON9_PERFCOUNTER_CNTL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_CNTL2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_STATE
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON9_PERFMON_CNTL
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON9_PERFMON_CNTL2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON9_PERFMON_CVALUE_LOW
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON9_PERFMON_HI
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON9_PERFMON_LOW
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+//HUBP3_DCSURF_SURFACE_CONFIG
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP3_DCSURF_ADDR_CONFIG
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP3_DCSURF_TILING_CONFIG
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP3_DCSURF_PRI_VIEWPORT_START
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP3_DCHUBP_CNTL
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP3_HUBP_CLK_CNTL
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP3_DCHUBP_VMPG_CONFIG
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP3_HUBPREQ_DEBUG_DB
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP3_HUBPREQ_DEBUG
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+//HUBPREQ3_DCSURF_SURFACE_PITCH
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ3_VMID_SETTINGS_0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_CONTROL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL2
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ3_DCN_EXPANSION_MODE
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ3_DCN_TTU_QOS_WM
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ3_BLANK_OFFSET_0
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ3_BLANK_OFFSET_1
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ3_DST_DIMENSIONS
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ3_DST_AFTER_SCALER
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ3_PREFETCH_SETTINGS
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ3_PREFETCH_SETTINGS_C
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ3_VBLANK_PARAMETERS_1
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_2
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_3
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_4
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ3_FLIP_PARAMETERS_1
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_2
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_1
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_2
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_3
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_4
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_5
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_6
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_7
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ3_PER_LINE_DELIVERY_PRE
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ3_PER_LINE_DELIVERY
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ3_CURSOR_SETTINGS
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ3_VBLANK_PARAMETERS_5
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_6
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_3
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_4
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_5
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_6
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+//HUBPRET3_HUBPRET_CONTROL
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET3_HUBPRET_READ_LINE0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE1
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_INTERRUPT
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET3_HUBPRET_READ_LINE_VALUE
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_STATUS
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+//CURSOR0_3_CURSOR_CONTROL
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_3_CURSOR_SIZE
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_3_CURSOR_POSITION
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_3_CURSOR_HOT_SPOT
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_3_CURSOR_STEREO_CONTROL
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_3_CURSOR_DST_OFFSET
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_3_DMDATA_ADDRESS_HIGH
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_3_DMDATA_ADDRESS_LOW
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_3_DMDATA_CNTL
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_3_DMDATA_QOS_CNTL
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_3_DMDATA_STATUS
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_3_DMDATA_SW_CNTL
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_3_DMDATA_SW_DATA
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON10_PERFCOUNTER_CNTL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_CNTL2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_STATE
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON10_PERFMON_CNTL
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON10_PERFMON_CNTL2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON10_PERFMON_CVALUE_LOW
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON10_PERFMON_HI
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON10_PERFMON_LOW
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG0_PRE_DEALPHA
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG0_PRE_CSC_MODE
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG0_PRE_CSC_C11_C12
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C13_C14
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C21_C22
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C23_C24
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C31_C32
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C33_C34
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C11_C12
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C13_C14
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C21_C22
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C23_C24
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C31_C32
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C33_C34
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_CNVC_COEF_FORMAT
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG0_PRE_DEGAM
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG0_PRE_REALPHA
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL0_SCL_BLACK_COLOR
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM0_CM_POST_CSC_CONTROL
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM0_CM_POST_CSC_C11_C12
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C13_C14
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C21_C22
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C23_C24
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C31_C32
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C33_C34
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_B_C11_C12
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C13_C14
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C21_C22
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C23_C24
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C31_C32
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C33_C34
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM0_CM_GAMCOR_CONTROL
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM0_CM_GAMCOR_LUT_INDEX
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM0_CM_GAMCOR_LUT_DATA
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM0_CM_GAMCOR_LUT_CONTROL
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_OFFSET_B
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_G
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_R
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_REGION_0_1
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_2_3
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_4_5
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_6_7
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_8_9
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_10_11
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_12_13
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_14_15
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_16_17
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_18_19
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_20_21
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_22_23
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_24_25
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_26_27
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_28_29
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_30_31
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_32_33
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_OFFSET_B
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_G
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_R
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_REGION_0_1
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_2_3
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_4_5
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_6_7
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_8_9
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_10_11
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_12_13
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_14_15
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_16_17
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_18_19
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_20_21
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_22_23
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_24_25
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_26_27
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_28_29
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_30_31
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_32_33
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_BLNDGAM_CONTROL
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM0_CM_BLNDGAM_LUT_INDEX
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM0_CM_BLNDGAM_LUT_DATA
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM0_CM_BLNDGAM_LUT_CONTROL
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM0_CM_SHAPER_CONTROL
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM0_CM_SHAPER_OFFSET_R
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_G
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_B
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_SCALE_R
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM0_CM_SHAPER_SCALE_G_B
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM0_CM_SHAPER_LUT_INDEX
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM0_CM_SHAPER_LUT_DATA
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM0_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM0_CM_SHAPER_RAMA_START_CNTL_B
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_G
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_R
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_B
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_G
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_R
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_REGION_0_1
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_2_3
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_4_5
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_6_7
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_8_9
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_10_11
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_12_13
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_14_15
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_16_17
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_18_19
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_20_21
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_22_23
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_24_25
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_26_27
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_28_29
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_30_31
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_32_33
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_B
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_G
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_R
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_B
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_G
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_R
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_REGION_0_1
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_2_3
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_4_5
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_6_7
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_8_9
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_10_11
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_12_13
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_14_15
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_16_17
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_18_19
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_20_21
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_22_23
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_24_25
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_26_27
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_28_29
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_30_31
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_32_33
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_MEM_PWR_CTRL2
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM0_CM_MEM_PWR_STATUS2
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM0_CM_3DLUT_MODE
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM0_CM_3DLUT_INDEX
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM0_CM_3DLUT_DATA
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM0_CM_3DLUT_DATA_30BIT
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM0_CM_3DLUT_READ_WRITE_CONTROL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM0_CM_3DLUT_OUT_NORM_FACTOR
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM0_CM_3DLUT_OUT_OFFSET_R
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_G
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_B
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM0_CM_TEST_DEBUG_INDEX
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM0_CM_TEST_DEBUG_DATA
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON11_PERFCOUNTER_CNTL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_CNTL2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_STATE
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON11_PERFMON_CNTL
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON11_PERFMON_CNTL2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON11_PERFMON_CVALUE_LOW
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON11_PERFMON_HI
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON11_PERFMON_LOW
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG1_PRE_DEALPHA
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG1_PRE_CSC_MODE
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG1_PRE_CSC_C11_C12
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C13_C14
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C21_C22
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C23_C24
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C31_C32
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C33_C34
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C11_C12
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C13_C14
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C21_C22
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C23_C24
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C31_C32
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C33_C34
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_CNVC_COEF_FORMAT
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG1_PRE_DEGAM
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG1_PRE_REALPHA
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL1_SCL_BLACK_COLOR
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM1_CM_POST_CSC_CONTROL
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM1_CM_POST_CSC_C11_C12
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C13_C14
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C21_C22
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C23_C24
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C31_C32
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C33_C34
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_B_C11_C12
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C13_C14
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C21_C22
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C23_C24
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C31_C32
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C33_C34
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM1_CM_GAMCOR_CONTROL
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM1_CM_GAMCOR_LUT_INDEX
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM1_CM_GAMCOR_LUT_DATA
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM1_CM_GAMCOR_LUT_CONTROL
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_OFFSET_B
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_G
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_R
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_REGION_0_1
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_2_3
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_4_5
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_6_7
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_8_9
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_10_11
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_12_13
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_14_15
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_16_17
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_18_19
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_20_21
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_22_23
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_24_25
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_26_27
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_28_29
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_30_31
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_32_33
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_OFFSET_B
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_G
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_R
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_REGION_0_1
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_2_3
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_4_5
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_6_7
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_8_9
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_10_11
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_12_13
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_14_15
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_16_17
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_18_19
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_20_21
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_22_23
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_24_25
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_26_27
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_28_29
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_30_31
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_32_33
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_BLNDGAM_CONTROL
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM1_CM_BLNDGAM_LUT_INDEX
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM1_CM_BLNDGAM_LUT_DATA
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM1_CM_BLNDGAM_LUT_CONTROL
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM1_CM_SHAPER_CONTROL
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM1_CM_SHAPER_OFFSET_R
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_G
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_B
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_SCALE_R
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM1_CM_SHAPER_SCALE_G_B
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM1_CM_SHAPER_LUT_INDEX
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM1_CM_SHAPER_LUT_DATA
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM1_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM1_CM_SHAPER_RAMA_START_CNTL_B
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_G
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_R
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_B
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_G
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_R
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_REGION_0_1
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_2_3
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_4_5
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_6_7
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_8_9
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_10_11
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_12_13
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_14_15
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_16_17
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_18_19
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_20_21
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_22_23
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_24_25
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_26_27
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_28_29
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_30_31
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_32_33
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_B
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_G
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_R
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_B
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_G
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_R
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_REGION_0_1
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_2_3
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_4_5
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_6_7
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_8_9
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_10_11
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_12_13
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_14_15
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_16_17
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_18_19
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_20_21
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_22_23
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_24_25
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_26_27
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_28_29
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_30_31
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_32_33
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_MEM_PWR_CTRL2
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM1_CM_MEM_PWR_STATUS2
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM1_CM_3DLUT_MODE
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM1_CM_3DLUT_INDEX
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM1_CM_3DLUT_DATA
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM1_CM_3DLUT_DATA_30BIT
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM1_CM_3DLUT_READ_WRITE_CONTROL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM1_CM_3DLUT_OUT_NORM_FACTOR
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM1_CM_3DLUT_OUT_OFFSET_R
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_G
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_B
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM1_CM_TEST_DEBUG_INDEX
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM1_CM_TEST_DEBUG_DATA
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON12_PERFCOUNTER_CNTL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_CNTL2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_STATE
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON12_PERFMON_CNTL
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON12_PERFMON_CNTL2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON12_PERFMON_CVALUE_LOW
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON12_PERFMON_HI
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON12_PERFMON_LOW
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG2_FORMAT_CONTROL
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG2_FCNV_FP_BIAS_R
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_G
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_B
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_R
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_G
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_B
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_COLOR_KEYER_CONTROL
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG2_COLOR_KEYER_ALPHA
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_RED
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_GREEN
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_BLUE
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG2_ALPHA_2BIT_LUT
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG2_PRE_DEALPHA
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG2_PRE_CSC_MODE
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG2_PRE_CSC_C11_C12
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C13_C14
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C21_C22
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C23_C24
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C31_C32
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C33_C34
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C11_C12
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C13_C14
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C21_C22
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C23_C24
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C31_C32
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C33_C34
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_CNVC_COEF_FORMAT
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG2_PRE_DEGAM
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG2_PRE_REALPHA
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+//CNVC_CUR2_CURSOR0_CONTROL
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR2_CURSOR0_COLOR0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_COLOR1
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+//DSCL2_SCL_COEF_RAM_TAP_SELECT
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL2_SCL_COEF_RAM_TAP_DATA
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL2_SCL_MODE
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL2_SCL_TAP_CONTROL
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL2_DSCL_CONTROL
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL2_DSCL_2TAP_CONTROL
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT_C
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL2_SCL_BLACK_COLOR
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL2_DSCL_UPDATE
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL2_DSCL_AUTOCAL
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL2_OTG_H_BLANK
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_OTG_V_BLANK
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_RECOUT_START
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL2_RECOUT_SIZE
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL2_MPC_SIZE
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL2_LB_DATA_FORMAT
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL2_LB_MEMORY_CTRL
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL2_LB_V_COUNTER
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL2_DSCL_MEM_PWR_CTRL
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL2_DSCL_MEM_PWR_STATUS
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL2_OBUF_CONTROL
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL2_OBUF_MEM_PWR_CTRL
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+//CM2_CM_CONTROL
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM2_CM_POST_CSC_CONTROL
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM2_CM_POST_CSC_C11_C12
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C13_C14
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C21_C22
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C23_C24
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C31_C32
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C33_C34
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_B_C11_C12
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C13_C14
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C21_C22
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C23_C24
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C31_C32
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C33_C34
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_CONTROL
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM2_CM_GAMUT_REMAP_C11_C12
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C13_C14
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C21_C22
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C23_C24
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C31_C32
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C33_C34
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C11_C12
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C13_C14
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C21_C22
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C23_C24
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C31_C32
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C33_C34
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM2_CM_BIAS_CR_R
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM2_CM_BIAS_Y_G_CB_B
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM2_CM_GAMCOR_CONTROL
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM2_CM_GAMCOR_LUT_INDEX
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM2_CM_GAMCOR_LUT_DATA
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM2_CM_GAMCOR_LUT_CONTROL
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_OFFSET_B
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_G
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_R
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_REGION_0_1
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_2_3
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_4_5
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_6_7
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_8_9
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_10_11
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_12_13
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_14_15
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_16_17
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_18_19
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_20_21
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_22_23
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_24_25
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_26_27
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_28_29
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_30_31
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_32_33
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_OFFSET_B
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_G
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_R
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_REGION_0_1
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_2_3
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_4_5
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_6_7
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_8_9
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_10_11
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_12_13
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_14_15
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_16_17
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_18_19
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_20_21
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_22_23
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_24_25
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_26_27
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_28_29
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_30_31
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_32_33
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_BLNDGAM_CONTROL
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM2_CM_BLNDGAM_LUT_INDEX
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM2_CM_BLNDGAM_LUT_DATA
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM2_CM_BLNDGAM_LUT_CONTROL
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_HDR_MULT_COEF
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM2_CM_MEM_PWR_CTRL
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM2_CM_MEM_PWR_STATUS
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM2_CM_DEALPHA
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM2_CM_COEF_FORMAT
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM2_CM_SHAPER_CONTROL
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM2_CM_SHAPER_OFFSET_R
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_G
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_B
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_SCALE_R
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM2_CM_SHAPER_SCALE_G_B
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM2_CM_SHAPER_LUT_INDEX
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM2_CM_SHAPER_LUT_DATA
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM2_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM2_CM_SHAPER_RAMA_START_CNTL_B
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_G
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_R
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_B
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_G
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_R
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_REGION_0_1
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_2_3
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_4_5
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_6_7
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_8_9
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_10_11
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_12_13
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_14_15
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_16_17
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_18_19
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_20_21
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_22_23
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_24_25
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_26_27
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_28_29
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_30_31
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_32_33
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_B
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_G
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_R
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_B
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_G
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_R
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_REGION_0_1
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_2_3
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_4_5
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_6_7
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_8_9
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_10_11
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_12_13
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_14_15
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_16_17
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_18_19
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_20_21
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_22_23
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_24_25
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_26_27
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_28_29
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_30_31
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_32_33
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_MEM_PWR_CTRL2
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM2_CM_MEM_PWR_STATUS2
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM2_CM_3DLUT_MODE
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM2_CM_3DLUT_INDEX
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM2_CM_3DLUT_DATA
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM2_CM_3DLUT_DATA_30BIT
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM2_CM_3DLUT_READ_WRITE_CONTROL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM2_CM_3DLUT_OUT_NORM_FACTOR
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM2_CM_3DLUT_OUT_OFFSET_R
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_G
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_B
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM2_CM_TEST_DEBUG_INDEX
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM2_CM_TEST_DEBUG_DATA
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+//DPP_TOP2_DPP_CONTROL
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP2_DPP_SOFT_RESET
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP2_DPP_CRC_VAL_R_G
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP2_DPP_CRC_VAL_B_A
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP2_DPP_CRC_CTRL
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP2_HOST_READ_CONTROL
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON13_PERFCOUNTER_CNTL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_CNTL2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_STATE
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON13_PERFMON_CNTL
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON13_PERFMON_CNTL2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON13_PERFMON_CVALUE_LOW
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON13_PERFMON_HI
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON13_PERFMON_LOW
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG3_FORMAT_CONTROL
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG3_FCNV_FP_BIAS_R
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_G
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_B
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_R
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_G
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_B
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_COLOR_KEYER_CONTROL
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG3_COLOR_KEYER_ALPHA
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_RED
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_GREEN
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_BLUE
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG3_ALPHA_2BIT_LUT
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG3_PRE_DEALPHA
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG3_PRE_CSC_MODE
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG3_PRE_CSC_C11_C12
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C13_C14
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C21_C22
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C23_C24
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C31_C32
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C33_C34
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C11_C12
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C13_C14
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C21_C22
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C23_C24
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C31_C32
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C33_C34
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_CNVC_COEF_FORMAT
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG3_PRE_DEGAM
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG3_PRE_REALPHA
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+//CNVC_CUR3_CURSOR0_CONTROL
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR3_CURSOR0_COLOR0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_COLOR1
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+//DSCL3_SCL_COEF_RAM_TAP_SELECT
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL3_SCL_COEF_RAM_TAP_DATA
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL3_SCL_MODE
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL3_SCL_TAP_CONTROL
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL3_DSCL_CONTROL
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL3_DSCL_2TAP_CONTROL
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT_C
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL3_SCL_BLACK_COLOR
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL3_DSCL_UPDATE
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL3_DSCL_AUTOCAL
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL3_OTG_H_BLANK
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_OTG_V_BLANK
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_RECOUT_START
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL3_RECOUT_SIZE
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL3_MPC_SIZE
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL3_LB_DATA_FORMAT
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL3_LB_MEMORY_CTRL
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL3_LB_V_COUNTER
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL3_DSCL_MEM_PWR_CTRL
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL3_DSCL_MEM_PWR_STATUS
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL3_OBUF_CONTROL
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL3_OBUF_MEM_PWR_CTRL
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+//CM3_CM_CONTROL
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM3_CM_POST_CSC_CONTROL
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM3_CM_POST_CSC_C11_C12
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C13_C14
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C21_C22
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C23_C24
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C31_C32
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C33_C34
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_B_C11_C12
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C13_C14
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C21_C22
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C23_C24
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C31_C32
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C33_C34
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_CONTROL
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM3_CM_GAMUT_REMAP_C11_C12
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C13_C14
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C21_C22
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C23_C24
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C31_C32
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C33_C34
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C11_C12
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C13_C14
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C21_C22
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C23_C24
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C31_C32
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C33_C34
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM3_CM_BIAS_CR_R
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM3_CM_BIAS_Y_G_CB_B
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM3_CM_GAMCOR_CONTROL
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM3_CM_GAMCOR_LUT_INDEX
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM3_CM_GAMCOR_LUT_DATA
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM3_CM_GAMCOR_LUT_CONTROL
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_OFFSET_B
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_G
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_R
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_REGION_0_1
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_2_3
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_4_5
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_6_7
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_8_9
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_10_11
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_12_13
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_14_15
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_16_17
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_18_19
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_20_21
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_22_23
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_24_25
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_26_27
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_28_29
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_30_31
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_32_33
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_OFFSET_B
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_G
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_R
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_REGION_0_1
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_2_3
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_4_5
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_6_7
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_8_9
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_10_11
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_12_13
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_14_15
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_16_17
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_18_19
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_20_21
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_22_23
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_24_25
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_26_27
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_28_29
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_30_31
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_32_33
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_BLNDGAM_CONTROL
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM3_CM_BLNDGAM_LUT_INDEX
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM3_CM_BLNDGAM_LUT_DATA
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM3_CM_BLNDGAM_LUT_CONTROL
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_HDR_MULT_COEF
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM3_CM_MEM_PWR_CTRL
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM3_CM_MEM_PWR_STATUS
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM3_CM_DEALPHA
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM3_CM_COEF_FORMAT
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM3_CM_SHAPER_CONTROL
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM3_CM_SHAPER_OFFSET_R
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_G
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_B
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_SCALE_R
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM3_CM_SHAPER_SCALE_G_B
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM3_CM_SHAPER_LUT_INDEX
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM3_CM_SHAPER_LUT_DATA
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM3_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM3_CM_SHAPER_RAMA_START_CNTL_B
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_G
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_R
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_B
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_G
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_R
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_REGION_0_1
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_2_3
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_4_5
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_6_7
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_8_9
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_10_11
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_12_13
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_14_15
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_16_17
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_18_19
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_20_21
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_22_23
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_24_25
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_26_27
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_28_29
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_30_31
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_32_33
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_B
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_G
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_R
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_B
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_G
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_R
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_REGION_0_1
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_2_3
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_4_5
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_6_7
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_8_9
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_10_11
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_12_13
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_14_15
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_16_17
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_18_19
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_20_21
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_22_23
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_24_25
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_26_27
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_28_29
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_30_31
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_32_33
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_MEM_PWR_CTRL2
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM3_CM_MEM_PWR_STATUS2
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM3_CM_3DLUT_MODE
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM3_CM_3DLUT_INDEX
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM3_CM_3DLUT_DATA
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM3_CM_3DLUT_DATA_30BIT
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM3_CM_3DLUT_READ_WRITE_CONTROL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM3_CM_3DLUT_OUT_NORM_FACTOR
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM3_CM_3DLUT_OUT_OFFSET_R
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_G
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_B
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM3_CM_TEST_DEBUG_INDEX
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM3_CM_TEST_DEBUG_DATA
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+//DPP_TOP3_DPP_CONTROL
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP3_DPP_SOFT_RESET
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP3_DPP_CRC_VAL_R_G
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP3_DPP_CRC_VAL_B_A
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP3_DPP_CRC_CTRL
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP3_HOST_READ_CONTROL
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON14_PERFCOUNTER_CNTL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_CNTL2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_STATE
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON14_PERFMON_CNTL
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON14_PERFMON_CNTL2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON14_PERFMON_CVALUE_LOW
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON14_PERFMON_HI
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON14_PERFMON_LOW
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+//MPCC2_MPCC_TOP_SEL
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_BOT_SEL
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_OPP_ID
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC2_MPCC_CONTROL
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC2_MPCC_SM_CONTROL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC2_MPCC_UPDATE_LOCK_SEL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC2_MPCC_TOP_GAIN
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_INSIDE
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC2_MPCC_BG_R_CR
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_BG_G_Y
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC2_MPCC_BG_B_CB
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_MEM_PWR_CTRL
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC2_MPCC_STATUS
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+//MPCC3_MPCC_TOP_SEL
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_BOT_SEL
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_OPP_ID
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC3_MPCC_CONTROL
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC3_MPCC_SM_CONTROL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC3_MPCC_UPDATE_LOCK_SEL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC3_MPCC_TOP_GAIN
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_INSIDE
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC3_MPCC_BG_R_CR
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_BG_G_Y
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC3_MPCC_BG_B_CB
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_MEM_PWR_CTRL
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC3_MPCC_STATUS
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
+//MPC_PERFMON_EVENT_CTRL
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
+//MPC_DPP_PENDING_STATUS
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L
+//MPC_PENDING_STATUS_MISC
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET2
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET2
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET2
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET2
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET3
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET3
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET3
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET3
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//MPC_DWB0_MUX
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON15_PERFCOUNTER_CNTL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_CNTL2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_STATE
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON15_PERFMON_CNTL
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON15_PERFMON_CNTL2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON15_PERFMON_CVALUE_LOW
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON15_PERFMON_HI
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON15_PERFMON_LOW
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+//MPCC_OGAM2_MPCC_OGAM_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+//MPCC_OGAM3_MPCC_OGAM_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT2_MUX
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT2_DENORM_CONTROL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT2_DENORM_CLAMP_G_Y
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT2_DENORM_CLAMP_B_CB
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT3_MUX
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT3_DENORM_CONTROL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT3_DENORM_CLAMP_G_Y
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT3_DENORM_CLAMP_B_CB
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_MODE
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT2_CSC_C11_C12_A
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_A
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_A
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_A
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_A
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_A
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C11_C12_B
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_B
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_B
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_B
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_B
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_B
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_MODE
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT3_CSC_C11_C12_A
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_A
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_A
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_A
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_A
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_A
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C11_C12_B
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_B
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_B
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_B
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_B
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_B
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+//MPC_RMU_CONTROL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX__SHIFT                                                                  0x0
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS__SHIFT                                                           0x4
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX__SHIFT                                                                  0x8
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS__SHIFT                                                           0xc
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_MASK                                                                    0x0000000FL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS_MASK                                                             0x000000F0L
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_MASK                                                                    0x00000F00L
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS_MASK                                                             0x0000F000L
+//MPC_RMU_MEM_PWR_CTRL
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE__SHIFT                                                   0x0
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS__SHIFT                                                     0x2
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE__SHIFT                                            0x4
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE__SHIFT                                             0x6
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE__SHIFT                                                0x8
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE__SHIFT                                                   0xa
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS__SHIFT                                                     0xc
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE__SHIFT                                            0xe
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE__SHIFT                                             0x10
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE__SHIFT                                                0x12
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE_MASK                                                     0x00000003L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS_MASK                                                       0x00000004L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE_MASK                                              0x00000030L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE_MASK                                               0x000000C0L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE_MASK                                                  0x00000300L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE_MASK                                                     0x00000C00L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS_MASK                                                       0x00001000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE_MASK                                              0x0000C000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE_MASK                                               0x00030000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE_MASK                                                  0x000C0000L
+//MPC_RMU0_SHAPER_CONTROL
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT                                               0x0
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT                                           0x8
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK                                                 0x00000003L
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK                                             0x00000300L
+//MPC_RMU0_SHAPER_OFFSET_R
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_G
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_B
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_SCALE_R
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT                                                0x0
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK                                                  0x0000FFFFL
+//MPC_RMU0_SHAPER_SCALE_G_B
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT                                              0x10
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK                                                0x0000FFFFL
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK                                                0xFFFF0000L
+//MPC_RMU0_SHAPER_LUT_INDEX
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT                                            0x0
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK                                              0x000000FFL
+//MPC_RMU0_SHAPER_LUT_DATA
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK                                                0x00FFFFFFL
+//MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT                            0x0
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT                                0x4
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK                              0x00000007L
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK                                  0x00000010L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_3DLUT_MODE
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT                                                        0x0
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT                                                        0x4
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT                                                0x8
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK                                                          0x00000003L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK                                                          0x00000010L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK                                                  0x00000300L
+//MPC_RMU0_3DLUT_INDEX
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT                                                      0x0
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK                                                        0x000007FFL
+//MPC_RMU0_3DLUT_DATA
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT                                                       0x0
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT                                                       0x10
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK                                                         0x0000FFFFL
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK                                                         0xFFFF0000L
+//MPC_RMU0_3DLUT_DATA_30BIT
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT                                            0x2
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK                                              0xFFFFFFFCL
+//MPC_RMU0_3DLUT_READ_WRITE_CONTROL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT                                 0x0
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT                                       0x4
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT                                      0x8
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT                                      0x10
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK                                   0x0000000FL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK                                         0x00000010L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK                                        0x00000100L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK                                        0x00030000L
+//MPC_RMU0_3DLUT_OUT_NORM_FACTOR
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT                                  0x0
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK                                    0x0000FFFFL
+//MPC_RMU0_3DLUT_OUT_OFFSET_R
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_G
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_B
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK                                           0xFFFF0000L
+//MPC_RMU1_SHAPER_CONTROL
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT                                               0x0
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT                                           0x8
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK                                                 0x00000003L
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK                                             0x00000300L
+//MPC_RMU1_SHAPER_OFFSET_R
+#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_OFFSET_G
+#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_OFFSET_B
+#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_SCALE_R
+#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT                                                0x0
+#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK                                                  0x0000FFFFL
+//MPC_RMU1_SHAPER_SCALE_G_B
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT                                              0x10
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK                                                0x0000FFFFL
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK                                                0xFFFF0000L
+//MPC_RMU1_SHAPER_LUT_INDEX
+#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT                                            0x0
+#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK                                              0x000000FFL
+//MPC_RMU1_SHAPER_LUT_DATA
+#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK                                                0x00FFFFFFL
+//MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT                            0x0
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT                                0x4
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK                              0x00000007L
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK                                  0x00000010L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_B
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_G
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_R
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_B
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_G
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_R
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_REGION_0_1
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_2_3
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_4_5
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_6_7
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_8_9
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_10_11
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_12_13
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_14_15
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_16_17
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_18_19
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_20_21
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_22_23
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_24_25
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_26_27
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_28_29
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_30_31
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_32_33
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_B
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_G
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_R
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_B
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_G
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_R
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_REGION_0_1
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_2_3
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_4_5
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_6_7
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_8_9
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_10_11
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_12_13
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_14_15
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_16_17
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_18_19
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_20_21
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_22_23
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_24_25
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_26_27
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_28_29
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_30_31
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_32_33
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_3DLUT_MODE
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT                                                        0x0
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT                                                        0x4
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT                                                0x8
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK                                                          0x00000003L
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK                                                          0x00000010L
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK                                                  0x00000300L
+//MPC_RMU1_3DLUT_INDEX
+#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT                                                      0x0
+#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK                                                        0x000007FFL
+//MPC_RMU1_3DLUT_DATA
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT                                                       0x0
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT                                                       0x10
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK                                                         0x0000FFFFL
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK                                                         0xFFFF0000L
+//MPC_RMU1_3DLUT_DATA_30BIT
+#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT                                            0x2
+#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK                                              0xFFFFFFFCL
+//MPC_RMU1_3DLUT_READ_WRITE_CONTROL
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT                                 0x0
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT                                       0x4
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT                                      0x8
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT                                      0x10
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK                                   0x0000000FL
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK                                         0x00000010L
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK                                        0x00000100L
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK                                        0x00030000L
+//MPC_RMU1_3DLUT_OUT_NORM_FACTOR
+#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT                                  0x0
+#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK                                    0x0000FFFFL
+//MPC_RMU1_3DLUT_OUT_OFFSET_R
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK                                           0xFFFF0000L
+//MPC_RMU1_3DLUT_OUT_OFFSET_G
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK                                           0xFFFF0000L
+//MPC_RMU1_3DLUT_OUT_OFFSET_B
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM0_BL1_PWM_USER_LEVEL
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM0_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM0_BL1_PWM_ABM_CNTL
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM0_BL1_PWM_GRP2_REG_LOCK
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM0_DC_ABM1_CNTL
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM0_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_12
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_34
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_CNTL_MISC
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM0_DC_ABM1_HG_MISC_CTRL
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM0_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM0_DC_ABM1_LS_PIXEL_COUNT
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_HG_SAMPLE_RATE
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_LS_SAMPLE_RATE
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_1
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_2
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_3
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_4
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_5
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_6
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_7
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_8
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_9
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_10
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_11
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_12
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_13
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_14
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_15
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_16
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_17
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_18
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_19
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_20
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_21
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_22
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_23
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_24
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_BL_MASTER_LOCK
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM1_BL1_PWM_USER_LEVEL
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM1_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM1_BL1_PWM_ABM_CNTL
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM1_BL1_PWM_GRP2_REG_LOCK
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM1_DC_ABM1_CNTL
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM1_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_12
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_34
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_CNTL_MISC
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM1_DC_ABM1_HG_MISC_CTRL
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM1_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM1_DC_ABM1_LS_PIXEL_COUNT
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_HG_SAMPLE_RATE
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_LS_SAMPLE_RATE
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_1
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_2
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_3
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_4
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_5
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_6
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_7
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_8
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_9
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_10
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_11
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_12
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_13
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_14
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_15
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_16
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_17
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_18
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_19
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_20
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_21
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_22
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_23
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_24
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_BL_MASTER_LOCK
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM2_BL1_PWM_USER_LEVEL
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM2_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM2_BL1_PWM_ABM_CNTL
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM2_BL1_PWM_GRP2_REG_LOCK
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM2_DC_ABM1_CNTL
+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM2_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_12
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_34
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_CNTL_MISC
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM2_DC_ABM1_HG_MISC_CTRL
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM2_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM2_DC_ABM1_LS_PIXEL_COUNT
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_HG_SAMPLE_RATE
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_LS_SAMPLE_RATE
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_1
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_2
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_3
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_4
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_5
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_6
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_7
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_8
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_9
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_10
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_11
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_12
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_13
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_14
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_15
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_16
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_17
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_18
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_19
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_20
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_21
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_22
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_23
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_24
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_BL_MASTER_LOCK
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM3_BL1_PWM_USER_LEVEL
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM3_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM3_BL1_PWM_ABM_CNTL
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM3_BL1_PWM_GRP2_REG_LOCK
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM3_DC_ABM1_CNTL
+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM3_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_12
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_34
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_CNTL_MISC
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM3_DC_ABM1_HG_MISC_CTRL
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM3_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM3_DC_ABM1_LS_PIXEL_COUNT
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_HG_SAMPLE_RATE
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_LS_SAMPLE_RATE
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_1
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_2
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_3
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_4
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_5
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_6
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_7
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_8
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_9
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_10
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_11
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_12
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_13
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_14
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_15
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_16
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_17
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_18
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_19
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_20
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_21
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_22
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_23
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_24
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_BL_MASTER_LOCK
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+//DPG2_DPG_CONTROL
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG2_DPG_RAMP_CONTROL
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG2_DPG_DIMENSIONS
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG2_DPG_COLOUR_R_CR
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG2_DPG_COLOUR_G_Y
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG2_DPG_COLOUR_B_CB
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG2_DPG_OFFSET_SEGMENT
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG2_DPG_STATUS
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT2_FMT_MAP420_MEMORY_CONTROL
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT2_FMT_422_CONTROL
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+//OPPBUF2_OPPBUF_CONTROL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF2_OPPBUF_CONTROL1
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+//OPP_PIPE2_OPP_PIPE_CONTROL
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+//DPG3_DPG_CONTROL
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG3_DPG_RAMP_CONTROL
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG3_DPG_DIMENSIONS
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG3_DPG_COLOUR_R_CR
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG3_DPG_COLOUR_G_Y
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG3_DPG_COLOUR_B_CB
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG3_DPG_OFFSET_SEGMENT
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG3_DPG_STATUS
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT3_FMT_MAP420_MEMORY_CONTROL
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT3_FMT_422_CONTROL
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+//OPPBUF3_OPPBUF_CONTROL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF3_OPPBUF_CONTROL1
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+//OPP_PIPE3_OPP_PIPE_CONTROL
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L
+//OPP_ABM_CONTROL
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON16_PERFCOUNTER_CNTL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_CNTL2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_STATE
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON16_PERFMON_CNTL
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON16_PERFMON_CNTL2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON16_PERFMON_CVALUE_LOW
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON16_PERFMON_HI
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON16_PERFMON_LOW
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM2_OPTC_DATA_SOURCE_SELECT
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM2_OPTC_DATA_FORMAT_CONTROL
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM2_OPTC_BYTES_PER_PIXEL
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM2_OPTC_WIDTH_CONTROL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM2_OPTC_INPUT_CLOCK_CONTROL
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM2_OPTC_MEMORY_CONFIG
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM2_OPTC_INPUT_SPARE_REGISTER
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM3_OPTC_DATA_SOURCE_SELECT
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM3_OPTC_DATA_FORMAT_CONTROL
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM3_OPTC_BYTES_PER_PIXEL
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM3_OPTC_WIDTH_CONTROL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM3_OPTC_INPUT_CLOCK_CONTROL
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM3_OPTC_MEMORY_CONFIG
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM3_OPTC_INPUT_SPARE_REGISTER
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG0_OTG_CRC_CNTL2
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG0_OTG_GLOBAL_CONTROL4
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_DRR_TIMING_INT_STATUS
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG0_OTG_DRR_V_TOTAL_CHANGE
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG0_OTG_DRR_TRIGGER_WINDOW
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG0_OTG_M_CONST_DTO0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG0_OTG_M_CONST_DTO1
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG1_OTG_CRC_CNTL2
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG1_OTG_GLOBAL_CONTROL4
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_DRR_TIMING_INT_STATUS
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG1_OTG_DRR_V_TOTAL_CHANGE
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG1_OTG_DRR_TRIGGER_WINDOW
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG1_OTG_M_CONST_DTO0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG1_OTG_M_CONST_DTO1
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+//OTG2_OTG_H_TOTAL
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_H_BLANK_START_END
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_H_SYNC_A
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_H_SYNC_A_CNTL
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG2_OTG_H_TIMING_CNTL
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG2_OTG_V_TOTAL
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_V_TOTAL_MIN
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MAX
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MID
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_CONTROL
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG2_OTG_V_TOTAL_INT_STATUS
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG2_OTG_VSYNC_NOM_INT_STATUS
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG2_OTG_V_BLANK_START_END
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_V_SYNC_A
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_V_SYNC_A_CNTL
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG2_OTG_TRIGA_CNTL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGA_MANUAL_TRIG
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_TRIGB_CNTL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGB_MANUAL_TRIG
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG2_OTG_FLOW_CONTROL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG2_OTG_CONTROL
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG2_OTG_INTERLACE_CONTROL
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG2_OTG_INTERLACE_STATUS
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG2_OTG_PIXEL_DATA_READBACK0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG2_OTG_PIXEL_DATA_READBACK1
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG2_OTG_STATUS
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG2_OTG_STATUS_POSITION
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG2_OTG_NOM_VERT_POSITION
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG2_OTG_STATUS_FRAME_COUNT
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG2_OTG_STATUS_VF_COUNT
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_STATUS_HV_COUNT
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_COUNT_CONTROL
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG2_OTG_COUNT_RESET
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG2_OTG_VERT_SYNC_CONTROL
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG2_OTG_STEREO_STATUS
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG2_OTG_STEREO_CONTROL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG2_OTG_SNAPSHOT_STATUS
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG2_OTG_SNAPSHOT_CONTROL
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG2_OTG_SNAPSHOT_POSITION
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG2_OTG_SNAPSHOT_FRAME
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG2_OTG_INTERRUPT_CONTROL
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG2_OTG_UPDATE_LOCK
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG2_OTG_MASTER_EN
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_CRC_CNTL
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG2_OTG_CRC_CNTL2
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_DATA_RG
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC0_DATA_B
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_DATA_RG
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC1_DATA_B
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_RG
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_B
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_RG
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_B
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG2_OTG_STATIC_SCREEN_CONTROL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG2_OTG_3D_STRUCTURE_CONTROL
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG2_OTG_GSL_VSYNC_GAP
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG2_OTG_MASTER_UPDATE_MODE
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG2_OTG_CLOCK_CONTROL
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG2_OTG_VSTARTUP_PARAM
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG2_OTG_VUPDATE_PARAM
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG2_OTG_VREADY_PARAM
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG2_OTG_GLOBAL_SYNC_STATUS
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG2_OTG_MASTER_UPDATE_LOCK
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG2_OTG_GSL_CONTROL
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG2_OTG_GSL_WINDOW_X
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG2_OTG_GSL_WINDOW_Y
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG2_OTG_VUPDATE_KEEPOUT
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL1
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL2
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL3
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG2_OTG_GLOBAL_CONTROL4
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG2_OTG_TRIG_MANUAL_CONTROL
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_MANUAL_FLOW_CONTROL
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_DRR_TIMING_INT_STATUS
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG2_OTG_DRR_V_TOTAL_CHANGE
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG2_OTG_DRR_TRIGGER_WINDOW
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG2_OTG_DRR_CONTROL
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG2_OTG_M_CONST_DTO0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG2_OTG_M_CONST_DTO1
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG2_OTG_REQUEST_CONTROL
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG2_OTG_DSC_START_POSITION
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG2_OTG_PIPE_UPDATE_STATUS
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG2_OTG_SPARE_REGISTER
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+//OTG3_OTG_H_TOTAL
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_H_BLANK_START_END
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_H_SYNC_A
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_H_SYNC_A_CNTL
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG3_OTG_H_TIMING_CNTL
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG3_OTG_V_TOTAL
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_V_TOTAL_MIN
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MAX
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MID
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_CONTROL
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG3_OTG_V_TOTAL_INT_STATUS
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG3_OTG_VSYNC_NOM_INT_STATUS
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG3_OTG_V_BLANK_START_END
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_V_SYNC_A
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_V_SYNC_A_CNTL
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG3_OTG_TRIGA_CNTL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGA_MANUAL_TRIG
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_TRIGB_CNTL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGB_MANUAL_TRIG
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG3_OTG_FLOW_CONTROL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG3_OTG_CONTROL
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG3_OTG_INTERLACE_CONTROL
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG3_OTG_INTERLACE_STATUS
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG3_OTG_PIXEL_DATA_READBACK0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG3_OTG_PIXEL_DATA_READBACK1
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG3_OTG_STATUS
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG3_OTG_STATUS_POSITION
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG3_OTG_NOM_VERT_POSITION
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG3_OTG_STATUS_FRAME_COUNT
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG3_OTG_STATUS_VF_COUNT
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_STATUS_HV_COUNT
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_COUNT_CONTROL
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG3_OTG_COUNT_RESET
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG3_OTG_VERT_SYNC_CONTROL
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG3_OTG_STEREO_STATUS
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG3_OTG_STEREO_CONTROL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG3_OTG_SNAPSHOT_STATUS
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG3_OTG_SNAPSHOT_CONTROL
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG3_OTG_SNAPSHOT_POSITION
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG3_OTG_SNAPSHOT_FRAME
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG3_OTG_INTERRUPT_CONTROL
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG3_OTG_UPDATE_LOCK
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG3_OTG_MASTER_EN
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_CRC_CNTL
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG3_OTG_CRC_CNTL2
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_DATA_RG
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC0_DATA_B
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_DATA_RG
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC1_DATA_B
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_RG
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_B
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_RG
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_B
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG3_OTG_STATIC_SCREEN_CONTROL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG3_OTG_3D_STRUCTURE_CONTROL
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG3_OTG_GSL_VSYNC_GAP
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG3_OTG_MASTER_UPDATE_MODE
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG3_OTG_CLOCK_CONTROL
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG3_OTG_VSTARTUP_PARAM
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG3_OTG_VUPDATE_PARAM
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG3_OTG_VREADY_PARAM
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG3_OTG_GLOBAL_SYNC_STATUS
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG3_OTG_MASTER_UPDATE_LOCK
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG3_OTG_GSL_CONTROL
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG3_OTG_GSL_WINDOW_X
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG3_OTG_GSL_WINDOW_Y
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG3_OTG_VUPDATE_KEEPOUT
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL1
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL2
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL3
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG3_OTG_GLOBAL_CONTROL4
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG3_OTG_TRIG_MANUAL_CONTROL
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_MANUAL_FLOW_CONTROL
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_DRR_TIMING_INT_STATUS
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG3_OTG_DRR_V_TOTAL_CHANGE
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG3_OTG_DRR_TRIGGER_WINDOW
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG3_OTG_DRR_CONTROL
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG3_OTG_M_CONST_DTO0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG3_OTG_M_CONST_DTO1
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG3_OTG_REQUEST_CONTROL
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG3_OTG_DSC_START_POSITION
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG3_OTG_PIPE_UPDATE_STATUS
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG3_OTG_SPARE_REGISTER
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+//DWB_SOURCE_SELECT
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT                                                     0x0
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT                                                     0x3
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT                                                     0x6
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK                                                       0x00000007L
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK                                                       0x00000038L
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK                                                       0x000001C0L
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON17_PERFCOUNTER_CNTL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_CNTL2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_STATE
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON17_PERFMON_CNTL
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON17_PERFMON_CNTL2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON17_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON17_PERFMON_CVALUE_LOW
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON17_PERFMON_HI
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON17_PERFMON_LOW
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+//HPD4_DC_HPD_INT_STATUS
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD4_DC_HPD_INT_CONTROL
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD4_DC_HPD_CONTROL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD4_DC_HPD_FAST_TRAIN_CNTL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP0_DP_DPHY_INTERNAL_CTRL
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP0_DP_DSC_BYTES_PER_PIXEL
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_GSP8_CNTL
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP9_CNTL
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP10_CNTL
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP11_CNTL
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP_EN_DB_STATUS
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG0_DIG_FIFO_STATUS
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP1_DP_DPHY_INTERNAL_CTRL
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP1_DP_DSC_BYTES_PER_PIXEL
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_GSP8_CNTL
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP9_CNTL
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP10_CNTL
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP11_CNTL
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP_EN_DB_STATUS
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG1_DIG_FIFO_STATUS
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP2_DP_DPHY_INTERNAL_CTRL
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSA_TIMING_PARAM1
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM2
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM3
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP2_DP_MSA_TIMING_PARAM4
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP2_DP_MSO_CNTL
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP2_DP_MSO_CNTL1
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP2_DP_DSC_CNTL
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP2_DP_SEC_CNTL2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL3
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL4
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL5
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL6
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP2_DP_SEC_CNTL7
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP2_DP_DB_CNTL
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP2_DP_MSA_VBID_MISC
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP2_DP_SEC_METADATA_TRANSMISSION
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP2_DP_DSC_BYTES_PER_PIXEL
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP2_DP_ALPM_CNTL
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_GSP8_CNTL
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP9_CNTL
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP10_CNTL
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP11_CNTL
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP_EN_DB_STATUS
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG2_DIG_FIFO_STATUS
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG2_HDMI_METADATA_PACKET_CONTROL
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG2_HDMI_DB_CONTROL
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG2_TMDS_CTL0_1_GEN_CNTL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG2_TMDS_CTL2_3_GEN_CNTL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG2_FORCE_DIG_DISABLE
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP3_DP_DPHY_INTERNAL_CTRL
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSA_TIMING_PARAM1
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM2
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM3
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP3_DP_MSA_TIMING_PARAM4
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP3_DP_MSO_CNTL
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP3_DP_MSO_CNTL1
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP3_DP_DSC_CNTL
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP3_DP_SEC_CNTL2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL3
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL4
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL5
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL6
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP3_DP_SEC_CNTL7
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP3_DP_DB_CNTL
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP3_DP_MSA_VBID_MISC
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP3_DP_SEC_METADATA_TRANSMISSION
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP3_DP_DSC_BYTES_PER_PIXEL
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP3_DP_ALPM_CNTL
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_GSP8_CNTL
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP9_CNTL
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP10_CNTL
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP11_CNTL
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP_EN_DB_STATUS
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG3_DIG_FIFO_STATUS
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG3_HDMI_METADATA_PACKET_CONTROL
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG3_HDMI_DB_CONTROL
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG3_TMDS_CTL0_1_GEN_CNTL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG3_TMDS_CTL2_3_GEN_CNTL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG3_FORCE_DIG_DISABLE
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+//DP4_DP_LINK_CNTL
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP4_DP_PIXEL_FORMAT
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP4_DP_MSA_COLORIMETRY
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP4_DP_CONFIG
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP4_DP_VID_STREAM_CNTL
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP4_DP_STEER_FIFO
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP4_DP_MSA_MISC
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP4_DP_DPHY_INTERNAL_CTRL
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP4_DP_VID_TIMING
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP4_DP_VID_N
+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP4_DP_VID_M
+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP4_DP_LINK_FRAMING_CNTL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP4_DP_HBR2_EYE_PATTERN
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP4_DP_VID_MSA_VBID
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP4_DP_VID_INTERRUPT_CNTL
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP4_DP_DPHY_CNTL
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP4_DP_DPHY_SYM0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM1
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM2
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP4_DP_DPHY_8B10B_CNTL
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP4_DP_DPHY_PRBS_CNTL
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP4_DP_DPHY_SCRAM_CNTL
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP4_DP_DPHY_CRC_EN
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP4_DP_DPHY_CRC_CNTL
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP4_DP_DPHY_CRC_RESULT
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP4_DP_DPHY_CRC_MST_CNTL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP4_DP_DPHY_CRC_MST_STATUS
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP4_DP_DPHY_FAST_TRAINING
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP4_DP_DPHY_FAST_TRAINING_STATUS
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP4_DP_SEC_CNTL
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL1
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_FRAMING1
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING2
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING3
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP4_DP_SEC_FRAMING4
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP4_DP_SEC_AUD_N
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_N_READBACK
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_M_READBACK
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_TIMESTAMP
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP4_DP_SEC_PACKET_CNTL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP4_DP_MSE_RATE_CNTL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP4_DP_MSE_RATE_UPDATE
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP4_DP_MSE_SAT0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT1
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT2
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT_UPDATE
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP4_DP_MSE_LINK_TIMING
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP4_DP_MSE_MISC_CNTL
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP4_DP_MSE_SAT0_STATUS
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT1_STATUS
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT2_STATUS
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSA_TIMING_PARAM1
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM2
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM3
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP4_DP_MSA_TIMING_PARAM4
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP4_DP_MSO_CNTL
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP4_DP_MSO_CNTL1
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP4_DP_DSC_CNTL
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP4_DP_SEC_CNTL2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL3
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL4
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL5
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL6
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP4_DP_SEC_CNTL7
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP4_DP_DB_CNTL
+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP4_DP_MSA_VBID_MISC
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP4_DP_SEC_METADATA_TRANSMISSION
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP4_DP_DSC_BYTES_PER_PIXEL
+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP4_DP_ALPM_CNTL
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_GSP8_CNTL
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP9_CNTL
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP10_CNTL
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP11_CNTL
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP_EN_DB_STATUS
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+//DIG4_DIG_FE_CNTL
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG4_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG4_DIG_OUTPUT_CRC_CNTL
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG4_DIG_OUTPUT_CRC_RESULT
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG4_DIG_CLOCK_PATTERN
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG4_DIG_TEST_PATTERN
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG4_DIG_RANDOM_PATTERN_SEED
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG4_DIG_FIFO_STATUS
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG4_HDMI_METADATA_PACKET_CONTROL
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG4_HDMI_CONTROL
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG4_HDMI_STATUS
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG4_HDMI_AUDIO_PACKET_CONTROL
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG4_HDMI_ACR_PACKET_CONTROL
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG4_HDMI_VBI_PACKET_CONTROL
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG4_HDMI_INFOFRAME_CONTROL0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG4_HDMI_INFOFRAME_CONTROL1
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG4_HDMI_GC
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG4_HDMI_DB_CONTROL
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG4_HDMI_ACR_32_0
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_32_1
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_44_0
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_44_1
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_48_0
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_48_1
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_STATUS_0
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG4_HDMI_ACR_STATUS_1
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG4_AFMT_CNTL
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG4_DIG_BE_CNTL
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG4_DIG_BE_EN_CNTL
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG4_TMDS_CNTL
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG4_TMDS_CONTROL_CHAR
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG4_TMDS_CONTROL0_FEEDBACK
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG4_TMDS_STEREOSYNC_CTL_SEL
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG4_TMDS_CTL_BITS
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG4_TMDS_DCBALANCER_CONTROL
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG4_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG4_TMDS_CTL0_1_GEN_CNTL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG4_TMDS_CTL2_3_GEN_CNTL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG4_DIG_VERSION
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG4_FORCE_DIG_DISABLE
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+//AFMT0_AFMT_VBI_PACKET_CONTROL
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT0_AFMT_AUDIO_INFO0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT0_AFMT_AUDIO_INFO1
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT0_AFMT_60958_0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT0_AFMT_60958_1
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_CONTROL
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT0_AFMT_RAMP_CONTROL0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT0_AFMT_RAMP_CONTROL1
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT0_AFMT_RAMP_CONTROL2
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_RAMP_CONTROL3
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_60958_2
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_RESULT
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT0_AFMT_STATUS
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT0_AFMT_INFOFRAME_CONTROL0
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT0_AFMT_INTERRUPT_STATUS
+//AFMT0_AFMT_AUDIO_SRC_CONTROL
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT0_AFMT_MEM_PWR
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+//AFMT1_AFMT_VBI_PACKET_CONTROL
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT1_AFMT_AUDIO_INFO0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT1_AFMT_AUDIO_INFO1
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT1_AFMT_60958_0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT1_AFMT_60958_1
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_CONTROL
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT1_AFMT_RAMP_CONTROL0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT1_AFMT_RAMP_CONTROL1
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT1_AFMT_RAMP_CONTROL2
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_RAMP_CONTROL3
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_60958_2
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_RESULT
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT1_AFMT_STATUS
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT1_AFMT_INFOFRAME_CONTROL0
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT1_AFMT_INTERRUPT_STATUS
+//AFMT1_AFMT_AUDIO_SRC_CONTROL
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT1_AFMT_MEM_PWR
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+//AFMT2_AFMT_VBI_PACKET_CONTROL
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT2_AFMT_AUDIO_INFO0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT2_AFMT_AUDIO_INFO1
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT2_AFMT_60958_0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT2_AFMT_60958_1
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_CONTROL
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT2_AFMT_RAMP_CONTROL0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT2_AFMT_RAMP_CONTROL1
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT2_AFMT_RAMP_CONTROL2
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_RAMP_CONTROL3
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_60958_2
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_RESULT
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT2_AFMT_STATUS
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT2_AFMT_INFOFRAME_CONTROL0
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT2_AFMT_INTERRUPT_STATUS
+//AFMT2_AFMT_AUDIO_SRC_CONTROL
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT2_AFMT_MEM_PWR
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+//AFMT3_AFMT_VBI_PACKET_CONTROL
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT3_AFMT_AUDIO_INFO0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT3_AFMT_AUDIO_INFO1
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT3_AFMT_60958_0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT3_AFMT_60958_1
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_CONTROL
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT3_AFMT_RAMP_CONTROL0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT3_AFMT_RAMP_CONTROL1
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT3_AFMT_RAMP_CONTROL2
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_RAMP_CONTROL3
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_60958_2
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_RESULT
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT3_AFMT_STATUS
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT3_AFMT_INFOFRAME_CONTROL0
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT3_AFMT_INTERRUPT_STATUS
+//AFMT3_AFMT_AUDIO_SRC_CONTROL
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT3_AFMT_MEM_PWR
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
+//AFMT4_AFMT_VBI_PACKET_CONTROL
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT4_AFMT_AUDIO_INFO0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT4_AFMT_AUDIO_INFO1
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT4_AFMT_60958_0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT4_AFMT_60958_1
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_CONTROL
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT4_AFMT_RAMP_CONTROL0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT4_AFMT_RAMP_CONTROL1
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT4_AFMT_RAMP_CONTROL2
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_RAMP_CONTROL3
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_60958_2
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_RESULT
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT4_AFMT_STATUS
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT4_AFMT_INFOFRAME_CONTROL0
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT4_AFMT_INTERRUPT_STATUS
+//AFMT4_AFMT_AUDIO_SRC_CONTROL
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT4_AFMT_MEM_PWR
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+//DME0_DME_CONTROL
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME0_DME_MEMORY_CONTROL
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG0_VPG_GENERIC_PACKET_DATA
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG0_VPG_GENERIC_STATUS
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG0_VPG_MEM_PWR
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG0_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG0_VPG_ISRC1_2_DATA
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG0_VPG_MPEG_INFO0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG0_VPG_MPEG_INFO1
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+//DME1_DME_CONTROL
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME1_DME_MEMORY_CONTROL
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG1_VPG_GENERIC_PACKET_DATA
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG1_VPG_GENERIC_STATUS
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG1_VPG_MEM_PWR
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG1_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG1_VPG_ISRC1_2_DATA
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG1_VPG_MPEG_INFO0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG1_VPG_MPEG_INFO1
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+//DME2_DME_CONTROL
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME2_DME_MEMORY_CONTROL
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG2_VPG_GENERIC_PACKET_DATA
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG2_VPG_GENERIC_STATUS
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG2_VPG_MEM_PWR
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG2_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG2_VPG_ISRC1_2_DATA
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG2_VPG_MPEG_INFO0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG2_VPG_MPEG_INFO1
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+//DME3_DME_CONTROL
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME3_DME_MEMORY_CONTROL
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG3_VPG_GENERIC_PACKET_DATA
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG3_VPG_GENERIC_STATUS
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG3_VPG_MEM_PWR
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG3_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG3_VPG_ISRC1_2_DATA
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG3_VPG_MPEG_INFO0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG3_VPG_MPEG_INFO1
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
+//DME4_DME_CONTROL
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME4_DME_MEMORY_CONTROL
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
+//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG4_VPG_GENERIC_PACKET_DATA
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG4_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG4_VPG_GENERIC_STATUS
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG4_VPG_MEM_PWR
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG4_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG4_VPG_ISRC1_2_DATA
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG4_VPG_MPEG_INFO0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG4_VPG_MPEG_INFO1
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX2_AUX_PHY_WAKE_CNTL
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX3_AUX_PHY_WAKE_CNTL
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+//DP_AUX4_AUX_CONTROL
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX4_AUX_SW_CONTROL
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX4_AUX_ARB_CONTROL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX4_AUX_INTERRUPT_CONTROL
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX4_AUX_SW_STATUS
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX4_AUX_LS_STATUS
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX4_AUX_SW_DATA
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX4_AUX_LS_DATA
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX4_AUX_DPHY_TX_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL1
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX4_AUX_DPHY_TX_STATUS
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX4_AUX_DPHY_RX_STATUS
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX4_AUX_PHY_WAKE_CNTL
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC5_HW_STATUS
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC5_SPEED
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC5_SETUP
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT                                                           0x5
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT                                                            0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT                                                          0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT                                                          0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT                                                          0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT                                                          0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT                                                          0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT                                                          0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT                                                          0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK                                                             0x00000020L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK                                                              0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK                                                            0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK                                                            0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK                                                            0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK                                                            0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK                                                            0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK                                                            0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK                                                            0x40000000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT                                                           0x18
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT                                                           0x19
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT                                                           0x1a
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT                                                           0x1b
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT                                                           0x1c
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT                                                           0x1d
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT                                                           0x1e
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK                                                             0x01000000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK                                                             0x02000000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK                                                             0x04000000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK                                                             0x08000000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK                                                             0x10000000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK                                                             0x20000000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK                                                             0x40000000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
+//DIO_GENERIC_INTERRUPT_MESSAGE
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT                                    0x0
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT                                   0x1
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK                                      0x00000001L
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK                                     0xFFFFFFFEL
+//DIO_GENERIC_INTERRUPT_CLEAR
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT                                       0x0
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK                                         0x00000001L
+//DIO_LINKA_CNTL
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKB_CNTL
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKC_CNTL
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKD_CNTL
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKE_CNTL
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKF_CNTL
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON18_PERFCOUNTER_CNTL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_CNTL2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_STATE
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON18_PERFMON_CNTL
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON18_PERFMON_CNTL2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON18_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON18_PERFMON_CVALUE_LOW
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON18_PERFMON_HI
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON18_PERFMON_LOW
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYE_LINK_CNTL
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//INTERCEPT_STATE
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE__SHIFT                                                 0x4
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE__SHIFT                                                 0x5
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE__SHIFT                                                 0x6
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE__SHIFT                                                 0x7
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE__SHIFT                                                 0x8
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE__SHIFT                                                 0x9
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE_MASK                                                   0x00000010L
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE_MASK                                                   0x00000020L
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE_MASK                                                   0x00000040L
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE_MASK                                                   0x00000080L
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE_MASK                                                   0x00000100L
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE_MASK                                                   0x00000200L
+//DCIO_BL_PWM_FRAME_START_DISP_SEL
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+//DC_GPIO_PWRSEQ1_EN
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
+//PWRSEQ0_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ0_PANEL_PWRSEQ_CNTL
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ0_PANEL_PWRSEQ_STATE
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ0_BL_PWM_CNTL
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ0_BL_PWM_CNTL2
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ0_BL_PWM_PERIOD_CNTL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ0_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ0_PWRSEQ_SPARE
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec
+//PWRSEQ1_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ1_PANEL_PWRSEQ_CNTL
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ1_PANEL_PWRSEQ_STATE
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ1_BL_PWM_CNTL
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ1_BL_PWM_CNTL2
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ1_BL_PWM_PERIOD_CNTL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ1_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ1_PWRSEQ_SPARE
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON19_PERFCOUNTER_CNTL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_CNTL2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_STATE
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON19_PERFMON_CNTL
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON19_PERFMON_CNTL2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON19_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON19_PERFMON_CVALUE_LOW
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON19_PERFMON_HI
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON19_PERFMON_LOW
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP1_DSC_DEBUG_CONTROL
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON20_PERFCOUNTER_CNTL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_CNTL2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_STATE
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON20_PERFMON_CNTL
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON20_PERFMON_CNTL2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON20_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON20_PERFMON_CVALUE_LOW
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON20_PERFMON_HI
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON20_PERFMON_LOW
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+//DSCC2_DSCC_CONFIG0
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC2_DSCC_CONFIG1
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC2_DSCC_STATUS
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC2_DSCC_PPS_CONFIG0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG1
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG2
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG3
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG4
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG5
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG6
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC2_DSCC_PPS_CONFIG7
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG8
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG9
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG11
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG12
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG13
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG14
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG15
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG16
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG17
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG18
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG19
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG20
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG21
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG22
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC2_DSCC_MEM_POWER_CONTROL
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_MAX_ABS_ERROR0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC2_DSCC_MAX_ABS_ERROR1
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+//DSCCIF2_DSCCIF_CONFIG0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF2_DSCCIF_CONFIG1
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+//DSC_TOP2_DSC_TOP_CONTROL
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP2_DSC_DEBUG_CONTROL
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON21_PERFCOUNTER_CNTL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_CNTL2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_STATE
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON21_PERFMON_CNTL
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON21_PERFMON_CNTL2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON21_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON21_PERFMON_CVALUE_LOW
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON21_PERFMON_HI
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON21_PERFMON_LOW
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0x7F000000L
+//HPO_TOP_HW_CONTROL
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
+//DP_STREAM_MAPPER_CONTROL0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL1
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL2
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL3
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+
+
+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON22_PERFCOUNTER_CNTL
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON22_PERFCOUNTER_CNTL2
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON22_PERFCOUNTER_STATE
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON22_PERFMON_CNTL
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON22_PERFMON_CNTL2
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON22_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON22_PERFMON_CVALUE_LOW
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON22_PERFMON_HI
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON22_PERFMON_LOW
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+//AFMT5_AFMT_VBI_PACKET_CONTROL
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT5_AFMT_AUDIO_INFO0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT5_AFMT_AUDIO_INFO1
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT5_AFMT_60958_0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT5_AFMT_60958_1
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_CONTROL
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT5_AFMT_RAMP_CONTROL0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT5_AFMT_RAMP_CONTROL1
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT5_AFMT_RAMP_CONTROL2
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_RAMP_CONTROL3
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_60958_2
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_RESULT
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT5_AFMT_STATUS
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT5_AFMT_INFOFRAME_CONTROL0
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT5_AFMT_INTERRUPT_STATUS
+//AFMT5_AFMT_AUDIO_SRC_CONTROL
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT5_AFMT_MEM_PWR
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+//DME5_DME_CONTROL
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME5_DME_MEMORY_CONTROL
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG5_VPG_GENERIC_PACKET_DATA
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG5_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG5_VPG_GENERIC_STATUS
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG5_VPG_MEM_PWR
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG5_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG5_VPG_ISRC1_2_DATA
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG5_VPG_MPEG_INFO0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG5_VPG_MPEG_INFO1
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+//APG0_APG_CONTROL
+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG0_APG_CONTROL2
+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG0_APG_DBG_GEN_CONTROL
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG0_APG_PACKET_CONTROL
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG0_APG_AUDIO_CRC_CONTROL
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG0_APG_AUDIO_CRC_CONTROL2
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG0_APG_AUDIO_CRC_RESULT
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG0_APG_STATUS
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG0_APG_STATUS2
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG0_APG_MEM_PWR
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG0_APG_SPARE
+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+//DME6_DME_CONTROL
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME6_DME_MEMORY_CONTROL
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG6_VPG_GENERIC_PACKET_DATA
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG6_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG6_VPG_GENERIC_STATUS
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG6_VPG_MEM_PWR
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG6_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG6_VPG_ISRC1_2_DATA
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG6_VPG_MPEG_INFO0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG6_VPG_MPEG_INFO1
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
+//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+//APG1_APG_CONTROL
+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG1_APG_CONTROL2
+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG1_APG_PACKET_CONTROL
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG1_APG_AUDIO_CRC_CONTROL
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG1_APG_AUDIO_CRC_CONTROL2
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG1_APG_AUDIO_CRC_RESULT
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG1_APG_STATUS
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG1_APG_STATUS2
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG1_APG_MEM_PWR
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG1_APG_SPARE
+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+//DME7_DME_CONTROL
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME7_DME_MEMORY_CONTROL
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG7_VPG_GENERIC_PACKET_DATA
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG7_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG7_VPG_GENERIC_STATUS
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG7_VPG_MEM_PWR
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG7_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG7_VPG_ISRC1_2_DATA
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG7_VPG_MPEG_INFO0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG7_VPG_MPEG_INFO1
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
+//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+//APG2_APG_CONTROL
+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG2_APG_CONTROL2
+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG2_APG_PACKET_CONTROL
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG2_APG_AUDIO_CRC_CONTROL
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG2_APG_AUDIO_CRC_CONTROL2
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG2_APG_AUDIO_CRC_RESULT
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG2_APG_STATUS
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG2_APG_STATUS2
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG2_APG_MEM_PWR
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG2_APG_SPARE
+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+//DME8_DME_CONTROL
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME8_DME_MEMORY_CONTROL
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG8_VPG_GENERIC_PACKET_DATA
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG8_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG8_VPG_GENERIC_STATUS
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG8_VPG_MEM_PWR
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG8_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG8_VPG_ISRC1_2_DATA
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG8_VPG_MPEG_INFO0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG8_VPG_MPEG_INFO1
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
+//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+//APG3_APG_CONTROL
+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG3_APG_CONTROL2
+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG3_APG_PACKET_CONTROL
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG3_APG_AUDIO_CRC_CONTROL
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG3_APG_AUDIO_CRC_CONTROL2
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG3_APG_AUDIO_CRC_RESULT
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG3_APG_STATUS
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG3_APG_STATUS2
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG3_APG_MEM_PWR
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG3_APG_SPARE
+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+//DME9_DME_CONTROL
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME9_DME_MEMORY_CONTROL
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG9_VPG_GENERIC_PACKET_DATA
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG9_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG9_VPG_GENERIC_STATUS
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG9_VPG_MEM_PWR
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG9_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG9_VPG_ISRC1_2_DATA
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG9_VPG_MPEG_INFO0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG9_VPG_MPEG_INFO1
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
+//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
+//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC0_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
+//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC1_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchvm_hvm_dispdec
+//DCHVM_CTRL0
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT                                                                   0x0
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK                                                                     0x00000001L
+//DCHVM_CTRL1
+#define DCHVM_CTRL1__DUMMY1__SHIFT                                                                            0x0
+#define DCHVM_CTRL1__DUMMY1_MASK                                                                              0xFFFFFFFFL
+//DCHVM_CLK_CTRL
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT                                                         0x0
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT                                                         0x1
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT                                                          0x4
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT                                                          0x5
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT                                                          0x8
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT                                                         0xa
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK                                                           0x00000001L
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK                                                           0x00000002L
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK                                                            0x00000010L
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK                                                            0x00000020L
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK                                                            0x00000300L
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK                                                           0x00000C00L
+//DCHVM_MEM_CTRL
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT                                                       0x0
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT                                                         0x2
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT                                                      0x4
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK                                                         0x00000001L
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK                                                           0x0000000CL
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK                                                        0x00000030L
+//DCHVM_RIOMMU_CTRL0
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT                                                        0x0
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT                                                         0x1
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK                                                          0x00000001L
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK                                                           0x00000002L
+//DCHVM_RIOMMU_STAT0
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT                                                              0x0
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT                                                       0x1
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK                                                                0x00000001L
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK                                                         0x00000002L
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT                                                                              0x0
+#define CRT0C__DISP_START_MASK                                                                                0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT                                                                              0x0
+#define CRT0D__DISP_START_MASK                                                                                0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
+#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
+#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
+
+
+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h
new file mode 100644
index 000000000000..6d6db95a391f
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef _dpcs_3_0_3_OFFSET_HEADER
+#define _dpcs_3_0_3_OFFSET_HEADER
+
+
+
+// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
+// base address: 0x0
+#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
+#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
+#define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
+#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
+#define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
+#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
+#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
+#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
+// base address: 0x0
+#define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
+#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
+#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
+#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
+#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
+#define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
+#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
+#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
+#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
+#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
+#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
+#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
+#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
+#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+
+
+// addressBlock: dpcssys_dpcssys_cr0_dispdec
+// base address: 0x0
+#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
+#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
+#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
+// base address: 0x360
+#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
+#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
+#define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
+#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
+#define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
+#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
+#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
+#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
+// base address: 0x360
+#define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
+#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
+#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
+#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
+#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
+#define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
+#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
+#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
+#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
+#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
+#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
+#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
+#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
+#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+
+
+// addressBlock: dpcssys_dpcssys_cr1_dispdec
+// base address: 0x360
+#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
+#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
+#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_sh_mask.h
new file mode 100644
index 000000000000..55743d06f728
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_sh_mask.h
@@ -0,0 +1,1192 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright (C) 2021 Advanced Micro Devices, Inc.
+ *
+ * Authors: AMD
+ */
+
+#ifndef _dpcs_3_0_3_SH_MASK_HEADER
+#define _dpcs_3_0_3_SH_MASK_HEADER
+
+
+// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
+//DPCSTX0_DPCSTX_TX_CLOCK_CNTL
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT                                       0x3
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK                                         0x00000008L
+//DPCSTX0_DPCSTX_TX_CNTL
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT__SHIFT                                               0xe
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT__SHIFT                                       0xf
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT__SHIFT                                       0x12
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT_MASK                                                 0x00004000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT_MASK                                         0x00008000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT_MASK                                         0x00040000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//DPCSTX0_DPCSTX_CBUS_CNTL
+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
+//DPCSTX0_DPCSTX_INTERRUPT_CNTL
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
+//DPCSTX0_DPCSTX_PLL_UPDATE_ADDR
+#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
+#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
+//DPCSTX0_DPCSTX_PLL_UPDATE_DATA
+#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
+#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
+//RDPCSTX0_RDPCSTX_CNTL
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL__SHIFT                                                  0x12
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL_MASK                                                    0x00040000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX0_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA
+#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
+//RDPCSTX0_RDPCS_TX_CR_ADDR
+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX0_RDPCS_TX_CR_DATA
+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX0_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX0_RDPCSTX_SCRATCH
+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX0_RDPCSTX_SPARE
+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX0_RDPCSTX_CNTL2
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX0_RDPCSTX_PHY_CNTL0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x0001C000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX0_RDPCSTX_PHY_CNTL2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX0_RDPCSTX_PHY_CNTL3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX0_RDPCSTX_PHY_CNTL9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX0_RDPCSTX_PHY_CNTL11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX0_RDPCSTX_PHY_CNTL13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE1
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE2
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE3
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+
+
+// addressBlock: dpcssys_dpcssys_cr0_dispdec
+//DPCSSYS_CR0_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR0_DPCSSYS_CR_DATA
+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
+//DPCSTX1_DPCSTX_TX_CLOCK_CNTL
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT                                       0x3
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK                                         0x00000008L
+//DPCSTX1_DPCSTX_TX_CNTL
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT__SHIFT                                               0xe
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT__SHIFT                                       0xf
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT__SHIFT                                       0x12
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT_MASK                                                 0x00004000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_10_BIT_MASK                                         0x00008000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_18_BIT_MASK                                         0x00040000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//DPCSTX1_DPCSTX_CBUS_CNTL
+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
+//DPCSTX1_DPCSTX_INTERRUPT_CNTL
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
+//DPCSTX1_DPCSTX_PLL_UPDATE_ADDR
+#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
+#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
+//DPCSTX1_DPCSTX_PLL_UPDATE_DATA
+#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
+#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
+//RDPCSTX1_RDPCSTX_CNTL
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL__SHIFT                                                  0x12
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_DATA_MODE_SEL_MASK                                                    0x00040000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX1_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA
+#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
+//RDPCSTX1_RDPCS_TX_CR_ADDR
+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX1_RDPCS_TX_CR_DATA
+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX1_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX1_RDPCSTX_SCRATCH
+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX1_RDPCSTX_SPARE
+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX1_RDPCSTX_CNTL2
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX1_RDPCSTX_PHY_CNTL0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x0001C000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX1_RDPCSTX_PHY_CNTL2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX1_RDPCSTX_PHY_CNTL3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX1_RDPCSTX_PHY_CNTL9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX1_RDPCSTX_PHY_CNTL11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX1_RDPCSTX_PHY_CNTL13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE1
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE2
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE3
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
index bb2c9c7a18df..bd37aa6b6560 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
@@ -33,6 +33,9 @@
 #define mmDF_CS_UMC_AON0_DramBaseAddress0								0x0044
 #define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX							0
 
+#define mmDF_GCM_AON0_DramMegaBaseAddress0								0x0064
+#define mmDF_GCM_AON0_DramMegaBaseAddress0_BASE_IDX							0
+
 #define smnPerfMonCtlLo0					0x01d440UL
 #define smnPerfMonCtlHi0					0x01d444UL
 #define smnPerfMonCtlLo1					0x01d450UL
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
index 7afa87c7ff54..f804e13b002e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
@@ -50,6 +50,7 @@
 #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK						0x00000001L
 #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK						0x00000002L
 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK						0x0000003CL
+#define ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK					0x0000007CL
 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK						0x00000E00L
 #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK						0xFFFFF000L
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
new file mode 100644
index 000000000000..92caf8441d1e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
@@ -0,0 +1,11936 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dpcs_4_2_0_OFFSET_HEADER
+#define _dpcs_4_2_0_OFFSET_HEADER
+
+
+
+// addressBlock: dpcssys_dpcssys_cr0_dispdec
+// base address: 0x0
+#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
+#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
+#define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr1_dispdec
+// base address: 0x360
+#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
+#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
+#define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr2_dispdec
+// base address: 0x6c0
+#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
+#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
+#define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr3_dispdec
+// base address: 0xa20
+#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
+#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
+#define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr4_dispdec
+// base address: 0xd80
+#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
+#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
+#define regDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19
+#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a
+#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21
+#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec
+// base address: 0x1b0
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85
+#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86
+#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d
+#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
+// base address: 0x0
+#define regRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
+#define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
+#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
+#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2933
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
+#define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
+#define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
+#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
+#define regRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
+#define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
+#define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
+#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
+#define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL15                                                                  0x2958
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL16                                                                  0x2959
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL17                                                                  0x295a
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCS_CNTL3                                                                         0x295c
+#define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x295d
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x295e
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
+// base address: 0x360
+#define regRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
+#define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
+#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
+#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2a0b
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
+#define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
+#define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
+#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
+#define regRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
+#define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
+#define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
+#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
+#define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL15                                                                  0x2a30
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL16                                                                  0x2a31
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL17                                                                  0x2a32
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCS_CNTL3                                                                         0x2a34
+#define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2a35
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2a36
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
+// base address: 0x6c0
+#define regRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
+#define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
+#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
+#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2ae3
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
+#define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
+#define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
+#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
+#define regRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
+#define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
+#define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
+#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
+#define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL15                                                                  0x2b08
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL16                                                                  0x2b09
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL17                                                                  0x2b0a
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCS_CNTL3                                                                         0x2b0c
+#define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2b0d
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2b0e
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
+// base address: 0xa20
+#define regRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
+#define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
+#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
+#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2bbb
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
+#define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
+#define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
+#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
+#define regRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
+#define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
+#define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
+#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
+#define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL15                                                                  0x2be0
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL16                                                                  0x2be1
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL17                                                                  0x2be2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCS_CNTL3                                                                         0x2be4
+#define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2be5
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2be6
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
+// base address: 0xd80
+#define regRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
+#define regRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
+#define regRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
+#define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2c93
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
+#define regRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
+#define regRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
+#define regRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
+#define regRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
+#define regRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
+#define regRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
+#define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
+#define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL15                                                                  0x2cb8
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL16                                                                  0x2cb9
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL17                                                                  0x2cba
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCS_CNTL3                                                                         0x2cbc
+#define regRDPCSTX4_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2cbd
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2cbe
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_LINK_CNTL                                                                            0x286d
+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_LINK_CNTL                                                                            0x286f
+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_LINK_CNTL                                                                            0x2871
+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_LINK_CNTL                                                                            0x2873
+#define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_LINK_CNTL                                                                            0x2875
+#define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dpcssys_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902
+#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_cr0_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR0_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR0_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR0_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR0_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR0_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR0_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR0_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR0_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR0_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr1_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR1_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR1_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR1_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR1_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR1_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR1_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR1_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR1_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR1_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR1_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR1_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR1_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr2_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR2_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR2_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR2_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR2_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR2_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR2_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR2_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR2_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR2_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR2_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR2_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR2_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr3_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR3_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR3_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR3_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR3_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR3_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR3_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR3_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR3_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR3_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR3_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR3_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR3_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr4_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR4_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR4_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR4_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR4_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR4_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR4_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR4_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR4_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR4_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR4_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR4_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR4_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h
new file mode 100644
index 000000000000..068f3b16a56b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h
@@ -0,0 +1,103385 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dpcs_4_2_0_SH_MASK_HEADER
+#define _dpcs_4_2_0_SH_MASK_HEADER
+
+
+// addressBlock: dpcssys_dpcssys_cr0_dispdec
+//DPCSSYS_CR0_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR0_DPCSSYS_CR_DATA
+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr1_dispdec
+//DPCSSYS_CR1_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR1_DPCSSYS_CR_DATA
+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr2_dispdec
+//DPCSSYS_CR2_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR2_DPCSSYS_CR_DATA
+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr3_dispdec
+//DPCSSYS_CR3_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR3_DPCSSYS_CR_DATA
+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr4_dispdec
+//DPCSSYS_CR4_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR4_DPCSSYS_CR_DATA
+#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec
+//PWRSEQ0_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ0_PANEL_PWRSEQ_CNTL
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ0_PANEL_PWRSEQ_STATE
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ0_BL_PWM_CNTL
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ0_BL_PWM_CNTL2
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ0_BL_PWM_PERIOD_CNTL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ0_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ0_PWRSEQ_SPARE
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec
+//PWRSEQ1_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ1_PANEL_PWRSEQ_CNTL
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ1_PANEL_PWRSEQ_STATE
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ1_BL_PWM_CNTL
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ1_BL_PWM_CNTL2
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ1_BL_PWM_PERIOD_CNTL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ1_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ1_PWRSEQ_SPARE
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
+//RDPCSTX0_RDPCSTX_CNTL
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX0_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX0_RDPCS_TX_CR_ADDR
+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX0_RDPCS_TX_CR_DATA
+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX0_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX0_RDPCSTX_SCRATCH
+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX0_RDPCSTX_SPARE
+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX0_RDPCSTX_CNTL2
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX0_RDPCSTX_PHY_CNTL0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX0_RDPCSTX_PHY_CNTL2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX0_RDPCSTX_PHY_CNTL3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX0_RDPCSTX_PHY_CNTL9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX0_RDPCSTX_PHY_CNTL11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX0_RDPCSTX_PHY_CNTL13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE1
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE2
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE3
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX0_RDPCSTX_PHY_CNTL15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX0_RDPCS_CNTL3
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
+//RDPCSTX1_RDPCSTX_CNTL
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX1_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX1_RDPCS_TX_CR_ADDR
+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX1_RDPCS_TX_CR_DATA
+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX1_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX1_RDPCSTX_SCRATCH
+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX1_RDPCSTX_SPARE
+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX1_RDPCSTX_CNTL2
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX1_RDPCSTX_PHY_CNTL0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX1_RDPCSTX_PHY_CNTL2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX1_RDPCSTX_PHY_CNTL3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX1_RDPCSTX_PHY_CNTL9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX1_RDPCSTX_PHY_CNTL11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX1_RDPCSTX_PHY_CNTL13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE1
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE2
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE3
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX1_RDPCSTX_PHY_CNTL15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX1_RDPCS_CNTL3
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
+//RDPCSTX2_RDPCSTX_CNTL
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX2_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX2_RDPCS_TX_CR_ADDR
+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX2_RDPCS_TX_CR_DATA
+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX2_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX2_RDPCSTX_SCRATCH
+#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX2_RDPCSTX_SPARE
+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX2_RDPCSTX_CNTL2
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX2_RDPCSTX_PHY_CNTL0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX2_RDPCSTX_PHY_CNTL2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX2_RDPCSTX_PHY_CNTL3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX2_RDPCSTX_PHY_CNTL9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX2_RDPCSTX_PHY_CNTL11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX2_RDPCSTX_PHY_CNTL13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE1
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE2
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE3
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX2_RDPCSTX_PHY_CNTL15
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL16
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL17
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX2_RDPCS_CNTL3
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
+//RDPCSTX3_RDPCSTX_CNTL
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX3_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX3_RDPCS_TX_CR_ADDR
+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX3_RDPCS_TX_CR_DATA
+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX3_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX3_RDPCSTX_SCRATCH
+#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX3_RDPCSTX_SPARE
+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX3_RDPCSTX_CNTL2
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX3_RDPCSTX_PHY_CNTL0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX3_RDPCSTX_PHY_CNTL2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX3_RDPCSTX_PHY_CNTL3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX3_RDPCSTX_PHY_CNTL9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX3_RDPCSTX_PHY_CNTL11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX3_RDPCSTX_PHY_CNTL13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE1
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE2
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE3
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX3_RDPCSTX_PHY_CNTL15
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL16
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL17
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX3_RDPCS_CNTL3
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
+//RDPCSTX4_RDPCSTX_CNTL
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX4_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX4_RDPCS_TX_CR_ADDR
+#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX4_RDPCS_TX_CR_DATA
+#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX4_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX4_RDPCSTX_SCRATCH
+#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX4_RDPCSTX_SPARE
+#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX4_RDPCSTX_CNTL2
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX4_RDPCSTX_PHY_CNTL0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX4_RDPCSTX_PHY_CNTL2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX4_RDPCSTX_PHY_CNTL3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX4_RDPCSTX_PHY_CNTL9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX4_RDPCSTX_PHY_CNTL11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX4_RDPCSTX_PHY_CNTL13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE1
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE2
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE3
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX4_RDPCSTX_PHY_CNTL15
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL16
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL17
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX4_RDPCS_CNTL3
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYE_LINK_CNTL
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//INTERCEPT_STATE
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE__SHIFT                                                 0x4
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE__SHIFT                                                 0x5
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE__SHIFT                                                 0x6
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE__SHIFT                                                 0x7
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE__SHIFT                                                 0x8
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE__SHIFT                                                 0x9
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE_MASK                                                   0x00000010L
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE_MASK                                                   0x00000020L
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE_MASK                                                   0x00000040L
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE_MASK                                                   0x00000080L
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE_MASK                                                   0x00000100L
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE_MASK                                                   0x00000200L
+//DCIO_BL_PWM_FRAME_START_DISP_SEL
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L
+
+
+// addressBlock: dpcssys_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+//DC_GPIO_PWRSEQ1_EN
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_cr0_rdpcstxcrind
+//DPCSSYS_CR0_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_BG1
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR0_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR0_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_BG2
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR0_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR0_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR0_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR0_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_BG3
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_BG1
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR0_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_BG2
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR0_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR0_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR0_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_BG3
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr1_rdpcstxcrind
+//DPCSSYS_CR1_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_BG1
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR1_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR1_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_BG2
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR1_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR1_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR1_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR1_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_BG3
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_BG1
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR1_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_BG2
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR1_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR1_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR1_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_BG3
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr2_rdpcstxcrind
+//DPCSSYS_CR2_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_BG1
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR2_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR2_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_BG2
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR2_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR2_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR2_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR2_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_BG3
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_BG1
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR2_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_BG2
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR2_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR2_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR2_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_BG3
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr3_rdpcstxcrind
+//DPCSSYS_CR3_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_BG1
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR3_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR3_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_BG2
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR3_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR3_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR3_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR3_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_BG3
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_BG1
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR3_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_BG2
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR3_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR3_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR3_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_BG3
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr4_rdpcstxcrind
+//DPCSSYS_CR4_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_BG1
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR4_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR4_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_BG2
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR4_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR4_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR4_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR4_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_BG3
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_BG1
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR4_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_BG2
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR4_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR4_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR4_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_BG3
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h
new file mode 100644
index 000000000000..dfacc6b5d89d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _mp_13_0_1_OFFSET_HEADER
+#define _mp_13_0_1_OFFSET_HEADER
+
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+// base address: 0x0
+#define regMP0_SMN_C2PMSG_32                                                                            0x0060
+#define regMP0_SMN_C2PMSG_32_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_33                                                                            0x0061
+#define regMP0_SMN_C2PMSG_33_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_34                                                                            0x0062
+#define regMP0_SMN_C2PMSG_34_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_35                                                                            0x0063
+#define regMP0_SMN_C2PMSG_35_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_36                                                                            0x0064
+#define regMP0_SMN_C2PMSG_36_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_37                                                                            0x0065
+#define regMP0_SMN_C2PMSG_37_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_38                                                                            0x0066
+#define regMP0_SMN_C2PMSG_38_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_39                                                                            0x0067
+#define regMP0_SMN_C2PMSG_39_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_40                                                                            0x0068
+#define regMP0_SMN_C2PMSG_40_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_41                                                                            0x0069
+#define regMP0_SMN_C2PMSG_41_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_42                                                                            0x006a
+#define regMP0_SMN_C2PMSG_42_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_43                                                                            0x006b
+#define regMP0_SMN_C2PMSG_43_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_44                                                                            0x006c
+#define regMP0_SMN_C2PMSG_44_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_45                                                                            0x006d
+#define regMP0_SMN_C2PMSG_45_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_46                                                                            0x006e
+#define regMP0_SMN_C2PMSG_46_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_47                                                                            0x006f
+#define regMP0_SMN_C2PMSG_47_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_48                                                                            0x0070
+#define regMP0_SMN_C2PMSG_48_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_49                                                                            0x0071
+#define regMP0_SMN_C2PMSG_49_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_50                                                                            0x0072
+#define regMP0_SMN_C2PMSG_50_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_51                                                                            0x0073
+#define regMP0_SMN_C2PMSG_51_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_52                                                                            0x0074
+#define regMP0_SMN_C2PMSG_52_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_53                                                                            0x0075
+#define regMP0_SMN_C2PMSG_53_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_54                                                                            0x0076
+#define regMP0_SMN_C2PMSG_54_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_55                                                                            0x0077
+#define regMP0_SMN_C2PMSG_55_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_56                                                                            0x0078
+#define regMP0_SMN_C2PMSG_56_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_57                                                                            0x0079
+#define regMP0_SMN_C2PMSG_57_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_58                                                                            0x007a
+#define regMP0_SMN_C2PMSG_58_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_59                                                                            0x007b
+#define regMP0_SMN_C2PMSG_59_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_60                                                                            0x007c
+#define regMP0_SMN_C2PMSG_60_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_61                                                                            0x007d
+#define regMP0_SMN_C2PMSG_61_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_62                                                                            0x007e
+#define regMP0_SMN_C2PMSG_62_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_63                                                                            0x007f
+#define regMP0_SMN_C2PMSG_63_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_64                                                                            0x0080
+#define regMP0_SMN_C2PMSG_64_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_65                                                                            0x0081
+#define regMP0_SMN_C2PMSG_65_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_66                                                                            0x0082
+#define regMP0_SMN_C2PMSG_66_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_67                                                                            0x0083
+#define regMP0_SMN_C2PMSG_67_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_68                                                                            0x0084
+#define regMP0_SMN_C2PMSG_68_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_69                                                                            0x0085
+#define regMP0_SMN_C2PMSG_69_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_70                                                                            0x0086
+#define regMP0_SMN_C2PMSG_70_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_71                                                                            0x0087
+#define regMP0_SMN_C2PMSG_71_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_72                                                                            0x0088
+#define regMP0_SMN_C2PMSG_72_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_73                                                                            0x0089
+#define regMP0_SMN_C2PMSG_73_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_74                                                                            0x008a
+#define regMP0_SMN_C2PMSG_74_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_75                                                                            0x008b
+#define regMP0_SMN_C2PMSG_75_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_76                                                                            0x008c
+#define regMP0_SMN_C2PMSG_76_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_77                                                                            0x008d
+#define regMP0_SMN_C2PMSG_77_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_78                                                                            0x008e
+#define regMP0_SMN_C2PMSG_78_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_79                                                                            0x008f
+#define regMP0_SMN_C2PMSG_79_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_80                                                                            0x0090
+#define regMP0_SMN_C2PMSG_80_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_81                                                                            0x0091
+#define regMP0_SMN_C2PMSG_81_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_82                                                                            0x0092
+#define regMP0_SMN_C2PMSG_82_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_83                                                                            0x0093
+#define regMP0_SMN_C2PMSG_83_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_84                                                                            0x0094
+#define regMP0_SMN_C2PMSG_84_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_85                                                                            0x0095
+#define regMP0_SMN_C2PMSG_85_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_86                                                                            0x0096
+#define regMP0_SMN_C2PMSG_86_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_87                                                                            0x0097
+#define regMP0_SMN_C2PMSG_87_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_88                                                                            0x0098
+#define regMP0_SMN_C2PMSG_88_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_89                                                                            0x0099
+#define regMP0_SMN_C2PMSG_89_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_90                                                                            0x009a
+#define regMP0_SMN_C2PMSG_90_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_91                                                                            0x009b
+#define regMP0_SMN_C2PMSG_91_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_92                                                                            0x009c
+#define regMP0_SMN_C2PMSG_92_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_93                                                                            0x009d
+#define regMP0_SMN_C2PMSG_93_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_94                                                                            0x009e
+#define regMP0_SMN_C2PMSG_94_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_95                                                                            0x009f
+#define regMP0_SMN_C2PMSG_95_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_96                                                                            0x00a0
+#define regMP0_SMN_C2PMSG_96_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_97                                                                            0x00a1
+#define regMP0_SMN_C2PMSG_97_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_98                                                                            0x00a2
+#define regMP0_SMN_C2PMSG_98_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_99                                                                            0x00a3
+#define regMP0_SMN_C2PMSG_99_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_100                                                                           0x00a4
+#define regMP0_SMN_C2PMSG_100_BASE_IDX                                                                  0
+#define regMP0_SMN_C2PMSG_101                                                                           0x00a5
+#define regMP0_SMN_C2PMSG_101_BASE_IDX                                                                  0
+#define regMP0_SMN_C2PMSG_102                                                                           0x00a6
+#define regMP0_SMN_C2PMSG_102_BASE_IDX                                                                  0
+#define regMP0_SMN_C2PMSG_103                                                                           0x00a7
+#define regMP0_SMN_C2PMSG_103_BASE_IDX                                                                  0
+#define regMP0_SMN_IH_CREDIT                                                                            0x00c1
+#define regMP0_SMN_IH_CREDIT_BASE_IDX                                                                   0
+#define regMP0_SMN_IH_SW_INT                                                                            0x00c2
+#define regMP0_SMN_IH_SW_INT_BASE_IDX                                                                   0
+#define regMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
+#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+// base address: 0x0
+#define regMP1_SMN_C2PMSG_32                                                                            0x0260
+#define regMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_33                                                                            0x0261
+#define regMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_34                                                                            0x0262
+#define regMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_35                                                                            0x0263
+#define regMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_36                                                                            0x0264
+#define regMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_37                                                                            0x0265
+#define regMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_38                                                                            0x0266
+#define regMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_39                                                                            0x0267
+#define regMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_40                                                                            0x0268
+#define regMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_41                                                                            0x0269
+#define regMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_42                                                                            0x026a
+#define regMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_43                                                                            0x026b
+#define regMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_44                                                                            0x026c
+#define regMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_45                                                                            0x026d
+#define regMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_46                                                                            0x026e
+#define regMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_47                                                                            0x026f
+#define regMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_48                                                                            0x0270
+#define regMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_49                                                                            0x0271
+#define regMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_50                                                                            0x0272
+#define regMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_51                                                                            0x0273
+#define regMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_52                                                                            0x0274
+#define regMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_53                                                                            0x0275
+#define regMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_54                                                                            0x0276
+#define regMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_55                                                                            0x0277
+#define regMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_56                                                                            0x0278
+#define regMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_57                                                                            0x0279
+#define regMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_58                                                                            0x027a
+#define regMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_59                                                                            0x027b
+#define regMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_60                                                                            0x027c
+#define regMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_61                                                                            0x027d
+#define regMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_62                                                                            0x027e
+#define regMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_63                                                                            0x027f
+#define regMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_64                                                                            0x0280
+#define regMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_65                                                                            0x0281
+#define regMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_66                                                                            0x0282
+#define regMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_67                                                                            0x0283
+#define regMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_68                                                                            0x0284
+#define regMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_69                                                                            0x0285
+#define regMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_70                                                                            0x0286
+#define regMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_71                                                                            0x0287
+#define regMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_72                                                                            0x0288
+#define regMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_73                                                                            0x0289
+#define regMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_74                                                                            0x028a
+#define regMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_75                                                                            0x028b
+#define regMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_76                                                                            0x028c
+#define regMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_77                                                                            0x028d
+#define regMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_78                                                                            0x028e
+#define regMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_79                                                                            0x028f
+#define regMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_80                                                                            0x0290
+#define regMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_81                                                                            0x0291
+#define regMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_82                                                                            0x0292
+#define regMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_83                                                                            0x0293
+#define regMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_84                                                                            0x0294
+#define regMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_85                                                                            0x0295
+#define regMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_86                                                                            0x0296
+#define regMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_87                                                                            0x0297
+#define regMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_88                                                                            0x0298
+#define regMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_89                                                                            0x0299
+#define regMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_90                                                                            0x029a
+#define regMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_91                                                                            0x029b
+#define regMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_92                                                                            0x029c
+#define regMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_93                                                                            0x029d
+#define regMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_94                                                                            0x029e
+#define regMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_95                                                                            0x029f
+#define regMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_96                                                                            0x02a0
+#define regMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_97                                                                            0x02a1
+#define regMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_98                                                                            0x02a2
+#define regMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_99                                                                            0x02a3
+#define regMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_100                                                                           0x02a4
+#define regMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
+#define regMP1_SMN_C2PMSG_101                                                                           0x02a5
+#define regMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
+#define regMP1_SMN_C2PMSG_102                                                                           0x02a6
+#define regMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
+#define regMP1_SMN_C2PMSG_103                                                                           0x02a7
+#define regMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
+#define regMP1_SMN_IH_CREDIT                                                                            0x02c1
+#define regMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
+#define regMP1_SMN_IH_SW_INT                                                                            0x02c2
+#define regMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
+#define regMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
+#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
+#define regMP1_SMN_FPS_CNT                                                                              0x02c4
+#define regMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
+#define regMP1_SMN_EXT_SCRATCH0                                                                         0x0340
+#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH1                                                                         0x0341
+#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH2                                                                         0x0342
+#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH3                                                                         0x0343
+#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH4                                                                         0x0344
+#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH5                                                                         0x0345
+#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH6                                                                         0x0346
+#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH7                                                                         0x0347
+#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h
new file mode 100644
index 000000000000..2d5e8b58e693
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _mp_13_0_1_SH_MASK_HEADER
+#define _mp_13_0_1_SH_MASK_HEADER
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+//MP0_SMN_C2PMSG_32
+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_33
+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_34
+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_35
+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_36
+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_37
+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_38
+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_39
+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_40
+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_41
+#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_42
+#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_43
+#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_44
+#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_45
+#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_46
+#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_47
+#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_48
+#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_49
+#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_50
+#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_51
+#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_52
+#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_53
+#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_54
+#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_55
+#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_56
+#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_57
+#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_58
+#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_59
+#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_60
+#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_61
+#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_62
+#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_63
+#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_64
+#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_65
+#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_66
+#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_67
+#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_68
+#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_69
+#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_70
+#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_71
+#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_72
+#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_73
+#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_74
+#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_75
+#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_76
+#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_77
+#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_78
+#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_79
+#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_80
+#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_81
+#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_82
+#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_83
+#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_84
+#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_85
+#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_86
+#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_87
+#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_88
+#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_89
+#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_90
+#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_91
+#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_92
+#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_93
+#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_94
+#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_95
+#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_96
+#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_97
+#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_98
+#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_99
+#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_100
+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_101
+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_102
+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_103
+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_IH_CREDIT
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
+#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
+#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
+//MP0_SMN_IH_SW_INT
+#define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
+#define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
+#define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
+#define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
+//MP0_SMN_IH_SW_INT_CTRL
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+//MP1_FIRMWARE_FLAGS
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                         0x0
+#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                                   0x1
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                           0x00000001L
+#define MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                                     0xFFFFFFFEL
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+//MP1_SMN_C2PMSG_32
+#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_33
+#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_34
+#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_35
+#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_36
+#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_37
+#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_38
+#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_39
+#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_40
+#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_41
+#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_42
+#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_43
+#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_44
+#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_45
+#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_46
+#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_47
+#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_48
+#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_49
+#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_50
+#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_51
+#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_52
+#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_53
+#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_54
+#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_55
+#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_56
+#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_57
+#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_58
+#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_59
+#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_60
+#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_61
+#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_62
+#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_63
+#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_64
+#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_65
+#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_66
+#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_67
+#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_68
+#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_69
+#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_70
+#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_71
+#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_72
+#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_73
+#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_74
+#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_75
+#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_76
+#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_77
+#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_78
+#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_79
+#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_80
+#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_81
+#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_82
+#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_83
+#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_84
+#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_85
+#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_86
+#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_87
+#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_88
+#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_89
+#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_90
+#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_91
+#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_92
+#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_93
+#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_94
+#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_95
+#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_96
+#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_97
+#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_98
+#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_99
+#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_100
+#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_101
+#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_102
+#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_103
+#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_IH_CREDIT
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
+#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
+#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
+//MP1_SMN_IH_SW_INT
+#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
+#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
+#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
+#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
+//MP1_SMN_IH_SW_INT_CTRL
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
+//MP1_SMN_FPS_CNT
+#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
+#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH0
+#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH1
+#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH2
+#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH3
+#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH4
+#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH5
+#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH6
+#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH7
+#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index 47eb84598b96..6a505d1b82a5 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -5178,11 +5178,11 @@ typedef struct  _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
 typedef struct  _ATOM_SVID2_VOLTAGE_OBJECT_V3
 {
    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_SVID2
-// 14:7 � PSI0_VID
-// 6 � PSI0_EN
-// 5 � PSI1
-// 4:2 � load line slope trim.
-// 1:0 � offset trim,
+// 14:7 - PSI0_VID
+// 6 - PSI0_EN
+// 5 - PSI1
+// 4:2 - load line slope trim.
+// 1:0 - offset trim,
    USHORT   usLoadLine_PSI;
 // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
    UCHAR    ucSVDGpioId;     //0~31 indicate GPIO0~31
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index f2564ba21c0b..3811e58dd857 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -197,6 +197,9 @@ enum atom_dp_vs_preemph_def{
   DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
 };
 
+#define BIOS_ATOM_PREFIX   "ATOMBIOS"
+#define BIOS_VERSION_PREFIX  "ATOMBIOSBK-AMD"
+#define BIOS_STRING_LENGTH 43
 
 /*
 enum atom_string_def{
@@ -209,12 +212,14 @@ atom_bios_string          = "ATOM"
 #pragma pack(1)                          /* BIOS data must use byte aligment*/
 
 enum atombios_image_offset{
-OFFSET_TO_ATOM_ROM_HEADER_POINTER          =0x00000048,
-OFFSET_TO_ATOM_ROM_IMAGE_SIZE              =0x00000002,
-OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE       =0x94,
-MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE      =20,  /*including the terminator 0x0!*/
-OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS   =0x2f,
-OFFSET_TO_GET_ATOMBIOS_STRING_START        =0x6e,
+  OFFSET_TO_ATOM_ROM_HEADER_POINTER          = 0x00000048,
+  OFFSET_TO_ATOM_ROM_IMAGE_SIZE              = 0x00000002,
+  OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE       = 0x94,
+  MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE      = 20,  /*including the terminator 0x0!*/
+  OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS   = 0x2f,
+  OFFSET_TO_GET_ATOMBIOS_STRING_START        = 0x6e,
+  OFFSET_TO_VBIOS_PART_NUMBER                = 0x80,
+  OFFSET_TO_VBIOS_DATE                       = 0x50,
 };
 
 /****************************************************************************   
@@ -501,6 +506,7 @@ enum atombios_firmware_capability
 	ATOM_FIRMWARE_CAP_SRAM_ECC      = 0x00000200,
 	ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x00000400,
 	ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
+	ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
 };
 
 enum atom_cooling_solution_id{
@@ -877,7 +883,8 @@ struct  atom_bracket_layout_record
 };
 
 enum atom_display_device_tag_def{
-  ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002,  //an embedded display is either an LVDS or eDP signal type of display
+  ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
+  ATOM_DISPLAY_LCD2_SUPPORT			       = 0x0020, //second edp device tag 0x0020 for backward compability
   ATOM_DISPLAY_DFP1_SUPPORT            = 0x0008,
   ATOM_DISPLAY_DFP2_SUPPORT            = 0x0080,
   ATOM_DISPLAY_DFP3_SUPPORT            = 0x0200,
@@ -1407,6 +1414,59 @@ struct atom_integrated_system_info_v2_1
 
 };
 
+struct atom_n6_display_phy_tuning_set {
+	uint8_t display_signal_type;
+	uint8_t phy_sel;
+	uint8_t preset_level;
+	uint8_t reserved1;
+	uint32_t reserved2;
+	uint32_t speed_upto;
+	uint8_t tx_vboost_level;
+	uint8_t tx_vreg_v2i;
+	uint8_t tx_vregdrv_byp;
+	uint8_t tx_term_cntl;
+	uint8_t tx_peak_level;
+	uint8_t tx_slew_en;
+	uint8_t tx_eq_pre;
+	uint8_t tx_eq_main;
+	uint8_t tx_eq_post;
+	uint8_t tx_en_inv_pre;
+	uint8_t tx_en_inv_post;
+	uint8_t reserved3;
+	uint32_t reserved4;
+	uint32_t reserved5;
+	uint32_t reserved6;
+};
+
+struct atom_display_phy_tuning_info {
+	struct atom_common_table_header table_header;
+	struct atom_n6_display_phy_tuning_set disp_phy_tuning[1];
+};
+
+struct atom_integrated_system_info_v2_2
+{
+	struct  atom_common_table_header  table_header;
+	uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
+	uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
+	uint32_t  system_config;
+	uint32_t  cpucapinfo;
+	uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
+	uint16_t  gpuclk_ss_type;
+	uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
+	uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
+	uint8_t   umachannelnumber;                 // number of memory channels
+	uint8_t   htc_hyst_limit;
+	uint8_t   htc_tmp_limit;
+	uint8_t   reserved1;
+	uint8_t   reserved2;
+	struct edp_info_table edp1_info;
+	struct edp_info_table edp2_info;
+	uint32_t  reserved3[8];
+	struct atom_external_display_connection_info extdispconninfo;
+
+	uint32_t  reserved4[189];
+};
+
 // system_config
 enum atom_system_vbiosmisc_def{
   INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
diff --git a/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h b/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h
new file mode 100644
index 000000000000..26044cb285d2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h
@@ -0,0 +1,1274 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _beige_goby_ip_offset_HEADER
+#define _beige_goby_ip_offset_HEADER
+
+
+#define MAX_INSTANCE                                        7
+#define MAX_SEGMENT                                         6
+
+
+struct IP_BASE_INSTANCE
+{
+    unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+                                        { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+                                        { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+                                        { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+                                        { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+                                        { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+                                        { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
+                                        { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
+                                        { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ATHUB_BASE__INST0_SEG0                     0x00000C00
+#define ATHUB_BASE__INST0_SEG1                     0x02408C00
+#define ATHUB_BASE__INST0_SEG2                     0
+#define ATHUB_BASE__INST0_SEG3                     0
+#define ATHUB_BASE__INST0_SEG4                     0
+#define ATHUB_BASE__INST0_SEG5                     0
+
+#define ATHUB_BASE__INST1_SEG0                     0
+#define ATHUB_BASE__INST1_SEG1                     0
+#define ATHUB_BASE__INST1_SEG2                     0
+#define ATHUB_BASE__INST1_SEG3                     0
+#define ATHUB_BASE__INST1_SEG4                     0
+#define ATHUB_BASE__INST1_SEG5                     0
+
+#define ATHUB_BASE__INST2_SEG0                     0
+#define ATHUB_BASE__INST2_SEG1                     0
+#define ATHUB_BASE__INST2_SEG2                     0
+#define ATHUB_BASE__INST2_SEG3                     0
+#define ATHUB_BASE__INST2_SEG4                     0
+#define ATHUB_BASE__INST2_SEG5                     0
+
+#define ATHUB_BASE__INST3_SEG0                     0
+#define ATHUB_BASE__INST3_SEG1                     0
+#define ATHUB_BASE__INST3_SEG2                     0
+#define ATHUB_BASE__INST3_SEG3                     0
+#define ATHUB_BASE__INST3_SEG4                     0
+#define ATHUB_BASE__INST3_SEG5                     0
+
+#define ATHUB_BASE__INST4_SEG0                     0
+#define ATHUB_BASE__INST4_SEG1                     0
+#define ATHUB_BASE__INST4_SEG2                     0
+#define ATHUB_BASE__INST4_SEG3                     0
+#define ATHUB_BASE__INST4_SEG4                     0
+#define ATHUB_BASE__INST4_SEG5                     0
+
+#define ATHUB_BASE__INST5_SEG0                     0
+#define ATHUB_BASE__INST5_SEG1                     0
+#define ATHUB_BASE__INST5_SEG2                     0
+#define ATHUB_BASE__INST5_SEG3                     0
+#define ATHUB_BASE__INST5_SEG4                     0
+#define ATHUB_BASE__INST5_SEG5                     0
+
+#define ATHUB_BASE__INST6_SEG0                     0
+#define ATHUB_BASE__INST6_SEG1                     0
+#define ATHUB_BASE__INST6_SEG2                     0
+#define ATHUB_BASE__INST6_SEG3                     0
+#define ATHUB_BASE__INST6_SEG4                     0
+#define ATHUB_BASE__INST6_SEG5                     0
+
+#define CLK_BASE__INST0_SEG0                       0x00016C00
+#define CLK_BASE__INST0_SEG1                       0x02401800
+#define CLK_BASE__INST0_SEG2                       0
+#define CLK_BASE__INST0_SEG3                       0
+#define CLK_BASE__INST0_SEG4                       0
+#define CLK_BASE__INST0_SEG5                       0
+
+#define CLK_BASE__INST1_SEG0                       0x00016E00
+#define CLK_BASE__INST1_SEG1                       0x02401C00
+#define CLK_BASE__INST1_SEG2                       0
+#define CLK_BASE__INST1_SEG3                       0
+#define CLK_BASE__INST1_SEG4                       0
+#define CLK_BASE__INST1_SEG5                       0
+
+#define CLK_BASE__INST2_SEG0                       0x00017000
+#define CLK_BASE__INST2_SEG1                       0x02402000
+#define CLK_BASE__INST2_SEG2                       0
+#define CLK_BASE__INST2_SEG3                       0
+#define CLK_BASE__INST2_SEG4                       0
+#define CLK_BASE__INST2_SEG5                       0
+
+#define CLK_BASE__INST3_SEG0                       0x00017200
+#define CLK_BASE__INST3_SEG1                       0x02402400
+#define CLK_BASE__INST3_SEG2                       0
+#define CLK_BASE__INST3_SEG3                       0
+#define CLK_BASE__INST3_SEG4                       0
+#define CLK_BASE__INST3_SEG5                       0
+
+#define CLK_BASE__INST4_SEG0                       0x0001B000
+#define CLK_BASE__INST4_SEG1                       0x0242D800
+#define CLK_BASE__INST4_SEG2                       0
+#define CLK_BASE__INST4_SEG3                       0
+#define CLK_BASE__INST4_SEG4                       0
+#define CLK_BASE__INST4_SEG5                       0
+
+#define CLK_BASE__INST5_SEG0                       0x0001B200
+#define CLK_BASE__INST5_SEG1                       0x0242DC00
+#define CLK_BASE__INST5_SEG2                       0
+#define CLK_BASE__INST5_SEG3                       0
+#define CLK_BASE__INST5_SEG4                       0
+#define CLK_BASE__INST5_SEG5                       0
+
+#define CLK_BASE__INST6_SEG0                       0x00017E00
+#define CLK_BASE__INST6_SEG1                       0x0240BC00
+#define CLK_BASE__INST6_SEG2                       0
+#define CLK_BASE__INST6_SEG3                       0
+#define CLK_BASE__INST6_SEG4                       0
+#define CLK_BASE__INST6_SEG5                       0
+
+#define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
+#define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
+#define DBGU_IO0_BASE__INST0_SEG2                  0
+#define DBGU_IO0_BASE__INST0_SEG3                  0
+#define DBGU_IO0_BASE__INST0_SEG4                  0
+#define DBGU_IO0_BASE__INST0_SEG5                  0
+
+#define DBGU_IO0_BASE__INST1_SEG0                  0x00000260
+#define DBGU_IO0_BASE__INST1_SEG1                  0x02413C00
+#define DBGU_IO0_BASE__INST1_SEG2                  0
+#define DBGU_IO0_BASE__INST1_SEG3                  0
+#define DBGU_IO0_BASE__INST1_SEG4                  0
+#define DBGU_IO0_BASE__INST1_SEG5                  0
+
+#define DBGU_IO0_BASE__INST2_SEG0                  0
+#define DBGU_IO0_BASE__INST2_SEG1                  0
+#define DBGU_IO0_BASE__INST2_SEG2                  0
+#define DBGU_IO0_BASE__INST2_SEG3                  0
+#define DBGU_IO0_BASE__INST2_SEG4                  0
+#define DBGU_IO0_BASE__INST2_SEG5                  0
+
+#define DBGU_IO0_BASE__INST3_SEG0                  0
+#define DBGU_IO0_BASE__INST3_SEG1                  0
+#define DBGU_IO0_BASE__INST3_SEG2                  0
+#define DBGU_IO0_BASE__INST3_SEG3                  0
+#define DBGU_IO0_BASE__INST3_SEG4                  0
+#define DBGU_IO0_BASE__INST3_SEG5                  0
+
+#define DBGU_IO0_BASE__INST4_SEG0                  0
+#define DBGU_IO0_BASE__INST4_SEG1                  0
+#define DBGU_IO0_BASE__INST4_SEG2                  0
+#define DBGU_IO0_BASE__INST4_SEG3                  0
+#define DBGU_IO0_BASE__INST4_SEG4                  0
+#define DBGU_IO0_BASE__INST4_SEG5                  0
+
+#define DBGU_IO0_BASE__INST5_SEG0                  0
+#define DBGU_IO0_BASE__INST5_SEG1                  0
+#define DBGU_IO0_BASE__INST5_SEG2                  0
+#define DBGU_IO0_BASE__INST5_SEG3                  0
+#define DBGU_IO0_BASE__INST5_SEG4                  0
+#define DBGU_IO0_BASE__INST5_SEG5                  0
+
+#define DBGU_IO0_BASE__INST6_SEG0                  0
+#define DBGU_IO0_BASE__INST6_SEG1                  0
+#define DBGU_IO0_BASE__INST6_SEG2                  0
+#define DBGU_IO0_BASE__INST6_SEG3                  0
+#define DBGU_IO0_BASE__INST6_SEG4                  0
+#define DBGU_IO0_BASE__INST6_SEG5                  0
+
+#define DF_BASE__INST0_SEG0                        0x00007000
+#define DF_BASE__INST0_SEG1                        0x0240B800
+#define DF_BASE__INST0_SEG2                        0
+#define DF_BASE__INST0_SEG3                        0
+#define DF_BASE__INST0_SEG4                        0
+#define DF_BASE__INST0_SEG5                        0
+
+#define DF_BASE__INST1_SEG0                        0
+#define DF_BASE__INST1_SEG1                        0
+#define DF_BASE__INST1_SEG2                        0
+#define DF_BASE__INST1_SEG3                        0
+#define DF_BASE__INST1_SEG4                        0
+#define DF_BASE__INST1_SEG5                        0
+
+#define DF_BASE__INST2_SEG0                        0
+#define DF_BASE__INST2_SEG1                        0
+#define DF_BASE__INST2_SEG2                        0
+#define DF_BASE__INST2_SEG3                        0
+#define DF_BASE__INST2_SEG4                        0
+#define DF_BASE__INST2_SEG5                        0
+
+#define DF_BASE__INST3_SEG0                        0
+#define DF_BASE__INST3_SEG1                        0
+#define DF_BASE__INST3_SEG2                        0
+#define DF_BASE__INST3_SEG3                        0
+#define DF_BASE__INST3_SEG4                        0
+#define DF_BASE__INST3_SEG5                        0
+
+#define DF_BASE__INST4_SEG0                        0
+#define DF_BASE__INST4_SEG1                        0
+#define DF_BASE__INST4_SEG2                        0
+#define DF_BASE__INST4_SEG3                        0
+#define DF_BASE__INST4_SEG4                        0
+#define DF_BASE__INST4_SEG5                        0
+
+#define DF_BASE__INST5_SEG0                        0
+#define DF_BASE__INST5_SEG1                        0
+#define DF_BASE__INST5_SEG2                        0
+#define DF_BASE__INST5_SEG3                        0
+#define DF_BASE__INST5_SEG4                        0
+#define DF_BASE__INST5_SEG5                        0
+
+#define DF_BASE__INST6_SEG0                        0
+#define DF_BASE__INST6_SEG1                        0
+#define DF_BASE__INST6_SEG2                        0
+#define DF_BASE__INST6_SEG3                        0
+#define DF_BASE__INST6_SEG4                        0
+#define DF_BASE__INST6_SEG5                        0
+
+#define DIO_BASE__INST0_SEG0                       0x02404000
+#define DIO_BASE__INST0_SEG1                       0
+#define DIO_BASE__INST0_SEG2                       0
+#define DIO_BASE__INST0_SEG3                       0
+#define DIO_BASE__INST0_SEG4                       0
+#define DIO_BASE__INST0_SEG5                       0
+
+#define DIO_BASE__INST1_SEG0                       0
+#define DIO_BASE__INST1_SEG1                       0
+#define DIO_BASE__INST1_SEG2                       0
+#define DIO_BASE__INST1_SEG3                       0
+#define DIO_BASE__INST1_SEG4                       0
+#define DIO_BASE__INST1_SEG5                       0
+
+#define DIO_BASE__INST2_SEG0                       0
+#define DIO_BASE__INST2_SEG1                       0
+#define DIO_BASE__INST2_SEG2                       0
+#define DIO_BASE__INST2_SEG3                       0
+#define DIO_BASE__INST2_SEG4                       0
+#define DIO_BASE__INST2_SEG5                       0
+
+#define DIO_BASE__INST3_SEG0                       0
+#define DIO_BASE__INST3_SEG1                       0
+#define DIO_BASE__INST3_SEG2                       0
+#define DIO_BASE__INST3_SEG3                       0
+#define DIO_BASE__INST3_SEG4                       0
+#define DIO_BASE__INST3_SEG5                       0
+
+#define DIO_BASE__INST4_SEG0                       0
+#define DIO_BASE__INST4_SEG1                       0
+#define DIO_BASE__INST4_SEG2                       0
+#define DIO_BASE__INST4_SEG3                       0
+#define DIO_BASE__INST4_SEG4                       0
+#define DIO_BASE__INST4_SEG5                       0
+
+#define DIO_BASE__INST5_SEG0                       0
+#define DIO_BASE__INST5_SEG1                       0
+#define DIO_BASE__INST5_SEG2                       0
+#define DIO_BASE__INST5_SEG3                       0
+#define DIO_BASE__INST5_SEG4                       0
+#define DIO_BASE__INST5_SEG5                       0
+
+#define DIO_BASE__INST6_SEG0                       0
+#define DIO_BASE__INST6_SEG1                       0
+#define DIO_BASE__INST6_SEG2                       0
+#define DIO_BASE__INST6_SEG3                       0
+#define DIO_BASE__INST6_SEG4                       0
+#define DIO_BASE__INST6_SEG5                       0
+
+#define DCN_BASE__INST0_SEG0                       0x00000012
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define DCN_BASE__INST0_SEG4                       0x02403C00
+#define DCN_BASE__INST0_SEG5                       0
+
+#define DCN_BASE__INST1_SEG0                       0
+#define DCN_BASE__INST1_SEG1                       0
+#define DCN_BASE__INST1_SEG2                       0
+#define DCN_BASE__INST1_SEG3                       0
+#define DCN_BASE__INST1_SEG4                       0
+#define DCN_BASE__INST1_SEG5                       0
+
+#define DCN_BASE__INST2_SEG0                       0
+#define DCN_BASE__INST2_SEG1                       0
+#define DCN_BASE__INST2_SEG2                       0
+#define DCN_BASE__INST2_SEG3                       0
+#define DCN_BASE__INST2_SEG4                       0
+#define DCN_BASE__INST2_SEG5                       0
+
+#define DCN_BASE__INST3_SEG0                       0
+#define DCN_BASE__INST3_SEG1                       0
+#define DCN_BASE__INST3_SEG2                       0
+#define DCN_BASE__INST3_SEG3                       0
+#define DCN_BASE__INST3_SEG4                       0
+#define DCN_BASE__INST3_SEG5                       0
+
+#define DCN_BASE__INST4_SEG0                       0
+#define DCN_BASE__INST4_SEG1                       0
+#define DCN_BASE__INST4_SEG2                       0
+#define DCN_BASE__INST4_SEG3                       0
+#define DCN_BASE__INST4_SEG4                       0
+#define DCN_BASE__INST4_SEG5                       0
+
+#define DCN_BASE__INST5_SEG0                       0
+#define DCN_BASE__INST5_SEG1                       0
+#define DCN_BASE__INST5_SEG2                       0
+#define DCN_BASE__INST5_SEG3                       0
+#define DCN_BASE__INST5_SEG4                       0
+#define DCN_BASE__INST5_SEG5                       0
+
+#define DCN_BASE__INST6_SEG0                       0
+#define DCN_BASE__INST6_SEG1                       0
+#define DCN_BASE__INST6_SEG2                       0
+#define DCN_BASE__INST6_SEG3                       0
+#define DCN_BASE__INST6_SEG4                       0
+#define DCN_BASE__INST6_SEG5                       0
+
+#define DPCS_BASE__INST0_SEG0                      0x00000012
+#define DPCS_BASE__INST0_SEG1                      0x000000C0
+#define DPCS_BASE__INST0_SEG2                      0x000034C0
+#define DPCS_BASE__INST0_SEG3                      0x00009000
+#define DPCS_BASE__INST0_SEG4                      0x02403C00
+#define DPCS_BASE__INST0_SEG5                      0
+
+#define DPCS_BASE__INST1_SEG0                      0
+#define DPCS_BASE__INST1_SEG1                      0
+#define DPCS_BASE__INST1_SEG2                      0
+#define DPCS_BASE__INST1_SEG3                      0
+#define DPCS_BASE__INST1_SEG4                      0
+#define DPCS_BASE__INST1_SEG5                      0
+
+#define DPCS_BASE__INST2_SEG0                      0
+#define DPCS_BASE__INST2_SEG1                      0
+#define DPCS_BASE__INST2_SEG2                      0
+#define DPCS_BASE__INST2_SEG3                      0
+#define DPCS_BASE__INST2_SEG4                      0
+#define DPCS_BASE__INST2_SEG5                      0
+
+#define DPCS_BASE__INST3_SEG0                      0
+#define DPCS_BASE__INST3_SEG1                      0
+#define DPCS_BASE__INST3_SEG2                      0
+#define DPCS_BASE__INST3_SEG3                      0
+#define DPCS_BASE__INST3_SEG4                      0
+#define DPCS_BASE__INST3_SEG5                      0
+
+#define DPCS_BASE__INST4_SEG0                      0
+#define DPCS_BASE__INST4_SEG1                      0
+#define DPCS_BASE__INST4_SEG2                      0
+#define DPCS_BASE__INST4_SEG3                      0
+#define DPCS_BASE__INST4_SEG4                      0
+#define DPCS_BASE__INST4_SEG5                      0
+
+#define DPCS_BASE__INST5_SEG0                      0
+#define DPCS_BASE__INST5_SEG1                      0
+#define DPCS_BASE__INST5_SEG2                      0
+#define DPCS_BASE__INST5_SEG3                      0
+#define DPCS_BASE__INST5_SEG4                      0
+#define DPCS_BASE__INST5_SEG5                      0
+
+#define DPCS_BASE__INST6_SEG0                      0
+#define DPCS_BASE__INST6_SEG1                      0
+#define DPCS_BASE__INST6_SEG2                      0
+#define DPCS_BASE__INST6_SEG3                      0
+#define DPCS_BASE__INST6_SEG4                      0
+#define DPCS_BASE__INST6_SEG5                      0
+
+#define FUSE_BASE__INST0_SEG0                      0x00017400
+#define FUSE_BASE__INST0_SEG1                      0x02401400
+#define FUSE_BASE__INST0_SEG2                      0
+#define FUSE_BASE__INST0_SEG3                      0
+#define FUSE_BASE__INST0_SEG4                      0
+#define FUSE_BASE__INST0_SEG5                      0
+
+#define FUSE_BASE__INST1_SEG0                      0
+#define FUSE_BASE__INST1_SEG1                      0
+#define FUSE_BASE__INST1_SEG2                      0
+#define FUSE_BASE__INST1_SEG3                      0
+#define FUSE_BASE__INST1_SEG4                      0
+#define FUSE_BASE__INST1_SEG5                      0
+
+#define FUSE_BASE__INST2_SEG0                      0
+#define FUSE_BASE__INST2_SEG1                      0
+#define FUSE_BASE__INST2_SEG2                      0
+#define FUSE_BASE__INST2_SEG3                      0
+#define FUSE_BASE__INST2_SEG4                      0
+#define FUSE_BASE__INST2_SEG5                      0
+
+#define FUSE_BASE__INST3_SEG0                      0
+#define FUSE_BASE__INST3_SEG1                      0
+#define FUSE_BASE__INST3_SEG2                      0
+#define FUSE_BASE__INST3_SEG3                      0
+#define FUSE_BASE__INST3_SEG4                      0
+#define FUSE_BASE__INST3_SEG5                      0
+
+#define FUSE_BASE__INST4_SEG0                      0
+#define FUSE_BASE__INST4_SEG1                      0
+#define FUSE_BASE__INST4_SEG2                      0
+#define FUSE_BASE__INST4_SEG3                      0
+#define FUSE_BASE__INST4_SEG4                      0
+#define FUSE_BASE__INST4_SEG5                      0
+
+#define FUSE_BASE__INST5_SEG0                      0
+#define FUSE_BASE__INST5_SEG1                      0
+#define FUSE_BASE__INST5_SEG2                      0
+#define FUSE_BASE__INST5_SEG3                      0
+#define FUSE_BASE__INST5_SEG4                      0
+#define FUSE_BASE__INST5_SEG5                      0
+
+#define FUSE_BASE__INST6_SEG0                      0
+#define FUSE_BASE__INST6_SEG1                      0
+#define FUSE_BASE__INST6_SEG2                      0
+#define FUSE_BASE__INST6_SEG3                      0
+#define FUSE_BASE__INST6_SEG4                      0
+#define FUSE_BASE__INST6_SEG5                      0
+
+#define GC_BASE__INST0_SEG0                        0x00001260
+#define GC_BASE__INST0_SEG1                        0x0000A000
+#define GC_BASE__INST0_SEG2                        0x0001C000
+#define GC_BASE__INST0_SEG3                        0x02402C00
+#define GC_BASE__INST0_SEG4                        0
+#define GC_BASE__INST0_SEG5                        0
+
+#define GC_BASE__INST1_SEG0                        0
+#define GC_BASE__INST1_SEG1                        0
+#define GC_BASE__INST1_SEG2                        0
+#define GC_BASE__INST1_SEG3                        0
+#define GC_BASE__INST1_SEG4                        0
+#define GC_BASE__INST1_SEG5                        0
+
+#define GC_BASE__INST2_SEG0                        0
+#define GC_BASE__INST2_SEG1                        0
+#define GC_BASE__INST2_SEG2                        0
+#define GC_BASE__INST2_SEG3                        0
+#define GC_BASE__INST2_SEG4                        0
+#define GC_BASE__INST2_SEG5                        0
+
+#define GC_BASE__INST3_SEG0                        0
+#define GC_BASE__INST3_SEG1                        0
+#define GC_BASE__INST3_SEG2                        0
+#define GC_BASE__INST3_SEG3                        0
+#define GC_BASE__INST3_SEG4                        0
+#define GC_BASE__INST3_SEG5                        0
+
+#define GC_BASE__INST4_SEG0                        0
+#define GC_BASE__INST4_SEG1                        0
+#define GC_BASE__INST4_SEG2                        0
+#define GC_BASE__INST4_SEG3                        0
+#define GC_BASE__INST4_SEG4                        0
+#define GC_BASE__INST4_SEG5                        0
+
+#define GC_BASE__INST5_SEG0                        0
+#define GC_BASE__INST5_SEG1                        0
+#define GC_BASE__INST5_SEG2                        0
+#define GC_BASE__INST5_SEG3                        0
+#define GC_BASE__INST5_SEG4                        0
+#define GC_BASE__INST5_SEG5                        0
+
+#define GC_BASE__INST6_SEG0                        0
+#define GC_BASE__INST6_SEG1                        0
+#define GC_BASE__INST6_SEG2                        0
+#define GC_BASE__INST6_SEG3                        0
+#define GC_BASE__INST6_SEG4                        0
+#define GC_BASE__INST6_SEG5                        0
+
+#define HDA_BASE__INST0_SEG0                       0x004C0000
+#define HDA_BASE__INST0_SEG1                       0x02404800
+#define HDA_BASE__INST0_SEG2                       0
+#define HDA_BASE__INST0_SEG3                       0
+#define HDA_BASE__INST0_SEG4                       0
+#define HDA_BASE__INST0_SEG5                       0
+
+#define HDA_BASE__INST1_SEG0                       0
+#define HDA_BASE__INST1_SEG1                       0
+#define HDA_BASE__INST1_SEG2                       0
+#define HDA_BASE__INST1_SEG3                       0
+#define HDA_BASE__INST1_SEG4                       0
+#define HDA_BASE__INST1_SEG5                       0
+
+#define HDA_BASE__INST2_SEG0                       0
+#define HDA_BASE__INST2_SEG1                       0
+#define HDA_BASE__INST2_SEG2                       0
+#define HDA_BASE__INST2_SEG3                       0
+#define HDA_BASE__INST2_SEG4                       0
+#define HDA_BASE__INST2_SEG5                       0
+
+#define HDA_BASE__INST3_SEG0                       0
+#define HDA_BASE__INST3_SEG1                       0
+#define HDA_BASE__INST3_SEG2                       0
+#define HDA_BASE__INST3_SEG3                       0
+#define HDA_BASE__INST3_SEG4                       0
+#define HDA_BASE__INST3_SEG5                       0
+
+#define HDA_BASE__INST4_SEG0                       0
+#define HDA_BASE__INST4_SEG1                       0
+#define HDA_BASE__INST4_SEG2                       0
+#define HDA_BASE__INST4_SEG3                       0
+#define HDA_BASE__INST4_SEG4                       0
+#define HDA_BASE__INST4_SEG5                       0
+
+#define HDA_BASE__INST5_SEG0                       0
+#define HDA_BASE__INST5_SEG1                       0
+#define HDA_BASE__INST5_SEG2                       0
+#define HDA_BASE__INST5_SEG3                       0
+#define HDA_BASE__INST5_SEG4                       0
+#define HDA_BASE__INST5_SEG5                       0
+
+#define HDA_BASE__INST6_SEG0                       0
+#define HDA_BASE__INST6_SEG1                       0
+#define HDA_BASE__INST6_SEG2                       0
+#define HDA_BASE__INST6_SEG3                       0
+#define HDA_BASE__INST6_SEG4                       0
+#define HDA_BASE__INST6_SEG5                       0
+
+#define HDP_BASE__INST0_SEG0                       0x00000F20
+#define HDP_BASE__INST0_SEG1                       0x0240A400
+#define HDP_BASE__INST0_SEG2                       0
+#define HDP_BASE__INST0_SEG3                       0
+#define HDP_BASE__INST0_SEG4                       0
+#define HDP_BASE__INST0_SEG5                       0
+
+#define HDP_BASE__INST1_SEG0                       0
+#define HDP_BASE__INST1_SEG1                       0
+#define HDP_BASE__INST1_SEG2                       0
+#define HDP_BASE__INST1_SEG3                       0
+#define HDP_BASE__INST1_SEG4                       0
+#define HDP_BASE__INST1_SEG5                       0
+
+#define HDP_BASE__INST2_SEG0                       0
+#define HDP_BASE__INST2_SEG1                       0
+#define HDP_BASE__INST2_SEG2                       0
+#define HDP_BASE__INST2_SEG3                       0
+#define HDP_BASE__INST2_SEG4                       0
+#define HDP_BASE__INST2_SEG5                       0
+
+#define HDP_BASE__INST3_SEG0                       0
+#define HDP_BASE__INST3_SEG1                       0
+#define HDP_BASE__INST3_SEG2                       0
+#define HDP_BASE__INST3_SEG3                       0
+#define HDP_BASE__INST3_SEG4                       0
+#define HDP_BASE__INST3_SEG5                       0
+
+#define HDP_BASE__INST4_SEG0                       0
+#define HDP_BASE__INST4_SEG1                       0
+#define HDP_BASE__INST4_SEG2                       0
+#define HDP_BASE__INST4_SEG3                       0
+#define HDP_BASE__INST4_SEG4                       0
+#define HDP_BASE__INST4_SEG5                       0
+
+#define HDP_BASE__INST5_SEG0                       0
+#define HDP_BASE__INST5_SEG1                       0
+#define HDP_BASE__INST5_SEG2                       0
+#define HDP_BASE__INST5_SEG3                       0
+#define HDP_BASE__INST5_SEG4                       0
+#define HDP_BASE__INST5_SEG5                       0
+
+#define HDP_BASE__INST6_SEG0                       0
+#define HDP_BASE__INST6_SEG1                       0
+#define HDP_BASE__INST6_SEG2                       0
+#define HDP_BASE__INST6_SEG3                       0
+#define HDP_BASE__INST6_SEG4                       0
+#define HDP_BASE__INST6_SEG5                       0
+
+#define MMHUB_BASE__INST0_SEG0                     0x0001A000
+#define MMHUB_BASE__INST0_SEG1                     0x02408800
+#define MMHUB_BASE__INST0_SEG2                     0
+#define MMHUB_BASE__INST0_SEG3                     0
+#define MMHUB_BASE__INST0_SEG4                     0
+#define MMHUB_BASE__INST0_SEG5                     0
+
+#define MMHUB_BASE__INST1_SEG0                     0
+#define MMHUB_BASE__INST1_SEG1                     0
+#define MMHUB_BASE__INST1_SEG2                     0
+#define MMHUB_BASE__INST1_SEG3                     0
+#define MMHUB_BASE__INST1_SEG4                     0
+#define MMHUB_BASE__INST1_SEG5                     0
+
+#define MMHUB_BASE__INST2_SEG0                     0
+#define MMHUB_BASE__INST2_SEG1                     0
+#define MMHUB_BASE__INST2_SEG2                     0
+#define MMHUB_BASE__INST2_SEG3                     0
+#define MMHUB_BASE__INST2_SEG4                     0
+#define MMHUB_BASE__INST2_SEG5                     0
+
+#define MMHUB_BASE__INST3_SEG0                     0
+#define MMHUB_BASE__INST3_SEG1                     0
+#define MMHUB_BASE__INST3_SEG2                     0
+#define MMHUB_BASE__INST3_SEG3                     0
+#define MMHUB_BASE__INST3_SEG4                     0
+#define MMHUB_BASE__INST3_SEG5                     0
+
+#define MMHUB_BASE__INST4_SEG0                     0
+#define MMHUB_BASE__INST4_SEG1                     0
+#define MMHUB_BASE__INST4_SEG2                     0
+#define MMHUB_BASE__INST4_SEG3                     0
+#define MMHUB_BASE__INST4_SEG4                     0
+#define MMHUB_BASE__INST4_SEG5                     0
+
+#define MMHUB_BASE__INST5_SEG0                     0
+#define MMHUB_BASE__INST5_SEG1                     0
+#define MMHUB_BASE__INST5_SEG2                     0
+#define MMHUB_BASE__INST5_SEG3                     0
+#define MMHUB_BASE__INST5_SEG4                     0
+#define MMHUB_BASE__INST5_SEG5                     0
+
+#define MMHUB_BASE__INST6_SEG0                     0
+#define MMHUB_BASE__INST6_SEG1                     0
+#define MMHUB_BASE__INST6_SEG2                     0
+#define MMHUB_BASE__INST6_SEG3                     0
+#define MMHUB_BASE__INST6_SEG4                     0
+#define MMHUB_BASE__INST6_SEG5                     0
+
+#define MP0_BASE__INST0_SEG0                       0x00016000
+#define MP0_BASE__INST0_SEG1                       0x00DC0000
+#define MP0_BASE__INST0_SEG2                       0x00E00000
+#define MP0_BASE__INST0_SEG3                       0x00E40000
+#define MP0_BASE__INST0_SEG4                       0x0243FC00
+#define MP0_BASE__INST0_SEG5                       0
+
+#define MP0_BASE__INST1_SEG0                       0
+#define MP0_BASE__INST1_SEG1                       0
+#define MP0_BASE__INST1_SEG2                       0
+#define MP0_BASE__INST1_SEG3                       0
+#define MP0_BASE__INST1_SEG4                       0
+#define MP0_BASE__INST1_SEG5                       0
+
+#define MP0_BASE__INST2_SEG0                       0
+#define MP0_BASE__INST2_SEG1                       0
+#define MP0_BASE__INST2_SEG2                       0
+#define MP0_BASE__INST2_SEG3                       0
+#define MP0_BASE__INST2_SEG4                       0
+#define MP0_BASE__INST2_SEG5                       0
+
+#define MP0_BASE__INST3_SEG0                       0
+#define MP0_BASE__INST3_SEG1                       0
+#define MP0_BASE__INST3_SEG2                       0
+#define MP0_BASE__INST3_SEG3                       0
+#define MP0_BASE__INST3_SEG4                       0
+#define MP0_BASE__INST3_SEG5                       0
+
+#define MP0_BASE__INST4_SEG0                       0
+#define MP0_BASE__INST4_SEG1                       0
+#define MP0_BASE__INST4_SEG2                       0
+#define MP0_BASE__INST4_SEG3                       0
+#define MP0_BASE__INST4_SEG4                       0
+#define MP0_BASE__INST4_SEG5                       0
+
+#define MP0_BASE__INST5_SEG0                       0
+#define MP0_BASE__INST5_SEG1                       0
+#define MP0_BASE__INST5_SEG2                       0
+#define MP0_BASE__INST5_SEG3                       0
+#define MP0_BASE__INST5_SEG4                       0
+#define MP0_BASE__INST5_SEG5                       0
+
+#define MP0_BASE__INST6_SEG0                       0
+#define MP0_BASE__INST6_SEG1                       0
+#define MP0_BASE__INST6_SEG2                       0
+#define MP0_BASE__INST6_SEG3                       0
+#define MP0_BASE__INST6_SEG4                       0
+#define MP0_BASE__INST6_SEG5                       0
+
+#define MP1_BASE__INST0_SEG0                       0x00016000
+#define MP1_BASE__INST0_SEG1                       0x00DC0000
+#define MP1_BASE__INST0_SEG2                       0x00E00000
+#define MP1_BASE__INST0_SEG3                       0x00E40000
+#define MP1_BASE__INST0_SEG4                       0x0243FC00
+#define MP1_BASE__INST0_SEG5                       0
+
+#define MP1_BASE__INST1_SEG0                       0
+#define MP1_BASE__INST1_SEG1                       0
+#define MP1_BASE__INST1_SEG2                       0
+#define MP1_BASE__INST1_SEG3                       0
+#define MP1_BASE__INST1_SEG4                       0
+#define MP1_BASE__INST1_SEG5                       0
+
+#define MP1_BASE__INST2_SEG0                       0
+#define MP1_BASE__INST2_SEG1                       0
+#define MP1_BASE__INST2_SEG2                       0
+#define MP1_BASE__INST2_SEG3                       0
+#define MP1_BASE__INST2_SEG4                       0
+#define MP1_BASE__INST2_SEG5                       0
+
+#define MP1_BASE__INST3_SEG0                       0
+#define MP1_BASE__INST3_SEG1                       0
+#define MP1_BASE__INST3_SEG2                       0
+#define MP1_BASE__INST3_SEG3                       0
+#define MP1_BASE__INST3_SEG4                       0
+#define MP1_BASE__INST3_SEG5                       0
+
+#define MP1_BASE__INST4_SEG0                       0
+#define MP1_BASE__INST4_SEG1                       0
+#define MP1_BASE__INST4_SEG2                       0
+#define MP1_BASE__INST4_SEG3                       0
+#define MP1_BASE__INST4_SEG4                       0
+#define MP1_BASE__INST4_SEG5                       0
+
+#define MP1_BASE__INST5_SEG0                       0
+#define MP1_BASE__INST5_SEG1                       0
+#define MP1_BASE__INST5_SEG2                       0
+#define MP1_BASE__INST5_SEG3                       0
+#define MP1_BASE__INST5_SEG4                       0
+#define MP1_BASE__INST5_SEG5                       0
+
+#define MP1_BASE__INST6_SEG0                       0
+#define MP1_BASE__INST6_SEG1                       0
+#define MP1_BASE__INST6_SEG2                       0
+#define MP1_BASE__INST6_SEG3                       0
+#define MP1_BASE__INST6_SEG4                       0
+#define MP1_BASE__INST6_SEG5                       0
+
+#define NBIO_BASE__INST0_SEG0                      0x00000000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+#define NBIO_BASE__INST0_SEG2                      0x00000D20
+#define NBIO_BASE__INST0_SEG3                      0x00010400
+#define NBIO_BASE__INST0_SEG4                      0x0241B000
+#define NBIO_BASE__INST0_SEG5                      0x04040000
+
+#define NBIO_BASE__INST1_SEG0                      0
+#define NBIO_BASE__INST1_SEG1                      0
+#define NBIO_BASE__INST1_SEG2                      0
+#define NBIO_BASE__INST1_SEG3                      0
+#define NBIO_BASE__INST1_SEG4                      0
+#define NBIO_BASE__INST1_SEG5                      0
+
+#define NBIO_BASE__INST2_SEG0                      0
+#define NBIO_BASE__INST2_SEG1                      0
+#define NBIO_BASE__INST2_SEG2                      0
+#define NBIO_BASE__INST2_SEG3                      0
+#define NBIO_BASE__INST2_SEG4                      0
+#define NBIO_BASE__INST2_SEG5                      0
+
+#define NBIO_BASE__INST3_SEG0                      0
+#define NBIO_BASE__INST3_SEG1                      0
+#define NBIO_BASE__INST3_SEG2                      0
+#define NBIO_BASE__INST3_SEG3                      0
+#define NBIO_BASE__INST3_SEG4                      0
+#define NBIO_BASE__INST3_SEG5                      0
+
+#define NBIO_BASE__INST4_SEG0                      0
+#define NBIO_BASE__INST4_SEG1                      0
+#define NBIO_BASE__INST4_SEG2                      0
+#define NBIO_BASE__INST4_SEG3                      0
+#define NBIO_BASE__INST4_SEG4                      0
+#define NBIO_BASE__INST4_SEG5                      0
+
+#define NBIO_BASE__INST5_SEG0                      0
+#define NBIO_BASE__INST5_SEG1                      0
+#define NBIO_BASE__INST5_SEG2                      0
+#define NBIO_BASE__INST5_SEG3                      0
+#define NBIO_BASE__INST5_SEG4                      0
+#define NBIO_BASE__INST5_SEG5                      0
+
+#define NBIO_BASE__INST6_SEG0                      0
+#define NBIO_BASE__INST6_SEG1                      0
+#define NBIO_BASE__INST6_SEG2                      0
+#define NBIO_BASE__INST6_SEG3                      0
+#define NBIO_BASE__INST6_SEG4                      0
+#define NBIO_BASE__INST6_SEG5                      0
+
+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
+#define OSSSYS_BASE__INST0_SEG2                    0
+#define OSSSYS_BASE__INST0_SEG3                    0
+#define OSSSYS_BASE__INST0_SEG4                    0
+#define OSSSYS_BASE__INST0_SEG5                    0
+
+#define OSSSYS_BASE__INST1_SEG0                    0
+#define OSSSYS_BASE__INST1_SEG1                    0
+#define OSSSYS_BASE__INST1_SEG2                    0
+#define OSSSYS_BASE__INST1_SEG3                    0
+#define OSSSYS_BASE__INST1_SEG4                    0
+#define OSSSYS_BASE__INST1_SEG5                    0
+
+#define OSSSYS_BASE__INST2_SEG0                    0
+#define OSSSYS_BASE__INST2_SEG1                    0
+#define OSSSYS_BASE__INST2_SEG2                    0
+#define OSSSYS_BASE__INST2_SEG3                    0
+#define OSSSYS_BASE__INST2_SEG4                    0
+#define OSSSYS_BASE__INST2_SEG5                    0
+
+#define OSSSYS_BASE__INST3_SEG0                    0
+#define OSSSYS_BASE__INST3_SEG1                    0
+#define OSSSYS_BASE__INST3_SEG2                    0
+#define OSSSYS_BASE__INST3_SEG3                    0
+#define OSSSYS_BASE__INST3_SEG4                    0
+#define OSSSYS_BASE__INST3_SEG5                    0
+
+#define OSSSYS_BASE__INST4_SEG0                    0
+#define OSSSYS_BASE__INST4_SEG1                    0
+#define OSSSYS_BASE__INST4_SEG2                    0
+#define OSSSYS_BASE__INST4_SEG3                    0
+#define OSSSYS_BASE__INST4_SEG4                    0
+#define OSSSYS_BASE__INST4_SEG5                    0
+
+#define OSSSYS_BASE__INST5_SEG0                    0
+#define OSSSYS_BASE__INST5_SEG1                    0
+#define OSSSYS_BASE__INST5_SEG2                    0
+#define OSSSYS_BASE__INST5_SEG3                    0
+#define OSSSYS_BASE__INST5_SEG4                    0
+#define OSSSYS_BASE__INST5_SEG5                    0
+
+#define OSSSYS_BASE__INST6_SEG0                    0
+#define OSSSYS_BASE__INST6_SEG1                    0
+#define OSSSYS_BASE__INST6_SEG2                    0
+#define OSSSYS_BASE__INST6_SEG3                    0
+#define OSSSYS_BASE__INST6_SEG4                    0
+#define OSSSYS_BASE__INST6_SEG5                    0
+
+#define PCIE0_BASE__INST0_SEG0                     0x00000000
+#define PCIE0_BASE__INST0_SEG1                     0x00000014
+#define PCIE0_BASE__INST0_SEG2                     0x00000D20
+#define PCIE0_BASE__INST0_SEG3                     0x00010400
+#define PCIE0_BASE__INST0_SEG4                     0x0241B000
+#define PCIE0_BASE__INST0_SEG5                     0x04040000
+
+#define PCIE0_BASE__INST1_SEG0                     0
+#define PCIE0_BASE__INST1_SEG1                     0
+#define PCIE0_BASE__INST1_SEG2                     0
+#define PCIE0_BASE__INST1_SEG3                     0
+#define PCIE0_BASE__INST1_SEG4                     0
+#define PCIE0_BASE__INST1_SEG5                     0
+
+#define PCIE0_BASE__INST2_SEG0                     0
+#define PCIE0_BASE__INST2_SEG1                     0
+#define PCIE0_BASE__INST2_SEG2                     0
+#define PCIE0_BASE__INST2_SEG3                     0
+#define PCIE0_BASE__INST2_SEG4                     0
+#define PCIE0_BASE__INST2_SEG5                     0
+
+#define PCIE0_BASE__INST3_SEG0                     0
+#define PCIE0_BASE__INST3_SEG1                     0
+#define PCIE0_BASE__INST3_SEG2                     0
+#define PCIE0_BASE__INST3_SEG3                     0
+#define PCIE0_BASE__INST3_SEG4                     0
+#define PCIE0_BASE__INST3_SEG5                     0
+
+#define PCIE0_BASE__INST4_SEG0                     0
+#define PCIE0_BASE__INST4_SEG1                     0
+#define PCIE0_BASE__INST4_SEG2                     0
+#define PCIE0_BASE__INST4_SEG3                     0
+#define PCIE0_BASE__INST4_SEG4                     0
+#define PCIE0_BASE__INST4_SEG5                     0
+
+#define PCIE0_BASE__INST5_SEG0                     0
+#define PCIE0_BASE__INST5_SEG1                     0
+#define PCIE0_BASE__INST5_SEG2                     0
+#define PCIE0_BASE__INST5_SEG3                     0
+#define PCIE0_BASE__INST5_SEG4                     0
+#define PCIE0_BASE__INST5_SEG5                     0
+
+#define PCIE0_BASE__INST6_SEG0                     0
+#define PCIE0_BASE__INST6_SEG1                     0
+#define PCIE0_BASE__INST6_SEG2                     0
+#define PCIE0_BASE__INST6_SEG3                     0
+#define PCIE0_BASE__INST6_SEG4                     0
+#define PCIE0_BASE__INST6_SEG5                     0
+
+#define SDMA0_BASE__INST0_SEG0                     0x00001260
+#define SDMA0_BASE__INST0_SEG1                     0x0000A000
+#define SDMA0_BASE__INST0_SEG2                     0x0001C000
+#define SDMA0_BASE__INST0_SEG3                     0x02402C00
+#define SDMA0_BASE__INST0_SEG4                     0
+#define SDMA0_BASE__INST0_SEG5                     0
+
+#define SDMA0_BASE__INST1_SEG0                     0
+#define SDMA0_BASE__INST1_SEG1                     0
+#define SDMA0_BASE__INST1_SEG2                     0
+#define SDMA0_BASE__INST1_SEG3                     0
+#define SDMA0_BASE__INST1_SEG4                     0
+#define SDMA0_BASE__INST1_SEG5                     0
+
+#define SDMA0_BASE__INST2_SEG0                     0
+#define SDMA0_BASE__INST2_SEG1                     0
+#define SDMA0_BASE__INST2_SEG2                     0
+#define SDMA0_BASE__INST2_SEG3                     0
+#define SDMA0_BASE__INST2_SEG4                     0
+#define SDMA0_BASE__INST2_SEG5                     0
+
+#define SDMA0_BASE__INST3_SEG0                     0
+#define SDMA0_BASE__INST3_SEG1                     0
+#define SDMA0_BASE__INST3_SEG2                     0
+#define SDMA0_BASE__INST3_SEG3                     0
+#define SDMA0_BASE__INST3_SEG4                     0
+#define SDMA0_BASE__INST3_SEG5                     0
+
+#define SDMA0_BASE__INST4_SEG0                     0
+#define SDMA0_BASE__INST4_SEG1                     0
+#define SDMA0_BASE__INST4_SEG2                     0
+#define SDMA0_BASE__INST4_SEG3                     0
+#define SDMA0_BASE__INST4_SEG4                     0
+#define SDMA0_BASE__INST4_SEG5                     0
+
+#define SDMA0_BASE__INST5_SEG0                     0
+#define SDMA0_BASE__INST5_SEG1                     0
+#define SDMA0_BASE__INST5_SEG2                     0
+#define SDMA0_BASE__INST5_SEG3                     0
+#define SDMA0_BASE__INST5_SEG4                     0
+#define SDMA0_BASE__INST5_SEG5                     0
+
+#define SDMA0_BASE__INST6_SEG0                     0
+#define SDMA0_BASE__INST6_SEG1                     0
+#define SDMA0_BASE__INST6_SEG2                     0
+#define SDMA0_BASE__INST6_SEG3                     0
+#define SDMA0_BASE__INST6_SEG4                     0
+#define SDMA0_BASE__INST6_SEG5                     0
+
+#define SMUIO_BASE__INST0_SEG0                     0x00016800
+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
+#define SMUIO_BASE__INST0_SEG2                     0x00440000
+#define SMUIO_BASE__INST0_SEG3                     0x02401000
+#define SMUIO_BASE__INST0_SEG4                     0
+#define SMUIO_BASE__INST0_SEG5                     0
+
+#define SMUIO_BASE__INST1_SEG0                     0
+#define SMUIO_BASE__INST1_SEG1                     0
+#define SMUIO_BASE__INST1_SEG2                     0
+#define SMUIO_BASE__INST1_SEG3                     0
+#define SMUIO_BASE__INST1_SEG4                     0
+#define SMUIO_BASE__INST1_SEG5                     0
+
+#define SMUIO_BASE__INST2_SEG0                     0
+#define SMUIO_BASE__INST2_SEG1                     0
+#define SMUIO_BASE__INST2_SEG2                     0
+#define SMUIO_BASE__INST2_SEG3                     0
+#define SMUIO_BASE__INST2_SEG4                     0
+#define SMUIO_BASE__INST2_SEG5                     0
+
+#define SMUIO_BASE__INST3_SEG0                     0
+#define SMUIO_BASE__INST3_SEG1                     0
+#define SMUIO_BASE__INST3_SEG2                     0
+#define SMUIO_BASE__INST3_SEG3                     0
+#define SMUIO_BASE__INST3_SEG4                     0
+#define SMUIO_BASE__INST3_SEG5                     0
+
+#define SMUIO_BASE__INST4_SEG0                     0
+#define SMUIO_BASE__INST4_SEG1                     0
+#define SMUIO_BASE__INST4_SEG2                     0
+#define SMUIO_BASE__INST4_SEG3                     0
+#define SMUIO_BASE__INST4_SEG4                     0
+#define SMUIO_BASE__INST4_SEG5                     0
+
+#define SMUIO_BASE__INST5_SEG0                     0
+#define SMUIO_BASE__INST5_SEG1                     0
+#define SMUIO_BASE__INST5_SEG2                     0
+#define SMUIO_BASE__INST5_SEG3                     0
+#define SMUIO_BASE__INST5_SEG4                     0
+#define SMUIO_BASE__INST5_SEG5                     0
+
+#define SMUIO_BASE__INST6_SEG0                     0
+#define SMUIO_BASE__INST6_SEG1                     0
+#define SMUIO_BASE__INST6_SEG2                     0
+#define SMUIO_BASE__INST6_SEG3                     0
+#define SMUIO_BASE__INST6_SEG4                     0
+#define SMUIO_BASE__INST6_SEG5                     0
+
+#define THM_BASE__INST0_SEG0                       0x00016600
+#define THM_BASE__INST0_SEG1                       0x02400C00
+#define THM_BASE__INST0_SEG2                       0
+#define THM_BASE__INST0_SEG3                       0
+#define THM_BASE__INST0_SEG4                       0
+#define THM_BASE__INST0_SEG5                       0
+
+#define THM_BASE__INST1_SEG0                       0
+#define THM_BASE__INST1_SEG1                       0
+#define THM_BASE__INST1_SEG2                       0
+#define THM_BASE__INST1_SEG3                       0
+#define THM_BASE__INST1_SEG4                       0
+#define THM_BASE__INST1_SEG5                       0
+
+#define THM_BASE__INST2_SEG0                       0
+#define THM_BASE__INST2_SEG1                       0
+#define THM_BASE__INST2_SEG2                       0
+#define THM_BASE__INST2_SEG3                       0
+#define THM_BASE__INST2_SEG4                       0
+#define THM_BASE__INST2_SEG5                       0
+
+#define THM_BASE__INST3_SEG0                       0
+#define THM_BASE__INST3_SEG1                       0
+#define THM_BASE__INST3_SEG2                       0
+#define THM_BASE__INST3_SEG3                       0
+#define THM_BASE__INST3_SEG4                       0
+#define THM_BASE__INST3_SEG5                       0
+
+#define THM_BASE__INST4_SEG0                       0
+#define THM_BASE__INST4_SEG1                       0
+#define THM_BASE__INST4_SEG2                       0
+#define THM_BASE__INST4_SEG3                       0
+#define THM_BASE__INST4_SEG4                       0
+#define THM_BASE__INST4_SEG5                       0
+
+#define THM_BASE__INST5_SEG0                       0
+#define THM_BASE__INST5_SEG1                       0
+#define THM_BASE__INST5_SEG2                       0
+#define THM_BASE__INST5_SEG3                       0
+#define THM_BASE__INST5_SEG4                       0
+#define THM_BASE__INST5_SEG5                       0
+
+#define THM_BASE__INST6_SEG0                       0
+#define THM_BASE__INST6_SEG1                       0
+#define THM_BASE__INST6_SEG2                       0
+#define THM_BASE__INST6_SEG3                       0
+#define THM_BASE__INST6_SEG4                       0
+#define THM_BASE__INST6_SEG5                       0
+
+#define UMC_BASE__INST0_SEG0                       0x00014000
+#define UMC_BASE__INST0_SEG1                       0x02425800
+#define UMC_BASE__INST0_SEG2                       0
+#define UMC_BASE__INST0_SEG3                       0
+#define UMC_BASE__INST0_SEG4                       0
+#define UMC_BASE__INST0_SEG5                       0
+
+#define UMC_BASE__INST1_SEG0                       0x00054000
+#define UMC_BASE__INST1_SEG1                       0x02425C00
+#define UMC_BASE__INST1_SEG2                       0
+#define UMC_BASE__INST1_SEG3                       0
+#define UMC_BASE__INST1_SEG4                       0
+#define UMC_BASE__INST1_SEG5                       0
+
+#define UMC_BASE__INST2_SEG0                       0
+#define UMC_BASE__INST2_SEG1                       0
+#define UMC_BASE__INST2_SEG2                       0
+#define UMC_BASE__INST2_SEG3                       0
+#define UMC_BASE__INST2_SEG4                       0
+#define UMC_BASE__INST2_SEG5                       0
+
+#define UMC_BASE__INST3_SEG0                       0
+#define UMC_BASE__INST3_SEG1                       0
+#define UMC_BASE__INST3_SEG2                       0
+#define UMC_BASE__INST3_SEG3                       0
+#define UMC_BASE__INST3_SEG4                       0
+#define UMC_BASE__INST3_SEG5                       0
+
+#define UMC_BASE__INST4_SEG0                       0
+#define UMC_BASE__INST4_SEG1                       0
+#define UMC_BASE__INST4_SEG2                       0
+#define UMC_BASE__INST4_SEG3                       0
+#define UMC_BASE__INST4_SEG4                       0
+#define UMC_BASE__INST4_SEG5                       0
+
+#define UMC_BASE__INST5_SEG0                       0
+#define UMC_BASE__INST5_SEG1                       0
+#define UMC_BASE__INST5_SEG2                       0
+#define UMC_BASE__INST5_SEG3                       0
+#define UMC_BASE__INST5_SEG4                       0
+#define UMC_BASE__INST5_SEG5                       0
+
+#define UMC_BASE__INST6_SEG0                       0
+#define UMC_BASE__INST6_SEG1                       0
+#define UMC_BASE__INST6_SEG2                       0
+#define UMC_BASE__INST6_SEG3                       0
+#define UMC_BASE__INST6_SEG4                       0
+#define UMC_BASE__INST6_SEG5                       0
+
+#define VCN0_BASE__INST0_SEG0                      0x00007800
+#define VCN0_BASE__INST0_SEG1                      0x00007E00
+#define VCN0_BASE__INST0_SEG2                      0x02403000
+#define VCN0_BASE__INST0_SEG3                      0
+#define VCN0_BASE__INST0_SEG4                      0
+#define VCN0_BASE__INST0_SEG5                      0
+
+#define VCN0_BASE__INST1_SEG0                      0
+#define VCN0_BASE__INST1_SEG1                      0
+#define VCN0_BASE__INST1_SEG2                      0
+#define VCN0_BASE__INST1_SEG3                      0
+#define VCN0_BASE__INST1_SEG4                      0
+#define VCN0_BASE__INST1_SEG5                      0
+
+#define VCN0_BASE__INST2_SEG0                      0
+#define VCN0_BASE__INST2_SEG1                      0
+#define VCN0_BASE__INST2_SEG2                      0
+#define VCN0_BASE__INST2_SEG3                      0
+#define VCN0_BASE__INST2_SEG4                      0
+#define VCN0_BASE__INST2_SEG5                      0
+
+#define VCN0_BASE__INST3_SEG0                      0
+#define VCN0_BASE__INST3_SEG1                      0
+#define VCN0_BASE__INST3_SEG2                      0
+#define VCN0_BASE__INST3_SEG3                      0
+#define VCN0_BASE__INST3_SEG4                      0
+#define VCN0_BASE__INST3_SEG5                      0
+
+#define VCN0_BASE__INST4_SEG0                      0
+#define VCN0_BASE__INST4_SEG1                      0
+#define VCN0_BASE__INST4_SEG2                      0
+#define VCN0_BASE__INST4_SEG3                      0
+#define VCN0_BASE__INST4_SEG4                      0
+#define VCN0_BASE__INST4_SEG5                      0
+
+#define VCN0_BASE__INST5_SEG0                      0
+#define VCN0_BASE__INST5_SEG1                      0
+#define VCN0_BASE__INST5_SEG2                      0
+#define VCN0_BASE__INST5_SEG3                      0
+#define VCN0_BASE__INST5_SEG4                      0
+#define VCN0_BASE__INST5_SEG5                      0
+
+#define VCN0_BASE__INST6_SEG0                      0
+#define VCN0_BASE__INST6_SEG1                      0
+#define VCN0_BASE__INST6_SEG2                      0
+#define VCN0_BASE__INST6_SEG3                      0
+#define VCN0_BASE__INST6_SEG4                      0
+#define VCN0_BASE__INST6_SEG5                      0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 353468667036..e38b191c7b7c 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -124,6 +124,8 @@ enum amd_pp_sensors {
 	AMDGPU_PP_SENSOR_VCE_POWER,
 	AMDGPU_PP_SENSOR_UVD_POWER,
 	AMDGPU_PP_SENSOR_GPU_POWER,
+	AMDGPU_PP_SENSOR_SS_APU_SHARE,
+	AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 	AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 	AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 	AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
@@ -192,6 +194,48 @@ enum pp_df_cstate {
 	DF_CSTATE_ALLOW,
 };
 
+/**
+ * DOC: amdgpu_pp_power
+ *
+ * APU power is managed to system-level requirements through the PPT
+ * (package power tracking) feature. PPT is intended to limit power to the
+ * requirements of the power source and could be dynamically updated to
+ * maximize APU performance within the system power budget.
+ *
+ * Two types of power measurement can be requested, where supported, with
+ * :c:type:`enum pp_power_type <pp_power_type>`.
+ */
+
+/**
+ * enum pp_power_limit_level - Used to query the power limits
+ *
+ * @PP_PWR_LIMIT_MIN: Minimum Power Limit
+ * @PP_PWR_LIMIT_CURRENT: Current Power Limit
+ * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
+ * @PP_PWR_LIMIT_MAX: Maximum Power Limit
+ */
+enum pp_power_limit_level
+{
+	PP_PWR_LIMIT_MIN = -1,
+	PP_PWR_LIMIT_CURRENT,
+	PP_PWR_LIMIT_DEFAULT,
+	PP_PWR_LIMIT_MAX,
+};
+
+/**
+ * enum pp_power_type - Used to specify the type of the requested power
+ *
+ * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
+ * moving average of APU power (default ~5000 ms).
+ * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
+ * where supported.
+ */
+enum pp_power_type
+{
+	PP_PWR_TYPE_SUSTAINED,
+	PP_PWR_TYPE_FAST,
+};
+
 #define PP_GROUP_MASK        0xF0000000
 #define PP_GROUP_SHIFT       28
 
@@ -291,8 +335,9 @@ struct amd_pm_funcs {
 				uint32_t block_type, bool gate);
 	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 	int (*set_power_limit)(void *handle, uint32_t n);
-	int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit,
-			bool default_limit);
+	int (*get_power_limit)(void *handle, uint32_t *limit,
+			enum pp_power_limit_level pp_limit_level,
+			enum pp_power_type power_type);
 	int (*get_power_profile_mode)(void *handle, char *buf);
 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 	int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
@@ -350,6 +395,7 @@ struct amd_pm_funcs {
 				   unsigned int *num_states);
 	int (*get_dpm_clock_table)(void *handle,
 				   struct dpm_clocks *clock_table);
+	int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 };
 
 struct metrics_table_header {
@@ -473,6 +519,140 @@ struct gpu_metrics_v1_1 {
 	uint16_t			temperature_hbm[NUM_HBM_INSTANCES];
 };
 
+struct gpu_metrics_v1_2 {
+	struct metrics_table_header	common_header;
+
+	/* Temperature */
+	uint16_t			temperature_edge;
+	uint16_t			temperature_hotspot;
+	uint16_t			temperature_mem;
+	uint16_t			temperature_vrgfx;
+	uint16_t			temperature_vrsoc;
+	uint16_t			temperature_vrmem;
+
+	/* Utilization */
+	uint16_t			average_gfx_activity;
+	uint16_t			average_umc_activity; // memory controller
+	uint16_t			average_mm_activity; // UVD or VCN
+
+	/* Power/Energy */
+	uint16_t			average_socket_power;
+	uint64_t			energy_accumulator;
+
+	/* Driver attached timestamp (in ns) */
+	uint64_t			system_clock_counter;
+
+	/* Average clocks */
+	uint16_t			average_gfxclk_frequency;
+	uint16_t			average_socclk_frequency;
+	uint16_t			average_uclk_frequency;
+	uint16_t			average_vclk0_frequency;
+	uint16_t			average_dclk0_frequency;
+	uint16_t			average_vclk1_frequency;
+	uint16_t			average_dclk1_frequency;
+
+	/* Current clocks */
+	uint16_t			current_gfxclk;
+	uint16_t			current_socclk;
+	uint16_t			current_uclk;
+	uint16_t			current_vclk0;
+	uint16_t			current_dclk0;
+	uint16_t			current_vclk1;
+	uint16_t			current_dclk1;
+
+	/* Throttle status (ASIC dependent) */
+	uint32_t			throttle_status;
+
+	/* Fans */
+	uint16_t			current_fan_speed;
+
+	/* Link width/speed */
+	uint16_t			pcie_link_width;
+	uint16_t			pcie_link_speed; // in 0.1 GT/s
+
+	uint16_t			padding;
+
+	uint32_t			gfx_activity_acc;
+	uint32_t			mem_activity_acc;
+
+	uint16_t			temperature_hbm[NUM_HBM_INSTANCES];
+
+	/* PMFW attached timestamp (10ns resolution) */
+	uint64_t			firmware_timestamp;
+};
+
+struct gpu_metrics_v1_3 {
+	struct metrics_table_header	common_header;
+
+	/* Temperature */
+	uint16_t			temperature_edge;
+	uint16_t			temperature_hotspot;
+	uint16_t			temperature_mem;
+	uint16_t			temperature_vrgfx;
+	uint16_t			temperature_vrsoc;
+	uint16_t			temperature_vrmem;
+
+	/* Utilization */
+	uint16_t			average_gfx_activity;
+	uint16_t			average_umc_activity; // memory controller
+	uint16_t			average_mm_activity; // UVD or VCN
+
+	/* Power/Energy */
+	uint16_t			average_socket_power;
+	uint64_t			energy_accumulator;
+
+	/* Driver attached timestamp (in ns) */
+	uint64_t			system_clock_counter;
+
+	/* Average clocks */
+	uint16_t			average_gfxclk_frequency;
+	uint16_t			average_socclk_frequency;
+	uint16_t			average_uclk_frequency;
+	uint16_t			average_vclk0_frequency;
+	uint16_t			average_dclk0_frequency;
+	uint16_t			average_vclk1_frequency;
+	uint16_t			average_dclk1_frequency;
+
+	/* Current clocks */
+	uint16_t			current_gfxclk;
+	uint16_t			current_socclk;
+	uint16_t			current_uclk;
+	uint16_t			current_vclk0;
+	uint16_t			current_dclk0;
+	uint16_t			current_vclk1;
+	uint16_t			current_dclk1;
+
+	/* Throttle status */
+	uint32_t			throttle_status;
+
+	/* Fans */
+	uint16_t			current_fan_speed;
+
+	/* Link width/speed */
+	uint16_t			pcie_link_width;
+	uint16_t			pcie_link_speed; // in 0.1 GT/s
+
+	uint16_t			padding;
+
+	uint32_t			gfx_activity_acc;
+	uint32_t			mem_activity_acc;
+
+	uint16_t			temperature_hbm[NUM_HBM_INSTANCES];
+
+	/* PMFW attached timestamp (10ns resolution) */
+	uint64_t			firmware_timestamp;
+
+	/* Voltage (mV) */
+	uint16_t			voltage_soc;
+	uint16_t			voltage_gfx;
+	uint16_t			voltage_mem;
+
+	uint16_t			padding1;
+
+	/* Throttle status (ASIC independent) */
+	uint64_t			indep_throttle_status;
+};
+
 /*
  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
  * Use gpu_metrics_v2_1 or later instead.
@@ -577,4 +757,57 @@ struct gpu_metrics_v2_1 {
 	uint16_t			padding[3];
 };
 
+struct gpu_metrics_v2_2 {
+	struct metrics_table_header	common_header;
+
+	/* Temperature */
+	uint16_t			temperature_gfx; // gfx temperature on APUs
+	uint16_t			temperature_soc; // soc temperature on APUs
+	uint16_t			temperature_core[8]; // CPU core temperature on APUs
+	uint16_t			temperature_l3[2];
+
+	/* Utilization */
+	uint16_t			average_gfx_activity;
+	uint16_t			average_mm_activity; // UVD or VCN
+
+	/* Driver attached timestamp (in ns) */
+	uint64_t			system_clock_counter;
+
+	/* Power/Energy */
+	uint16_t			average_socket_power; // dGPU + APU power on A + A platform
+	uint16_t			average_cpu_power;
+	uint16_t			average_soc_power;
+	uint16_t			average_gfx_power;
+	uint16_t			average_core_power[8]; // CPU core power on APUs
+
+	/* Average clocks */
+	uint16_t			average_gfxclk_frequency;
+	uint16_t			average_socclk_frequency;
+	uint16_t			average_uclk_frequency;
+	uint16_t			average_fclk_frequency;
+	uint16_t			average_vclk_frequency;
+	uint16_t			average_dclk_frequency;
+
+	/* Current clocks */
+	uint16_t			current_gfxclk;
+	uint16_t			current_socclk;
+	uint16_t			current_uclk;
+	uint16_t			current_fclk;
+	uint16_t			current_vclk;
+	uint16_t			current_dclk;
+	uint16_t			current_coreclk[8]; // CPU core clocks
+	uint16_t			current_l3clk[2];
+
+	/* Throttle status (ASIC dependent) */
+	uint32_t			throttle_status;
+
+	/* Fans */
+	uint16_t			fan_pwm;
+
+	uint16_t			padding[3];
+
+	/* Throttle status (ASIC independent) */
+	uint64_t			indep_throttle_status;
+};
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/yellow_carp_offset.h b/drivers/gpu/drm/amd/include/yellow_carp_offset.h
new file mode 100644
index 000000000000..76b9eb3f441d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/yellow_carp_offset.h
@@ -0,0 +1,1366 @@
+#ifndef YELLOW_CARP_OFFSET_H
+#define YELLOW_CARP_OFFSET_H
+
+
+#define MAX_INSTANCE                                        7
+#define MAX_SEGMENT                                         6
+
+
+struct IP_BASE_INSTANCE
+{
+    unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+                                        { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+                                        { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+                                        { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+                                        { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+                                        { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+                                        { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0x00000260, 0x00000280, 0x0240B400, 0x02413C00, 0x02416000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x02447800, 0x00C00000, 0x03640000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } },
+                                        { { 0x02411C00, 0x04480000, 0, 0, 0, 0 } },
+                                        { { 0x02412000, 0x044C0000, 0, 0, 0, 0 } },
+                                        { { 0x02412400, 0x04500000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
+                                        { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0x02425C00, 0, 0 } },
+                                        { { 0x00094000, 0x000D4000, 0x02426000, 0x02426400, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ACP_BASE__INST0_SEG0                       0x02403800
+#define ACP_BASE__INST0_SEG1                       0x00480000
+#define ACP_BASE__INST0_SEG2                       0
+#define ACP_BASE__INST0_SEG3                       0
+#define ACP_BASE__INST0_SEG4                       0
+#define ACP_BASE__INST0_SEG5                       0
+
+#define ACP_BASE__INST1_SEG0                       0
+#define ACP_BASE__INST1_SEG1                       0
+#define ACP_BASE__INST1_SEG2                       0
+#define ACP_BASE__INST1_SEG3                       0
+#define ACP_BASE__INST1_SEG4                       0
+#define ACP_BASE__INST1_SEG5                       0
+
+#define ACP_BASE__INST2_SEG0                       0
+#define ACP_BASE__INST2_SEG1                       0
+#define ACP_BASE__INST2_SEG2                       0
+#define ACP_BASE__INST2_SEG3                       0
+#define ACP_BASE__INST2_SEG4                       0
+#define ACP_BASE__INST2_SEG5                       0
+
+#define ACP_BASE__INST3_SEG0                       0
+#define ACP_BASE__INST3_SEG1                       0
+#define ACP_BASE__INST3_SEG2                       0
+#define ACP_BASE__INST3_SEG3                       0
+#define ACP_BASE__INST3_SEG4                       0
+#define ACP_BASE__INST3_SEG5                       0
+
+#define ACP_BASE__INST4_SEG0                       0
+#define ACP_BASE__INST4_SEG1                       0
+#define ACP_BASE__INST4_SEG2                       0
+#define ACP_BASE__INST4_SEG3                       0
+#define ACP_BASE__INST4_SEG4                       0
+#define ACP_BASE__INST4_SEG5                       0
+
+#define ACP_BASE__INST5_SEG0                       0
+#define ACP_BASE__INST5_SEG1                       0
+#define ACP_BASE__INST5_SEG2                       0
+#define ACP_BASE__INST5_SEG3                       0
+#define ACP_BASE__INST5_SEG4                       0
+#define ACP_BASE__INST5_SEG5                       0
+
+#define ACP_BASE__INST6_SEG0                       0
+#define ACP_BASE__INST6_SEG1                       0
+#define ACP_BASE__INST6_SEG2                       0
+#define ACP_BASE__INST6_SEG3                       0
+#define ACP_BASE__INST6_SEG4                       0
+#define ACP_BASE__INST6_SEG5                       0
+
+#define ATHUB_BASE__INST0_SEG0                     0x00000C00
+#define ATHUB_BASE__INST0_SEG1                     0x00013300
+#define ATHUB_BASE__INST0_SEG2                     0x02408C00
+#define ATHUB_BASE__INST0_SEG3                     0
+#define ATHUB_BASE__INST0_SEG4                     0
+#define ATHUB_BASE__INST0_SEG5                     0
+
+#define ATHUB_BASE__INST1_SEG0                     0
+#define ATHUB_BASE__INST1_SEG1                     0
+#define ATHUB_BASE__INST1_SEG2                     0
+#define ATHUB_BASE__INST1_SEG3                     0
+#define ATHUB_BASE__INST1_SEG4                     0
+#define ATHUB_BASE__INST1_SEG5                     0
+
+#define ATHUB_BASE__INST2_SEG0                     0
+#define ATHUB_BASE__INST2_SEG1                     0
+#define ATHUB_BASE__INST2_SEG2                     0
+#define ATHUB_BASE__INST2_SEG3                     0
+#define ATHUB_BASE__INST2_SEG4                     0
+#define ATHUB_BASE__INST2_SEG5                     0
+
+#define ATHUB_BASE__INST3_SEG0                     0
+#define ATHUB_BASE__INST3_SEG1                     0
+#define ATHUB_BASE__INST3_SEG2                     0
+#define ATHUB_BASE__INST3_SEG3                     0
+#define ATHUB_BASE__INST3_SEG4                     0
+#define ATHUB_BASE__INST3_SEG5                     0
+
+#define ATHUB_BASE__INST4_SEG0                     0
+#define ATHUB_BASE__INST4_SEG1                     0
+#define ATHUB_BASE__INST4_SEG2                     0
+#define ATHUB_BASE__INST4_SEG3                     0
+#define ATHUB_BASE__INST4_SEG4                     0
+#define ATHUB_BASE__INST4_SEG5                     0
+
+#define ATHUB_BASE__INST5_SEG0                     0
+#define ATHUB_BASE__INST5_SEG1                     0
+#define ATHUB_BASE__INST5_SEG2                     0
+#define ATHUB_BASE__INST5_SEG3                     0
+#define ATHUB_BASE__INST5_SEG4                     0
+#define ATHUB_BASE__INST5_SEG5                     0
+
+#define ATHUB_BASE__INST6_SEG0                     0
+#define ATHUB_BASE__INST6_SEG1                     0
+#define ATHUB_BASE__INST6_SEG2                     0
+#define ATHUB_BASE__INST6_SEG3                     0
+#define ATHUB_BASE__INST6_SEG4                     0
+#define ATHUB_BASE__INST6_SEG5                     0
+
+#define CLK_BASE__INST0_SEG0                       0x00016C00
+#define CLK_BASE__INST0_SEG1                       0x02401800
+#define CLK_BASE__INST0_SEG2                       0
+#define CLK_BASE__INST0_SEG3                       0
+#define CLK_BASE__INST0_SEG4                       0
+#define CLK_BASE__INST0_SEG5                       0
+
+#define CLK_BASE__INST1_SEG0                       0x00016E00
+#define CLK_BASE__INST1_SEG1                       0x02401C00
+#define CLK_BASE__INST1_SEG2                       0
+#define CLK_BASE__INST1_SEG3                       0
+#define CLK_BASE__INST1_SEG4                       0
+#define CLK_BASE__INST1_SEG5                       0
+
+#define CLK_BASE__INST2_SEG0                       0x00017000
+#define CLK_BASE__INST2_SEG1                       0x02402000
+#define CLK_BASE__INST2_SEG2                       0
+#define CLK_BASE__INST2_SEG3                       0
+#define CLK_BASE__INST2_SEG4                       0
+#define CLK_BASE__INST2_SEG5                       0
+
+#define CLK_BASE__INST3_SEG0                       0x00017200
+#define CLK_BASE__INST3_SEG1                       0x02402400
+#define CLK_BASE__INST3_SEG2                       0
+#define CLK_BASE__INST3_SEG3                       0
+#define CLK_BASE__INST3_SEG4                       0
+#define CLK_BASE__INST3_SEG5                       0
+
+#define CLK_BASE__INST4_SEG0                       0x0001B000
+#define CLK_BASE__INST4_SEG1                       0x0242D800
+#define CLK_BASE__INST4_SEG2                       0
+#define CLK_BASE__INST4_SEG3                       0
+#define CLK_BASE__INST4_SEG4                       0
+#define CLK_BASE__INST4_SEG5                       0
+
+#define CLK_BASE__INST5_SEG0                       0x0001B200
+#define CLK_BASE__INST5_SEG1                       0x0242DC00
+#define CLK_BASE__INST5_SEG2                       0
+#define CLK_BASE__INST5_SEG3                       0
+#define CLK_BASE__INST5_SEG4                       0
+#define CLK_BASE__INST5_SEG5                       0
+
+#define CLK_BASE__INST6_SEG0                       0x0001B400
+#define CLK_BASE__INST6_SEG1                       0x0242E000
+#define CLK_BASE__INST6_SEG2                       0
+#define CLK_BASE__INST6_SEG3                       0
+#define CLK_BASE__INST6_SEG4                       0
+#define CLK_BASE__INST6_SEG5                       0
+
+#define DBGU_IO_BASE__INST0_SEG0                   0x000001E0
+#define DBGU_IO_BASE__INST0_SEG1                   0x00000260
+#define DBGU_IO_BASE__INST0_SEG2                   0x00000280
+#define DBGU_IO_BASE__INST0_SEG3                   0x0240B400
+#define DBGU_IO_BASE__INST0_SEG4                   0x02413C00
+#define DBGU_IO_BASE__INST0_SEG5                   0x02416000
+
+#define DBGU_IO_BASE__INST1_SEG0                   0
+#define DBGU_IO_BASE__INST1_SEG1                   0
+#define DBGU_IO_BASE__INST1_SEG2                   0
+#define DBGU_IO_BASE__INST1_SEG3                   0
+#define DBGU_IO_BASE__INST1_SEG4                   0
+#define DBGU_IO_BASE__INST1_SEG5                   0
+
+#define DBGU_IO_BASE__INST2_SEG0                   0
+#define DBGU_IO_BASE__INST2_SEG1                   0
+#define DBGU_IO_BASE__INST2_SEG2                   0
+#define DBGU_IO_BASE__INST2_SEG3                   0
+#define DBGU_IO_BASE__INST2_SEG4                   0
+#define DBGU_IO_BASE__INST2_SEG5                   0
+
+#define DBGU_IO_BASE__INST3_SEG0                   0
+#define DBGU_IO_BASE__INST3_SEG1                   0
+#define DBGU_IO_BASE__INST3_SEG2                   0
+#define DBGU_IO_BASE__INST3_SEG3                   0
+#define DBGU_IO_BASE__INST3_SEG4                   0
+#define DBGU_IO_BASE__INST3_SEG5                   0
+
+#define DBGU_IO_BASE__INST4_SEG0                   0
+#define DBGU_IO_BASE__INST4_SEG1                   0
+#define DBGU_IO_BASE__INST4_SEG2                   0
+#define DBGU_IO_BASE__INST4_SEG3                   0
+#define DBGU_IO_BASE__INST4_SEG4                   0
+#define DBGU_IO_BASE__INST4_SEG5                   0
+
+#define DBGU_IO_BASE__INST5_SEG0                   0
+#define DBGU_IO_BASE__INST5_SEG1                   0
+#define DBGU_IO_BASE__INST5_SEG2                   0
+#define DBGU_IO_BASE__INST5_SEG3                   0
+#define DBGU_IO_BASE__INST5_SEG4                   0
+#define DBGU_IO_BASE__INST5_SEG5                   0
+
+#define DBGU_IO_BASE__INST6_SEG0                   0
+#define DBGU_IO_BASE__INST6_SEG1                   0
+#define DBGU_IO_BASE__INST6_SEG2                   0
+#define DBGU_IO_BASE__INST6_SEG3                   0
+#define DBGU_IO_BASE__INST6_SEG4                   0
+#define DBGU_IO_BASE__INST6_SEG5                   0
+
+#define DCN_BASE__INST0_SEG0                       0x00000012
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define DCN_BASE__INST0_SEG4                       0x02403C00
+#define DCN_BASE__INST0_SEG5                       0
+
+#define DCN_BASE__INST1_SEG0                       0
+#define DCN_BASE__INST1_SEG1                       0
+#define DCN_BASE__INST1_SEG2                       0
+#define DCN_BASE__INST1_SEG3                       0
+#define DCN_BASE__INST1_SEG4                       0
+#define DCN_BASE__INST1_SEG5                       0
+
+#define DCN_BASE__INST2_SEG0                       0
+#define DCN_BASE__INST2_SEG1                       0
+#define DCN_BASE__INST2_SEG2                       0
+#define DCN_BASE__INST2_SEG3                       0
+#define DCN_BASE__INST2_SEG4                       0
+#define DCN_BASE__INST2_SEG5                       0
+
+#define DCN_BASE__INST3_SEG0                       0
+#define DCN_BASE__INST3_SEG1                       0
+#define DCN_BASE__INST3_SEG2                       0
+#define DCN_BASE__INST3_SEG3                       0
+#define DCN_BASE__INST3_SEG4                       0
+#define DCN_BASE__INST3_SEG5                       0
+
+#define DCN_BASE__INST4_SEG0                       0
+#define DCN_BASE__INST4_SEG1                       0
+#define DCN_BASE__INST4_SEG2                       0
+#define DCN_BASE__INST4_SEG3                       0
+#define DCN_BASE__INST4_SEG4                       0
+#define DCN_BASE__INST4_SEG5                       0
+
+#define DCN_BASE__INST5_SEG0                       0
+#define DCN_BASE__INST5_SEG1                       0
+#define DCN_BASE__INST5_SEG2                       0
+#define DCN_BASE__INST5_SEG3                       0
+#define DCN_BASE__INST5_SEG4                       0
+#define DCN_BASE__INST5_SEG5                       0
+
+#define DCN_BASE__INST6_SEG0                       0
+#define DCN_BASE__INST6_SEG1                       0
+#define DCN_BASE__INST6_SEG2                       0
+#define DCN_BASE__INST6_SEG3                       0
+#define DCN_BASE__INST6_SEG4                       0
+#define DCN_BASE__INST6_SEG5                       0
+
+#define DPCS_BASE__INST0_SEG0                      0x00000012
+#define DPCS_BASE__INST0_SEG1                      0x000000C0
+#define DPCS_BASE__INST0_SEG2                      0x000034C0
+#define DPCS_BASE__INST0_SEG3                      0x00009000
+#define DPCS_BASE__INST0_SEG4                      0x02403C00
+#define DPCS_BASE__INST0_SEG5                      0
+
+#define DPCS_BASE__INST1_SEG0                      0
+#define DPCS_BASE__INST1_SEG1                      0
+#define DPCS_BASE__INST1_SEG2                      0
+#define DPCS_BASE__INST1_SEG3                      0
+#define DPCS_BASE__INST1_SEG4                      0
+#define DPCS_BASE__INST1_SEG5                      0
+
+#define DPCS_BASE__INST2_SEG0                      0
+#define DPCS_BASE__INST2_SEG1                      0
+#define DPCS_BASE__INST2_SEG2                      0
+#define DPCS_BASE__INST2_SEG3                      0
+#define DPCS_BASE__INST2_SEG4                      0
+#define DPCS_BASE__INST2_SEG5                      0
+
+#define DPCS_BASE__INST3_SEG0                      0
+#define DPCS_BASE__INST3_SEG1                      0
+#define DPCS_BASE__INST3_SEG2                      0
+#define DPCS_BASE__INST3_SEG3                      0
+#define DPCS_BASE__INST3_SEG4                      0
+#define DPCS_BASE__INST3_SEG5                      0
+
+#define DPCS_BASE__INST4_SEG0                      0
+#define DPCS_BASE__INST4_SEG1                      0
+#define DPCS_BASE__INST4_SEG2                      0
+#define DPCS_BASE__INST4_SEG3                      0
+#define DPCS_BASE__INST4_SEG4                      0
+#define DPCS_BASE__INST4_SEG5                      0
+
+#define DPCS_BASE__INST5_SEG0                      0
+#define DPCS_BASE__INST5_SEG1                      0
+#define DPCS_BASE__INST5_SEG2                      0
+#define DPCS_BASE__INST5_SEG3                      0
+#define DPCS_BASE__INST5_SEG4                      0
+#define DPCS_BASE__INST5_SEG5                      0
+
+#define DPCS_BASE__INST6_SEG0                      0
+#define DPCS_BASE__INST6_SEG1                      0
+#define DPCS_BASE__INST6_SEG2                      0
+#define DPCS_BASE__INST6_SEG3                      0
+#define DPCS_BASE__INST6_SEG4                      0
+#define DPCS_BASE__INST6_SEG5                      0
+
+#define DF_BASE__INST0_SEG0                        0x00007000
+#define DF_BASE__INST0_SEG1                        0x0240B800
+#define DF_BASE__INST0_SEG2                        0x02447800
+#define DF_BASE__INST0_SEG3                        0x00C00000
+#define DF_BASE__INST0_SEG4                        0x03640000
+#define DF_BASE__INST0_SEG5                        0
+
+#define DF_BASE__INST1_SEG0                        0
+#define DF_BASE__INST1_SEG1                        0
+#define DF_BASE__INST1_SEG2                        0
+#define DF_BASE__INST1_SEG3                        0
+#define DF_BASE__INST1_SEG4                        0
+#define DF_BASE__INST1_SEG5                        0
+
+#define DF_BASE__INST2_SEG0                        0
+#define DF_BASE__INST2_SEG1                        0
+#define DF_BASE__INST2_SEG2                        0
+#define DF_BASE__INST2_SEG3                        0
+#define DF_BASE__INST2_SEG4                        0
+#define DF_BASE__INST2_SEG5                        0
+
+#define DF_BASE__INST3_SEG0                        0
+#define DF_BASE__INST3_SEG1                        0
+#define DF_BASE__INST3_SEG2                        0
+#define DF_BASE__INST3_SEG3                        0
+#define DF_BASE__INST3_SEG4                        0
+#define DF_BASE__INST3_SEG5                        0
+
+#define DF_BASE__INST4_SEG0                        0
+#define DF_BASE__INST4_SEG1                        0
+#define DF_BASE__INST4_SEG2                        0
+#define DF_BASE__INST4_SEG3                        0
+#define DF_BASE__INST4_SEG4                        0
+#define DF_BASE__INST4_SEG5                        0
+
+#define DF_BASE__INST5_SEG0                        0
+#define DF_BASE__INST5_SEG1                        0
+#define DF_BASE__INST5_SEG2                        0
+#define DF_BASE__INST5_SEG3                        0
+#define DF_BASE__INST5_SEG4                        0
+#define DF_BASE__INST5_SEG5                        0
+
+#define DF_BASE__INST6_SEG0                        0
+#define DF_BASE__INST6_SEG1                        0
+#define DF_BASE__INST6_SEG2                        0
+#define DF_BASE__INST6_SEG3                        0
+#define DF_BASE__INST6_SEG4                        0
+#define DF_BASE__INST6_SEG5                        0
+
+#define FCH_BASE__INST0_SEG0                       0x0240C000
+#define FCH_BASE__INST0_SEG1                       0x00B40000
+#define FCH_BASE__INST0_SEG2                       0x11000000
+#define FCH_BASE__INST0_SEG3                       0
+#define FCH_BASE__INST0_SEG4                       0
+#define FCH_BASE__INST0_SEG5                       0
+
+#define FCH_BASE__INST1_SEG0                       0
+#define FCH_BASE__INST1_SEG1                       0
+#define FCH_BASE__INST1_SEG2                       0
+#define FCH_BASE__INST1_SEG3                       0
+#define FCH_BASE__INST1_SEG4                       0
+#define FCH_BASE__INST1_SEG5                       0
+
+#define FCH_BASE__INST2_SEG0                       0
+#define FCH_BASE__INST2_SEG1                       0
+#define FCH_BASE__INST2_SEG2                       0
+#define FCH_BASE__INST2_SEG3                       0
+#define FCH_BASE__INST2_SEG4                       0
+#define FCH_BASE__INST2_SEG5                       0
+
+#define FCH_BASE__INST3_SEG0                       0
+#define FCH_BASE__INST3_SEG1                       0
+#define FCH_BASE__INST3_SEG2                       0
+#define FCH_BASE__INST3_SEG3                       0
+#define FCH_BASE__INST3_SEG4                       0
+#define FCH_BASE__INST3_SEG5                       0
+
+#define FCH_BASE__INST4_SEG0                       0
+#define FCH_BASE__INST4_SEG1                       0
+#define FCH_BASE__INST4_SEG2                       0
+#define FCH_BASE__INST4_SEG3                       0
+#define FCH_BASE__INST4_SEG4                       0
+#define FCH_BASE__INST4_SEG5                       0
+
+#define FCH_BASE__INST5_SEG0                       0
+#define FCH_BASE__INST5_SEG1                       0
+#define FCH_BASE__INST5_SEG2                       0
+#define FCH_BASE__INST5_SEG3                       0
+#define FCH_BASE__INST5_SEG4                       0
+#define FCH_BASE__INST5_SEG5                       0
+
+#define FCH_BASE__INST6_SEG0                       0
+#define FCH_BASE__INST6_SEG1                       0
+#define FCH_BASE__INST6_SEG2                       0
+#define FCH_BASE__INST6_SEG3                       0
+#define FCH_BASE__INST6_SEG4                       0
+#define FCH_BASE__INST6_SEG5                       0
+
+#define FUSE_BASE__INST0_SEG0                      0x00017400
+#define FUSE_BASE__INST0_SEG1                      0x02401400
+#define FUSE_BASE__INST0_SEG2                      0
+#define FUSE_BASE__INST0_SEG3                      0
+#define FUSE_BASE__INST0_SEG4                      0
+#define FUSE_BASE__INST0_SEG5                      0
+
+#define FUSE_BASE__INST1_SEG0                      0
+#define FUSE_BASE__INST1_SEG1                      0
+#define FUSE_BASE__INST1_SEG2                      0
+#define FUSE_BASE__INST1_SEG3                      0
+#define FUSE_BASE__INST1_SEG4                      0
+#define FUSE_BASE__INST1_SEG5                      0
+
+#define FUSE_BASE__INST2_SEG0                      0
+#define FUSE_BASE__INST2_SEG1                      0
+#define FUSE_BASE__INST2_SEG2                      0
+#define FUSE_BASE__INST2_SEG3                      0
+#define FUSE_BASE__INST2_SEG4                      0
+#define FUSE_BASE__INST2_SEG5                      0
+
+#define FUSE_BASE__INST3_SEG0                      0
+#define FUSE_BASE__INST3_SEG1                      0
+#define FUSE_BASE__INST3_SEG2                      0
+#define FUSE_BASE__INST3_SEG3                      0
+#define FUSE_BASE__INST3_SEG4                      0
+#define FUSE_BASE__INST3_SEG5                      0
+
+#define FUSE_BASE__INST4_SEG0                      0
+#define FUSE_BASE__INST4_SEG1                      0
+#define FUSE_BASE__INST4_SEG2                      0
+#define FUSE_BASE__INST4_SEG3                      0
+#define FUSE_BASE__INST4_SEG4                      0
+#define FUSE_BASE__INST4_SEG5                      0
+
+#define FUSE_BASE__INST5_SEG0                      0
+#define FUSE_BASE__INST5_SEG1                      0
+#define FUSE_BASE__INST5_SEG2                      0
+#define FUSE_BASE__INST5_SEG3                      0
+#define FUSE_BASE__INST5_SEG4                      0
+#define FUSE_BASE__INST5_SEG5                      0
+
+#define FUSE_BASE__INST6_SEG0                      0
+#define FUSE_BASE__INST6_SEG1                      0
+#define FUSE_BASE__INST6_SEG2                      0
+#define FUSE_BASE__INST6_SEG3                      0
+#define FUSE_BASE__INST6_SEG4                      0
+#define FUSE_BASE__INST6_SEG5                      0
+
+#define GC_BASE__INST0_SEG0                        0x00001260
+#define GC_BASE__INST0_SEG1                        0x0000A000
+#define GC_BASE__INST0_SEG2                        0x02402C00
+#define GC_BASE__INST0_SEG3                        0
+#define GC_BASE__INST0_SEG4                        0
+#define GC_BASE__INST0_SEG5                        0
+
+#define GC_BASE__INST1_SEG0                        0
+#define GC_BASE__INST1_SEG1                        0
+#define GC_BASE__INST1_SEG2                        0
+#define GC_BASE__INST1_SEG3                        0
+#define GC_BASE__INST1_SEG4                        0
+#define GC_BASE__INST1_SEG5                        0
+
+#define GC_BASE__INST2_SEG0                        0
+#define GC_BASE__INST2_SEG1                        0
+#define GC_BASE__INST2_SEG2                        0
+#define GC_BASE__INST2_SEG3                        0
+#define GC_BASE__INST2_SEG4                        0
+#define GC_BASE__INST2_SEG5                        0
+
+#define GC_BASE__INST3_SEG0                        0
+#define GC_BASE__INST3_SEG1                        0
+#define GC_BASE__INST3_SEG2                        0
+#define GC_BASE__INST3_SEG3                        0
+#define GC_BASE__INST3_SEG4                        0
+#define GC_BASE__INST3_SEG5                        0
+
+#define GC_BASE__INST4_SEG0                        0
+#define GC_BASE__INST4_SEG1                        0
+#define GC_BASE__INST4_SEG2                        0
+#define GC_BASE__INST4_SEG3                        0
+#define GC_BASE__INST4_SEG4                        0
+#define GC_BASE__INST4_SEG5                        0
+
+#define GC_BASE__INST5_SEG0                        0
+#define GC_BASE__INST5_SEG1                        0
+#define GC_BASE__INST5_SEG2                        0
+#define GC_BASE__INST5_SEG3                        0
+#define GC_BASE__INST5_SEG4                        0
+#define GC_BASE__INST5_SEG5                        0
+
+#define GC_BASE__INST6_SEG0                        0
+#define GC_BASE__INST6_SEG1                        0
+#define GC_BASE__INST6_SEG2                        0
+#define GC_BASE__INST6_SEG3                        0
+#define GC_BASE__INST6_SEG4                        0
+#define GC_BASE__INST6_SEG5                        0
+
+#define HDP_BASE__INST0_SEG0                       0x00000F20
+#define HDP_BASE__INST0_SEG1                       0x0240A400
+#define HDP_BASE__INST0_SEG2                       0
+#define HDP_BASE__INST0_SEG3                       0
+#define HDP_BASE__INST0_SEG4                       0
+#define HDP_BASE__INST0_SEG5                       0
+
+#define HDP_BASE__INST1_SEG0                       0
+#define HDP_BASE__INST1_SEG1                       0
+#define HDP_BASE__INST1_SEG2                       0
+#define HDP_BASE__INST1_SEG3                       0
+#define HDP_BASE__INST1_SEG4                       0
+#define HDP_BASE__INST1_SEG5                       0
+
+#define HDP_BASE__INST2_SEG0                       0
+#define HDP_BASE__INST2_SEG1                       0
+#define HDP_BASE__INST2_SEG2                       0
+#define HDP_BASE__INST2_SEG3                       0
+#define HDP_BASE__INST2_SEG4                       0
+#define HDP_BASE__INST2_SEG5                       0
+
+#define HDP_BASE__INST3_SEG0                       0
+#define HDP_BASE__INST3_SEG1                       0
+#define HDP_BASE__INST3_SEG2                       0
+#define HDP_BASE__INST3_SEG3                       0
+#define HDP_BASE__INST3_SEG4                       0
+#define HDP_BASE__INST3_SEG5                       0
+
+#define HDP_BASE__INST4_SEG0                       0
+#define HDP_BASE__INST4_SEG1                       0
+#define HDP_BASE__INST4_SEG2                       0
+#define HDP_BASE__INST4_SEG3                       0
+#define HDP_BASE__INST4_SEG4                       0
+#define HDP_BASE__INST4_SEG5                       0
+
+#define HDP_BASE__INST5_SEG0                       0
+#define HDP_BASE__INST5_SEG1                       0
+#define HDP_BASE__INST5_SEG2                       0
+#define HDP_BASE__INST5_SEG3                       0
+#define HDP_BASE__INST5_SEG4                       0
+#define HDP_BASE__INST5_SEG5                       0
+
+#define HDP_BASE__INST6_SEG0                       0
+#define HDP_BASE__INST6_SEG1                       0
+#define HDP_BASE__INST6_SEG2                       0
+#define HDP_BASE__INST6_SEG3                       0
+#define HDP_BASE__INST6_SEG4                       0
+#define HDP_BASE__INST6_SEG5                       0
+
+#define IOHC0_BASE__INST0_SEG0                     0x00010000
+#define IOHC0_BASE__INST0_SEG1                     0x02406000
+#define IOHC0_BASE__INST0_SEG2                     0x04EC0000
+#define IOHC0_BASE__INST0_SEG3                     0
+#define IOHC0_BASE__INST0_SEG4                     0
+#define IOHC0_BASE__INST0_SEG5                     0
+
+#define IOHC0_BASE__INST1_SEG0                     0
+#define IOHC0_BASE__INST1_SEG1                     0
+#define IOHC0_BASE__INST1_SEG2                     0
+#define IOHC0_BASE__INST1_SEG3                     0
+#define IOHC0_BASE__INST1_SEG4                     0
+#define IOHC0_BASE__INST1_SEG5                     0
+
+#define IOHC0_BASE__INST2_SEG0                     0
+#define IOHC0_BASE__INST2_SEG1                     0
+#define IOHC0_BASE__INST2_SEG2                     0
+#define IOHC0_BASE__INST2_SEG3                     0
+#define IOHC0_BASE__INST2_SEG4                     0
+#define IOHC0_BASE__INST2_SEG5                     0
+
+#define IOHC0_BASE__INST3_SEG0                     0
+#define IOHC0_BASE__INST3_SEG1                     0
+#define IOHC0_BASE__INST3_SEG2                     0
+#define IOHC0_BASE__INST3_SEG3                     0
+#define IOHC0_BASE__INST3_SEG4                     0
+#define IOHC0_BASE__INST3_SEG5                     0
+
+#define IOHC0_BASE__INST4_SEG0                     0
+#define IOHC0_BASE__INST4_SEG1                     0
+#define IOHC0_BASE__INST4_SEG2                     0
+#define IOHC0_BASE__INST4_SEG3                     0
+#define IOHC0_BASE__INST4_SEG4                     0
+#define IOHC0_BASE__INST4_SEG5                     0
+
+#define IOHC0_BASE__INST5_SEG0                     0
+#define IOHC0_BASE__INST5_SEG1                     0
+#define IOHC0_BASE__INST5_SEG2                     0
+#define IOHC0_BASE__INST5_SEG3                     0
+#define IOHC0_BASE__INST5_SEG4                     0
+#define IOHC0_BASE__INST5_SEG5                     0
+
+#define IOHC0_BASE__INST6_SEG0                     0
+#define IOHC0_BASE__INST6_SEG1                     0
+#define IOHC0_BASE__INST6_SEG2                     0
+#define IOHC0_BASE__INST6_SEG3                     0
+#define IOHC0_BASE__INST6_SEG4                     0
+#define IOHC0_BASE__INST6_SEG5                     0
+
+#define MMHUB_BASE__INST0_SEG0                     0x00013200
+#define MMHUB_BASE__INST0_SEG1                     0x0001A000
+#define MMHUB_BASE__INST0_SEG2                     0x02408800
+#define MMHUB_BASE__INST0_SEG3                     0
+#define MMHUB_BASE__INST0_SEG4                     0
+#define MMHUB_BASE__INST0_SEG5                     0
+
+#define MMHUB_BASE__INST1_SEG0                     0
+#define MMHUB_BASE__INST1_SEG1                     0
+#define MMHUB_BASE__INST1_SEG2                     0
+#define MMHUB_BASE__INST1_SEG3                     0
+#define MMHUB_BASE__INST1_SEG4                     0
+#define MMHUB_BASE__INST1_SEG5                     0
+
+#define MMHUB_BASE__INST2_SEG0                     0
+#define MMHUB_BASE__INST2_SEG1                     0
+#define MMHUB_BASE__INST2_SEG2                     0
+#define MMHUB_BASE__INST2_SEG3                     0
+#define MMHUB_BASE__INST2_SEG4                     0
+#define MMHUB_BASE__INST2_SEG5                     0
+
+#define MMHUB_BASE__INST3_SEG0                     0
+#define MMHUB_BASE__INST3_SEG1                     0
+#define MMHUB_BASE__INST3_SEG2                     0
+#define MMHUB_BASE__INST3_SEG3                     0
+#define MMHUB_BASE__INST3_SEG4                     0
+#define MMHUB_BASE__INST3_SEG5                     0
+
+#define MMHUB_BASE__INST4_SEG0                     0
+#define MMHUB_BASE__INST4_SEG1                     0
+#define MMHUB_BASE__INST4_SEG2                     0
+#define MMHUB_BASE__INST4_SEG3                     0
+#define MMHUB_BASE__INST4_SEG4                     0
+#define MMHUB_BASE__INST4_SEG5                     0
+
+#define MMHUB_BASE__INST5_SEG0                     0
+#define MMHUB_BASE__INST5_SEG1                     0
+#define MMHUB_BASE__INST5_SEG2                     0
+#define MMHUB_BASE__INST5_SEG3                     0
+#define MMHUB_BASE__INST5_SEG4                     0
+#define MMHUB_BASE__INST5_SEG5                     0
+
+#define MMHUB_BASE__INST6_SEG0                     0
+#define MMHUB_BASE__INST6_SEG1                     0
+#define MMHUB_BASE__INST6_SEG2                     0
+#define MMHUB_BASE__INST6_SEG3                     0
+#define MMHUB_BASE__INST6_SEG4                     0
+#define MMHUB_BASE__INST6_SEG5                     0
+
+#define MP0_BASE__INST0_SEG0                       0x00016000
+#define MP0_BASE__INST0_SEG1                       0x0243FC00
+#define MP0_BASE__INST0_SEG2                       0x00DC0000
+#define MP0_BASE__INST0_SEG3                       0x00E00000
+#define MP0_BASE__INST0_SEG4                       0x00E40000
+#define MP0_BASE__INST0_SEG5                       0
+
+#define MP0_BASE__INST1_SEG0                       0
+#define MP0_BASE__INST1_SEG1                       0
+#define MP0_BASE__INST1_SEG2                       0
+#define MP0_BASE__INST1_SEG3                       0
+#define MP0_BASE__INST1_SEG4                       0
+#define MP0_BASE__INST1_SEG5                       0
+
+#define MP0_BASE__INST2_SEG0                       0
+#define MP0_BASE__INST2_SEG1                       0
+#define MP0_BASE__INST2_SEG2                       0
+#define MP0_BASE__INST2_SEG3                       0
+#define MP0_BASE__INST2_SEG4                       0
+#define MP0_BASE__INST2_SEG5                       0
+
+#define MP0_BASE__INST3_SEG0                       0
+#define MP0_BASE__INST3_SEG1                       0
+#define MP0_BASE__INST3_SEG2                       0
+#define MP0_BASE__INST3_SEG3                       0
+#define MP0_BASE__INST3_SEG4                       0
+#define MP0_BASE__INST3_SEG5                       0
+
+#define MP0_BASE__INST4_SEG0                       0
+#define MP0_BASE__INST4_SEG1                       0
+#define MP0_BASE__INST4_SEG2                       0
+#define MP0_BASE__INST4_SEG3                       0
+#define MP0_BASE__INST4_SEG4                       0
+#define MP0_BASE__INST4_SEG5                       0
+
+#define MP0_BASE__INST5_SEG0                       0
+#define MP0_BASE__INST5_SEG1                       0
+#define MP0_BASE__INST5_SEG2                       0
+#define MP0_BASE__INST5_SEG3                       0
+#define MP0_BASE__INST5_SEG4                       0
+#define MP0_BASE__INST5_SEG5                       0
+
+#define MP0_BASE__INST6_SEG0                       0
+#define MP0_BASE__INST6_SEG1                       0
+#define MP0_BASE__INST6_SEG2                       0
+#define MP0_BASE__INST6_SEG3                       0
+#define MP0_BASE__INST6_SEG4                       0
+#define MP0_BASE__INST6_SEG5                       0
+
+#define MP1_BASE__INST0_SEG0                       0x00016000
+#define MP1_BASE__INST0_SEG1                       0x0243FC00
+#define MP1_BASE__INST0_SEG2                       0x00DC0000
+#define MP1_BASE__INST0_SEG3                       0x00E00000
+#define MP1_BASE__INST0_SEG4                       0x00E40000
+#define MP1_BASE__INST0_SEG5                       0
+
+#define MP1_BASE__INST1_SEG0                       0
+#define MP1_BASE__INST1_SEG1                       0
+#define MP1_BASE__INST1_SEG2                       0
+#define MP1_BASE__INST1_SEG3                       0
+#define MP1_BASE__INST1_SEG4                       0
+#define MP1_BASE__INST1_SEG5                       0
+
+#define MP1_BASE__INST2_SEG0                       0
+#define MP1_BASE__INST2_SEG1                       0
+#define MP1_BASE__INST2_SEG2                       0
+#define MP1_BASE__INST2_SEG3                       0
+#define MP1_BASE__INST2_SEG4                       0
+#define MP1_BASE__INST2_SEG5                       0
+
+#define MP1_BASE__INST3_SEG0                       0
+#define MP1_BASE__INST3_SEG1                       0
+#define MP1_BASE__INST3_SEG2                       0
+#define MP1_BASE__INST3_SEG3                       0
+#define MP1_BASE__INST3_SEG4                       0
+#define MP1_BASE__INST3_SEG5                       0
+
+#define MP1_BASE__INST4_SEG0                       0
+#define MP1_BASE__INST4_SEG1                       0
+#define MP1_BASE__INST4_SEG2                       0
+#define MP1_BASE__INST4_SEG3                       0
+#define MP1_BASE__INST4_SEG4                       0
+#define MP1_BASE__INST4_SEG5                       0
+
+#define MP1_BASE__INST5_SEG0                       0
+#define MP1_BASE__INST5_SEG1                       0
+#define MP1_BASE__INST5_SEG2                       0
+#define MP1_BASE__INST5_SEG3                       0
+#define MP1_BASE__INST5_SEG4                       0
+#define MP1_BASE__INST5_SEG5                       0
+
+#define MP1_BASE__INST6_SEG0                       0
+#define MP1_BASE__INST6_SEG1                       0
+#define MP1_BASE__INST6_SEG2                       0
+#define MP1_BASE__INST6_SEG3                       0
+#define MP1_BASE__INST6_SEG4                       0
+#define MP1_BASE__INST6_SEG5                       0
+
+#define MP2_BASE__INST0_SEG0                       0x00016000
+#define MP2_BASE__INST0_SEG1                       0x0243FC00
+#define MP2_BASE__INST0_SEG2                       0x00DC0000
+#define MP2_BASE__INST0_SEG3                       0x00E00000
+#define MP2_BASE__INST0_SEG4                       0x00E40000
+#define MP2_BASE__INST0_SEG5                       0
+
+#define MP2_BASE__INST1_SEG0                       0
+#define MP2_BASE__INST1_SEG1                       0
+#define MP2_BASE__INST1_SEG2                       0
+#define MP2_BASE__INST1_SEG3                       0
+#define MP2_BASE__INST1_SEG4                       0
+#define MP2_BASE__INST1_SEG5                       0
+
+#define MP2_BASE__INST2_SEG0                       0
+#define MP2_BASE__INST2_SEG1                       0
+#define MP2_BASE__INST2_SEG2                       0
+#define MP2_BASE__INST2_SEG3                       0
+#define MP2_BASE__INST2_SEG4                       0
+#define MP2_BASE__INST2_SEG5                       0
+
+#define MP2_BASE__INST3_SEG0                       0
+#define MP2_BASE__INST3_SEG1                       0
+#define MP2_BASE__INST3_SEG2                       0
+#define MP2_BASE__INST3_SEG3                       0
+#define MP2_BASE__INST3_SEG4                       0
+#define MP2_BASE__INST3_SEG5                       0
+
+#define MP2_BASE__INST4_SEG0                       0
+#define MP2_BASE__INST4_SEG1                       0
+#define MP2_BASE__INST4_SEG2                       0
+#define MP2_BASE__INST4_SEG3                       0
+#define MP2_BASE__INST4_SEG4                       0
+#define MP2_BASE__INST4_SEG5                       0
+
+#define MP2_BASE__INST5_SEG0                       0
+#define MP2_BASE__INST5_SEG1                       0
+#define MP2_BASE__INST5_SEG2                       0
+#define MP2_BASE__INST5_SEG3                       0
+#define MP2_BASE__INST5_SEG4                       0
+#define MP2_BASE__INST5_SEG5                       0
+
+#define MP2_BASE__INST6_SEG0                       0
+#define MP2_BASE__INST6_SEG1                       0
+#define MP2_BASE__INST6_SEG2                       0
+#define MP2_BASE__INST6_SEG3                       0
+#define MP2_BASE__INST6_SEG4                       0
+#define MP2_BASE__INST6_SEG5                       0
+
+#define NBIO_BASE__INST0_SEG0                      0x00000000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+#define NBIO_BASE__INST0_SEG2                      0x00000D20
+#define NBIO_BASE__INST0_SEG3                      0x00010400
+#define NBIO_BASE__INST0_SEG4                      0x0241B000
+#define NBIO_BASE__INST0_SEG5                      0x04040000
+
+#define NBIO_BASE__INST1_SEG0                      0
+#define NBIO_BASE__INST1_SEG1                      0
+#define NBIO_BASE__INST1_SEG2                      0
+#define NBIO_BASE__INST1_SEG3                      0
+#define NBIO_BASE__INST1_SEG4                      0
+#define NBIO_BASE__INST1_SEG5                      0
+
+#define NBIO_BASE__INST2_SEG0                      0
+#define NBIO_BASE__INST2_SEG1                      0
+#define NBIO_BASE__INST2_SEG2                      0
+#define NBIO_BASE__INST2_SEG3                      0
+#define NBIO_BASE__INST2_SEG4                      0
+#define NBIO_BASE__INST2_SEG5                      0
+
+#define NBIO_BASE__INST3_SEG0                      0
+#define NBIO_BASE__INST3_SEG1                      0
+#define NBIO_BASE__INST3_SEG2                      0
+#define NBIO_BASE__INST3_SEG3                      0
+#define NBIO_BASE__INST3_SEG4                      0
+#define NBIO_BASE__INST3_SEG5                      0
+
+#define NBIO_BASE__INST4_SEG0                      0
+#define NBIO_BASE__INST4_SEG1                      0
+#define NBIO_BASE__INST4_SEG2                      0
+#define NBIO_BASE__INST4_SEG3                      0
+#define NBIO_BASE__INST4_SEG4                      0
+#define NBIO_BASE__INST4_SEG5                      0
+
+#define NBIO_BASE__INST5_SEG0                      0
+#define NBIO_BASE__INST5_SEG1                      0
+#define NBIO_BASE__INST5_SEG2                      0
+#define NBIO_BASE__INST5_SEG3                      0
+#define NBIO_BASE__INST5_SEG4                      0
+#define NBIO_BASE__INST5_SEG5                      0
+
+#define NBIO_BASE__INST6_SEG0                      0
+#define NBIO_BASE__INST6_SEG1                      0
+#define NBIO_BASE__INST6_SEG2                      0
+#define NBIO_BASE__INST6_SEG3                      0
+#define NBIO_BASE__INST6_SEG4                      0
+#define NBIO_BASE__INST6_SEG5                      0
+
+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
+#define OSSSYS_BASE__INST0_SEG2                    0
+#define OSSSYS_BASE__INST0_SEG3                    0
+#define OSSSYS_BASE__INST0_SEG4                    0
+#define OSSSYS_BASE__INST0_SEG5                    0
+
+#define OSSSYS_BASE__INST1_SEG0                    0
+#define OSSSYS_BASE__INST1_SEG1                    0
+#define OSSSYS_BASE__INST1_SEG2                    0
+#define OSSSYS_BASE__INST1_SEG3                    0
+#define OSSSYS_BASE__INST1_SEG4                    0
+#define OSSSYS_BASE__INST1_SEG5                    0
+
+#define OSSSYS_BASE__INST2_SEG0                    0
+#define OSSSYS_BASE__INST2_SEG1                    0
+#define OSSSYS_BASE__INST2_SEG2                    0
+#define OSSSYS_BASE__INST2_SEG3                    0
+#define OSSSYS_BASE__INST2_SEG4                    0
+#define OSSSYS_BASE__INST2_SEG5                    0
+
+#define OSSSYS_BASE__INST3_SEG0                    0
+#define OSSSYS_BASE__INST3_SEG1                    0
+#define OSSSYS_BASE__INST3_SEG2                    0
+#define OSSSYS_BASE__INST3_SEG3                    0
+#define OSSSYS_BASE__INST3_SEG4                    0
+#define OSSSYS_BASE__INST3_SEG5                    0
+
+#define OSSSYS_BASE__INST4_SEG0                    0
+#define OSSSYS_BASE__INST4_SEG1                    0
+#define OSSSYS_BASE__INST4_SEG2                    0
+#define OSSSYS_BASE__INST4_SEG3                    0
+#define OSSSYS_BASE__INST4_SEG4                    0
+#define OSSSYS_BASE__INST4_SEG5                    0
+
+#define OSSSYS_BASE__INST5_SEG0                    0
+#define OSSSYS_BASE__INST5_SEG1                    0
+#define OSSSYS_BASE__INST5_SEG2                    0
+#define OSSSYS_BASE__INST5_SEG3                    0
+#define OSSSYS_BASE__INST5_SEG4                    0
+#define OSSSYS_BASE__INST5_SEG5                    0
+
+#define OSSSYS_BASE__INST6_SEG0                    0
+#define OSSSYS_BASE__INST6_SEG1                    0
+#define OSSSYS_BASE__INST6_SEG2                    0
+#define OSSSYS_BASE__INST6_SEG3                    0
+#define OSSSYS_BASE__INST6_SEG4                    0
+#define OSSSYS_BASE__INST6_SEG5                    0
+
+#define PCIE_BASE__INST0_SEG0                      0x02411800
+#define PCIE_BASE__INST0_SEG1                      0x04440000
+#define PCIE_BASE__INST0_SEG2                      0
+#define PCIE_BASE__INST0_SEG3                      0
+#define PCIE_BASE__INST0_SEG4                      0
+#define PCIE_BASE__INST0_SEG5                      0
+
+#define PCIE_BASE__INST1_SEG0                      0x02411C00
+#define PCIE_BASE__INST1_SEG1                      0x04480000
+#define PCIE_BASE__INST1_SEG2                      0
+#define PCIE_BASE__INST1_SEG3                      0
+#define PCIE_BASE__INST1_SEG4                      0
+#define PCIE_BASE__INST1_SEG5                      0
+
+#define PCIE_BASE__INST2_SEG0                      0x02412000
+#define PCIE_BASE__INST2_SEG1                      0x044C0000
+#define PCIE_BASE__INST2_SEG2                      0
+#define PCIE_BASE__INST2_SEG3                      0
+#define PCIE_BASE__INST2_SEG4                      0
+#define PCIE_BASE__INST2_SEG5                      0
+
+#define PCIE_BASE__INST3_SEG0                      0x02412400
+#define PCIE_BASE__INST3_SEG1                      0x04500000
+#define PCIE_BASE__INST3_SEG2                      0
+#define PCIE_BASE__INST3_SEG3                      0
+#define PCIE_BASE__INST3_SEG4                      0
+#define PCIE_BASE__INST3_SEG5                      0
+
+#define PCIE_BASE__INST4_SEG0                      0
+#define PCIE_BASE__INST4_SEG1                      0
+#define PCIE_BASE__INST4_SEG2                      0
+#define PCIE_BASE__INST4_SEG3                      0
+#define PCIE_BASE__INST4_SEG4                      0
+#define PCIE_BASE__INST4_SEG5                      0
+
+#define PCIE_BASE__INST5_SEG0                      0
+#define PCIE_BASE__INST5_SEG1                      0
+#define PCIE_BASE__INST5_SEG2                      0
+#define PCIE_BASE__INST5_SEG3                      0
+#define PCIE_BASE__INST5_SEG4                      0
+#define PCIE_BASE__INST5_SEG5                      0
+
+#define PCIE_BASE__INST6_SEG0                      0
+#define PCIE_BASE__INST6_SEG1                      0
+#define PCIE_BASE__INST6_SEG2                      0
+#define PCIE_BASE__INST6_SEG3                      0
+#define PCIE_BASE__INST6_SEG4                      0
+#define PCIE_BASE__INST6_SEG5                      0
+
+#define SDMA0_BASE__INST0_SEG0                     0x00001260
+#define SDMA0_BASE__INST0_SEG1                     0x0000A000
+#define SDMA0_BASE__INST0_SEG2                     0x02402C00
+#define SDMA0_BASE__INST0_SEG3                     0
+#define SDMA0_BASE__INST0_SEG4                     0
+#define SDMA0_BASE__INST0_SEG5                     0
+
+#define SDMA0_BASE__INST1_SEG0                     0
+#define SDMA0_BASE__INST1_SEG1                     0
+#define SDMA0_BASE__INST1_SEG2                     0
+#define SDMA0_BASE__INST1_SEG3                     0
+#define SDMA0_BASE__INST1_SEG4                     0
+#define SDMA0_BASE__INST1_SEG5                     0
+
+#define SDMA0_BASE__INST2_SEG0                     0
+#define SDMA0_BASE__INST2_SEG1                     0
+#define SDMA0_BASE__INST2_SEG2                     0
+#define SDMA0_BASE__INST2_SEG3                     0
+#define SDMA0_BASE__INST2_SEG4                     0
+#define SDMA0_BASE__INST2_SEG5                     0
+
+#define SDMA0_BASE__INST3_SEG0                     0
+#define SDMA0_BASE__INST3_SEG1                     0
+#define SDMA0_BASE__INST3_SEG2                     0
+#define SDMA0_BASE__INST3_SEG3                     0
+#define SDMA0_BASE__INST3_SEG4                     0
+#define SDMA0_BASE__INST3_SEG5                     0
+
+#define SDMA0_BASE__INST4_SEG0                     0
+#define SDMA0_BASE__INST4_SEG1                     0
+#define SDMA0_BASE__INST4_SEG2                     0
+#define SDMA0_BASE__INST4_SEG3                     0
+#define SDMA0_BASE__INST4_SEG4                     0
+#define SDMA0_BASE__INST4_SEG5                     0
+
+#define SDMA0_BASE__INST5_SEG0                     0
+#define SDMA0_BASE__INST5_SEG1                     0
+#define SDMA0_BASE__INST5_SEG2                     0
+#define SDMA0_BASE__INST5_SEG3                     0
+#define SDMA0_BASE__INST5_SEG4                     0
+#define SDMA0_BASE__INST5_SEG5                     0
+
+#define SDMA0_BASE__INST6_SEG0                     0
+#define SDMA0_BASE__INST6_SEG1                     0
+#define SDMA0_BASE__INST6_SEG2                     0
+#define SDMA0_BASE__INST6_SEG3                     0
+#define SDMA0_BASE__INST6_SEG4                     0
+#define SDMA0_BASE__INST6_SEG5                     0
+
+#define SMUIO_BASE__INST0_SEG0                     0x00016800
+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
+#define SMUIO_BASE__INST0_SEG2                     0x02401000
+#define SMUIO_BASE__INST0_SEG3                     0x00440000
+#define SMUIO_BASE__INST0_SEG4                     0
+#define SMUIO_BASE__INST0_SEG5                     0
+
+#define SMUIO_BASE__INST1_SEG0                     0x0001BC00
+#define SMUIO_BASE__INST1_SEG1                     0x0242D400
+#define SMUIO_BASE__INST1_SEG2                     0
+#define SMUIO_BASE__INST1_SEG3                     0
+#define SMUIO_BASE__INST1_SEG4                     0
+#define SMUIO_BASE__INST1_SEG5                     0
+
+#define SMUIO_BASE__INST2_SEG0                     0
+#define SMUIO_BASE__INST2_SEG1                     0
+#define SMUIO_BASE__INST2_SEG2                     0
+#define SMUIO_BASE__INST2_SEG3                     0
+#define SMUIO_BASE__INST2_SEG4                     0
+#define SMUIO_BASE__INST2_SEG5                     0
+
+#define SMUIO_BASE__INST3_SEG0                     0
+#define SMUIO_BASE__INST3_SEG1                     0
+#define SMUIO_BASE__INST3_SEG2                     0
+#define SMUIO_BASE__INST3_SEG3                     0
+#define SMUIO_BASE__INST3_SEG4                     0
+#define SMUIO_BASE__INST3_SEG5                     0
+
+#define SMUIO_BASE__INST4_SEG0                     0
+#define SMUIO_BASE__INST4_SEG1                     0
+#define SMUIO_BASE__INST4_SEG2                     0
+#define SMUIO_BASE__INST4_SEG3                     0
+#define SMUIO_BASE__INST4_SEG4                     0
+#define SMUIO_BASE__INST4_SEG5                     0
+
+#define SMUIO_BASE__INST5_SEG0                     0
+#define SMUIO_BASE__INST5_SEG1                     0
+#define SMUIO_BASE__INST5_SEG2                     0
+#define SMUIO_BASE__INST5_SEG3                     0
+#define SMUIO_BASE__INST5_SEG4                     0
+#define SMUIO_BASE__INST5_SEG5                     0
+
+#define SMUIO_BASE__INST6_SEG0                     0
+#define SMUIO_BASE__INST6_SEG1                     0
+#define SMUIO_BASE__INST6_SEG2                     0
+#define SMUIO_BASE__INST6_SEG3                     0
+#define SMUIO_BASE__INST6_SEG4                     0
+#define SMUIO_BASE__INST6_SEG5                     0
+
+#define THM_BASE__INST0_SEG0                       0x00016600
+#define THM_BASE__INST0_SEG1                       0x02400C00
+#define THM_BASE__INST0_SEG2                       0
+#define THM_BASE__INST0_SEG3                       0
+#define THM_BASE__INST0_SEG4                       0
+#define THM_BASE__INST0_SEG5                       0
+
+#define THM_BASE__INST1_SEG0                       0
+#define THM_BASE__INST1_SEG1                       0
+#define THM_BASE__INST1_SEG2                       0
+#define THM_BASE__INST1_SEG3                       0
+#define THM_BASE__INST1_SEG4                       0
+#define THM_BASE__INST1_SEG5                       0
+
+#define THM_BASE__INST2_SEG0                       0
+#define THM_BASE__INST2_SEG1                       0
+#define THM_BASE__INST2_SEG2                       0
+#define THM_BASE__INST2_SEG3                       0
+#define THM_BASE__INST2_SEG4                       0
+#define THM_BASE__INST2_SEG5                       0
+
+#define THM_BASE__INST3_SEG0                       0
+#define THM_BASE__INST3_SEG1                       0
+#define THM_BASE__INST3_SEG2                       0
+#define THM_BASE__INST3_SEG3                       0
+#define THM_BASE__INST3_SEG4                       0
+#define THM_BASE__INST3_SEG5                       0
+
+#define THM_BASE__INST4_SEG0                       0
+#define THM_BASE__INST4_SEG1                       0
+#define THM_BASE__INST4_SEG2                       0
+#define THM_BASE__INST4_SEG3                       0
+#define THM_BASE__INST4_SEG4                       0
+#define THM_BASE__INST4_SEG5                       0
+
+#define THM_BASE__INST5_SEG0                       0
+#define THM_BASE__INST5_SEG1                       0
+#define THM_BASE__INST5_SEG2                       0
+#define THM_BASE__INST5_SEG3                       0
+#define THM_BASE__INST5_SEG4                       0
+#define THM_BASE__INST5_SEG5                       0
+
+#define THM_BASE__INST6_SEG0                       0
+#define THM_BASE__INST6_SEG1                       0
+#define THM_BASE__INST6_SEG2                       0
+#define THM_BASE__INST6_SEG3                       0
+#define THM_BASE__INST6_SEG4                       0
+#define THM_BASE__INST6_SEG5                       0
+
+#define UMC_BASE__INST0_SEG0                       0x00014000
+#define UMC_BASE__INST0_SEG1                       0x00054000
+#define UMC_BASE__INST0_SEG2                       0x02425800
+#define UMC_BASE__INST0_SEG3                       0x02425C00
+#define UMC_BASE__INST0_SEG4                       0
+#define UMC_BASE__INST0_SEG5                       0
+
+#define UMC_BASE__INST1_SEG0                       0x00094000
+#define UMC_BASE__INST1_SEG1                       0x000D4000
+#define UMC_BASE__INST1_SEG2                       0x02426000
+#define UMC_BASE__INST1_SEG3                       0x02426400
+#define UMC_BASE__INST1_SEG4                       0
+#define UMC_BASE__INST1_SEG5                       0
+
+#define UMC_BASE__INST2_SEG0                       0
+#define UMC_BASE__INST2_SEG1                       0
+#define UMC_BASE__INST2_SEG2                       0
+#define UMC_BASE__INST2_SEG3                       0
+#define UMC_BASE__INST2_SEG4                       0
+#define UMC_BASE__INST2_SEG5                       0
+
+#define UMC_BASE__INST3_SEG0                       0
+#define UMC_BASE__INST3_SEG1                       0
+#define UMC_BASE__INST3_SEG2                       0
+#define UMC_BASE__INST3_SEG3                       0
+#define UMC_BASE__INST3_SEG4                       0
+#define UMC_BASE__INST3_SEG5                       0
+
+#define UMC_BASE__INST4_SEG0                       0
+#define UMC_BASE__INST4_SEG1                       0
+#define UMC_BASE__INST4_SEG2                       0
+#define UMC_BASE__INST4_SEG3                       0
+#define UMC_BASE__INST4_SEG4                       0
+#define UMC_BASE__INST4_SEG5                       0
+
+#define UMC_BASE__INST5_SEG0                       0
+#define UMC_BASE__INST5_SEG1                       0
+#define UMC_BASE__INST5_SEG2                       0
+#define UMC_BASE__INST5_SEG3                       0
+#define UMC_BASE__INST5_SEG4                       0
+#define UMC_BASE__INST5_SEG5                       0
+
+#define UMC_BASE__INST6_SEG0                       0
+#define UMC_BASE__INST6_SEG1                       0
+#define UMC_BASE__INST6_SEG2                       0
+#define UMC_BASE__INST6_SEG3                       0
+#define UMC_BASE__INST6_SEG4                       0
+#define UMC_BASE__INST6_SEG5                       0
+
+#define VCN_BASE__INST0_SEG0                       0x00007800
+#define VCN_BASE__INST0_SEG1                       0x00007E00
+#define VCN_BASE__INST0_SEG2                       0x02403000
+#define VCN_BASE__INST0_SEG3                       0
+#define VCN_BASE__INST0_SEG4                       0
+#define VCN_BASE__INST0_SEG5                       0
+
+#define VCN_BASE__INST1_SEG0                       0
+#define VCN_BASE__INST1_SEG1                       0
+#define VCN_BASE__INST1_SEG2                       0
+#define VCN_BASE__INST1_SEG3                       0
+#define VCN_BASE__INST1_SEG4                       0
+#define VCN_BASE__INST1_SEG5                       0
+
+#define VCN_BASE__INST2_SEG0                       0
+#define VCN_BASE__INST2_SEG1                       0
+#define VCN_BASE__INST2_SEG2                       0
+#define VCN_BASE__INST2_SEG3                       0
+#define VCN_BASE__INST2_SEG4                       0
+#define VCN_BASE__INST2_SEG5                       0
+
+#define VCN_BASE__INST3_SEG0                       0
+#define VCN_BASE__INST3_SEG1                       0
+#define VCN_BASE__INST3_SEG2                       0
+#define VCN_BASE__INST3_SEG3                       0
+#define VCN_BASE__INST3_SEG4                       0
+#define VCN_BASE__INST3_SEG5                       0
+
+#define VCN_BASE__INST4_SEG0                       0
+#define VCN_BASE__INST4_SEG1                       0
+#define VCN_BASE__INST4_SEG2                       0
+#define VCN_BASE__INST4_SEG3                       0
+#define VCN_BASE__INST4_SEG4                       0
+#define VCN_BASE__INST4_SEG5                       0
+
+#define VCN_BASE__INST5_SEG0                       0
+#define VCN_BASE__INST5_SEG1                       0
+#define VCN_BASE__INST5_SEG2                       0
+#define VCN_BASE__INST5_SEG3                       0
+#define VCN_BASE__INST5_SEG4                       0
+#define VCN_BASE__INST5_SEG5                       0
+
+#define VCN_BASE__INST6_SEG0                       0
+#define VCN_BASE__INST6_SEG1                       0
+#define VCN_BASE__INST6_SEG2                       0
+#define VCN_BASE__INST6_SEG3                       0
+#define VCN_BASE__INST6_SEG4                       0
+#define VCN_BASE__INST6_SEG5                       0
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 9a54066ec0af..a276ebad47e6 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -411,7 +411,8 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 	struct amdgpu_device *adev = drm_to_adev(ddev);
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 	struct pp_states_info data;
-	int i, buf_len, ret;
+	uint32_t i;
+	int buf_len, ret;
 
 	if (amdgpu_in_reset(adev))
 		return -EPERM;
@@ -433,9 +434,9 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 	pm_runtime_mark_last_busy(ddev->dev);
 	pm_runtime_put_autosuspend(ddev->dev);
 
-	buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
+	buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 	for (i = 0; i < data.nums; i++)
-		buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
+		buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 				(data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 				(data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 				(data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
@@ -735,6 +736,23 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
  * - a list of valid ranges for sclk, mclk, and voltage curve points
  *   labeled OD_RANGE
  *
+ * < For APUs >
+ *
+ * Reading the file will display:
+ *
+ * - minimum and maximum engine clock labeled OD_SCLK
+ *
+ * - a list of valid ranges for sclk labeled OD_RANGE
+ *
+ * < For VanGogh >
+ *
+ * Reading the file will display:
+ *
+ * - minimum and maximum engine clock labeled OD_SCLK
+ * - minimum and maximum core clocks labeled OD_CCLK
+ *
+ * - a list of valid ranges for sclk and cclk labeled OD_RANGE
+ *
  * To manually adjust these settings:
  *
  * - First select manual using power_dpm_force_performance_level
@@ -743,7 +761,10 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
  *   string that contains "s/m index clock" to the file. The index
  *   should be 0 if to set minimum clock. And 1 if to set maximum
  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
- *   "m 1 800" will update maximum mclk to be 800Mhz.
+ *   "m 1 800" will update maximum mclk to be 800Mhz. For core
+ *   clocks on VanGogh, the string contains "p core index clock".
+ *   E.g., "p 2 0 800" would set the minimum core clock on core
+ *   2 to 800Mhz.
  *
  *   For sclk voltage curve, enter the new values by writing a
  *   string that contains "vc point clock voltage" to the file. The
@@ -903,7 +924,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 		size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 		size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
 	} else {
-		size = snprintf(buf, PAGE_SIZE, "\n");
+		size = sysfs_emit(buf, "\n");
 	}
 	pm_runtime_mark_last_busy(ddev->dev);
 	pm_runtime_put_autosuspend(ddev->dev);
@@ -989,7 +1010,7 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
 	if (adev->powerplay.pp_funcs->get_ppfeature_status)
 		size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 	else
-		size = snprintf(buf, PAGE_SIZE, "\n");
+		size = sysfs_emit(buf, "\n");
 
 	pm_runtime_mark_last_busy(ddev->dev);
 	pm_runtime_put_autosuspend(ddev->dev);
@@ -1050,7 +1071,7 @@ static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
 	if (adev->powerplay.pp_funcs->print_clock_levels)
 		size = amdgpu_dpm_print_clock_levels(adev, type, buf);
 	else
-		size = snprintf(buf, PAGE_SIZE, "\n");
+		size = sysfs_emit(buf, "\n");
 
 	pm_runtime_mark_last_busy(ddev->dev);
 	pm_runtime_put_autosuspend(ddev->dev);
@@ -1449,7 +1470,7 @@ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 	if (adev->powerplay.pp_funcs->get_power_profile_mode)
 		size = amdgpu_dpm_get_power_profile_mode(adev, buf);
 	else
-		size = snprintf(buf, PAGE_SIZE, "\n");
+		size = sysfs_emit(buf, "\n");
 
 	pm_runtime_mark_last_busy(ddev->dev);
 	pm_runtime_put_autosuspend(ddev->dev);
@@ -1797,6 +1818,190 @@ out:
 	return size;
 }
 
+/**
+ * DOC: smartshift_apu_power
+ *
+ * The amdgpu driver provides a sysfs API for reporting APU power
+ * share if it supports smartshift. The value is expressed as
+ * the proportion of stapm limit where stapm limit is the total APU
+ * power limit. The result is in percentage. If APU power is 130% of
+ * STAPM, then APU is using 30% of the dGPU's headroom.
+ */
+
+static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
+					       char *buf)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = drm_to_adev(ddev);
+	uint32_t ss_power, size;
+	int r = 0;
+
+	if (amdgpu_in_reset(adev))
+		return -EPERM;
+	if (adev->in_suspend && !adev->in_runpm)
+		return -EPERM;
+
+	r = pm_runtime_get_sync(ddev->dev);
+	if (r < 0) {
+		pm_runtime_put_autosuspend(ddev->dev);
+		return r;
+	}
+
+	r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+				   (void *)&ss_power, &size);
+	if (r)
+		goto out;
+
+	r = sysfs_emit(buf, "%u%%\n", ss_power);
+
+out:
+	pm_runtime_mark_last_busy(ddev->dev);
+	pm_runtime_put_autosuspend(ddev->dev);
+	return r;
+}
+
+/**
+ * DOC: smartshift_dgpu_power
+ *
+ * The amdgpu driver provides a sysfs API for reporting the dGPU power
+ * share if the device is in HG and supports smartshift. The value
+ * is expressed as the proportion of stapm limit where stapm limit
+ * is the total APU power limit. The value is in percentage. If dGPU
+ * power is 20% higher than STAPM power(120%), it's using 20% of the
+ * APU's power headroom.
+ */
+
+static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
+						char *buf)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = drm_to_adev(ddev);
+	uint32_t ss_power, size;
+	int r = 0;
+
+	if (amdgpu_in_reset(adev))
+		return -EPERM;
+	if (adev->in_suspend && !adev->in_runpm)
+		return -EPERM;
+
+	r = pm_runtime_get_sync(ddev->dev);
+	if (r < 0) {
+		pm_runtime_put_autosuspend(ddev->dev);
+		return r;
+	}
+
+	r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+				   (void *)&ss_power, &size);
+
+	if (r)
+		goto out;
+
+	r = sysfs_emit(buf, "%u%%\n", ss_power);
+
+out:
+	pm_runtime_mark_last_busy(ddev->dev);
+	pm_runtime_put_autosuspend(ddev->dev);
+	return r;
+}
+
+/**
+ * DOC: smartshift_bias
+ *
+ * The amdgpu driver provides a sysfs API for reporting the
+ * smartshift(SS2.0) bias level. The value ranges from -100 to 100
+ * and the default is 0. -100 sets maximum preference to APU
+ * and 100 sets max perference to dGPU.
+ */
+
+static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
+					  struct device_attribute *attr,
+					  char *buf)
+{
+	int r = 0;
+
+	r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
+
+	return r;
+}
+
+static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
+					  struct device_attribute *attr,
+					  const char *buf, size_t count)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = drm_to_adev(ddev);
+	int r = 0;
+	int bias = 0;
+
+	if (amdgpu_in_reset(adev))
+		return -EPERM;
+	if (adev->in_suspend && !adev->in_runpm)
+		return -EPERM;
+
+	r = pm_runtime_get_sync(ddev->dev);
+	if (r < 0) {
+		pm_runtime_put_autosuspend(ddev->dev);
+		return r;
+	}
+
+	r = kstrtoint(buf, 10, &bias);
+	if (r)
+		goto out;
+
+	if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
+		bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
+	else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
+		bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
+
+	amdgpu_smartshift_bias = bias;
+	r = count;
+
+	/* TODO: upadte bias level with SMU message */
+
+out:
+	pm_runtime_mark_last_busy(ddev->dev);
+	pm_runtime_put_autosuspend(ddev->dev);
+	return r;
+}
+
+
+static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
+				uint32_t mask, enum amdgpu_device_attr_states *states)
+{
+	uint32_t ss_power, size;
+
+	if (!amdgpu_acpi_is_power_shift_control_supported())
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if ((adev->flags & AMD_IS_PX) &&
+		 !amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+
+	return 0;
+}
+
+static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
+			       uint32_t mask, enum amdgpu_device_attr_states *states)
+{
+	uint32_t ss_power, size;
+
+	if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+
+	return 0;
+}
+
 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
 	AMDGPU_DEVICE_ATTR_RW(power_dpm_state,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
 	AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
@@ -1823,6 +2028,12 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
 	AMDGPU_DEVICE_ATTR_RO(unique_id,				ATTR_FLAG_BASIC),
 	AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,		ATTR_FLAG_BASIC),
 	AMDGPU_DEVICE_ATTR_RO(gpu_metrics,				ATTR_FLAG_BASIC),
+	AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,			ATTR_FLAG_BASIC,
+			      .attr_update = ss_power_attr_update),
+	AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,			ATTR_FLAG_BASIC,
+			      .attr_update = ss_power_attr_update),
+	AMDGPU_DEVICE_ATTR_RW(smartshift_bias,				ATTR_FLAG_BASIC,
+			      .attr_update = ss_bias_attr_update),
 };
 
 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
@@ -1922,7 +2133,7 @@ static int amdgpu_device_attr_create(struct amdgpu_device *adev,
 
 	BUG_ON(!attr);
 
-	attr_update = attr->attr_update ? attr_update : default_attr_update;
+	attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
 
 	ret = attr_update(adev, attr, mask, &attr_states);
 	if (ret) {
@@ -2697,9 +2908,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-	int limit_type = to_sensor_dev_attr(attr)->index;
-	uint32_t limit = limit_type << 24;
-	uint32_t max_limit = 0;
+	enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+	enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_MAX;
+	uint32_t limit;
 	ssize_t size;
 	int r;
 
@@ -2714,16 +2925,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 		return r;
 	}
 
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, &max_limit, true);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000);
-	} else {
-		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
+					      pp_limit_level, power_type);
+	else
+		r = -ENODATA;
+
+	if (!r)
+		size = sysfs_emit(buf, "%u\n", limit * 1000000);
+	else
+		size = sysfs_emit(buf, "\n");
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2737,8 +2948,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-	int limit_type = to_sensor_dev_attr(attr)->index;
-	uint32_t limit = limit_type << 24;
+	enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+	enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_CURRENT;
+	uint32_t limit;
 	ssize_t size;
 	int r;
 
@@ -2753,16 +2965,16 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
 		return r;
 	}
 
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, NULL, false);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else {
-		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
+					      pp_limit_level, power_type);
+	else
+		r = -ENODATA;
+
+	if (!r)
+		size = sysfs_emit(buf, "%u\n", limit * 1000000);
+	else
+		size = sysfs_emit(buf, "\n");
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2776,8 +2988,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-	int limit_type = to_sensor_dev_attr(attr)->index;
-	uint32_t limit = limit_type << 24;
+	enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+	enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_DEFAULT;
+	uint32_t limit;
 	ssize_t size;
 	int r;
 
@@ -2792,16 +3005,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
 		return r;
 	}
 
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, NULL, true);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else {
-		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
+					      pp_limit_level, power_type);
+	else
+		r = -ENODATA;
+
+	if (!r)
+		size = sysfs_emit(buf, "%u\n", limit * 1000000);
+	else
+		size = sysfs_emit(buf, "\n");
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -3534,6 +3747,45 @@ out:
 
 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
 
+/*
+ * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
+ *
+ * Reads debug memory region allocated to PMFW
+ */
+static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
+					 size_t size, loff_t *pos)
+{
+	struct amdgpu_device *adev = file_inode(f)->i_private;
+	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+	void *pp_handle = adev->powerplay.pp_handle;
+	size_t smu_prv_buf_size;
+	void *smu_prv_buf;
+
+	if (amdgpu_in_reset(adev))
+		return -EPERM;
+	if (adev->in_suspend && !adev->in_runpm)
+		return -EPERM;
+
+	if (pp_funcs && pp_funcs->get_smu_prv_buf_details)
+		pp_funcs->get_smu_prv_buf_details(pp_handle, &smu_prv_buf,
+						  &smu_prv_buf_size);
+	else
+		return -ENOSYS;
+
+	if (!smu_prv_buf || !smu_prv_buf_size)
+		return -EINVAL;
+
+	return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
+				       smu_prv_buf_size);
+}
+
+static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.read = amdgpu_pm_prv_buffer_read,
+	.llseek = default_llseek,
+};
+
 #endif
 
 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
@@ -3545,5 +3797,10 @@ void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
 	debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
 			    &amdgpu_debugfs_pm_info_fops);
 
+	if (adev->pm.smu_prv_buffer_size > 0)
+		debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
+					 adev,
+					 &amdgpu_debugfs_pm_prv_buffer_fops,
+					 adev->pm.smu_prv_buffer_size);
 #endif
 }
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 8bb224f6c762..3e89852e4820 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -35,6 +35,48 @@
 
 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
 
+// Power Throttlers
+#define SMU_THROTTLER_PPT0_BIT			0
+#define SMU_THROTTLER_PPT1_BIT			1
+#define SMU_THROTTLER_PPT2_BIT			2
+#define SMU_THROTTLER_PPT3_BIT			3
+#define SMU_THROTTLER_SPL_BIT			4
+#define SMU_THROTTLER_FPPT_BIT			5
+#define SMU_THROTTLER_SPPT_BIT			6
+#define SMU_THROTTLER_SPPT_APU_BIT		7
+
+// Current Throttlers
+#define SMU_THROTTLER_TDC_GFX_BIT		16
+#define SMU_THROTTLER_TDC_SOC_BIT		17
+#define SMU_THROTTLER_TDC_MEM_BIT		18
+#define SMU_THROTTLER_TDC_VDD_BIT		19
+#define SMU_THROTTLER_TDC_CVIP_BIT		20
+#define SMU_THROTTLER_EDC_CPU_BIT		21
+#define SMU_THROTTLER_EDC_GFX_BIT		22
+#define SMU_THROTTLER_APCC_BIT			23
+
+// Temperature
+#define SMU_THROTTLER_TEMP_GPU_BIT		32
+#define SMU_THROTTLER_TEMP_CORE_BIT		33
+#define SMU_THROTTLER_TEMP_MEM_BIT		34
+#define SMU_THROTTLER_TEMP_EDGE_BIT		35
+#define SMU_THROTTLER_TEMP_HOTSPOT_BIT		36
+#define SMU_THROTTLER_TEMP_SOC_BIT		37
+#define SMU_THROTTLER_TEMP_VR_GFX_BIT		38
+#define SMU_THROTTLER_TEMP_VR_SOC_BIT		39
+#define SMU_THROTTLER_TEMP_VR_MEM0_BIT		40
+#define SMU_THROTTLER_TEMP_VR_MEM1_BIT		41
+#define SMU_THROTTLER_TEMP_LIQUID0_BIT		42
+#define SMU_THROTTLER_TEMP_LIQUID1_BIT		43
+#define SMU_THROTTLER_VRHOT0_BIT		44
+#define SMU_THROTTLER_VRHOT1_BIT		45
+#define SMU_THROTTLER_PROCHOT_CPU_BIT		46
+#define SMU_THROTTLER_PROCHOT_GFX_BIT		47
+
+// Other
+#define SMU_THROTTLER_PPM_BIT			56
+#define SMU_THROTTLER_FIT_BIT			57
+
 struct smu_hw_power_state {
 	unsigned int magic;
 };
@@ -392,10 +434,18 @@ struct smu_baco_context
 	bool platform_support;
 };
 
+struct smu_freq_info {
+	uint32_t min;
+	uint32_t max;
+	uint32_t freq_level;
+};
+
 struct pstates_clk_freq {
 	uint32_t			min;
 	uint32_t			standard;
 	uint32_t			peak;
+	struct smu_freq_info		custom;
+	struct smu_freq_info		curr;
 };
 
 struct smu_umd_pstate_table {
@@ -715,7 +765,10 @@ struct pptable_funcs {
 	/**
 	 * @get_power_limit: Get the device's power limits.
 	 */
-	int (*get_power_limit)(struct smu_context *smu);
+	int (*get_power_limit)(struct smu_context *smu,
+			       uint32_t *current_power_limit,
+			       uint32_t *default_power_limit,
+			       uint32_t *max_power_limit);
 
 	/**
 	 * @get_ppt_limit: Get the device's ppt limits.
@@ -924,7 +977,9 @@ struct pptable_funcs {
 	 * @disable_all_features_with_exception: Disable all features with
 	 *                                       exception to those in &mask.
 	 */
-	int (*disable_all_features_with_exception)(struct smu_context *smu, enum smu_feature_mask mask);
+	int (*disable_all_features_with_exception)(struct smu_context *smu,
+						   bool no_hw_disablement,
+						   enum smu_feature_mask mask);
 
 	/**
 	 * @notify_display_change: Enable fast memory clock switching.
@@ -1177,6 +1232,12 @@ struct pptable_funcs {
 	 */
 	int (*wait_for_event)(struct smu_context *smu,
 			      enum smu_event_type event, uint64_t event_arg);
+
+	/**
+	 * @sned_hbm_bad_pages_num:  message SMU to update bad page number
+	 *										of SMUBUS table.
+	 */
+	int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
 };
 
 typedef enum {
@@ -1210,6 +1271,8 @@ typedef enum {
 	METRICS_CURR_FANSPEED,
 	METRICS_VOLTAGE_VDDSOC,
 	METRICS_VOLTAGE_VDDGFX,
+	METRICS_SS_APU_SHARE,
+	METRICS_SS_DGPU_SHARE,
 } MetricsMember_t;
 
 enum smu_cmn2asic_mapping_type {
@@ -1252,9 +1315,10 @@ enum smu_cmn2asic_mapping_type {
 	[profile] = {1, (workload)}
 
 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
-int smu_get_power_limit(struct smu_context *smu,
+int smu_get_power_limit(void *handle,
 			uint32_t *limit,
-			enum smu_ppt_limit_level limit_level);
+			enum pp_power_limit_level pp_limit_level,
+			enum pp_power_type pp_power_type);
 
 bool smu_mode1_reset_is_support(struct smu_context *smu);
 bool smu_mode2_reset_is_support(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index fa95147b5a63..61c87c39be80 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -129,8 +129,8 @@
 #define FEATURE_SMNCLK_DPM_BIT          47
 #define FEATURE_PERLINK_GMIDOWN_BIT     48
 #define FEATURE_GFX_EDC_BIT             49
-#define FEATURE_SPARE_50_BIT            50
-#define FEATURE_SPARE_51_BIT            51
+#define FEATURE_GFX_PER_PART_VMIN_BIT   50
+#define FEATURE_SMART_SHIFT_BIT         51
 #define FEATURE_SPARE_52_BIT            52
 #define FEATURE_SPARE_53_BIT            53
 #define FEATURE_SPARE_54_BIT            54
@@ -941,6 +941,367 @@ typedef struct {
 } PPTable_t;
 
 typedef struct {
+  // MAJOR SECTION: SKU PARAMETERS
+
+  uint32_t Version;
+
+  // SECTION: Feature Enablement
+  uint32_t FeaturesToRun[NUM_FEATURES / 32];
+
+  // SECTION: Infrastructure Limits
+  uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts
+  uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
+  uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT];  // Watts
+  uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT];  // Time constant of LPF in ms
+
+  uint16_t TdcLimit[TDC_THROTTLER_COUNT];             // Amps
+  uint16_t TdcLimitTau[TDC_THROTTLER_COUNT];          // Time constant of LPF in ms
+
+  uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius
+
+  uint32_t FitLimit;                // Failures in time (failures per million parts over the defined lifetime)
+
+  // SECTION: Power Configuration
+  uint8_t      TotalPowerConfig;    //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e
+  uint8_t      TotalPowerPadding[3];  
+
+  // SECTION: APCC Settings
+  uint32_t     ApccPlusResidencyLimit;
+
+  //SECTION: SMNCLK DPM
+  uint16_t       SmnclkDpmFreq        [NUM_SMNCLK_DPM_LEVELS];       // in MHz
+  uint16_t       SmnclkDpmVoltage     [NUM_SMNCLK_DPM_LEVELS];       // mV(Q2)
+
+  uint32_t       PaddingAPCC;
+  uint16_t       PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];  //In mV(Q2)
+  uint16_t       PaddingPerPartDroop;
+
+  // SECTION: Throttler settings
+  uint32_t ThrottlerControlMask;   // See Throtter masks defines
+
+  // SECTION: FW DSTATE Settings  
+  uint32_t FwDStateMask;           // See FW DState masks defines
+
+  // SECTION: ULV Settings
+  uint16_t  UlvVoltageOffsetSoc; // In mV(Q2)
+  uint16_t  UlvVoltageOffsetGfx; // In mV(Q2)
+
+  uint16_t     MinVoltageUlvGfx; // In mV(Q2)  Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 
+  uint16_t     MinVoltageUlvSoc; // In mV(Q2)  Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
+
+  uint16_t     SocLIVmin;
+  uint16_t     SocLIVminoffset;
+
+  uint8_t   GceaLinkMgrIdleThreshold;        //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events
+  uint8_t   paddingRlcUlvParams[3];
+
+  // SECTION: Voltage Control Parameters
+  uint16_t     MinVoltageGfx;     // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
+  uint16_t     MinVoltageSoc;     // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
+  uint16_t     MaxVoltageGfx;     // In mV(Q2) Maximum Voltage allowable of VDD_GFX
+  uint16_t     MaxVoltageSoc;     // In mV(Q2) Maximum Voltage allowable of VDD_SOC
+
+  uint16_t     LoadLineResistanceGfx;   // In mOhms with 8 fractional bits
+  uint16_t     LoadLineResistanceSoc;   // In mOhms with 8 fractional bits
+
+  // SECTION: Temperature Dependent Vmin
+  uint16_t     VDDGFX_TVmin;       //Celcius
+  uint16_t     VDDSOC_TVmin;       //Celcius
+  uint16_t     VDDGFX_Vmin_HiTemp; // mV Q2
+  uint16_t     VDDGFX_Vmin_LoTemp; // mV Q2
+  uint16_t     VDDSOC_Vmin_HiTemp; // mV Q2
+  uint16_t     VDDSOC_Vmin_LoTemp; // mV Q2
+
+  uint16_t     VDDGFX_TVminHystersis; // Celcius
+  uint16_t     VDDSOC_TVminHystersis; // Celcius
+
+  //SECTION: DPM Config 1
+  DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
+
+  uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];     // In MHz
+  uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];     // In MHz
+  uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];     // In MHz
+  uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];     // In MHz
+  uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];     // In MHz
+  uint16_t       FreqTableDcefclk  [NUM_DCEFCLK_DPM_LEVELS ];     // In MHz
+  uint16_t       FreqTableDispclk  [NUM_DISPCLK_DPM_LEVELS ];     // In MHz
+  uint16_t       FreqTablePixclk   [NUM_PIXCLK_DPM_LEVELS  ];     // In MHz
+  uint16_t       FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ];     // In MHz
+  uint16_t       FreqTableDtbclk   [NUM_DTBCLK_DPM_LEVELS  ];     // In MHz
+  uint16_t       FreqTableFclk     [NUM_FCLK_DPM_LEVELS    ];     // In MHz
+  uint32_t       Paddingclks;
+
+  DroopInt_t     PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format
+
+  uint32_t       DcModeMaxFreq     [PPCLK_COUNT            ];     // In MHz
+
+  uint8_t        FreqTableUclkDiv  [NUM_UCLK_DPM_LEVELS    ];     // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
+
+  // Used for MALL performance boost
+  uint16_t       FclkBoostFreq;                                   // In Mhz
+  uint16_t       FclkParamPadding;
+
+  // SECTION: DPM Config 2
+  uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];       // in MHz
+  uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];       // mV(Q2)
+  uint16_t       MemVddciVoltage   [NUM_UCLK_DPM_LEVELS];         // mV(Q2)
+  uint16_t       MemMvddVoltage    [NUM_UCLK_DPM_LEVELS];         // mV(Q2)
+  // GFXCLK DPM
+  uint16_t        GfxclkFgfxoffEntry;   // in Mhz
+  uint16_t        GfxclkFinit;          // in Mhz 
+  uint16_t        GfxclkFidle;          // in MHz 
+  uint8_t         GfxclkSource;         // 0 = PLL, 1 = DFLL
+  uint8_t         GfxclkPadding;
+
+  // GFX GPO 
+  uint8_t         GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM
+  uint8_t         GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled
+  uint8_t         GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled
+  uint8_t         GfxGpoPadding[1];
+  uint32_t        GfxGpoVotingAllow;    //For indicating which feature changes should result in a GPO table recalculation
+
+  uint32_t        GfxGpoPadding32[4];
+
+  uint16_t        GfxDcsFopt;           // Optimal GFXCLK for DCS in Mhz
+  uint16_t        GfxDcsFclkFopt;       // Optimal FCLK for DCS in Mhz
+  uint16_t        GfxDcsUclkFopt;       // Optimal UCLK for DCS in Mhz
+
+  uint16_t        DcsGfxOffVoltage;     //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase  
+
+  uint16_t        DcsMinGfxOffTime;     //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
+  uint16_t        DcsMaxGfxOffTime;      //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
+
+  uint32_t        DcsMinCreditAccum;    //Min amount of positive credit accumulation before waking GFX up as part of DCS.
+
+  uint16_t        DcsExitHysteresis;    //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 
+  uint16_t        DcsTimeout;           //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
+
+  uint32_t        DcsParamPadding[5];
+
+  uint16_t        FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8
+
+  // UCLK section
+  uint8_t      LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only
+  uint8_t      PaddingMem[3];
+
+  uint8_t      UclkDpmPstates     [NUM_UCLK_DPM_LEVELS];     // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
+
+  // Used for 2-Step UCLK change workaround
+  UclkDpmChangeRange_t UclkDpmSrcFreqRange;  // In Mhz
+  UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz
+  uint16_t UclkDpmMidstepFreq;               // In Mhz
+  uint16_t UclkMidstepPadding;
+
+  // Link DPM Settings
+  uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
+  uint8_t      PcieLaneCount[NUM_LINK_LEVELS];          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
+  uint16_t     LclkFreq[NUM_LINK_LEVELS];              
+
+  // SECTION: Fan Control
+  uint16_t     FanStopTemp;          //Celcius
+  uint16_t     FanStartTemp;         //Celcius
+
+  uint16_t     FanGain[TEMP_COUNT];
+
+  uint16_t     FanPwmMin;
+  uint16_t     FanAcousticLimitRpm;
+  uint16_t     FanThrottlingRpm;
+  uint16_t     FanMaximumRpm;
+  uint16_t     MGpuFanBoostLimitRpm;  
+  uint16_t     FanTargetTemperature;
+  uint16_t     FanTargetGfxclk;
+  uint16_t     FanPadding16;
+  uint8_t      FanTempInputSelect;
+  uint8_t      FanPadding;
+  uint8_t      FanZeroRpmEnable; 
+  uint8_t      FanTachEdgePerRev;
+
+  // The following are AFC override parameters. Leave at 0 to use FW defaults.
+  int16_t      FuzzyFan_ErrorSetDelta;
+  int16_t      FuzzyFan_ErrorRateSetDelta;
+  int16_t      FuzzyFan_PwmSetDelta;
+  uint16_t     FuzzyFan_Reserved;
+
+  // SECTION: AVFS 
+  // Overrides
+  uint8_t           OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
+  uint8_t           dBtcGbGfxDfllModelSelect;  //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)  
+  uint8_t           Padding8_Avfs;
+
+  QuadraticInt_t    qAvfsGb[AVFS_VOLTAGE_COUNT];              // GHz->V Override of fused curve 
+  DroopInt_t        dBtcGbGfxPll;         // GHz->V BtcGb
+  DroopInt_t        dBtcGbGfxDfll;        // GHz->V BtcGb
+  DroopInt_t        dBtcGbSoc;            // GHz->V BtcGb
+  LinearInt_t       qAgingGb[AVFS_VOLTAGE_COUNT];          // GHz->V 
+
+  PiecewiseLinearDroopInt_t   PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format
+
+  QuadraticInt_t    qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 
+
+  uint16_t          DcTol[AVFS_VOLTAGE_COUNT];            // mV Q2
+
+  uint8_t           DcBtcEnabled[AVFS_VOLTAGE_COUNT];
+  uint8_t           Padding8_GfxBtc[2];
+
+  uint16_t          DcBtcMin[AVFS_VOLTAGE_COUNT];       // mV Q2
+  uint16_t          DcBtcMax[AVFS_VOLTAGE_COUNT];       // mV Q2
+
+  uint16_t          DcBtcGb[AVFS_VOLTAGE_COUNT];       // mV Q2
+
+  // SECTION: XGMI
+  uint8_t           XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low.  0-P0, 1-P1, 2-P2, 3-P3.
+  uint8_t           XgmiDpmSpare[2];
+
+  // SECTION: Advanced Options
+  uint32_t          DebugOverrides;
+  QuadraticInt_t    ReservedEquation0;
+  QuadraticInt_t    ReservedEquation1;
+  QuadraticInt_t    ReservedEquation2;
+  QuadraticInt_t    ReservedEquation3;
+
+  // SECTION: Sku Reserved
+  uint8_t          CustomerVariant;
+
+    //VC BTC parameters are only applicable to VDD_GFX domain
+  uint8_t          VcBtcEnabled;
+  uint16_t         VcBtcVminT0;                 // T0_VMIN
+  uint16_t         VcBtcFixedVminAgingOffset;   // FIXED_VMIN_AGING_OFFSET 
+  uint16_t         VcBtcVmin2PsmDegrationGb;    // VMIN_TO_PSM_DEGRADATION_GB 
+  uint32_t         VcBtcPsmA;                   // A_PSM
+  uint32_t         VcBtcPsmB;                   // B_PSM
+  uint32_t         VcBtcVminA;                  // A_VMIN
+  uint32_t         VcBtcVminB;                  // B_VMIN  
+
+  //GPIO Board feature
+  uint16_t         LedGpio;            //GeneriA GPIO flag used to control the radeon LEDs
+  uint16_t         GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 
+
+  uint32_t         SkuReserved[63];
+
+
+
+  // MAJOR SECTION: BOARD PARAMETERS
+
+  //SECTION: Gaming Clocks
+  uint32_t     GamingClk[6];
+
+  // SECTION: I2C Control
+  I2cControllerConfig_t  I2cControllers[NUM_I2C_CONTROLLERS];     
+
+  uint8_t      GpioScl;  // GPIO Number for SCL Line, used only for CKSVII2C1
+  uint8_t      GpioSda;  // GPIO Number for SDA Line, used only for CKSVII2C1
+  uint8_t      FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
+  uint8_t      I2cSpare[1];
+
+  // SECTION: SVI2 Board Parameters
+  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
+  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
+  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
+  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
+
+  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+  uint8_t      VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+  uint8_t      MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+
+  // SECTION: Telemetry Settings
+  uint16_t     GfxMaxCurrent;   // in Amps
+  int8_t       GfxOffset;       // in Amps
+  uint8_t      Padding_TelemetryGfx;
+
+  uint16_t     SocMaxCurrent;   // in Amps
+  int8_t       SocOffset;       // in Amps
+  uint8_t      Padding_TelemetrySoc;
+
+  uint16_t     Mem0MaxCurrent;   // in Amps
+  int8_t       Mem0Offset;       // in Amps
+  uint8_t      Padding_TelemetryMem0;
+
+  uint16_t     Mem1MaxCurrent;   // in Amps
+  int8_t       Mem1Offset;       // in Amps
+  uint8_t      Padding_TelemetryMem1;
+
+  uint32_t     MvddRatio; // This is used for MVDD  Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
+
+  // SECTION: GPIO Settings
+  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
+  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
+  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
+  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
+
+  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event 
+  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event 
+  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
+  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
+
+  // LED Display Settings
+  uint8_t      LedPin0;         // GPIO number for LedPin[0]
+  uint8_t      LedPin1;         // GPIO number for LedPin[1]
+  uint8_t      LedPin2;         // GPIO number for LedPin[2]
+  uint8_t      LedEnableMask;
+
+  uint8_t      LedPcie;        // GPIO number for PCIE results
+  uint8_t      LedError;       // GPIO number for Error Cases
+  uint8_t      LedSpare1[2];
+
+  // SECTION: Clock Spread Spectrum
+
+  // GFXCLK PLL Spread Spectrum
+  uint8_t      PllGfxclkSpreadEnabled;   // on or off
+  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
+  uint16_t     PllGfxclkSpreadFreq;      // kHz
+
+  // GFXCLK DFLL Spread Spectrum
+  uint8_t      DfllGfxclkSpreadEnabled;   // on or off
+  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
+  uint16_t     DfllGfxclkSpreadFreq;      // kHz
+
+  // UCLK Spread Spectrum
+  uint16_t     UclkSpreadPadding;
+  uint16_t     UclkSpreadFreq;      // kHz
+
+  // FCLK Spread Spectrum
+  uint8_t      FclkSpreadEnabled;   // on or off
+  uint8_t      FclkSpreadPercent;   // Q4.4
+  uint16_t     FclkSpreadFreq;      // kHz
+
+  // Section: Memory Config
+  uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 
+
+  uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines
+  uint8_t      PaddingMem1[3];
+
+  // Section: Total Board Power
+  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
+  uint16_t     BoardPowerPadding; 
+
+  // SECTION: XGMI Training
+  uint8_t      XgmiLinkSpeed   [NUM_XGMI_PSTATE_LEVELS];
+  uint8_t      XgmiLinkWidth   [NUM_XGMI_PSTATE_LEVELS];
+
+  uint16_t     XgmiFclkFreq    [NUM_XGMI_PSTATE_LEVELS];
+  uint16_t     XgmiSocVoltage  [NUM_XGMI_PSTATE_LEVELS];
+
+  // SECTION: UMC feature flags
+  uint8_t      HsrEnabled;
+  uint8_t      VddqOffEnabled;
+  uint8_t      PaddingUmcFlags[2];
+
+  // UCLK Spread Spectrum
+  uint8_t      UclkSpreadPercent[16];   
+
+  // SECTION: Board Reserved
+  uint32_t     BoardReserved[11];
+
+  // SECTION: Structure Padding
+
+  // Padding for MMHUB - do not modify this
+  uint32_t     MmHubPadding[8]; // SMU internal use
+
+
+} PPTable_beige_goby_t;
+
+typedef struct {
   // Time constant parameters for clock averages in ms
   uint16_t     GfxclkAverageLpfTau;
   uint16_t     FclkAverageLpfTau;
@@ -1265,4 +1626,5 @@ typedef struct {
 // These defines are used with the SMC_MSG_SetUclkFastSwitch message.
 #define UCLK_SWITCH_SLOW 0
 #define UCLK_SWITCH_FAST 1
+#define UCLK_SWITCH_DUMMY 2
 #endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h
index d23533bda002..a017983ff1fa 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_aldebaran.h
@@ -64,7 +64,7 @@
 #define FEATURE_SMUIO_CG_BIT            28
 #define FEATURE_THM_CG_BIT              29
 #define FEATURE_CLK_CG_BIT              30
-#define FEATURE_SPARE_31_BIT            31
+#define FEATURE_EDC_BIT                 31
 #define FEATURE_SPARE_32_BIT            32
 #define FEATURE_SPARE_33_BIT            33
 #define FEATURE_SPARE_34_BIT            34
@@ -439,8 +439,11 @@ typedef struct {
   int8_t   XgmiOffset;     // in Amps
   uint8_t  Padding_TelemetryXgmi;
 
+  uint16_t  EdcPowerLimit;
+  uint16_t  spare6;
+
   //reserved
-  uint32_t reserved[15];
+  uint32_t reserved[14];
 
 } PPTable_t;
 
diff --git a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h
new file mode 100644
index 000000000000..25540cb28208
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU13_DRIVER_IF_YELLOW_CARP_H__
+#define __SMU13_DRIVER_IF_YELLOW_CARP_H__
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU13_DRIVER_IF_VERSION 4
+
+typedef struct {
+  int32_t value;
+  uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+  DSPCLK_DCFCLK = 0,
+  DSPCLK_DISPCLK,
+  DSPCLK_PIXCLK,
+  DSPCLK_PHYCLK,
+  DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+  uint16_t Freq; // in MHz
+  uint16_t Vid;  // min voltage in SVI3 VID
+} DisplayClockTable_t;
+
+typedef struct {
+  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MinMclk;
+  uint16_t MaxMclk;
+
+  uint8_t  WmSetting;
+  uint8_t  WmType;  // Used for normal pstate change or memory retraining
+  uint8_t  Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+  WM_SOCCLK = 0,
+  WM_DCFCLK,
+  WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+  uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+  CUSTOM_DPM_SETTING_GFXCLK,
+  CUSTOM_DPM_SETTING_CCLK,
+  CUSTOM_DPM_SETTING_FCLK_CCX,
+  CUSTOM_DPM_SETTING_FCLK_GFX,
+  CUSTOM_DPM_SETTING_FCLK_STALLS,
+  CUSTOM_DPM_SETTING_LCLK,
+  CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+  uint8_t             ActiveHystLimit;
+  uint8_t             IdleHystLimit;
+  uint8_t             FPS;
+  uint8_t             MinActiveFreqType;
+  FloatInIntFormat_t  MinActiveFreq;
+  FloatInIntFormat_t  PD_Data_limit;
+  FloatInIntFormat_t  PD_Data_time_constant;
+  FloatInIntFormat_t  PD_Data_error_coeff;
+  FloatInIntFormat_t  PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_DCFCLK_DPM_LEVELS   8
+#define NUM_DISPCLK_DPM_LEVELS  8
+#define NUM_DPPCLK_DPM_LEVELS   8
+#define NUM_SOCCLK_DPM_LEVELS   8
+#define NUM_VCN_DPM_LEVELS      8
+#define NUM_SOC_VOLTAGE_LEVELS  8
+#define NUM_DF_PSTATE_LEVELS    4
+
+typedef struct {
+  uint32_t FClk;
+  uint32_t MemClk;
+  uint32_t Voltage;
+  uint8_t  WckRatio;
+  uint8_t  Spare[3];
+} DfPstateTable_t;
+
+//Freq in MHz
+//Voltage in milli volts with 2 fractional bits
+typedef struct {
+  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+  uint32_t VClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t DClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+  DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
+
+  uint8_t  NumDcfClkLevelsEnabled;
+  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
+  uint8_t  NumSocClkLevelsEnabled;
+  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
+  uint8_t  NumDfPstatesEnabled;
+  uint8_t  spare[3];
+
+  uint32_t MinGfxClk;
+  uint32_t MaxGfxClk;
+} DpmClocks_t;
+
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL            0
+#define THROTTLER_STATUS_BIT_FPPT           1
+#define THROTTLER_STATUS_BIT_SPPT           2
+#define THROTTLER_STATUS_BIT_SPPT_APU       3
+#define THROTTLER_STATUS_BIT_THM_CORE       4
+#define THROTTLER_STATUS_BIT_THM_GFX        5
+#define THROTTLER_STATUS_BIT_THM_SOC        6
+#define THROTTLER_STATUS_BIT_TDC_VDD        7
+#define THROTTLER_STATUS_BIT_TDC_SOC        8
+#define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
+#define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
+#define THROTTLER_STATUS_BIT_EDC_CPU       11
+#define THROTTLER_STATUS_BIT_EDC_GFX       12
+
+typedef struct {
+  uint16_t GfxclkFrequency;             //[MHz]
+  uint16_t SocclkFrequency;             //[MHz]
+  uint16_t VclkFrequency;               //[MHz]
+  uint16_t DclkFrequency;               //[MHz]
+  uint16_t MemclkFrequency;             //[MHz]
+  uint16_t spare;
+
+  uint16_t GfxActivity;                 //[centi]
+  uint16_t UvdActivity;                 //[centi]
+
+  uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
+
+  //3rd party tools in Windows need this info in the case of APUs
+  uint16_t CoreFrequency[8];            //[MHz]
+  uint16_t CorePower[8];                //[mW]
+  uint16_t CoreTemperature[8];          //[centi-Celsius]
+  uint16_t L3Frequency;                 //[MHz]
+  uint16_t L3Temperature;               //[centi-Celsius]
+
+  uint16_t GfxTemperature;              //[centi-Celsius]
+  uint16_t SocTemperature;              //[centi-Celsius]
+  uint16_t ThrottlerStatus;
+
+  uint16_t CurrentSocketPower;          //[mW]
+  uint16_t StapmOpnLimit;               //[W]
+  uint16_t StapmCurrentLimit;           //[W]
+  uint32_t ApuPower;                    //[mW]
+  uint32_t dGpuPower;                   //[mW]
+
+  uint16_t VddTdcValue;                 //[mA]
+  uint16_t SocTdcValue;                 //[mA]
+  uint16_t VddEdcValue;                 //[mA]
+  uint16_t SocEdcValue;                 //[mA]
+
+  uint16_t InfrastructureCpuMaxFreq;    //[MHz]
+  uint16_t InfrastructureGfxMaxFreq;    //[MHz]
+
+  uint16_t SkinTemp;
+  uint16_t DeviceState;
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT          2
+#define WORKLOAD_PPLIB_VR_BIT             3
+#define WORKLOAD_PPLIB_COMPUTE_BIT        4
+#define WORKLOAD_PPLIB_CUSTOM_BIT         5
+#define WORKLOAD_PPLIB_COUNT              6
+
+#define TABLE_BIOS_IF               0 // Called by BIOS
+#define TABLE_WATERMARKS            1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM            2 // Called by Driver
+#define TABLE_SPARE1                3
+#define TABLE_DPMCLOCKS             4 // Called by Driver and VBIOS
+#define TABLE_MOMENTARY_PM          5 // Called by Tools
+#define TABLE_MODERN_STDBY          6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS           7 // Called by Driver
+#define TABLE_INFRASTRUCTURE_LIMITS 8
+#define TABLE_COUNT                 9
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index bb55a96f98e9..1962a5877191 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -34,6 +34,7 @@
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
+#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0x9
 
 /* MP Apertures */
 #define MP0_Public			0x03800000
@@ -243,6 +244,9 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
 int smu_v11_0_baco_enter(struct smu_context *smu);
 int smu_v11_0_baco_exit(struct smu_context *smu);
 
+int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
+				      enum smu_v11_0_baco_seq baco_seq);
+
 int smu_v11_0_mode1_reset(struct smu_context *smu);
 
 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
index 8145e1cbf181..6119a36b2cba 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
@@ -26,7 +26,7 @@
 #include "amdgpu_smu.h"
 
 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
-#define SMU13_DRIVER_IF_VERSION_ALDE 0x6
+#define SMU13_DRIVER_IF_VERSION_ALDE 0x07
 
 /* MP Apertures */
 #define MP0_Public			0x03800000
@@ -51,12 +51,6 @@
 #define CTF_OFFSET_HOTSPOT		5
 #define CTF_OFFSET_MEM			5
 
-static const struct smu_temperature_range smu13_thermal_policy[] =
-{
-	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
-	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
-};
-
 struct smu_13_0_max_sustainable_clocks {
 	uint32_t display_clock;
 	uint32_t phy_clock;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h
new file mode 100644
index 000000000000..b6c976a4d578
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU_V13_0_1_H__
+#define __SMU_V13_0_1_H__
+
+#include "amdgpu_smu.h"
+
+#define SMU13_0_1_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+#define SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP 0x3
+
+/* MP Apertures */
+#define MP0_Public			0x03800000
+#define MP0_SRAM			0x03900000
+#define MP1_Public			0x03b00000
+#define MP1_SRAM			0x03c00004
+
+/* address block */
+#define smnMP1_FIRMWARE_FLAGS		0x3010024
+
+
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
+int smu_v13_0_1_check_fw_status(struct smu_context *smu);
+
+int smu_v13_0_1_check_fw_version(struct smu_context *smu);
+
+int smu_v13_0_1_fini_smc_tables(struct smu_context *smu);
+
+int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu);
+
+int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu);
+
+int smu_v13_0_1_set_driver_table_location(struct smu_context *smu);
+
+int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable);
+#endif
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
new file mode 100644
index 000000000000..5627de734246
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SMU_V13_0_1_PMFW_H__
+#define __SMU_V13_0_1_PMFW_H__
+
+#include "smu13_driver_if_yellow_carp.h"
+
+#pragma pack(push, 1)
+
+#define ENABLE_DEBUG_FEATURES
+
+// Firmware features 
+// Feature Control Defines
+#define FEATURE_CCLK_DPM_BIT                 0
+#define FEATURE_FAN_CONTROLLER_BIT           1
+#define FEATURE_DATA_CALCULATION_BIT         2
+#define FEATURE_PPT_BIT                      3
+#define FEATURE_TDC_BIT                      4
+#define FEATURE_THERMAL_BIT                  5
+#define FEATURE_FIT_BIT                      6
+#define FEATURE_EDC_BIT                      7
+#define FEATURE_PLL_POWER_DOWN_BIT           8
+#define FEATURE_ULV_BIT                      9
+#define FEATURE_VDDOFF_BIT                  10
+#define FEATURE_VCN_DPM_BIT                 11
+#define FEATURE_CSTATE_BOOST_BIT            12
+#define FEATURE_FCLK_DPM_BIT                13
+#define FEATURE_SOCCLK_DPM_BIT              14
+#define FEATURE_MP0CLK_DPM_BIT              15
+#define FEATURE_LCLK_DPM_BIT                16
+#define FEATURE_SHUBCLK_DPM_BIT             17
+#define FEATURE_DCFCLK_DPM_BIT              18
+#define FEATURE_GFX_DPM_BIT                 19
+#define FEATURE_DS_GFXCLK_BIT               20
+#define FEATURE_DS_SOCCLK_BIT               21
+#define FEATURE_DS_LCLK_BIT                 22
+#define FEATURE_DS_DCFCLK_BIT               23
+#define FEATURE_DS_SHUBCLK_BIT              24
+#define FEATURE_GFX_TEMP_VMIN_BIT           25
+#define FEATURE_ZSTATES_BIT                 26
+#define FEATURE_WHISPER_MODE_BIT            27
+#define FEATURE_DS_FCLK_BIT                 28
+#define FEATURE_DS_SMNCLK_BIT               29
+#define FEATURE_DS_MP1CLK_BIT               30
+#define FEATURE_DS_MP0CLK_BIT               31
+#define FEATURE_CLK_LOW_POWER_BIT           32
+#define FEATURE_FUSE_PG_BIT                 33
+#define FEATURE_GFX_DEM_BIT                 34
+#define FEATURE_PSI_BIT                     35
+#define FEATURE_PROCHOT_BIT                 36
+#define FEATURE_CPUOFF_BIT                  37
+#define FEATURE_STAPM_BIT                   38
+#define FEATURE_S0I3_BIT                    39
+#define FEATURE_DF_LIGHT_CSTATE             40   // shift the order or DFCstate annd DF light Cstate
+#define FEATURE_PERF_LIMIT_BIT              41
+#define FEATURE_CORE_DLDO_BIT               42
+#define FEATURE_RSMU_LOW_POWER_BIT          43
+#define FEATURE_SMN_LOW_POWER_BIT           44
+#define FEATURE_THM_LOW_POWER_BIT           45
+#define FEATURE_SMUIO_LOW_POWER_BIT         46
+#define FEATURE_MP1_LOW_POWER_BIT           47
+#define FEATURE_DS_VCN_BIT                  48
+#define FEATURE_CPPC_BIT                    49
+#define FEATURE_CPPC_PREFERRED_CORES        50
+#define FEATURE_SMART_SHIFT_BIT             51
+#define FEATURE_DF_CSTATES_BIT              52
+#define FEATURE_MSMU_LOW_POWER_BIT          53
+#define FEATURE_SOC_VOLTAGE_MON_BIT         54
+#define FEATURE_ATHUB_PG_BIT                55
+#define FEATURE_VDDOFF_ECO_BIT              56
+#define FEATURE_ZSTATES_ECO_BIT             57
+#define FEATURE_CC6_BIT                     58
+#define FEATURE_DS_UMCCLK_BIT               59
+#define FEATURE_DS_HSPCLK_BIT               60 
+#define NUM_FEATURES                        61
+
+typedef struct {
+  // MP1_EXT_SCRATCH0
+  uint32_t DpmHandlerID         : 8;
+  uint32_t ActivityMonitorID    : 8;
+  uint32_t DpmTimerID           : 8;
+  uint32_t DpmHubID             : 4;
+  uint32_t DpmHubTask           : 4;
+  // MP1_EXT_SCRATCH1
+  uint32_t GfxoffStatus         : 8;
+  uint32_t GfxStatus            : 2;
+  uint32_t CpuOff               : 2;
+  uint32_t VddOff               : 1;
+  uint32_t InUlv                : 1;
+  uint32_t InWhisperMode        : 1;
+  uint32_t spare0               : 1;
+  uint32_t ZstateStatus         : 4;
+  uint32_t spare1               :12;
+  // MP1_EXT_SCRATCH2
+  uint32_t P2JobHandler         :24;
+  uint32_t RsmuPmiP2FinishedCnt : 8;
+  // MP1_EXT_SCRATCH3
+  uint32_t PostCode             :32;
+  // MP1_EXT_SCRATCH4
+  uint32_t MsgPortBusy          :15;
+  uint32_t RsmuPmiP1Pending     : 1;
+  uint32_t DfCstateExitPending  : 1;
+  uint32_t Pc6EntryPending      : 1;
+  uint32_t Pc6ExitPending       : 1;
+  uint32_t WarmResetPending     : 1;
+  uint32_t Mp0ClkPending        : 1;
+  uint32_t spare2               : 3;
+  uint32_t RsmuPmiP2PendingCnt  : 8;
+  // MP1_EXT_SCRATCH5
+  uint32_t IdleMask             :32;
+  // MP1_EXT_SCRATCH6 = RTOS threads' status
+  // MP1_EXT_SCRATCH7 = RTOS Current Job
+} FwStatus_t;
+
+
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
new file mode 100644
index 000000000000..1d3447991d0c
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_13_0_1_PPSMC_H
+#define SMU_13_0_1_PPSMC_H
+
+/** @def PPS_PMFW_IF_VER 
+* PPS (PPLib) to PMFW IF version 1.0
+*/
+#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor 
+
+/** @defgroup ResponseCodes PMFW Response Codes: 
+*  @{
+*/
+#define PPSMC_Result_OK                    0x1  ///< Message Response OK 
+#define PPSMC_Result_Failed                0xFF ///< Message Response Failed 
+#define PPSMC_Result_UnknownCmd            0xFE ///< Message Response Unknown Command 
+#define PPSMC_Result_CmdRejectedPrereq     0xFD ///< Message Response Command Failed Prerequisite
+#define PPSMC_Result_CmdRejectedBusy       0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
+/** @}*/
+
+/** @defgroup definitions Message definitions
+*  @{
+*/
+#define PPSMC_MSG_TestMessage                   0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team 
+#define PPSMC_MSG_GetSmuVersion                 0x02 ///< Get PMFW version
+#define PPSMC_MSG_GetDriverIfVersion            0x03 ///< Get PMFW_DRIVER_IF version
+#define PPSMC_MSG_EnableGfxOff                  0x04 ///< Enable GFXOFF
+#define PPSMC_MSG_DisableGfxOff                 0x05 ///< Disable GFXOFF
+#define PPSMC_MSG_PowerDownVcn                  0x06 ///< Power down VCN
+#define PPSMC_MSG_PowerUpVcn                    0x07 ///< Power up VCN; VCN is power gated by default
+#define PPSMC_MSG_SetHardMinVcn                 0x08 ///< For wireless display
+#define PPSMC_MSG_SetSoftMinGfxclk              0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
+#define PPSMC_MSG_ActiveProcessNotify           0x0A ///< Set active work load type
+#define PPSMC_MSG_ForcePowerDownGfx             0x0B ///< Force power down GFX, i.e. enter GFXOFF
+#define PPSMC_MSG_PrepareMp1ForUnload           0x0C ///< Prepare PMFW for GFX driver unload
+#define PPSMC_MSG_SetDriverDramAddrHigh         0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
+#define PPSMC_MSG_SetDriverDramAddrLow          0x0E ///< Set low 32 bits of DRAM address for Driver table transfer 
+#define PPSMC_MSG_TransferTableSmu2Dram         0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM
+#define PPSMC_MSG_TransferTableDram2Smu         0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM
+#define PPSMC_MSG_GfxDeviceDriverReset          0x11 ///< Request GFX mode 2 reset
+#define PPSMC_MSG_GetEnabledSmuFeatures         0x12 ///< Get enabled features in PMFW
+#define PPSMC_MSG_SetHardMinSocclkByFreq        0x13 ///< Set hard min for SOC CLK
+#define PPSMC_MSG_SetSoftMinFclk                0x14 ///< Set hard min for FCLK
+#define PPSMC_MSG_SetSoftMinVcn                 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_SPARE0                        0x16 ///< Spared
+#define PPSMC_MSG_GetGfxclkFrequency            0x17 ///< Get GFX clock frequency
+#define PPSMC_MSG_GetFclkFrequency              0x18 ///< Get FCLK frequency
+#define PPSMC_MSG_AllowGfxOff                   0x19 ///< Inform PMFW of allowing GFXOFF entry
+#define PPSMC_MSG_DisallowGfxOff                0x1A ///< Inform PMFW of disallowing GFXOFF entry
+#define PPSMC_MSG_SetSoftMaxGfxClk              0x1B ///< Set soft max for GFX CLK
+#define PPSMC_MSG_SetHardMinGfxClk              0x1C ///< Set hard min for GFX CLK
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x1D ///< Set soft max for SOC CLK
+#define PPSMC_MSG_SetSoftMaxFclkByFreq          0x1E ///< Set soft max for FCLK
+#define PPSMC_MSG_SetSoftMaxVcn                 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_SetPowerLimitPercentage       0x20 ///< Set power limit percentage
+#define PPSMC_MSG_PowerDownJpeg                 0x21 ///< Power down Jpeg
+#define PPSMC_MSG_PowerUpJpeg                   0x22 ///< Power up Jpeg; VCN is power gated by default
+#define PPSMC_MSG_SetHardMinFclkByFreq          0x23 ///< Set hard min for FCLK
+#define PPSMC_MSG_SetSoftMinSocclkByFreq        0x24 ///< Set soft min for SOC CLK
+#define PPSMC_MSG_AllowZstates                  0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
+#define PPSMC_MSG_DisallowZstates               0x26 ///< Inform PMFW of disallowing Zstate entry, i.e. there is Miracast activity
+#define PPSMC_MSG_RequestActiveWgp              0x27 ///< Request GFX active WGP number
+#define PPSMC_MSG_QueryActiveWgp                0x28 ///< Query the anumber of active WGP number
+#define PPSMC_Message_Count                     0x29 ///< Total number of PPS messages
+/** @}*/
+ 
+/** @enum Mode_Reset_e 
+* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset 
+*/ 
+typedef enum {
+  MODE1_RESET = 1,  ///< Mode reset type 1
+  MODE2_RESET = 2   ///< Mode reset type 2
+} Mode_Reset_e;    
+/** @}*/
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index ee6340c6f921..d2a38246a78a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1035,31 +1035,42 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
 }
 
 static int pp_get_power_limit(void *handle, uint32_t *limit,
-		uint32_t *max_limit, bool default_limit)
+			      enum pp_power_limit_level pp_limit_level,
+			      enum pp_power_type power_type)
 {
 	struct pp_hwmgr *hwmgr = handle;
+	int ret = 0;
 
 	if (!hwmgr || !hwmgr->pm_en ||!limit)
 		return -EINVAL;
 
+	if (power_type != PP_PWR_TYPE_SUSTAINED)
+		return -EOPNOTSUPP;
+
 	mutex_lock(&hwmgr->smu_lock);
 
-	if (default_limit) {
-		*limit = hwmgr->default_power_limit;
-		if (max_limit) {
-			*max_limit = *limit;
+	switch (pp_limit_level) {
+		case PP_PWR_LIMIT_CURRENT:
+			*limit = hwmgr->power_limit;
+			break;
+		case PP_PWR_LIMIT_DEFAULT:
+			*limit = hwmgr->default_power_limit;
+			break;
+		case PP_PWR_LIMIT_MAX:
+			*limit = hwmgr->default_power_limit;
 			if (hwmgr->od_enabled) {
-				*max_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
-				*max_limit /= 100;
+				*limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
+				*limit /= 100;
 			}
-		}
+			break;
+		default:
+			ret = -EOPNOTSUPP;
+			break;
 	}
-	else
-		*limit = hwmgr->power_limit;
 
 	mutex_unlock(&hwmgr->smu_lock);
 
-	return 0;
+	return ret;
 }
 
 static int pp_display_configuration_change(void *handle,
@@ -1651,6 +1662,26 @@ static int pp_gfx_state_change_set(void *handle, uint32_t state)
 	return 0;
 }
 
+static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size)
+{
+	struct pp_hwmgr *hwmgr = handle;
+	struct amdgpu_device *adev = hwmgr->adev;
+
+	if (!addr || !size)
+		return -EINVAL;
+
+	*addr = NULL;
+	*size = 0;
+	mutex_lock(&hwmgr->smu_lock);
+	if (adev->pm.smu_prv_buffer) {
+		amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr);
+		*size = adev->pm.smu_prv_buffer_size;
+	}
+	mutex_unlock(&hwmgr->smu_lock);
+
+	return 0;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
 	.load_firmware = pp_dpm_load_fw,
 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1714,4 +1745,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
 	.set_xgmi_pstate = pp_set_xgmi_pstate,
 	.get_gpu_metrics = pp_get_gpu_metrics,
 	.gfx_state_change_set = pp_gfx_state_change_set,
+	.get_smu_prv_buf_details = pp_get_prv_buffer_details,
 };
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
index 25b5831a15cd..981dc8c7112d 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
@@ -82,7 +82,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 
 	/* Skip for suspend/resume case */
 	if (!hwmgr->pp_one_vf && smum_is_dpm_running(hwmgr)
-	    && !amdgpu_passthrough(adev) && adev->in_suspend) {
+	    && !amdgpu_passthrough(adev) && adev->in_suspend
+		&& adev->asic_type != CHIP_RAVEN) {
 		pr_info("dpm has been enabled\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
index b1038d30c8dc..f503e61faa60 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
@@ -275,7 +275,7 @@ static const ATOM_VOLTAGE_OBJECT_V3 *atomctrl_lookup_voltage_type_v3(
 }
 
 /**
- * atomctrl_get_memory_pll_dividers_si().
+ * atomctrl_get_memory_pll_dividers_si
  *
  * @hwmgr:           input parameter: pointer to HwMgr
  * @clock_value:     input parameter: memory clock
@@ -328,7 +328,7 @@ int atomctrl_get_memory_pll_dividers_si(
 }
 
 /**
- * atomctrl_get_memory_pll_dividers_vi().
+ * atomctrl_get_memory_pll_dividers_vi
  *
  * @hwmgr:                 input parameter: pointer to HwMgr
  * @clock_value:           input parameter: memory clock
@@ -1104,7 +1104,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
 }
 
 /**
- * atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table.
+ * atomctrl_get_voltage_evv_on_sclk: gets voltage via call to ATOM COMMAND table.
  * @hwmgr:              input: pointer to hwManager
  * @voltage_type:       input: type of EVV voltage VDDC or VDDGFX
  * @sclk:               input: in 10Khz unit. DPM state SCLK frequency
@@ -1144,7 +1144,7 @@ int atomctrl_get_voltage_evv_on_sclk(
 }
 
 /**
- * atomctrl_get_voltage_evv gets voltage via call to ATOM COMMAND table.
+ * atomctrl_get_voltage_evv: gets voltage via call to ATOM COMMAND table.
  * @hwmgr:              input: pointer to hwManager
  * @virtual_voltage_id: input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
  * @voltage: 	       output: real voltage level in unit of mv
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 27cf22716793..43c3f6e755e7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -377,6 +377,27 @@ static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
 
 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
+	struct amdgpu_device *adev = hwmgr->adev;
+	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+	int ret = -EINVAL;
+
+	if (adev->in_suspend) {
+		pr_info("restore the fine grain parameters\n");
+
+		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_SetHardMinGfxClk,
+					smu10_data->gfx_actual_soft_min_freq,
+					NULL);
+		if (ret)
+			return ret;
+		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_SetSoftMaxGfxClk,
+					smu10_data->gfx_actual_soft_max_freq,
+					NULL);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
index 0d38d4206848..6cfe148ed45b 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
@@ -129,10 +129,10 @@ int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 }
 
 /**
-* Reset Fan Speed Control to default mode.
-* @hwmgr:  the address of the powerplay hardware manager.
-* Exception: Should always succeed.
-*/
+ * smu7_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode.
+ * @hwmgr:  the address of the powerplay hardware manager.
+ * Exception: Should always succeed.
+ */
 int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
 {
 	if (!hwmgr->fan_ctrl_is_in_default_mode) {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 31c61ac3bd5e..25979106fd25 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -544,7 +544,7 @@ static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 
 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 /**
- * Get Leakage VDDC based on leakage ID.
+ * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID.
  *
  * @hwmgr:  the address of the powerplay hardware manager.
  * return:  always 0.
@@ -600,7 +600,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 }
 
 /**
- * Change virtual leakage voltage to actual value.
+ * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value.
  *
  * @hwmgr:         the address of the powerplay hardware manager.
  * @voltage:       pointer to changing voltage
@@ -626,7 +626,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 }
 
 /**
- * Patch voltage lookup table by EVV leakages.
+ * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
  *
  * @hwmgr:         the address of the powerplay hardware manager.
  * @lookup_table:  pointer to voltage lookup table
@@ -1003,7 +1003,7 @@ static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 }
 
 /**
- * Remove repeated voltage values and create table with unique values.
+ * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values.
  *
  * @hwmgr:      the address of the powerplay hardware manager.
  * @vol_table:  the pointer to changing voltage table
@@ -1152,7 +1152,7 @@ static void vega10_trim_voltage_table_to_fit_state_table(
 }
 
 /**
- * Create Voltage Tables.
+ * vega10_construct_voltage_tables - Create Voltage Tables.
  *
  * @hwmgr:  the address of the powerplay hardware manager.
  * return:  always 0
@@ -1595,7 +1595,8 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
 }
 
 /**
- * Populates single SMC GFXSCLK structure using the provided engine clock
+ * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure
+ *                                    using the provided engine clock
  *
  * @hwmgr:      the address of the hardware manager
  * @gfx_clock:  the GFX clock to use to populate the structure.
@@ -1660,7 +1661,8 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
 }
 
 /**
- * Populates single SMC SOCCLK structure using the provided clock.
+ * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure
+ *                                    using the provided clock.
  *
  * @hwmgr:     the address of the hardware manager.
  * @soc_clock: the SOC clock to use to populate the structure.
@@ -1710,7 +1712,8 @@ static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
 }
 
 /**
- * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
+ * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure
+ *                                      based on the trimmed allowed dpm engine clock states
  *
  * @hwmgr:      the address of the hardware manager
  */
@@ -1859,7 +1862,8 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
 }
 
 /**
- * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
+ * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure
+ *                                     based on the trimmed allowed dpm memory clock states.
  *
  * @hwmgr:  the address of the hardware manager.
  * return:   PP_Result_OK on success.
@@ -2537,7 +2541,7 @@ static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
 }
 
 /**
- * Initializes the SMC table and uploads it
+ * vega10_init_smc_table - Initializes the SMC table and uploads it
  *
  * @hwmgr:  the address of the powerplay hardware manager.
  * return:  always 0
@@ -2919,7 +2923,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
 }
 
 /**
- * Tell SMC to enabled the supported DPMs.
+ * vega10_start_dpm - Tell SMC to enabled the supported DPMs.
  *
  * @hwmgr:   the address of the powerplay hardware manager.
  * @bitmap:  bitmap for the features to enabled.
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
index 1a097e608808..29e0d1d4035a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
@@ -803,7 +803,7 @@ static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
 #endif
 
 /**
- * Initializes the SMC table and uploads it
+ * vega12_init_smc_table - Initializes the SMC table and uploads it
  *
  * @hwmgr:  the address of the powerplay hardware manager.
  * return:  always 0
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
index 0dc16f25a463..ed3dff0b52d2 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
@@ -159,7 +159,8 @@ int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 }
 
 /**
- * Set the requested temperature range for high and low alert signals
+ * vega12_thermal_set_temperature_range - Set the requested temperature range
+ *                                        for high and low alert signals
  *
  * @hwmgr: The address of the hardware manager.
  * @range: Temperature range to be programmed for
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
index 2a28c9df15a0..8d99c7a5abf8 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
@@ -85,7 +85,7 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
 		return 0;
 
 	if (state == BACO_STATE_IN) {
-		if (!ras || !ras->supported) {
+		if (!ras || !adev->ras_enabled) {
 			data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
 			data |= 0x80000000;
 			WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index d3177a534fdf..0791309586c5 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -772,7 +772,7 @@ static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 }
 
 /**
- * Initializes the SMC table and uploads it
+ * vega20_init_smc_table - Initializes the SMC table and uploads it
  *
  * @hwmgr:  the address of the powerplay hardware manager.
  * return:  always 0
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index c29d8b3131b7..cb375f1beebd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -35,6 +35,7 @@
 #include "renoir_ppt.h"
 #include "vangogh_ppt.h"
 #include "aldebaran_ppt.h"
+#include "yellow_carp_ppt.h"
 #include "amd_pcie.h"
 
 /*
@@ -570,6 +571,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 		sienna_cichlid_set_ppt_funcs(smu);
 		break;
 	case CHIP_ALDEBARAN:
@@ -583,6 +585,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 		vangogh_set_ppt_funcs(smu);
 		break;
+	case CHIP_YELLOW_CARP:
+		yellow_carp_set_ppt_funcs(smu);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -666,6 +671,9 @@ static int smu_late_init(void *handle)
 		return ret;
 	}
 
+	if (adev->asic_type == CHIP_YELLOW_CARP)
+		return 0;
+
 	if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
 		ret = smu_set_default_od_settings(smu);
 		if (ret) {
@@ -680,13 +688,17 @@ static int smu_late_init(void *handle)
 		return ret;
 	}
 
-	ret = smu_get_asic_power_limits(smu);
+	ret = smu_get_asic_power_limits(smu,
+					&smu->current_power_limit,
+					&smu->default_power_limit,
+					&smu->max_power_limit);
 	if (ret) {
 		dev_err(adev->dev, "Failed to get asic power limits!\n");
 		return ret;
 	}
 
-	smu_get_unique_id(smu);
+	if (!amdgpu_sriov_vf(adev))
+		smu_get_unique_id(smu);
 
 	smu_get_fan_parameters(smu);
 
@@ -1370,15 +1382,20 @@ static int smu_disable_dpms(struct smu_context *smu)
 	if (smu->uploading_custom_pp_table &&
 	    (adev->asic_type >= CHIP_NAVI10) &&
 	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
-		return 0;
+		return smu_disable_all_features_with_exception(smu,
+							       true,
+							       SMU_FEATURE_COUNT);
 
 	/*
 	 * For Sienna_Cichlid, PMFW will handle the features disablement properly
 	 * on BACO in. Driver involvement is unnecessary.
 	 */
-	if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+	if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
+	     ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
 	     use_baco)
-		return 0;
+		return smu_disable_all_features_with_exception(smu,
+							       true,
+							       SMU_FEATURE_BACO_BIT);
 
 	/*
 	 * For gpu reset, runpm and hibernation through BACO,
@@ -1386,6 +1403,7 @@ static int smu_disable_dpms(struct smu_context *smu)
 	 */
 	if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
 		ret = smu_disable_all_features_with_exception(smu,
+							      false,
 							      SMU_FEATURE_BACO_BIT);
 		if (ret)
 			dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
@@ -2164,16 +2182,57 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
 	return ret;
 }
 
-int smu_get_power_limit(struct smu_context *smu,
+/**
+ * smu_get_power_limit - Request one of the SMU Power Limits
+ *
+ * @handle: pointer to smu context
+ * @limit: requested limit is written back to this variable
+ * @pp_limit_level: &pp_power_limit_level which limit of the power to return
+ * @pp_power_type: &pp_power_type type of power
+ * Return:  0 on success, <0 on error
+ *
+ */
+int smu_get_power_limit(void *handle,
 			uint32_t *limit,
-			enum smu_ppt_limit_level limit_level)
+			enum pp_power_limit_level pp_limit_level,
+			enum pp_power_type pp_power_type)
 {
-	uint32_t limit_type = *limit >> 24;
+	struct smu_context *smu = handle;
+	enum smu_ppt_limit_level limit_level;
+	uint32_t limit_type;
 	int ret = 0;
 
 	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 		return -EOPNOTSUPP;
 
+	switch(pp_power_type) {
+	case PP_PWR_TYPE_SUSTAINED:
+		limit_type = SMU_DEFAULT_PPT_LIMIT;
+		break;
+	case PP_PWR_TYPE_FAST:
+		limit_type = SMU_FAST_PPT_LIMIT;
+		break;
+	default:
+		return -EOPNOTSUPP;
+		break;
+	}
+
+	switch(pp_limit_level){
+	case PP_PWR_LIMIT_CURRENT:
+		limit_level = SMU_PPT_LIMIT_CURRENT;
+		break;
+	case PP_PWR_LIMIT_DEFAULT:
+		limit_level = SMU_PPT_LIMIT_DEFAULT;
+		break;
+	case PP_PWR_LIMIT_MAX:
+		limit_level = SMU_PPT_LIMIT_MAX;
+		break;
+	case PP_PWR_LIMIT_MIN:
+	default:
+		return -EOPNOTSUPP;
+		break;
+	}
+
 	mutex_lock(&smu->mutex);
 
 	if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
@@ -2182,6 +2241,15 @@ int smu_get_power_limit(struct smu_context *smu,
 	} else {
 		switch (limit_level) {
 		case SMU_PPT_LIMIT_CURRENT:
+			if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
+			     (smu->adev->asic_type == CHIP_SIENNA_CICHLID) ||
+			     (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) ||
+			     (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) ||
+			     (smu->adev->asic_type == CHIP_BEIGE_GOBY))
+				ret = smu_get_asic_power_limits(smu,
+								&smu->current_power_limit,
+								NULL,
+								NULL);
 			*limit = smu->current_power_limit;
 			break;
 		case SMU_PPT_LIMIT_DEFAULT:
@@ -2933,6 +3001,26 @@ int smu_set_light_sbr(struct smu_context *smu, bool enable)
 	return ret;
 }
 
+static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
+{
+	struct smu_context *smu = handle;
+	struct smu_table_context *smu_table = &smu->smu_table;
+	struct smu_table *memory_pool = &smu_table->memory_pool;
+
+	if (!addr || !size)
+		return -EINVAL;
+
+	*addr = NULL;
+	*size = 0;
+	mutex_lock(&smu->mutex);
+	if (memory_pool->bo) {
+		*addr = memory_pool->cpu_addr;
+		*size = memory_pool->size;
+	}
+	mutex_unlock(&smu->mutex);
+
+	return 0;
+}
 
 static const struct amd_pm_funcs swsmu_pm_funcs = {
 	/* export for sysfs */
@@ -2940,6 +3028,8 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
 	.get_fan_control_mode    = smu_get_fan_control_mode,
 	.set_fan_speed_percent   = smu_set_fan_speed_percent,
 	.get_fan_speed_percent   = smu_get_fan_speed_percent,
+	.force_clock_level       = smu_force_ppclk_levels,
+	.print_clock_levels      = smu_print_ppclk_levels,
 	.force_performance_level = smu_force_performance_level,
 	.read_sensor             = smu_read_sensor,
 	.get_performance_level   = smu_get_performance_level,
@@ -2952,38 +3042,38 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
 	.switch_power_profile    = smu_switch_power_profile,
 	/* export to amdgpu */
 	.dispatch_tasks          = smu_handle_dpm_task,
+	.load_firmware           = smu_load_microcode,
 	.set_powergating_by_smu  = smu_dpm_set_power_gate,
 	.set_power_limit         = smu_set_power_limit,
+	.get_power_limit         = smu_get_power_limit,
+	.get_power_profile_mode  = smu_get_power_profile_mode,
+	.set_power_profile_mode  = smu_set_power_profile_mode,
 	.odn_edit_dpm_table      = smu_od_edit_dpm_table,
 	.set_mp1_state           = smu_set_mp1_state,
+	.gfx_state_change_set    = smu_gfx_state_change_set,
 	/* export to DC */
-	.get_sclk                = smu_get_sclk,
-	.get_mclk                = smu_get_mclk,
-	.enable_mgpu_fan_boost   = smu_enable_mgpu_fan_boost,
-	.get_asic_baco_capability = smu_get_baco_capability,
-	.set_asic_baco_state     = smu_baco_set_state,
-	.get_ppfeature_status    = smu_sys_get_pp_feature_mask,
-	.set_ppfeature_status    = smu_sys_set_pp_feature_mask,
-	.asic_reset_mode_2       = smu_mode2_reset,
-	.set_df_cstate           = smu_set_df_cstate,
-	.set_xgmi_pstate         = smu_set_xgmi_pstate,
-	.get_gpu_metrics         = smu_sys_get_gpu_metrics,
-	.set_power_profile_mode  = smu_set_power_profile_mode,
-	.get_power_profile_mode  = smu_get_power_profile_mode,
-	.force_clock_level       = smu_force_ppclk_levels,
-	.print_clock_levels      = smu_print_ppclk_levels,
-	.get_uclk_dpm_states     = smu_get_uclk_dpm_states,
-	.get_dpm_clock_table     = smu_get_dpm_clock_table,
-	.display_configuration_change        = smu_display_configuration_change,
-	.get_clock_by_type_with_latency      = smu_get_clock_by_type_with_latency,
-	.display_clock_voltage_request       = smu_display_clock_voltage_request,
-	.set_active_display_count            = smu_set_display_count,
-	.set_min_deep_sleep_dcefclk          = smu_set_deep_sleep_dcefclk,
+	.get_sclk                         = smu_get_sclk,
+	.get_mclk                         = smu_get_mclk,
+	.display_configuration_change     = smu_display_configuration_change,
+	.get_clock_by_type_with_latency   = smu_get_clock_by_type_with_latency,
+	.display_clock_voltage_request    = smu_display_clock_voltage_request,
+	.enable_mgpu_fan_boost            = smu_enable_mgpu_fan_boost,
+	.set_active_display_count         = smu_set_display_count,
+	.set_min_deep_sleep_dcefclk       = smu_set_deep_sleep_dcefclk,
+	.get_asic_baco_capability         = smu_get_baco_capability,
+	.set_asic_baco_state              = smu_baco_set_state,
+	.get_ppfeature_status             = smu_sys_get_pp_feature_mask,
+	.set_ppfeature_status             = smu_sys_set_pp_feature_mask,
+	.asic_reset_mode_2                = smu_mode2_reset,
+	.set_df_cstate                    = smu_set_df_cstate,
+	.set_xgmi_pstate                  = smu_set_xgmi_pstate,
+	.get_gpu_metrics                  = smu_sys_get_gpu_metrics,
 	.set_watermarks_for_clock_ranges     = smu_set_watermarks_for_clock_ranges,
 	.display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
 	.get_max_sustainable_clocks_by_dc    = smu_get_max_sustainable_clocks_by_dc,
-	.load_firmware           = smu_load_microcode,
-	.gfx_state_change_set    = smu_gfx_state_change_set,
+	.get_uclk_dpm_states              = smu_get_uclk_dpm_states,
+	.get_dpm_clock_table              = smu_get_dpm_clock_table,
+	.get_smu_prv_buf_details = smu_get_prv_buffer_details,
 };
 
 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 77693bf0840c..094df6f87cfc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -211,6 +211,26 @@ static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t arcturus_throttler_map[] = {
+	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
+	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
+	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_TEMP_VR_MEM_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
+	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
+	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
+	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
+	[THROTTLER_PPM_BIT]		= (SMU_THROTTLER_PPM_BIT),
+	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
+	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
+	[THROTTLER_VRHOT0_BIT]		= (SMU_THROTTLER_VRHOT0_BIT),
+	[THROTTLER_VRHOT1_BIT]		= (SMU_THROTTLER_VRHOT1_BIT),
+};
+
 static int arcturus_tables_init(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
@@ -237,7 +257,7 @@ static int arcturus_tables_init(struct smu_context *smu)
 		return -ENOMEM;
 	smu_table->metrics_time = 0;
 
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table) {
 		kfree(smu_table->metrics_table);
@@ -380,16 +400,31 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
 	return 0;
 }
 
-static int arcturus_check_powerplay_table(struct smu_context *smu)
+static void arcturus_check_bxco_support(struct smu_context *smu)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_powerplay_table *powerplay_table =
 		table_context->power_play_table;
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t val;
 
 	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
+	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
+		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+		smu_baco->platform_support =
+			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+									false;
+	}
+}
+
+static int arcturus_check_powerplay_table(struct smu_context *smu)
+{
+	struct smu_table_context *table_context = &smu->smu_table;
+	struct smu_11_0_powerplay_table *powerplay_table =
+		table_context->power_play_table;
+
+	arcturus_check_bxco_support(smu);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
@@ -822,6 +857,52 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
 				now) ? "*" : ""));
 		break;
 
+	case SMU_VCLK:
+		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
+			return ret;
+		}
+
+		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
+		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
+			return ret;
+		}
+
+		for (i = 0; i < single_dpm_table->count; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+				i, single_dpm_table->dpm_levels[i].value,
+				(clocks.num_levels == 1) ? "*" :
+				(arcturus_freqs_in_same_level(
+				clocks.data[i].clocks_in_khz / 1000,
+				now) ? "*" : ""));
+		break;
+
+	case SMU_DCLK:
+		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
+			return ret;
+		}
+
+		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
+		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
+			return ret;
+		}
+
+		for (i = 0; i < single_dpm_table->count; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+				i, single_dpm_table->dpm_levels[i].value,
+				(clocks.num_levels == 1) ? "*" :
+				(arcturus_freqs_in_same_level(
+				clocks.data[i].clocks_in_khz / 1000,
+				now) ? "*" : ""));
+		break;
+
 	case SMU_PCIE:
 		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
@@ -1113,7 +1194,10 @@ static int arcturus_get_fan_parameters(struct smu_context *smu)
 	return 0;
 }
 
-static int arcturus_get_power_limit(struct smu_context *smu)
+static int arcturus_get_power_limit(struct smu_context *smu,
+				    uint32_t *current_power_limit,
+				    uint32_t *default_power_limit,
+				    uint32_t *max_power_limit)
 {
 	struct smu_11_0_powerplay_table *powerplay_table =
 		(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
@@ -1129,17 +1213,24 @@ static int arcturus_get_power_limit(struct smu_context *smu)
 		power_limit =
 			pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
 	}
-	smu->current_power_limit = smu->default_power_limit = power_limit;
 
-	if (smu->od_enabled) {
-		od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
+	if (current_power_limit)
+		*current_power_limit = power_limit;
+	if (default_power_limit)
+		*default_power_limit = power_limit;
 
-		dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
+	if (max_power_limit) {
+		if (smu->od_enabled) {
+			od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
 
-		power_limit *= (100 + od_percent);
-		power_limit /= 100;
+			dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
+
+			power_limit *= (100 + od_percent);
+			power_limit /= 100;
+		}
+
+		*max_power_limit = power_limit;
 	}
-	smu->max_power_limit = power_limit;
 
 	return 0;
 }
@@ -2101,18 +2192,6 @@ static void arcturus_get_unique_id(struct smu_context *smu)
 	sprintf(adev->serial, "%llx", id);
 }
 
-static bool arcturus_is_baco_supported(struct smu_context *smu)
-{
-	struct amdgpu_device *adev = smu->adev;
-	uint32_t val;
-
-	if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
-		return false;
-
-	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-	return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
-}
-
 static int arcturus_set_df_cstate(struct smu_context *smu,
 				  enum pp_df_cstate state)
 {
@@ -2229,8 +2308,8 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
 					void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v1_3 *gpu_metrics =
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int ret = 0;
 
@@ -2240,7 +2319,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2269,6 +2348,9 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   arcturus_throttler_map);
 
 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2281,7 +2363,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
 
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 
 static const struct pptable_funcs arcturus_ppt_funcs = {
@@ -2347,7 +2429,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
 	.register_irq_handler = smu_v11_0_register_irq_handler,
 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-	.baco_is_support= arcturus_is_baco_supported,
+	.baco_is_support = smu_v11_0_baco_is_support,
 	.baco_get_state = smu_v11_0_baco_get_state,
 	.baco_set_state = smu_v11_0_baco_set_state,
 	.baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 0eaf86b5e698..1ba42b69ce74 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -80,10 +80,10 @@ static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
 	MSG_MAP(SetAllowedFeaturesMaskHigh,	PPSMC_MSG_SetAllowedFeaturesMaskHigh,	0),
 	MSG_MAP(EnableAllSmuFeatures,		PPSMC_MSG_EnableAllSmuFeatures,		0),
 	MSG_MAP(DisableAllSmuFeatures,		PPSMC_MSG_DisableAllSmuFeatures,	0),
-	MSG_MAP(EnableSmuFeaturesLow,		PPSMC_MSG_EnableSmuFeaturesLow,		1),
-	MSG_MAP(EnableSmuFeaturesHigh,		PPSMC_MSG_EnableSmuFeaturesHigh,	1),
-	MSG_MAP(DisableSmuFeaturesLow,		PPSMC_MSG_DisableSmuFeaturesLow,	1),
-	MSG_MAP(DisableSmuFeaturesHigh,		PPSMC_MSG_DisableSmuFeaturesHigh,	1),
+	MSG_MAP(EnableSmuFeaturesLow,		PPSMC_MSG_EnableSmuFeaturesLow,		0),
+	MSG_MAP(EnableSmuFeaturesHigh,		PPSMC_MSG_EnableSmuFeaturesHigh,	0),
+	MSG_MAP(DisableSmuFeaturesLow,		PPSMC_MSG_DisableSmuFeaturesLow,	0),
+	MSG_MAP(DisableSmuFeaturesHigh,		PPSMC_MSG_DisableSmuFeaturesHigh,	0),
 	MSG_MAP(GetEnabledSmuFeaturesLow,	PPSMC_MSG_GetEnabledSmuFeaturesLow,	1),
 	MSG_MAP(GetEnabledSmuFeaturesHigh,	PPSMC_MSG_GetEnabledSmuFeaturesHigh,	1),
 	MSG_MAP(SetWorkloadMask,		PPSMC_MSG_SetWorkloadMask,		1),
@@ -238,6 +238,28 @@ static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] =
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t navi1x_throttler_map[] = {
+	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
+	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
+	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_TEMP_VR_MEM0_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+	[THROTTLER_TEMP_VR_MEM1_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
+	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+	[THROTTLER_TEMP_LIQUID0_BIT]	= (SMU_THROTTLER_TEMP_LIQUID0_BIT),
+	[THROTTLER_TEMP_LIQUID1_BIT]	= (SMU_THROTTLER_TEMP_LIQUID1_BIT),
+	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
+	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
+	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
+	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
+	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
+	[THROTTLER_PPM_BIT]		= (SMU_THROTTLER_PPM_BIT),
+	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
+};
+
+
 static bool is_asic_secure(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
@@ -340,19 +362,34 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
 	return 0;
 }
 
-static int navi10_check_powerplay_table(struct smu_context *smu)
+static void navi10_check_bxco_support(struct smu_context *smu)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_powerplay_table *powerplay_table =
 		table_context->power_play_table;
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t val;
+
+	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
+	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
+		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+		smu_baco->platform_support =
+			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+									false;
+	}
+}
+
+static int navi10_check_powerplay_table(struct smu_context *smu)
+{
+	struct smu_table_context *table_context = &smu->smu_table;
+	struct smu_11_0_powerplay_table *powerplay_table =
+		table_context->power_play_table;
 
 	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 		smu->dc_controlled_by_gpio = true;
 
-	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
+	navi10_check_bxco_support(smu);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
@@ -431,30 +468,6 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
 	return 0;
 }
 
-static int navi10_set_mp1_state(struct smu_context *smu,
-				enum pp_mp1_state mp1_state)
-{
-	struct amdgpu_device *adev = smu->adev;
-	uint32_t mp1_fw_flags;
-	int ret = 0;
-
-	ret = smu_cmn_set_mp1_state(smu, mp1_state);
-	if (ret)
-		return ret;
-
-	if (mp1_state == PP_MP1_STATE_UNLOAD) {
-		mp1_fw_flags = RREG32_PCIE(MP1_Public |
-					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
-
-		mp1_fw_flags &= ~MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK;
-
-		WREG32_PCIE(MP1_Public |
-			    (smnMP1_FIRMWARE_FLAGS & 0xffffffff), mp1_fw_flags);
-	}
-
-	return 0;
-}
-
 static int navi10_setup_pptable(struct smu_context *smu)
 {
 	int ret = 0;
@@ -505,7 +518,7 @@ static int navi10_tables_init(struct smu_context *smu)
 		goto err0_out;
 	smu_table->metrics_time = 0;
 
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table)
 		goto err1_out;
@@ -1273,6 +1286,8 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 	case SMU_MCLK:
 	case SMU_UCLK:
 	case SMU_FCLK:
+	case SMU_VCLK:
+	case SMU_DCLK:
 	case SMU_DCEFCLK:
 		ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 		if (ret)
@@ -2121,7 +2136,10 @@ static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
 	return ret;
 }
 
-static int navi10_get_power_limit(struct smu_context *smu)
+static int navi10_get_power_limit(struct smu_context *smu,
+				  uint32_t *current_power_limit,
+				  uint32_t *default_power_limit,
+				  uint32_t *max_power_limit)
 {
 	struct smu_11_0_powerplay_table *powerplay_table =
 		(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
@@ -2138,18 +2156,25 @@ static int navi10_get_power_limit(struct smu_context *smu)
 		power_limit =
 			pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
 	}
-	smu->current_power_limit = smu->default_power_limit = power_limit;
 
-	if (smu->od_enabled &&
-	    navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
-		od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
+	if (current_power_limit)
+		*current_power_limit = power_limit;
+	if (default_power_limit)
+		*default_power_limit = power_limit;
+
+	if (max_power_limit) {
+		if (smu->od_enabled &&
+		    navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
+			od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
+
+			dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
 
-		dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
+			power_limit *= (100 + od_percent);
+			power_limit /= 100;
+		}
 
-		power_limit *= (100 + od_percent);
-		power_limit /= 100;
+		*max_power_limit = power_limit;
 	}
-	smu->max_power_limit = power_limit;
 
 	return 0;
 }
@@ -2240,16 +2265,27 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
 	return 0;
 }
 
-static bool navi10_is_baco_supported(struct smu_context *smu)
+static int navi10_baco_enter(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
-	uint32_t val;
 
-	if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
-		return false;
+	if (adev->in_runpm)
+		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+	else
+		return smu_v11_0_baco_enter(smu);
+}
+
+static int navi10_baco_exit(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
 
-	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-	return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+	if (adev->in_runpm) {
+		/* Wait for PMFW handling for the Dstate change */
+		msleep(10);
+		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
+	} else {
+		return smu_v11_0_baco_exit(smu);
+	}
 }
 
 static int navi10_set_default_od_settings(struct smu_context *smu)
@@ -2627,8 +2663,8 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
 					     void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v1_3 *gpu_metrics =
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_legacy_t metrics;
 	int ret = 0;
 
@@ -2646,7 +2682,7 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
 
 	mutex_unlock(&smu->metrics_lock);
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2671,6 +2707,9 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   navi1x_throttler_map);
 
 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2681,17 +2720,27 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
 
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
+	if (metrics.CurrGfxVoltageOffset)
+		gpu_metrics->voltage_gfx =
+			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+	if (metrics.CurrMemVidOffset)
+		gpu_metrics->voltage_mem =
+			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
+	if (metrics.CurrSocVoltageOffset)
+		gpu_metrics->voltage_soc =
+			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
+
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 
 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v1_3 *gpu_metrics =
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int ret = 0;
 
@@ -2709,7 +2758,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
 
 	mutex_unlock(&smu->metrics_lock);
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2738,6 +2787,9 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   navi1x_throttler_map);
 
 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2746,17 +2798,27 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
 
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
+	if (metrics.CurrGfxVoltageOffset)
+		gpu_metrics->voltage_gfx =
+			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+	if (metrics.CurrMemVidOffset)
+		gpu_metrics->voltage_mem =
+			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
+	if (metrics.CurrSocVoltageOffset)
+		gpu_metrics->voltage_soc =
+			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
+
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 
 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
 					     void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v1_3 *gpu_metrics =
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_NV12_legacy_t metrics;
 	int ret = 0;
 
@@ -2774,7 +2836,7 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
 
 	mutex_unlock(&smu->metrics_lock);
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2804,6 +2866,9 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   navi1x_throttler_map);
 
 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2814,17 +2879,27 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
 
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
+	if (metrics.CurrGfxVoltageOffset)
+		gpu_metrics->voltage_gfx =
+			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+	if (metrics.CurrMemVidOffset)
+		gpu_metrics->voltage_mem =
+			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
+	if (metrics.CurrSocVoltageOffset)
+		gpu_metrics->voltage_soc =
+			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
+
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 
 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v1_3 *gpu_metrics =
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_NV12_t metrics;
 	int ret = 0;
 
@@ -2842,7 +2917,7 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
 
 	mutex_unlock(&smu->metrics_lock);
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2876,6 +2951,9 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   navi1x_throttler_map);
 
 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2884,9 +2962,19 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
 
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
+	if (metrics.CurrGfxVoltageOffset)
+		gpu_metrics->voltage_gfx =
+			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
+	if (metrics.CurrMemVidOffset)
+		gpu_metrics->voltage_mem =
+			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
+	if (metrics.CurrSocVoltageOffset)
+		gpu_metrics->voltage_soc =
+			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
+
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 
 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
@@ -3047,11 +3135,11 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 	.register_irq_handler = smu_v11_0_register_irq_handler,
 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-	.baco_is_support= navi10_is_baco_supported,
+	.baco_is_support = smu_v11_0_baco_is_support,
 	.baco_get_state = smu_v11_0_baco_get_state,
 	.baco_set_state = smu_v11_0_baco_set_state,
-	.baco_enter = smu_v11_0_baco_enter,
-	.baco_exit = smu_v11_0_baco_exit,
+	.baco_enter = navi10_baco_enter,
+	.baco_exit = navi10_baco_exit,
 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
 	.set_default_od_settings = navi10_set_default_od_settings,
@@ -3067,7 +3155,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 	.get_fan_parameters = navi10_get_fan_parameters,
 	.post_init = navi10_post_smu_init,
 	.interrupt_work = smu_v11_0_interrupt_work,
-	.set_mp1_state = navi10_set_mp1_state,
+	.set_mp1_state = smu_cmn_set_mp1_state,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b124a5e40dd6..c751f717a0da 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -73,6 +73,21 @@
 
 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
 
+#define GET_PPTABLE_MEMBER(field, member) do {\
+	if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
+		(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
+	else\
+		(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
+} while(0)
+
+static int get_table_size(struct smu_context *smu)
+{
+	if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
+		return sizeof(PPTable_beige_goby_t);
+	else
+		return sizeof(PPTable_t);
+}
+
 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
 	MSG_MAP(TestMessage,			PPSMC_MSG_TestMessage,                 1),
 	MSG_MAP(GetSmuVersion,			PPSMC_MSG_GetSmuVersion,               1),
@@ -224,6 +239,27 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t sienna_cichlid_throttler_map[] = {
+	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
+	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
+	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_TEMP_VR_MEM0_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+	[THROTTLER_TEMP_VR_MEM1_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
+	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+	[THROTTLER_TEMP_LIQUID0_BIT]	= (SMU_THROTTLER_TEMP_LIQUID0_BIT),
+	[THROTTLER_TEMP_LIQUID1_BIT]	= (SMU_THROTTLER_TEMP_LIQUID1_BIT),
+	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
+	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
+	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
+	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
+	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
+	[THROTTLER_PPM_BIT]		= (SMU_THROTTLER_PPM_BIT),
+	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
+};
+
 static int
 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 				  uint32_t *feature_mask, uint32_t num)
@@ -302,25 +338,40 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 	if (smu->dc_controlled_by_gpio)
        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 
-	if (amdgpu_aspm == 1)
+	if (amdgpu_aspm)
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 
 	return 0;
 }
 
-static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
+static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_7_powerplay_table *powerplay_table =
 		table_context->power_play_table;
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t val;
+
+	if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
+	    powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
+		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+		smu_baco->platform_support =
+			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+									false;
+	}
+}
+
+static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
+{
+	struct smu_table_context *table_context = &smu->smu_table;
+	struct smu_11_0_7_powerplay_table *powerplay_table =
+		table_context->power_play_table;
 
 	if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 		smu->dc_controlled_by_gpio = true;
 
-	if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
+	sienna_cichlid_check_bxco_support(smu);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
@@ -336,10 +387,9 @@ static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 
 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 {
-	struct smu_table_context *table_context = &smu->smu_table;
-	PPTable_t *smc_pptable = table_context->driver_pptable;
 	struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 	int index, ret;
+	I2cControllerConfig_t *table_member;
 
 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 					    smc_dpm_info);
@@ -348,9 +398,9 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 				      (uint8_t **)&smc_dpm_table);
 	if (ret)
 		return ret;
-
-	memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
-	       sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
+	GET_PPTABLE_MEMBER(I2cControllers, &table_member);
+	memcpy(table_member, smc_dpm_table->I2cControllers,
+			sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 	
 	return 0;
 }
@@ -360,9 +410,11 @@ static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_7_powerplay_table *powerplay_table =
 		table_context->power_play_table;
+	int table_size;
 
+	table_size = get_table_size(smu);
 	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
-	       sizeof(PPTable_t));
+	       table_size);
 
 	return 0;
 }
@@ -394,9 +446,11 @@ static int sienna_cichlid_tables_init(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
 	struct smu_table *tables = smu_table->tables;
+	int table_size;
 
-	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
-		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	table_size = get_table_size(smu);
+	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
+			       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
@@ -416,7 +470,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu)
 		goto err0_out;
 	smu_table->metrics_time = 0;
 
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table)
 		goto err1_out;
@@ -572,13 +626,14 @@ static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 {
 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
-	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 	struct smu_11_0_dpm_table *dpm_table;
 	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
+	DpmDescriptor_t *table_member;
 
 	/* socclk dpm table setup */
 	dpm_table = &dpm_context->dpm_tables.soc_table;
+	GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 		ret = smu_v11_0_set_single_dpm_table(smu,
 						     SMU_SOCCLK,
@@ -586,7 +641,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
+			!table_member[PPCLK_SOCCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
@@ -604,7 +659,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
+			!table_member[PPCLK_GFXCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
@@ -622,7 +677,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
+			!table_member[PPCLK_UCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
@@ -640,7 +695,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
+			!table_member[PPCLK_FCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
@@ -658,7 +713,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
+			!table_member[PPCLK_VCLK_0].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
@@ -677,7 +732,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 			if (ret)
 				return ret;
 			dpm_table->is_fine_grained =
-				!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
+				!table_member[PPCLK_VCLK_1].SnapToDiscrete;
 		} else {
 			dpm_table->count = 1;
 			dpm_table->dpm_levels[0].value =
@@ -697,7 +752,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
+			!table_member[PPCLK_DCLK_0].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
@@ -716,7 +771,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 			if (ret)
 				return ret;
 			dpm_table->is_fine_grained =
-				!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
+				!table_member[PPCLK_DCLK_1].SnapToDiscrete;
 		} else {
 			dpm_table->count = 1;
 			dpm_table->dpm_levels[0].value =
@@ -736,7 +791,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
+			!table_member[PPCLK_DCEFCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
@@ -754,7 +809,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
+			!table_member[PPCLK_PIXCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
@@ -772,7 +827,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
+			!table_member[PPCLK_DISPCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
@@ -790,7 +845,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		if (ret)
 			return ret;
 		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
+			!table_member[PPCLK_PHYCLK].SnapToDiscrete;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
@@ -911,14 +966,15 @@ static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 
 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 {
-	PPTable_t *pptable = smu->smu_table.driver_pptable;
 	DpmDescriptor_t *dpm_desc = NULL;
+	DpmDescriptor_t *table_member;
 	uint32_t clk_index = 0;
 
+	GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 	clk_index = smu_cmn_to_asic_specific_index(smu,
 						   CMN2ASIC_MAPPING_CLK,
 						   clk_type);
-	dpm_desc = &pptable->DpmDescriptor[clk_index];
+	dpm_desc = &table_member[clk_index];
 
 	/* 0 - Fine grained DPM, 1 - Discrete DPM */
 	return dpm_desc->SnapToDiscrete == 0;
@@ -947,7 +1003,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
-	PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
+	uint16_t *table_member;
+
 	struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
 	OverDriveTable_t *od_table =
 		(OverDriveTable_t *)table_context->overdrive_table;
@@ -966,6 +1023,10 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 	case SMU_MCLK:
 	case SMU_UCLK:
 	case SMU_FCLK:
+	case SMU_VCLK:
+	case SMU_VCLK1:
+	case SMU_DCLK:
+	case SMU_DCLK1:
 	case SMU_DCEFCLK:
 		ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 		if (ret)
@@ -1016,6 +1077,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 	case SMU_PCIE:
 		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
+		GET_PPTABLE_MEMBER(LclkFreq, &table_member);
 		for (i = 0; i < NUM_LINK_LEVELS; i++)
 			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
@@ -1028,7 +1090,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
-					pptable->LclkFreq[i],
+					table_member[i],
 					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 					"*" : "");
@@ -1275,9 +1337,10 @@ static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
 
 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
 {
-	PPTable_t *pptable = smu->smu_table.driver_pptable;
+	uint16_t *table_member;
 
-	smu->fan_max_rpm = pptable->FanMaximumRpm;
+	GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
+	smu->fan_max_rpm = *table_member;
 
 	return 0;
 }
@@ -1568,8 +1631,7 @@ static int sienna_cichlid_read_sensor(struct smu_context *smu,
 				 void *data, uint32_t *size)
 {
 	int ret = 0;
-	struct smu_table_context *table_context = &smu->smu_table;
-	PPTable_t *pptable = table_context->driver_pptable;
+	uint16_t *temp;
 
 	if(!data || !size)
 		return -EINVAL;
@@ -1577,7 +1639,8 @@ static int sienna_cichlid_read_sensor(struct smu_context *smu,
 	mutex_lock(&smu->sensor_lock);
 	switch (sensor) {
 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
-		*(uint32_t *)data = pptable->FanMaximumRpm;
+		GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
+		*(uint16_t *)data = *temp;
 		*size = 4;
 		break;
 	case AMDGPU_PP_SENSOR_MEM_LOAD:
@@ -1645,14 +1708,16 @@ static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t
 	uint16_t *dpm_levels = NULL;
 	uint16_t i = 0;
 	struct smu_table_context *table_context = &smu->smu_table;
-	PPTable_t *driver_ppt = NULL;
+	DpmDescriptor_t *table_member1;
+	uint16_t *table_member2;
 
 	if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
 		return -EINVAL;
 
-	driver_ppt = table_context->driver_pptable;
-	num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
-	dpm_levels = driver_ppt->FreqTableUclk;
+	GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
+	num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
+	GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
+	dpm_levels = table_member2;
 
 	if (num_discrete_levels == 0 || dpm_levels == NULL)
 		return -EINVAL;
@@ -1674,25 +1739,29 @@ static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_7_powerplay_table *powerplay_table =
 				table_context->power_play_table;
-	PPTable_t *pptable = smu->smu_table.driver_pptable;
+	uint16_t *table_member;
+	uint16_t temp_edge, temp_hotspot, temp_mem;
 
 	if (!range)
 		return -EINVAL;
 
 	memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
 
-	range->max = pptable->TemperatureLimit[TEMP_EDGE] *
-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-	range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-	range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-	range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
+	GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
+	temp_edge = table_member[TEMP_EDGE];
+	temp_hotspot = table_member[TEMP_HOTSPOT];
+	temp_mem = table_member[TEMP_MEM];
+
+	range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+	range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-	range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
+	range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+	range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-	range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
+	range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+	range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
 	range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
 
 	return 0;
@@ -1722,33 +1791,39 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
 	return ret;
 }
 
-static int sienna_cichlid_get_power_limit(struct smu_context *smu)
+static int sienna_cichlid_get_power_limit(struct smu_context *smu,
+					  uint32_t *current_power_limit,
+					  uint32_t *default_power_limit,
+					  uint32_t *max_power_limit)
 {
 	struct smu_11_0_7_powerplay_table *powerplay_table =
 		(struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
-	PPTable_t *pptable = smu->smu_table.driver_pptable;
 	uint32_t power_limit, od_percent;
+	uint16_t *table_member;
+
+	GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
 
 	if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
-		/* the last hope to figure out the ppt limit */
-		if (!pptable) {
-			dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
-			return -EINVAL;
-		}
 		power_limit =
-			pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+			table_member[PPT_THROTTLER_PPT0];
 	}
-	smu->current_power_limit = smu->default_power_limit = power_limit;
 
-	if (smu->od_enabled) {
-		od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
+	if (current_power_limit)
+		*current_power_limit = power_limit;
+	if (default_power_limit)
+		*default_power_limit = power_limit;
+
+	if (max_power_limit) {
+		if (smu->od_enabled) {
+			od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
 
-		dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
+			dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
 
-		power_limit *= (100 + od_percent);
-		power_limit /= 100;
+			power_limit *= (100 + od_percent);
+			power_limit /= 100;
+		}
+		*max_power_limit = power_limit;
 	}
-	smu->max_power_limit = power_limit;
 
 	return 0;
 }
@@ -1758,36 +1833,39 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
 					 uint32_t pcie_width_cap)
 {
 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
-	PPTable_t *pptable = smu->smu_table.driver_pptable;
+
 	uint32_t smu_pcie_arg;
+	uint8_t *table_member1, *table_member2;
 	int ret, i;
 
+	GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
+	GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
+
 	/* lclk dpm table setup */
 	for (i = 0; i < MAX_PCIE_CONF; i++) {
-		dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
-		dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
+		dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
+		dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
 	}
 
 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
 		smu_pcie_arg = (i << 16) |
-			((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
-					(pptable->PcieGenSpeed[i] << 8) :
-					(pcie_gen_cap << 8)) |
-			((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
-					pptable->PcieLaneCount[i] :
-					pcie_width_cap);
+			((table_member1[i] <= pcie_gen_cap) ?
+			 (table_member1[i] << 8) :
+			 (pcie_gen_cap << 8)) |
+			((table_member2[i] <= pcie_width_cap) ?
+			 table_member2[i] :
+			 pcie_width_cap);
 
 		ret = smu_cmn_send_smc_msg_with_param(smu,
-					  SMU_MSG_OverridePcieParameters,
-					  smu_pcie_arg,
-					  NULL);
-
+				SMU_MSG_OverridePcieParameters,
+				smu_pcie_arg,
+				NULL);
 		if (ret)
 			return ret;
 
-		if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
+		if (table_member1[i] > pcie_gen_cap)
 			dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
-		if (pptable->PcieLaneCount[i] > pcie_width_cap)
+		if (table_member2[i] > pcie_width_cap)
 			dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
 	}
 
@@ -2052,16 +2130,27 @@ static int sienna_cichlid_run_btc(struct smu_context *smu)
 	return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 }
 
-static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
+static int sienna_cichlid_baco_enter(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
-	uint32_t val;
 
-	if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
-		return false;
+	if (adev->in_runpm)
+		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+	else
+		return smu_v11_0_baco_enter(smu);
+}
+
+static int sienna_cichlid_baco_exit(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
 
-	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-	return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+	if (adev->in_runpm) {
+		/* Wait for PMFW handling for the Dstate change */
+		msleep(10);
+		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
+	} else {
+		return smu_v11_0_baco_exit(smu);
+	}
 }
 
 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
@@ -2086,12 +2175,646 @@ static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
 	return val != 0x0;
 }
 
+static void beige_goby_dump_pptable(struct smu_context *smu)
+{
+	struct smu_table_context *table_context = &smu->smu_table;
+	PPTable_beige_goby_t *pptable = table_context->driver_pptable;
+	int i;
+
+	dev_info(smu->adev->dev, "Dumped PPTable:\n");
+
+	dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
+	dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
+	dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
+
+	for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
+		dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
+		dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
+		dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
+		dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
+	}
+
+	for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
+		dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
+		dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
+	}
+
+	for (i = 0; i < TEMP_COUNT; i++) {
+		dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
+	}
+
+	dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
+	dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
+	dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
+	dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
+	dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
+
+	dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
+	for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
+		dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
+		dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
+	}
+	dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
+
+	dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
+
+	dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
+	dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
+	dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
+	dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
+
+	dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
+
+	dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
+
+	dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
+	dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
+	dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
+	dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
+
+	dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
+	dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
+
+	dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
+	dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
+	dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
+	dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
+	dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
+	dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
+	dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
+	dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
+
+	dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
+			pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
+
+	dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
+			pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
+
+	dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_UCLK].Padding,
+			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
+			pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
+
+	dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_FCLK].Padding,
+			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
+			pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
+
+	dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
+			pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
+
+	dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
+			pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
+
+	dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
+			pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
+
+	dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
+			"  .VoltageMode          = 0x%02x\n"
+			"  .SnapToDiscrete       = 0x%02x\n"
+			"  .NumDiscreteLevels    = 0x%02x\n"
+			"  .padding              = 0x%02x\n"
+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+			"  .SsFmin               = 0x%04x\n"
+			"  .Padding_16           = 0x%04x\n",
+			pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
+			pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
+
+	dev_info(smu->adev->dev, "FreqTableGfx\n");
+	for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
+
+	dev_info(smu->adev->dev, "FreqTableVclk\n");
+	for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
+
+	dev_info(smu->adev->dev, "FreqTableDclk\n");
+	for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
+
+	dev_info(smu->adev->dev, "FreqTableSocclk\n");
+	for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
+
+	dev_info(smu->adev->dev, "FreqTableUclk\n");
+	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
+
+	dev_info(smu->adev->dev, "FreqTableFclk\n");
+	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
+
+	dev_info(smu->adev->dev, "DcModeMaxFreq\n");
+	dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
+	dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
+	dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
+	dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
+	dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
+	dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
+	dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
+	dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
+
+	dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
+	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
+
+	dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
+	dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
+
+	dev_info(smu->adev->dev, "Mp0clkFreq\n");
+	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
+
+	dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
+	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
+
+	dev_info(smu->adev->dev, "MemVddciVoltage\n");
+	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
+
+	dev_info(smu->adev->dev, "MemMvddVoltage\n");
+	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
+
+	dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
+	dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
+	dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
+	dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
+	dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
+
+	dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
+
+	dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
+	dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
+	dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
+	dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
+	dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
+	dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
+	dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
+	dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
+	dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
+	dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
+	dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
+
+	dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
+	dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
+	dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
+	dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
+	dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
+	dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
+
+	dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
+	dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
+	dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
+	dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
+	dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
+
+	dev_info(smu->adev->dev, "FlopsPerByteTable\n");
+	for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
+
+	dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
+	dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
+	dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
+	dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
+
+	dev_info(smu->adev->dev, "UclkDpmPstates\n");
+	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
+
+	dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
+	dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
+		pptable->UclkDpmSrcFreqRange.Fmin);
+	dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
+		pptable->UclkDpmSrcFreqRange.Fmax);
+	dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
+	dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
+		pptable->UclkDpmTargFreqRange.Fmin);
+	dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
+		pptable->UclkDpmTargFreqRange.Fmax);
+	dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
+	dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
+
+	dev_info(smu->adev->dev, "PcieGenSpeed\n");
+	for (i = 0; i < NUM_LINK_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
+
+	dev_info(smu->adev->dev, "PcieLaneCount\n");
+	for (i = 0; i < NUM_LINK_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
+
+	dev_info(smu->adev->dev, "LclkFreq\n");
+	for (i = 0; i < NUM_LINK_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
+
+	dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
+	dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
+
+	dev_info(smu->adev->dev, "FanGain\n");
+	for (i = 0; i < TEMP_COUNT; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
+
+	dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
+	dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
+	dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
+	dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
+	dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
+	dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
+	dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
+	dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
+	dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
+	dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
+	dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
+	dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
+
+	dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
+	dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
+	dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
+	dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
+
+	dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
+	dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
+	dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
+	dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
+
+	dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
+			pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
+			pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
+	dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
+			pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
+			pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
+	dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->dBtcGbGfxPll.a,
+			pptable->dBtcGbGfxPll.b,
+			pptable->dBtcGbGfxPll.c);
+	dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->dBtcGbGfxDfll.a,
+			pptable->dBtcGbGfxDfll.b,
+			pptable->dBtcGbGfxDfll.c);
+	dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->dBtcGbSoc.a,
+			pptable->dBtcGbSoc.b,
+			pptable->dBtcGbSoc.c);
+	dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
+			pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
+			pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
+	dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
+			pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
+			pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
+
+	dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
+	for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
+		dev_info(smu->adev->dev, "		Fset[%d] = 0x%x\n",
+			i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
+		dev_info(smu->adev->dev, "		Vdroop[%d] = 0x%x\n",
+			i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
+	}
+
+	dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
+	dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
+
+	dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
+	dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
+
+	dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
+	dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
+	dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
+	dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
+
+	dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
+	dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
+	dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
+	dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
+
+	dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
+	dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
+
+	dev_info(smu->adev->dev, "XgmiDpmPstates\n");
+	for (i = 0; i < NUM_XGMI_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
+	dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
+	dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
+
+	dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
+	dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->ReservedEquation0.a,
+			pptable->ReservedEquation0.b,
+			pptable->ReservedEquation0.c);
+	dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->ReservedEquation1.a,
+			pptable->ReservedEquation1.b,
+			pptable->ReservedEquation1.c);
+	dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->ReservedEquation2.a,
+			pptable->ReservedEquation2.b,
+			pptable->ReservedEquation2.c);
+	dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
+			pptable->ReservedEquation3.a,
+			pptable->ReservedEquation3.b,
+			pptable->ReservedEquation3.c);
+
+	dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
+	dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
+	dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
+	dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
+	dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
+	dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
+	dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
+	dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
+
+	dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
+	dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
+	dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
+	dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
+	dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
+	dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
+
+	for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
+		dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
+		dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
+				pptable->I2cControllers[i].Enabled);
+		dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
+				pptable->I2cControllers[i].Speed);
+		dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
+				pptable->I2cControllers[i].SlaveAddress);
+		dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
+				pptable->I2cControllers[i].ControllerPort);
+		dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
+				pptable->I2cControllers[i].ControllerName);
+		dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
+				pptable->I2cControllers[i].ThermalThrotter);
+		dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
+				pptable->I2cControllers[i].I2cProtocol);
+		dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
+				pptable->I2cControllers[i].PaddingConfig);
+	}
+
+	dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
+	dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
+	dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
+	dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
+
+	dev_info(smu->adev->dev, "Board Parameters:\n");
+	dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
+	dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
+	dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
+	dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
+	dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
+	dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
+	dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
+	dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
+
+	dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
+	dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
+	dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
+
+	dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
+	dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
+	dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
+
+	dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
+	dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
+	dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
+
+	dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
+	dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
+	dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
+
+	dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
+
+	dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
+	dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
+	dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
+	dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
+	dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
+	dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
+	dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
+	dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
+	dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
+	dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
+	dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
+	dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
+	dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
+	dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
+	dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
+	dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
+
+	dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
+	dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
+	dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
+
+	dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
+	dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
+	dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
+
+	dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
+	dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
+
+	dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
+	dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
+	dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
+
+	dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
+	dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
+	dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
+	dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
+	dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
+
+	dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
+	dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
+
+	dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
+	dev_info(smu->adev->dev, "XgmiLinkWidth\n");
+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
+	dev_info(smu->adev->dev, "XgmiFclkFreq\n");
+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
+	dev_info(smu->adev->dev, "XgmiSocVoltage\n");
+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+		dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
+
+	dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
+	dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
+	dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
+	dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
+
+	dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
+	dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
+	dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
+	dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
+	dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
+	dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
+	dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
+	dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
+	dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
+	dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
+	dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
+
+	dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
+	dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
+	dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
+	dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
+	dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
+	dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
+	dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
+	dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
+}
+
 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	PPTable_t *pptable = table_context->driver_pptable;
 	int i;
 
+	if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
+		beige_goby_dump_pptable(smu);
+		return;
+	}
+
 	dev_info(smu->adev->dev, "Dumped PPTable:\n");
 
 	dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
@@ -2950,8 +3673,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
 					      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v1_3 *gpu_metrics =
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetricsExternal_t metrics_external;
 	SmuMetrics_t *metrics =
 		&(metrics_external.SmuMetrics);
@@ -2965,7 +3688,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
 	gpu_metrics->temperature_edge = metrics->TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
@@ -3000,6 +3723,9 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
 
 	gpu_metrics->throttle_status = metrics->ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics->ThrottlerStatus,
+							   sienna_cichlid_throttler_map);
 
 	gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
 
@@ -3022,7 +3748,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
 
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 
 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
@@ -3202,11 +3928,11 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
 	.register_irq_handler = smu_v11_0_register_irq_handler,
 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-	.baco_is_support= sienna_cichlid_is_baco_supported,
+	.baco_is_support = smu_v11_0_baco_is_support,
 	.baco_get_state = smu_v11_0_baco_get_state,
 	.baco_set_state = smu_v11_0_baco_set_state,
-	.baco_enter = smu_v11_0_baco_enter,
-	.baco_exit = smu_v11_0_baco_exit,
+	.baco_enter = sienna_cichlid_baco_enter,
+	.baco_exit = sienna_cichlid_baco_exit,
 	.mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
 	.mode1_reset = smu_v11_0_mode1_reset,
 	.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 6274cae4a065..388c5cb5c647 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -63,6 +63,7 @@ MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
 
 #define SMU11_VOLTAGE_SCALE 4
 
@@ -115,6 +116,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
 	case CHIP_DIMGREY_CAVEFISH:
 		chip_name = "dimgrey_cavefish";
 		break;
+	case CHIP_BEIGE_GOBY:
+		chip_name = "beige_goby";
+		break;
 	default:
 		dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
 		return -EINVAL;
@@ -259,6 +263,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
 	case CHIP_DIMGREY_CAVEFISH:
 		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
 		break;
+	case CHIP_BEIGE_GOBY:
+		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
+		break;
 	default:
 		dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
@@ -729,7 +736,7 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 	 * display num currently
 	 */
 	if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
-	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
+	    adev->asic_type <= CHIP_BEIGE_GOBY)
 		return 0;
 
 	return smu_cmn_send_smc_msg_with_param(smu,
@@ -1121,6 +1128,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
 		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 			return 0;
@@ -1466,7 +1474,8 @@ int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
 	return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
 }
 
-static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
+int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
+				      enum smu_v11_0_baco_seq baco_seq)
 {
 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
 }
@@ -1475,7 +1484,7 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
 {
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
 
-	if (!smu_baco->platform_support)
+	if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
 		return false;
 
 	/* Arcturus does not support this bit mask */
@@ -1531,7 +1540,8 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
 								      NULL);
 			break;
 		default:
-			if (!ras || !ras->supported || adev->gmc.xgmi.pending_reset) {
+			if (!ras || !adev->ras_enabled ||
+			    adev->gmc.xgmi.pending_reset) {
 				if (adev->asic_type == CHIP_ARCTURUS) {
 					data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
 					data |= 0x80000000;
@@ -1569,16 +1579,8 @@ out:
 
 int smu_v11_0_baco_enter(struct smu_context *smu)
 {
-	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
 
-	/* Arcturus does not need this audio workaround */
-	if (adev->asic_type != CHIP_ARCTURUS) {
-		ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
-		if (ret)
-			return ret;
-	}
-
 	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 77f532a49e37..18681dc458da 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -190,6 +190,20 @@ static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT]
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t vangogh_throttler_map[] = {
+	[THROTTLER_STATUS_BIT_SPL]	= (SMU_THROTTLER_SPL_BIT),
+	[THROTTLER_STATUS_BIT_FPPT]	= (SMU_THROTTLER_FPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT]	= (SMU_THROTTLER_SPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT_APU]	= (SMU_THROTTLER_SPPT_APU_BIT),
+	[THROTTLER_STATUS_BIT_THM_CORE]	= (SMU_THROTTLER_TEMP_CORE_BIT),
+	[THROTTLER_STATUS_BIT_THM_GFX]	= (SMU_THROTTLER_TEMP_GPU_BIT),
+	[THROTTLER_STATUS_BIT_THM_SOC]	= (SMU_THROTTLER_TEMP_SOC_BIT),
+	[THROTTLER_STATUS_BIT_TDC_VDD]	= (SMU_THROTTLER_TDC_VDD_BIT),
+	[THROTTLER_STATUS_BIT_TDC_SOC]	= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_STATUS_BIT_TDC_GFX]	= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_STATUS_BIT_TDC_CVIP]	= (SMU_THROTTLER_TDC_CVIP_BIT),
+};
+
 static int vangogh_tables_init(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
@@ -226,7 +240,7 @@ static int vangogh_tables_init(struct smu_context *smu)
 		goto err0_out;
 	smu_table->metrics_time = 0;
 
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table)
 		goto err1_out;
@@ -1632,8 +1646,8 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v2_1 *gpu_metrics =
-		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v2_2 *gpu_metrics =
+		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
 	SmuMetrics_legacy_t metrics;
 	int ret = 0;
 
@@ -1641,7 +1655,7 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 
 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 	gpu_metrics->temperature_soc = metrics.SocTemperature;
@@ -1674,20 +1688,23 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   vangogh_throttler_map);
 
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v2_1);
+	return sizeof(struct gpu_metrics_v2_2);
 }
 
 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v2_1 *gpu_metrics =
-		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v2_2 *gpu_metrics =
+		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int ret = 0;
 
@@ -1695,7 +1712,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 
 	gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
 	gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
@@ -1735,12 +1752,15 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
 
 	gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
+							   vangogh_throttler_map);
 
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v2_1);
+	return sizeof(struct gpu_metrics_v2_2);
 }
 
 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
@@ -2051,7 +2071,10 @@ static int vangogh_mode2_reset(struct smu_context *smu)
 	return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
 }
 
-static int vangogh_get_power_limit(struct smu_context *smu)
+static int vangogh_get_power_limit(struct smu_context *smu,
+				   uint32_t *current_power_limit,
+				   uint32_t *default_power_limit,
+				   uint32_t *max_power_limit)
 {
 	struct smu_11_5_power_context *power_context =
 								smu->smu_power.power_context;
@@ -2067,8 +2090,12 @@ static int vangogh_get_power_limit(struct smu_context *smu)
 		return ret;
 	}
 	/* convert from milliwatt to watt */
-	smu->current_power_limit = smu->default_power_limit = ppt_limit / 1000;
-	smu->max_power_limit = 29;
+	if (current_power_limit)
+		*current_power_limit = ppt_limit / 1000;
+	if (default_power_limit)
+		*default_power_limit = ppt_limit / 1000;
+	if (max_power_limit)
+		*max_power_limit = 29;
 
 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
 	if (ret) {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index f43b4c623685..9a9c24a6ec35 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -109,6 +109,8 @@ static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
 	CLK_MAP(SOCCLK, CLOCK_SOCCLK),
 	CLK_MAP(UCLK, CLOCK_FCLK),
 	CLK_MAP(MCLK, CLOCK_FCLK),
+	CLK_MAP(VCLK, CLOCK_VCLK),
+	CLK_MAP(DCLK, CLOCK_DCLK),
 };
 
 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
@@ -126,6 +128,22 @@ static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] =
 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t renoir_throttler_map[] = {
+	[THROTTLER_STATUS_BIT_SPL]		= (SMU_THROTTLER_SPL_BIT),
+	[THROTTLER_STATUS_BIT_FPPT]		= (SMU_THROTTLER_FPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT]		= (SMU_THROTTLER_SPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT_APU]		= (SMU_THROTTLER_SPPT_APU_BIT),
+	[THROTTLER_STATUS_BIT_THM_CORE]		= (SMU_THROTTLER_TEMP_CORE_BIT),
+	[THROTTLER_STATUS_BIT_THM_GFX]		= (SMU_THROTTLER_TEMP_GPU_BIT),
+	[THROTTLER_STATUS_BIT_THM_SOC]		= (SMU_THROTTLER_TEMP_SOC_BIT),
+	[THROTTLER_STATUS_BIT_TDC_VDD]		= (SMU_THROTTLER_TDC_VDD_BIT),
+	[THROTTLER_STATUS_BIT_TDC_SOC]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_STATUS_BIT_PROCHOT_CPU]	= (SMU_THROTTLER_PROCHOT_CPU_BIT),
+	[THROTTLER_STATUS_BIT_PROCHOT_GFX]	= (SMU_THROTTLER_PROCHOT_GFX_BIT),
+	[THROTTLER_STATUS_BIT_EDC_CPU]		= (SMU_THROTTLER_EDC_CPU_BIT),
+	[THROTTLER_STATUS_BIT_EDC_GFX]		= (SMU_THROTTLER_EDC_GFX_BIT),
+};
+
 static int renoir_init_smc_tables(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
@@ -151,7 +169,7 @@ static int renoir_init_smc_tables(struct smu_context *smu)
 	if (!smu_table->watermarks_table)
 		goto err2_out;
 
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table)
 		goto err3_out;
@@ -202,6 +220,17 @@ static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type
 			return -EINVAL;
 		*freq = clk_table->FClocks[dpm_level].Freq;
 		break;
+	case SMU_VCLK:
+		if (dpm_level >= NUM_VCN_DPM_LEVELS)
+			return -EINVAL;
+		*freq = clk_table->VClocks[dpm_level].Freq;
+		break;
+	case SMU_DCLK:
+		if (dpm_level >= NUM_VCN_DPM_LEVELS)
+			return -EINVAL;
+		*freq = clk_table->DClocks[dpm_level].Freq;
+		break;
+
 	default:
 		return -EINVAL;
 	}
@@ -532,6 +561,14 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 		count = NUM_FCLK_DPM_LEVELS;
 		cur_value = metrics.ClockFrequency[CLOCK_FCLK];
 		break;
+	case SMU_VCLK:
+		count = NUM_VCN_DPM_LEVELS;
+		cur_value = metrics.ClockFrequency[CLOCK_VCLK];
+		break;
+	case SMU_DCLK:
+		count = NUM_VCN_DPM_LEVELS;
+		cur_value = metrics.ClockFrequency[CLOCK_DCLK];
+		break;
 	default:
 		break;
 	}
@@ -543,6 +580,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 	case SMU_MCLK:
 	case SMU_DCEFCLK:
 	case SMU_FCLK:
+	case SMU_VCLK:
+	case SMU_DCLK:
 		for (i = 0; i < count; i++) {
 			ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
 			if (ret)
@@ -730,6 +769,16 @@ static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks
 		clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
 	}
 
+	for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
+		clock_table->VClocks[i].Freq = table->VClocks[i].Freq;
+		clock_table->VClocks[i].Vol = table->VClocks[i].Vol;
+	}
+
+	for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
+		clock_table->DClocks[i].Freq = table->DClocks[i].Freq;
+		clock_table->DClocks[i].Vol = table->DClocks[i].Vol;
+	}
+
 	return 0;
 }
 
@@ -1131,6 +1180,28 @@ static int renoir_get_smu_metrics_data(struct smu_context *smu,
 	case METRICS_VOLTAGE_VDDSOC:
 		*value = metrics->Voltage[1];
 		break;
+	case METRICS_SS_APU_SHARE:
+		/* return the percentage of APU power with respect to APU's power limit.
+		 * percentage is reported, this isn't boost value. Smartshift power
+		 * boost/shift is only when the percentage is more than 100.
+		 */
+		if (metrics->StapmOriginalLimit > 0)
+			*value =  (metrics->ApuPower * 100) / metrics->StapmOriginalLimit;
+		else
+			*value = 0;
+		break;
+	case METRICS_SS_DGPU_SHARE:
+		/* return the percentage of dGPU power with respect to dGPU's power limit.
+		 * percentage is reported, this isn't boost value. Smartshift power
+		 * boost/shift is only when the percentage is more than 100.
+		 */
+		if ((metrics->dGpuPower > 0) &&
+		    (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit))
+			*value = (metrics->dGpuPower * 100) /
+				  (metrics->StapmCurrentLimit - metrics->StapmOriginalLimit);
+		else
+			*value = 0;
+		break;
 	default:
 		*value = UINT_MAX;
 		break;
@@ -1202,6 +1273,18 @@ static int renoir_read_sensor(struct smu_context *smu,
 						  (uint32_t *)data);
 		*size = 4;
 		break;
+	case AMDGPU_PP_SENSOR_SS_APU_SHARE:
+		ret = renoir_get_smu_metrics_data(smu,
+						  METRICS_SS_APU_SHARE,
+						  (uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
+		ret = renoir_get_smu_metrics_data(smu,
+						  METRICS_SS_DGPU_SHARE,
+						  (uint32_t *)data);
+		*size = 4;
+		break;
 	default:
 		ret = -EOPNOTSUPP;
 		break;
@@ -1231,8 +1314,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v2_1 *gpu_metrics =
-		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v2_2 *gpu_metrics =
+		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int ret = 0;
 
@@ -1240,7 +1323,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 
 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 	gpu_metrics->temperature_soc = metrics.SocTemperature;
@@ -1278,6 +1361,9 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+		smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+						   renoir_throttler_map);
 
 	gpu_metrics->fan_pwm = metrics.FanPwm;
 
@@ -1285,7 +1371,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
 
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v2_1);
+	return sizeof(struct gpu_metrics_v2_2);
 }
 
 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
index 652b4e554378..9b3a8503f5cd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
@@ -23,7 +23,7 @@
 # Makefile for the 'smu manager' sub-component of powerplay.
 # It provides the smu management services for the driver.
 
-SMU13_MGR = smu_v13_0.o aldebaran_ppt.o
+SMU13_MGR = smu_v13_0.o aldebaran_ppt.o smu_v13_0_1.o yellow_carp_ppt.o
 
 AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR))
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index dcbe3a72da09..9316a726195c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -78,7 +78,11 @@
 
 #define smnPCIE_ESM_CTRL			0x111003D0
 
-#define CLOCK_VALID (1 << 31)
+static const struct smu_temperature_range smu13_thermal_policy[] =
+{
+	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
+	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
+};
 
 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),
@@ -187,6 +191,20 @@ static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 	TAB_MAP(I2C_COMMANDS),
 };
 
+static const uint8_t aldebaran_throttler_map[] = {
+	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
+	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
+	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_TDC_HBM_BIT]		= (SMU_THROTTLER_TDC_MEM_BIT),
+	[THROTTLER_TEMP_GPU_BIT]	= (SMU_THROTTLER_TEMP_GPU_BIT),
+	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
+	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+	[THROTTLER_TEMP_VR_MEM_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
+};
+
 static int aldebaran_tables_init(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
@@ -209,7 +227,7 @@ static int aldebaran_tables_init(struct smu_context *smu)
 		return -ENOMEM;
 	smu_table->metrics_time = 0;
 
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table) {
 		kfree(smu_table->metrics_table);
@@ -351,13 +369,6 @@ static int aldebaran_check_powerplay_table(struct smu_context *smu)
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_13_0_powerplay_table *powerplay_table =
 		table_context->power_play_table;
-	struct smu_baco_context *smu_baco = &smu->smu_baco;
-
-	mutex_lock(&smu_baco->mutex);
-	if (powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
-	mutex_unlock(&smu_baco->mutex);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
@@ -455,12 +466,18 @@ static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 
 	pstate_table->gfxclk_pstate.min = gfx_table->min;
 	pstate_table->gfxclk_pstate.peak = gfx_table->max;
+	pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
+	pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
 
 	pstate_table->uclk_pstate.min = mem_table->min;
 	pstate_table->uclk_pstate.peak = mem_table->max;
+	pstate_table->uclk_pstate.curr.min = mem_table->min;
+	pstate_table->uclk_pstate.curr.max = mem_table->max;
 
 	pstate_table->socclk_pstate.min = soc_table->min;
 	pstate_table->socclk_pstate.peak = soc_table->max;
+	pstate_table->socclk_pstate.curr.min = soc_table->min;
+	pstate_table->socclk_pstate.curr.max = soc_table->max;
 
 	if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 	    mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
@@ -507,6 +524,16 @@ static int aldebaran_freqs_in_same_level(int32_t frequency1,
 	return (abs(frequency1 - frequency2) <= EPSILON);
 }
 
+static bool aldebaran_is_primary(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+
+	if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
+		return adev->smuio.funcs->get_die_id(adev) == 0;
+
+	return true;
+}
+
 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 					  MetricsMember_t member,
 					  uint32_t *value)
@@ -560,7 +587,10 @@ static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 		*value = metrics->AverageUclkActivity;
 		break;
 	case METRICS_AVERAGE_SOCKETPOWER:
-		*value = metrics->AverageSocketPower << 8;
+		/* Valid power data is available only from primary die */
+		*value = aldebaran_is_primary(smu) ?
+				 metrics->AverageSocketPower << 8 :
+				 0;
 		break;
 	case METRICS_TEMPERATURE_EDGE:
 		*value = metrics->TemperatureEdge *
@@ -669,6 +699,7 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
 {
 	int i, now, size = 0;
 	int ret = 0;
+	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 	struct pp_clock_levels_with_latency clocks;
 	struct smu_13_0_dpm_table *single_dpm_table;
 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
@@ -703,12 +734,8 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
 
 		display_levels = clocks.num_levels;
 
-		min_clk = smu->gfx_actual_hard_min_freq & CLOCK_VALID ?
-				  smu->gfx_actual_hard_min_freq & ~CLOCK_VALID :
-				  single_dpm_table->dpm_levels[0].value;
-		max_clk = smu->gfx_actual_soft_max_freq & CLOCK_VALID ?
-				  smu->gfx_actual_soft_max_freq & ~CLOCK_VALID :
-				  single_dpm_table->dpm_levels[1].value;
+		min_clk = pstate_table->gfxclk_pstate.curr.min;
+		max_clk = pstate_table->gfxclk_pstate.curr.max;
 
 		freq_values[0] = min_clk;
 		freq_values[1] = max_clk;
@@ -815,6 +842,52 @@ static int aldebaran_print_clk_levels(struct smu_context *smu,
 								       now) ? "*" : ""));
 		break;
 
+	case SMU_VCLK:
+		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
+			return ret;
+		}
+
+		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
+		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
+			return ret;
+		}
+
+		for (i = 0; i < single_dpm_table->count; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+					i, single_dpm_table->dpm_levels[i].value,
+					(clocks.num_levels == 1) ? "*" :
+					(aldebaran_freqs_in_same_level(
+								       clocks.data[i].clocks_in_khz / 1000,
+								       now) ? "*" : ""));
+		break;
+
+	case SMU_DCLK:
+		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
+			return ret;
+		}
+
+		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
+		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
+		if (ret) {
+			dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
+			return ret;
+		}
+
+		for (i = 0; i < single_dpm_table->count; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+					i, single_dpm_table->dpm_levels[i].value,
+					(clocks.num_levels == 1) ? "*" :
+					(aldebaran_freqs_in_same_level(
+								       clocks.data[i].clocks_in_khz / 1000,
+								       now) ? "*" : ""));
+		break;
+
 	default:
 		break;
 	}
@@ -1086,7 +1159,10 @@ static int aldebaran_read_sensor(struct smu_context *smu,
 	return ret;
 }
 
-static int aldebaran_get_power_limit(struct smu_context *smu)
+static int aldebaran_get_power_limit(struct smu_context *smu,
+				     uint32_t *current_power_limit,
+				     uint32_t *default_power_limit,
+				     uint32_t *max_power_limit)
 {
 	PPTable_t *pptable = smu->smu_table.driver_pptable;
 	uint32_t power_limit = 0;
@@ -1095,24 +1171,46 @@ static int aldebaran_get_power_limit(struct smu_context *smu)
 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 		return -EINVAL;
 
-	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
+	/* Valid power data is available only from primary die.
+	 * For secondary die show the value as 0.
+	 */
+	if (aldebaran_is_primary(smu)) {
+		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
+					   &power_limit);
 
-	if (ret) {
-		/* the last hope to figure out the ppt limit */
-		if (!pptable) {
-			dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
-			return -EINVAL;
+		if (ret) {
+			/* the last hope to figure out the ppt limit */
+			if (!pptable) {
+				dev_err(smu->adev->dev,
+					"Cannot get PPT limit due to pptable missing!");
+				return -EINVAL;
+			}
+			power_limit = pptable->PptLimit;
 		}
-		power_limit = pptable->PptLimit;
 	}
 
-	smu->current_power_limit = smu->default_power_limit = power_limit;
-	if (pptable)
-		smu->max_power_limit = pptable->PptLimit;
+	if (current_power_limit)
+		*current_power_limit = power_limit;
+	if (default_power_limit)
+		*default_power_limit = power_limit;
+
+	if (max_power_limit) {
+		if (pptable)
+			*max_power_limit = pptable->PptLimit;
+	}
 
 	return 0;
 }
 
+static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n)
+{
+	/* Power limit can be set only through primary die */
+	if (aldebaran_is_primary(smu))
+		return smu_v13_0_set_power_limit(smu, n);
+
+	return -EINVAL;
+}
+
 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
 {
 	int ret;
@@ -1128,15 +1226,17 @@ static int aldebaran_set_performance_level(struct smu_context *smu,
 					   enum amd_dpm_forced_level level)
 {
 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
+	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+	struct smu_13_0_dpm_table *gfx_table =
+		&dpm_context->dpm_tables.gfx_table;
+	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 
 	/* Disable determinism if switching to another mode */
-	if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
-			&& (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
+	if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
+	    (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
 		smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
-
-	/* Reset user min/max gfx clock */
-	smu->gfx_actual_hard_min_freq = 0;
-	smu->gfx_actual_soft_max_freq = 0;
+		pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
+	}
 
 	switch (level) {
 
@@ -1163,6 +1263,7 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
 {
 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 	struct amdgpu_device *adev = smu->adev;
 	uint32_t min_clk;
 	uint32_t max_clk;
@@ -1176,15 +1277,23 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
 		return -EINVAL;
 
 	if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-		min_clk = max(min, dpm_context->dpm_tables.gfx_table.min);
-		max_clk = min(max, dpm_context->dpm_tables.gfx_table.max);
-		ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
-							    min_clk, max_clk);
+		if (min >= max) {
+			dev_err(smu->adev->dev,
+				"Minimum GFX clk should be less than the maximum allowed clock\n");
+			return -EINVAL;
+		}
 
+		if ((min == pstate_table->gfxclk_pstate.curr.min) &&
+		    (max == pstate_table->gfxclk_pstate.curr.max))
+			return 0;
+
+		ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
+							    min, max);
 		if (!ret) {
-			smu->gfx_actual_hard_min_freq = min_clk | CLOCK_VALID;
-			smu->gfx_actual_soft_max_freq = max_clk | CLOCK_VALID;
+			pstate_table->gfxclk_pstate.curr.min = min;
+			pstate_table->gfxclk_pstate.curr.max = max;
 		}
+
 		return ret;
 	}
 
@@ -1209,10 +1318,8 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
 				dev_err(adev->dev,
 						"Failed to enable determinism at GFX clock %d MHz\n", max);
 			} else {
-				smu->gfx_actual_hard_min_freq =
-					min_clk | CLOCK_VALID;
-				smu->gfx_actual_soft_max_freq =
-					max | CLOCK_VALID;
+				pstate_table->gfxclk_pstate.curr.min = min_clk;
+				pstate_table->gfxclk_pstate.curr.max = max;
 			}
 		}
 	}
@@ -1225,6 +1332,7 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_
 {
 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 	uint32_t min_clk;
 	uint32_t max_clk;
 	int ret = 0;
@@ -1245,16 +1353,22 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_
 			if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
 				dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
 					input[1], dpm_context->dpm_tables.gfx_table.min);
+				pstate_table->gfxclk_pstate.custom.min =
+					pstate_table->gfxclk_pstate.curr.min;
 				return -EINVAL;
 			}
-			smu->gfx_actual_hard_min_freq = input[1];
+
+			pstate_table->gfxclk_pstate.custom.min = input[1];
 		} else if (input[0] == 1) {
 			if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
 				dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
 					input[1], dpm_context->dpm_tables.gfx_table.max);
+				pstate_table->gfxclk_pstate.custom.max =
+					pstate_table->gfxclk_pstate.curr.max;
 				return -EINVAL;
 			}
-			smu->gfx_actual_soft_max_freq = input[1];
+
+			pstate_table->gfxclk_pstate.custom.max = input[1];
 		} else {
 			return -EINVAL;
 		}
@@ -1276,8 +1390,17 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_
 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
 			return -EINVAL;
 		} else {
-			min_clk = smu->gfx_actual_hard_min_freq;
-			max_clk = smu->gfx_actual_soft_max_freq;
+			if (!pstate_table->gfxclk_pstate.custom.min)
+				pstate_table->gfxclk_pstate.custom.min =
+					pstate_table->gfxclk_pstate.curr.min;
+
+			if (!pstate_table->gfxclk_pstate.custom.max)
+				pstate_table->gfxclk_pstate.custom.max =
+					pstate_table->gfxclk_pstate.curr.max;
+
+			min_clk = pstate_table->gfxclk_pstate.custom.min;
+			max_clk = pstate_table->gfxclk_pstate.custom.max;
+
 			return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
 		}
 		break;
@@ -1290,10 +1413,13 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_
 
 static bool aldebaran_is_dpm_running(struct smu_context *smu)
 {
-	int ret = 0;
+	int ret;
 	uint32_t feature_mask[2];
 	unsigned long feature_enabled;
+
 	ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
+	if (ret)
+		return false;
 	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 					  ((uint64_t)feature_mask[1] << 32));
 	return !!(feature_enabled & SMC_DPM_FEATURE);
@@ -1632,8 +1758,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
 					 void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+	struct gpu_metrics_v1_3 *gpu_metrics =
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int i, ret = 0;
 
@@ -1643,7 +1769,7 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
 	if (ret)
 		return ret;
 
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -1656,8 +1782,16 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
 	gpu_metrics->average_mm_activity = 0;
 
-	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
-	gpu_metrics->energy_accumulator = 0;
+	/* Valid power data is available only from primary die */
+	if (aldebaran_is_primary(smu)) {
+		gpu_metrics->average_socket_power = metrics.AverageSocketPower;
+		gpu_metrics->energy_accumulator =
+			(uint64_t)metrics.EnergyAcc64bitHigh << 32 |
+			metrics.EnergyAcc64bitLow;
+	} else {
+		gpu_metrics->average_socket_power = 0;
+		gpu_metrics->energy_accumulator = 0;
+	}
 
 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
@@ -1672,6 +1806,9 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   aldebaran_throttler_map);
 
 	gpu_metrics->current_fan_speed = 0;
 
@@ -1688,9 +1825,12 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
 	for (i = 0; i < NUM_HBM_INSTANCES; i++)
 		gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
 
+	gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
+					metrics.TimeStampLow;
+
 	*table = (void *)gpu_metrics;
 
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 
 static int aldebaran_mode2_reset(struct smu_context *smu)
@@ -1779,10 +1919,22 @@ static int aldebaran_set_mp1_state(struct smu_context *smu,
 	case PP_MP1_STATE_UNLOAD:
 		return smu_cmn_set_mp1_state(smu, mp1_state);
 	default:
-		return -EINVAL;
+		return 0;
 	}
+}
 
-	return 0;
+static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
+		uint32_t size)
+{
+	int ret = 0;
+
+	/* message SMU to update the bad page number on SMUBUS */
+	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
+	if (ret)
+		dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
+				__func__);
+
+	return ret;
 }
 
 static const struct pptable_funcs aldebaran_ppt_funcs = {
@@ -1821,7 +1973,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
 	.get_enabled_mask = smu_cmn_get_enabled_mask,
 	.feature_is_enabled = smu_cmn_feature_is_enabled,
 	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
-	.set_power_limit = smu_v13_0_set_power_limit,
+	.set_power_limit = aldebaran_set_power_limit,
 	.init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
 	.enable_thermal_alert = smu_v13_0_enable_thermal_alert,
 	.disable_thermal_alert = smu_v13_0_disable_thermal_alert,
@@ -1847,6 +1999,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
 	.wait_for_event = smu_v13_0_wait_for_event,
 	.i2c_init = aldebaran_i2c_control_init,
 	.i2c_fini = aldebaran_i2c_control_fini,
+	.send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
 };
 
 void aldebaran_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0864083e7435..a3dc7194aaf8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1626,6 +1626,9 @@ int smu_v13_0_set_performance_level(struct smu_context *smu,
 							    sclk_max);
 		if (ret)
 			return ret;
+
+		pstate_table->gfxclk_pstate.curr.min = sclk_min;
+		pstate_table->gfxclk_pstate.curr.max = sclk_max;
 	}
 
 	if (mclk_min && mclk_max) {
@@ -1635,6 +1638,9 @@ int smu_v13_0_set_performance_level(struct smu_context *smu,
 							    mclk_max);
 		if (ret)
 			return ret;
+
+		pstate_table->uclk_pstate.curr.min = mclk_min;
+		pstate_table->uclk_pstate.curr.max = mclk_max;
 	}
 
 	if (socclk_min && socclk_max) {
@@ -1644,6 +1650,9 @@ int smu_v13_0_set_performance_level(struct smu_context *smu,
 							    socclk_max);
 		if (ret)
 			return ret;
+
+		pstate_table->socclk_pstate.curr.min = socclk_min;
+		pstate_table->socclk_pstate.curr.max = socclk_max;
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c
new file mode 100644
index 000000000000..61917b49f2bf
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+//#include <linux/reboot.h>
+
+#define SWSMU_CODE_LAYER_L3
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v13_0_1.h"
+#include "soc15_common.h"
+#include "smu_cmn.h"
+#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
+#include "amdgpu_atombios.h"
+#include "atom.h"
+
+#include "asic_reg/mp/mp_13_0_1_offset.h"
+#include "asic_reg/mp/mp_13_0_1_sh_mask.h"
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+int smu_v13_0_1_check_fw_status(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t mp1_fw_flags;
+
+	mp1_fw_flags = RREG32_PCIE(MP1_Public |
+				   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+
+	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
+		return 0;
+
+	return -EIO;
+}
+
+int smu_v13_0_1_check_fw_version(struct smu_context *smu)
+{
+	uint32_t if_version = 0xff, smu_version = 0xff;
+	uint16_t smu_major;
+	uint8_t smu_minor, smu_debug;
+	int ret = 0;
+
+	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
+	if (ret)
+		return ret;
+
+	smu_major = (smu_version >> 16) & 0xffff;
+	smu_minor = (smu_version >> 8) & 0xff;
+	smu_debug = (smu_version >> 0) & 0xff;
+
+	switch (smu->adev->asic_type) {
+	case CHIP_YELLOW_CARP:
+		smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP;
+		break;
+
+	default:
+		dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
+		smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_INV;
+		break;
+	}
+
+	dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
+			 smu_version, smu_major, smu_minor, smu_debug);
+
+	/*
+	 * 1. if_version mismatch is not critical as our fw is designed
+	 * to be backward compatible.
+	 * 2. New fw usually brings some optimizations. But that's visible
+	 * only on the paired driver.
+	 * Considering above, we just leave user a warning message instead
+	 * of halt driver loading.
+	 */
+	if (if_version != smu->smc_driver_if_version) {
+		dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
+			 "smu fw version = 0x%08x (%d.%d.%d)\n",
+			 smu->smc_driver_if_version, if_version,
+			 smu_version, smu_major, smu_minor, smu_debug);
+		dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
+	}
+
+	return ret;
+}
+
+int smu_v13_0_1_fini_smc_tables(struct smu_context *smu)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+
+	kfree(smu_table->clocks_table);
+	smu_table->clocks_table = NULL;
+
+	kfree(smu_table->metrics_table);
+	smu_table->metrics_table = NULL;
+
+	kfree(smu_table->watermarks_table);
+	smu_table->watermarks_table = NULL;
+
+	return 0;
+}
+
+static int smu_v13_0_1_atom_get_smu_clockinfo(struct amdgpu_device *adev,
+						uint8_t clk_id,
+						uint8_t syspll_id,
+						uint32_t *clk_freq)
+{
+	struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
+	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
+	int ret, index;
+
+	input.clk_id = clk_id;
+	input.syspll_id = syspll_id;
+	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+					    getsmuclockinfo);
+
+	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+					(uint32_t *)&input);
+	if (ret)
+		return -EINVAL;
+
+	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+	*clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
+	return 0;
+}
+
+int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu)
+{
+	int ret, index;
+	uint16_t size;
+	uint8_t frev, crev;
+	struct atom_common_table_header *header;
+	struct atom_firmware_info_v3_4 *v_3_4;
+	struct atom_firmware_info_v3_3 *v_3_3;
+	struct atom_firmware_info_v3_1 *v_3_1;
+
+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+					    firmwareinfo);
+
+	ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
+					     (uint8_t **)&header);
+	if (ret)
+		return ret;
+
+	if (header->format_revision != 3) {
+		dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
+		return -EINVAL;
+	}
+
+	switch (header->content_revision) {
+	case 0:
+	case 1:
+	case 2:
+		v_3_1 = (struct atom_firmware_info_v3_1 *)header;
+		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
+		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
+		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
+		smu->smu_table.boot_values.socclk = 0;
+		smu->smu_table.boot_values.dcefclk = 0;
+		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
+		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
+		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
+		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
+		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
+		break;
+	case 3:
+		v_3_3 = (struct atom_firmware_info_v3_3 *)header;
+		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
+		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
+		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
+		smu->smu_table.boot_values.socclk = 0;
+		smu->smu_table.boot_values.dcefclk = 0;
+		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
+		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
+		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
+		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
+		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
+		break;
+	case 4:
+	default:
+		v_3_4 = (struct atom_firmware_info_v3_4 *)header;
+		smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
+		smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
+		smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
+		smu->smu_table.boot_values.socclk = 0;
+		smu->smu_table.boot_values.dcefclk = 0;
+		smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
+		smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
+		smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
+		smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
+		smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
+		break;
+	}
+
+	smu->smu_table.boot_values.format_revision = header->format_revision;
+	smu->smu_table.boot_values.content_revision = header->content_revision;
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.socclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.dcefclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_ECLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.eclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_VCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.vclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_DCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.dclk);
+
+	if ((smu->smu_table.boot_values.format_revision == 3) &&
+	    (smu->smu_table.boot_values.content_revision >= 2))
+		smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+						(uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
+						(uint8_t)SMU11_SYSPLL1_2_ID,
+						&smu->smu_table.boot_values.fclk);
+
+	return 0;
+}
+
+int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+
+	return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+}
+
+int smu_v13_0_1_set_driver_table_location(struct smu_context *smu)
+{
+	struct smu_table *driver_table = &smu->smu_table.driver_table;
+	int ret = 0;
+
+	if (!driver_table->mc_address)
+		return 0;
+
+	ret = smu_cmn_send_smc_msg_with_param(smu,
+			SMU_MSG_SetDriverDramAddrHigh,
+			upper_32_bits(driver_table->mc_address),
+			NULL);
+
+	if (ret)
+		return ret;
+
+	ret = smu_cmn_send_smc_msg_with_param(smu,
+			SMU_MSG_SetDriverDramAddrLow,
+			lower_32_bits(driver_table->mc_address),
+			NULL);
+
+	return ret;
+}
+
+int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+	struct amdgpu_device *adev = smu->adev;
+
+	switch (adev->asic_type) {
+	case CHIP_YELLOW_CARP:
+		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
+			return 0;
+		if (enable)
+			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
+		else
+			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
new file mode 100644
index 000000000000..7664334d8144
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -0,0 +1,1244 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#define SWSMU_CODE_LAYER_L2
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v13_0_1.h"
+#include "smu13_driver_if_yellow_carp.h"
+#include "yellow_carp_ppt.h"
+#include "smu_v13_0_1_ppsmc.h"
+#include "smu_v13_0_1_pmfw.h"
+#include "smu_cmn.h"
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE ( \
+	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
+	FEATURE_MASK(FEATURE_VCN_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_FCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_LCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
+	FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+
+static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
+	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,			1),
+	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,		1),
+	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,		1),
+	MSG_MAP(EnableGfxOff,                   PPSMC_MSG_EnableGfxOff,			1),
+	MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,			1),
+	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,		1),
+	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,			1),
+	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,			1),
+	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,		1),
+	MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,		1),
+	MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,      1),
+	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,	1),
+	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,		1),
+	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,	1),
+	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,	1),
+	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,		1),
+	MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,	1),
+	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,	1),
+	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,		1),
+	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,		1),
+	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,		1),
+	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,		1),
+	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,		1),
+	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,	1),
+	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,		1),
+	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,		1),
+	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,	1),
+	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,		1),
+	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,			1),
+	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,		1),
+	MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,	1),
+};
+
+static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = {
+	FEA_MAP(CCLK_DPM),
+	FEA_MAP(FAN_CONTROLLER),
+	FEA_MAP(PPT),
+	FEA_MAP(TDC),
+	FEA_MAP(THERMAL),
+	FEA_MAP(ULV),
+	FEA_MAP(VCN_DPM),
+	FEA_MAP_REVERSE(FCLK),
+	FEA_MAP_REVERSE(SOCCLK),
+	FEA_MAP(LCLK_DPM),
+	FEA_MAP(SHUBCLK_DPM),
+	FEA_MAP(DCFCLK_DPM),
+	FEA_MAP_HALF_REVERSE(GFX),
+	FEA_MAP(DS_GFXCLK),
+	FEA_MAP(DS_SOCCLK),
+	FEA_MAP(DS_LCLK),
+	FEA_MAP(DS_DCFCLK),
+	FEA_MAP(DS_FCLK),
+	FEA_MAP(DS_MP1CLK),
+	FEA_MAP(DS_MP0CLK),
+	FEA_MAP(GFX_DEM),
+	FEA_MAP(PSI),
+	FEA_MAP(PROCHOT),
+	FEA_MAP(CPUOFF),
+	FEA_MAP(STAPM),
+	FEA_MAP(S0I3),
+	FEA_MAP(PERF_LIMIT),
+	FEA_MAP(CORE_DLDO),
+	FEA_MAP(RSMU_LOW_POWER),
+	FEA_MAP(SMN_LOW_POWER),
+	FEA_MAP(THM_LOW_POWER),
+	FEA_MAP(SMUIO_LOW_POWER),
+	FEA_MAP(MP1_LOW_POWER),
+	FEA_MAP(DS_VCN),
+	FEA_MAP(CPPC),
+	FEA_MAP(DF_CSTATES),
+	FEA_MAP(MSMU_LOW_POWER),
+	FEA_MAP(ATHUB_PG),
+};
+
+static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
+	TAB_MAP_VALID(WATERMARKS),
+	TAB_MAP_VALID(SMU_METRICS),
+	TAB_MAP_VALID(CUSTOM_DPM),
+	TAB_MAP_VALID(DPMCLOCKS),
+};
+
+static struct cmn2asic_mapping yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
+};
+	
+static int yellow_carp_init_smc_tables(struct smu_context *smu)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+	struct smu_table *tables = smu_table->tables;
+
+	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+
+	smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
+	if (!smu_table->clocks_table)
+		goto err0_out;
+
+	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+	if (!smu_table->metrics_table)
+		goto err1_out;
+	smu_table->metrics_time = 0;
+
+	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
+	if (!smu_table->watermarks_table)
+		goto err2_out;
+
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
+	if (!smu_table->gpu_metrics_table)
+		goto err3_out;
+
+	return 0;
+
+err3_out:
+	kfree(smu_table->watermarks_table);
+err2_out:
+	kfree(smu_table->metrics_table);
+err1_out:
+	kfree(smu_table->clocks_table);
+err0_out:
+	return -ENOMEM;
+}
+
+static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
+{
+	struct smu_feature *feature = &smu->smu_feature;
+	uint32_t feature_mask[2];
+	int ret = 0;
+
+	if (!en)
+		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
+
+	bitmap_zero(feature->enabled, feature->feature_num);
+	bitmap_zero(feature->supported, feature->feature_num);
+
+	if (!en)
+		return ret;
+
+	ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+	if (ret)
+		return ret;
+
+	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
+		    feature->feature_num);
+	bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
+		    feature->feature_num);
+
+	return 0;
+}
+
+static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+
+	/* vcn dpm on is a prerequisite for vcn power gate messages */
+	if (enable)
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
+						      0, NULL);
+	else
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
+						      0, NULL);
+
+	return ret;
+}
+
+static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+
+	if (enable)
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
+						      0, NULL);
+	else
+		ret = smu_cmn_send_smc_msg_with_param(smu,
+						      SMU_MSG_PowerDownJpeg, 0,
+						      NULL);
+
+	return ret;
+}
+
+
+static bool yellow_carp_is_dpm_running(struct smu_context *smu)
+{
+	int ret = 0;
+	uint32_t feature_mask[2];
+	uint64_t feature_enabled;
+
+	ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+
+	if (ret)
+		return false;
+
+	feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
+
+	return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
+static int yellow_carp_post_smu_init(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	int ret = 0;
+
+	/* allow message will be sent after enable message on Yellow Carp*/
+	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
+	if (ret)
+		dev_err(adev->dev, "Failed to Enable GfxOff!\n");
+	return ret;
+}
+
+static int yellow_carp_mode_reset(struct smu_context *smu, int type)
+{
+	int ret = 0, index = 0;
+
+	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
+				SMU_MSG_GfxDeviceDriverReset);
+	if (index < 0)
+		return index == -EACCES ? 0 : index;
+
+	mutex_lock(&smu->message_lock);
+
+	ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
+
+	mutex_unlock(&smu->message_lock);
+
+	mdelay(10);
+
+	return ret;
+}
+
+static int yellow_carp_mode2_reset(struct smu_context *smu)
+{
+	return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2);
+}
+
+static int yellow_carp_get_smu_metrics_data(struct smu_context *smu,
+							MetricsMember_t member,
+							uint32_t *value)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+
+	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
+	int ret = 0;
+
+	mutex_lock(&smu->metrics_lock);
+
+	ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
+	if (ret) {
+		mutex_unlock(&smu->metrics_lock);
+		return ret;
+	}
+
+	switch (member) {
+	case METRICS_AVERAGE_GFXCLK:
+		*value = metrics->GfxclkFrequency;
+		break;
+	case METRICS_AVERAGE_SOCCLK:
+		*value = metrics->SocclkFrequency;
+		break;
+	case METRICS_AVERAGE_VCLK:
+		*value = metrics->VclkFrequency;
+		break;
+	case METRICS_AVERAGE_DCLK:
+		*value = metrics->DclkFrequency;
+		break;
+	case METRICS_AVERAGE_UCLK:
+		*value = metrics->MemclkFrequency;
+		break;
+	case METRICS_AVERAGE_GFXACTIVITY:
+		*value = metrics->GfxActivity / 100;
+		break;
+	case METRICS_AVERAGE_VCNACTIVITY:
+		*value = metrics->UvdActivity;
+		break;
+	case METRICS_AVERAGE_SOCKETPOWER:
+		*value = (metrics->CurrentSocketPower << 8) / 1000;
+		break;
+	case METRICS_TEMPERATURE_EDGE:
+		*value = metrics->GfxTemperature / 100 *
+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+		break;
+	case METRICS_TEMPERATURE_HOTSPOT:
+		*value = metrics->SocTemperature / 100 *
+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+		break;
+	case METRICS_THROTTLER_STATUS:
+		*value = metrics->ThrottlerStatus;
+		break;
+	case METRICS_VOLTAGE_VDDGFX:
+		*value = metrics->Voltage[0];
+		break;
+	case METRICS_VOLTAGE_VDDSOC:
+		*value = metrics->Voltage[1];
+		break;
+	case METRICS_SS_APU_SHARE:
+		/* return the percentage of APU power with respect to APU's power limit.
+		 * percentage is reported, this isn't boost value. Smartshift power
+		 * boost/shift is only when the percentage is more than 100.
+		 */
+		if (metrics->StapmOpnLimit > 0)
+			*value =  (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
+		else
+			*value = 0;
+		break;
+	case METRICS_SS_DGPU_SHARE:
+		/* return the percentage of dGPU power with respect to dGPU's power limit.
+		 * percentage is reported, this isn't boost value. Smartshift power
+		 * boost/shift is only when the percentage is more than 100.
+		 */
+		if ((metrics->dGpuPower > 0) &&
+		    (metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
+			*value = (metrics->dGpuPower * 100) /
+				  (metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
+		else
+			*value = 0;
+		break;
+	default:
+		*value = UINT_MAX;
+		break;
+	}
+
+	mutex_unlock(&smu->metrics_lock);
+
+	return ret;
+}
+
+static int yellow_carp_read_sensor(struct smu_context *smu,
+					enum amd_pp_sensors sensor,
+					void *data, uint32_t *size)
+{
+	int ret = 0;
+
+	if (!data || !size)
+		return -EINVAL;
+
+	mutex_lock(&smu->sensor_lock);
+	switch (sensor) {
+	case AMDGPU_PP_SENSOR_GPU_LOAD:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_GFXACTIVITY,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GPU_POWER:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_SOCKETPOWER,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_EDGE_TEMP:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_TEMPERATURE_EDGE,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_TEMPERATURE_HOTSPOT,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GFX_MCLK:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_UCLK,
+								(uint32_t *)data);
+		*(uint32_t *)data *= 100;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GFX_SCLK:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_GFXCLK,
+								(uint32_t *)data);
+		*(uint32_t *)data *= 100;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_VDDGFX:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_VOLTAGE_VDDGFX,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_VDDNB:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_VOLTAGE_VDDSOC,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_SS_APU_SHARE:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+						       METRICS_SS_APU_SHARE,
+						       (uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+						       METRICS_SS_DGPU_SHARE,
+						       (uint32_t *)data);
+		*size = 4;
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+	mutex_unlock(&smu->sensor_lock);
+
+	return ret;
+}
+
+static int yellow_carp_set_watermarks_table(struct smu_context *smu,
+				struct pp_smu_wm_range_sets *clock_ranges)
+{
+	int i;
+	int ret = 0;
+	Watermarks_t *table = smu->smu_table.watermarks_table;
+
+	if (!table || !clock_ranges)
+		return -EINVAL;
+
+	if (clock_ranges) {
+		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
+			clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
+			return -EINVAL;
+
+		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
+			table->WatermarkRow[WM_DCFCLK][i].MinClock =
+				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MaxClock =
+				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MinMclk =
+				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
+				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
+
+			table->WatermarkRow[WM_DCFCLK][i].WmSetting =
+				clock_ranges->reader_wm_sets[i].wm_inst;
+		}
+
+		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
+			table->WatermarkRow[WM_SOCCLK][i].MinClock =
+				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MaxClock =
+				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MinMclk =
+				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
+				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
+
+			table->WatermarkRow[WM_SOCCLK][i].WmSetting =
+				clock_ranges->writer_wm_sets[i].wm_inst;
+		}
+
+		smu->watermarks_bitmap |= WATERMARKS_EXIST;
+	}
+
+	/* pass data to smu controller */
+	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+		ret = smu_cmn_write_watermarks_table(smu);
+		if (ret) {
+			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
+			return ret;
+		}
+		smu->watermarks_bitmap |= WATERMARKS_LOADED;
+	}
+
+	return 0;
+}
+
+static int yellow_carp_get_power_profile_mode(struct smu_context *smu,
+						char *buf)
+{
+	static const char *profile_name[] = {
+					"BOOTUP_DEFAULT",
+					"3D_FULL_SCREEN",
+					"POWER_SAVING",
+					"VIDEO",
+					"VR",
+					"COMPUTE",
+					"CUSTOM"};
+	uint32_t i, size = 0;
+	int16_t workload_type = 0;
+
+	if (!buf)
+		return -EINVAL;
+
+	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+		/*
+		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT.
+		 * Not all profile modes are supported on yellow carp.
+		 */
+		workload_type = smu_cmn_to_asic_specific_index(smu,
+							       CMN2ASIC_MAPPING_WORKLOAD,
+							       i);
+
+		if (workload_type < 0)
+			continue;
+
+		size += sprintf(buf + size, "%2d %14s%s\n",
+			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
+	}
+
+	return size;
+}
+
+static int yellow_carp_set_power_profile_mode(struct smu_context *smu,
+						long *input, uint32_t size)
+{
+	int workload_type, ret;
+	uint32_t profile_mode = input[size];
+
+	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
+		return -EINVAL;
+	}
+
+	if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
+			profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
+		return 0;
+
+	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+	workload_type = smu_cmn_to_asic_specific_index(smu,
+						       CMN2ASIC_MAPPING_WORKLOAD,
+						       profile_mode);
+	if (workload_type < 0) {
+		dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on YELLOWCARP\n",
+					profile_mode);
+		return -EINVAL;
+	}
+
+	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
+				    1 << workload_type,
+				    NULL);
+	if (ret) {
+		dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
+					workload_type);
+		return ret;
+	}
+
+	smu->power_profile_mode = profile_mode;
+
+	return 0;
+}
+
+static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
+						void **table)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+	struct gpu_metrics_v2_1 *gpu_metrics =
+		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+	SmuMetrics_t metrics;
+	int ret = 0;
+
+	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
+	if (ret)
+		return ret;
+
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+
+	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
+	gpu_metrics->temperature_soc = metrics.SocTemperature;
+	memcpy(&gpu_metrics->temperature_core[0],
+		&metrics.CoreTemperature[0],
+		sizeof(uint16_t) * 8);
+	gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
+
+	gpu_metrics->average_gfx_activity = metrics.GfxActivity;
+	gpu_metrics->average_mm_activity = metrics.UvdActivity;
+
+	gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
+	gpu_metrics->average_gfx_power = metrics.Power[0];
+	gpu_metrics->average_soc_power = metrics.Power[1];
+	memcpy(&gpu_metrics->average_core_power[0],
+		&metrics.CorePower[0],
+		sizeof(uint16_t) * 8);
+
+	gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
+	gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
+	gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
+	gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
+	gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
+	gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
+
+	memcpy(&gpu_metrics->current_coreclk[0],
+		&metrics.CoreFrequency[0],
+		sizeof(uint16_t) * 8);
+	gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
+
+	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+
+	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
+
+	*table = (void *)gpu_metrics;
+
+	return sizeof(struct gpu_metrics_v2_1);
+}
+
+static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
+					long input[], uint32_t size)
+{
+	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
+	int ret = 0;
+
+	/* Only allowed in manual mode */
+	if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+		return -EINVAL;
+
+	switch (type) {
+	case PP_OD_EDIT_SCLK_VDDC_TABLE:
+		if (size != 2) {
+			dev_err(smu->adev->dev, "Input parameter number not correct\n");
+			return -EINVAL;
+		}
+
+		if (input[0] == 0) {
+			if (input[1] < smu->gfx_default_hard_min_freq) {
+				dev_warn(smu->adev->dev,
+					"Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
+					input[1], smu->gfx_default_hard_min_freq);
+				return -EINVAL;
+			}
+			smu->gfx_actual_hard_min_freq = input[1];
+		} else if (input[0] == 1) {
+			if (input[1] > smu->gfx_default_soft_max_freq) {
+				dev_warn(smu->adev->dev,
+					"Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
+					input[1], smu->gfx_default_soft_max_freq);
+				return -EINVAL;
+			}
+			smu->gfx_actual_soft_max_freq = input[1];
+		} else {
+			return -EINVAL;
+		}
+		break;
+	case PP_OD_RESTORE_DEFAULT_TABLE:
+		if (size != 0) {
+			dev_err(smu->adev->dev, "Input parameter number not correct\n");
+			return -EINVAL;
+		} else {
+			smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+			smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+		}
+		break;
+	case PP_OD_COMMIT_DPM_TABLE:
+		if (size != 0) {
+			dev_err(smu->adev->dev, "Input parameter number not correct\n");
+			return -EINVAL;
+		} else {
+			if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
+				dev_err(smu->adev->dev,
+					"The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
+					smu->gfx_actual_hard_min_freq,
+					smu->gfx_actual_soft_max_freq);
+				return -EINVAL;
+			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
+									smu->gfx_actual_hard_min_freq, NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set hard min sclk failed!");
+				return ret;
+			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
+									smu->gfx_actual_soft_max_freq, NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set soft max sclk failed!");
+				return ret;
+			}
+		}
+		break;
+	default:
+		return -ENOSYS;
+	}
+
+	return ret;
+}
+
+static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
+						enum smu_clk_type clk_type,
+						uint32_t *value)
+{
+	MetricsMember_t member_type;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+		member_type = METRICS_AVERAGE_SOCCLK;
+		break;
+	case SMU_VCLK:
+	    member_type = METRICS_AVERAGE_VCLK;
+		break;
+	case SMU_DCLK:
+		member_type = METRICS_AVERAGE_DCLK;
+		break;
+	case SMU_MCLK:
+		member_type = METRICS_AVERAGE_UCLK;
+		break;
+	case SMU_FCLK:
+		return smu_cmn_send_smc_msg_with_param(smu,
+				SMU_MSG_GetFclkFrequency, 0, value);
+	default:
+		return -EINVAL;
+	}
+
+	return yellow_carp_get_smu_metrics_data(smu, member_type, value);
+}
+
+static int yellow_carp_get_dpm_level_count(struct smu_context *smu,
+						enum smu_clk_type clk_type,
+						uint32_t *count)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+		*count = clk_table->NumSocClkLevelsEnabled;
+		break;
+	case SMU_VCLK:
+		*count = clk_table->VcnClkLevelsEnabled;
+		break;
+	case SMU_DCLK:
+		*count = clk_table->VcnClkLevelsEnabled;
+		break;
+	case SMU_MCLK:
+		*count = clk_table->NumDfPstatesEnabled;
+		break;
+	case SMU_FCLK:
+		*count = clk_table->NumDfPstatesEnabled;
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu,
+						enum smu_clk_type clk_type,
+						uint32_t dpm_level,
+						uint32_t *freq)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+
+	if (!clk_table || clk_type >= SMU_CLK_COUNT)
+		return -EINVAL;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+		if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->SocClocks[dpm_level];
+		break;
+	case SMU_VCLK:
+		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->VClocks[dpm_level];
+		break;
+	case SMU_DCLK:
+		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->DClocks[dpm_level];
+		break;
+	case SMU_UCLK:
+	case SMU_MCLK:
+		if (dpm_level >= clk_table->NumDfPstatesEnabled)
+			return -EINVAL;
+		*freq = clk_table->DfPstateTable[dpm_level].MemClk;
+		break;
+	case SMU_FCLK:
+		if (dpm_level >= clk_table->NumDfPstatesEnabled)
+			return -EINVAL;
+		*freq = clk_table->DfPstateTable[dpm_level].FClk;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
+						enum smu_clk_type clk_type)
+{
+	enum smu_feature_mask feature_id = 0;
+
+	switch (clk_type) {
+	case SMU_MCLK:
+	case SMU_UCLK:
+	case SMU_FCLK:
+		feature_id = SMU_FEATURE_DPM_FCLK_BIT;
+		break;
+	case SMU_GFXCLK:
+	case SMU_SCLK:
+		feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
+		break;
+	case SMU_SOCCLK:
+		feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
+		break;
+	case SMU_VCLK:
+	case SMU_DCLK:
+		feature_id = SMU_FEATURE_VCN_DPM_BIT;
+		break;
+	default:
+		return true;
+	}
+
+	return smu_cmn_feature_is_enabled(smu, feature_id);
+}
+
+static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
+							enum smu_clk_type clk_type,
+							uint32_t *min,
+							uint32_t *max)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+	uint32_t clock_limit;
+	uint32_t max_dpm_level, min_dpm_level;
+	int ret = 0;
+
+	if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
+		switch (clk_type) {
+		case SMU_MCLK:
+		case SMU_UCLK:
+			clock_limit = smu->smu_table.boot_values.uclk;
+			break;
+		case SMU_FCLK:
+			clock_limit = smu->smu_table.boot_values.fclk;
+			break;
+		case SMU_GFXCLK:
+		case SMU_SCLK:
+			clock_limit = smu->smu_table.boot_values.gfxclk;
+			break;
+		case SMU_SOCCLK:
+			clock_limit = smu->smu_table.boot_values.socclk;
+			break;
+		case SMU_VCLK:
+			clock_limit = smu->smu_table.boot_values.vclk;
+			break;
+		case SMU_DCLK:
+			clock_limit = smu->smu_table.boot_values.dclk;
+			break;
+		default:
+			clock_limit = 0;
+			break;
+		}
+
+		/* clock in Mhz unit */
+		if (min)
+			*min = clock_limit / 100;
+		if (max)
+			*max = clock_limit / 100;
+
+		return 0;
+	}
+
+	if (max) {
+		switch (clk_type) {
+		case SMU_GFXCLK:
+		case SMU_SCLK:
+			*max = clk_table->MaxGfxClk;
+			break;
+		case SMU_MCLK:
+		case SMU_UCLK:
+		case SMU_FCLK:
+			max_dpm_level = 0;
+			break;
+		case SMU_SOCCLK:
+			max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
+			break;
+		case SMU_VCLK:
+		case SMU_DCLK:
+			max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
+			break;
+		default:
+			ret = -EINVAL;
+			goto failed;
+		}
+
+		if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
+			ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
+			if (ret)
+				goto failed;
+		}
+	}
+
+	if (min) {
+		switch (clk_type) {
+		case SMU_GFXCLK:
+		case SMU_SCLK:
+			*min = clk_table->MinGfxClk;
+			break;
+		case SMU_MCLK:
+		case SMU_UCLK:
+		case SMU_FCLK:
+			min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
+			break;
+		case SMU_SOCCLK:
+			min_dpm_level = 0;
+			break;
+		case SMU_VCLK:
+		case SMU_DCLK:
+			min_dpm_level = 0;
+			break;
+		default:
+			ret = -EINVAL;
+			goto failed;
+		}
+
+		if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
+			ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
+			if (ret)
+				goto failed;
+		}
+	}
+
+failed:
+	return ret;
+}
+
+static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
+							enum smu_clk_type clk_type,
+							uint32_t min,
+							uint32_t max)
+{
+	enum smu_message_type msg_set_min, msg_set_max;
+	int ret = 0;
+
+	if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
+		return -EINVAL;
+
+	switch (clk_type) {
+	case SMU_GFXCLK:
+	case SMU_SCLK:
+		msg_set_min = SMU_MSG_SetHardMinGfxClk;
+		msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
+		break;
+	case SMU_FCLK:
+		msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
+		msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
+		break;
+	case SMU_SOCCLK:
+		msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
+		msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
+		break;
+	case SMU_VCLK:
+	case SMU_DCLK:
+		msg_set_min = SMU_MSG_SetHardMinVcn;
+		msg_set_max = SMU_MSG_SetSoftMaxVcn;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+	if (ret)
+		goto out;
+
+	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+static int yellow_carp_print_clk_levels(struct smu_context *smu,
+				enum smu_clk_type clk_type, char *buf)
+{
+	int i, size = 0, ret = 0;
+	uint32_t cur_value = 0, value = 0, count = 0;
+
+	switch (clk_type) {
+	case SMU_OD_SCLK:
+		size = sprintf(buf, "%s:\n", "OD_SCLK");
+		size += sprintf(buf + size, "0: %10uMhz\n",
+		(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
+		size += sprintf(buf + size, "1: %10uMhz\n",
+		(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
+		break;
+	case SMU_OD_RANGE:
+		size = sprintf(buf, "%s:\n", "OD_RANGE");
+		size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
+						smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
+		break;
+	case SMU_SOCCLK:
+	case SMU_VCLK:
+	case SMU_DCLK:
+	case SMU_MCLK:
+	case SMU_FCLK:
+		ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
+		if (ret)
+			goto print_clk_out;
+
+		ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
+		if (ret)
+			goto print_clk_out;
+
+		for (i = 0; i < count; i++) {
+			ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value);
+			if (ret)
+				goto print_clk_out;
+
+			size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+					cur_value == value ? "*" : "");
+		}
+		break;
+	default:
+		break;
+	}
+
+print_clk_out:
+	return size;
+}
+
+static int yellow_carp_force_clk_levels(struct smu_context *smu,
+				enum smu_clk_type clk_type, uint32_t mask)
+{
+	uint32_t soft_min_level = 0, soft_max_level = 0;
+	uint32_t min_freq = 0, max_freq = 0;
+	int ret = 0;
+
+	soft_min_level = mask ? (ffs(mask) - 1) : 0;
+	soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+	case SMU_FCLK:
+	case SMU_VCLK:
+	case SMU_DCLK:
+		ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
+		if (ret)
+			goto force_level_out;
+
+		ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
+		if (ret)
+			goto force_level_out;
+
+		ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
+		if (ret)
+			goto force_level_out;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+force_level_out:
+	return ret;
+}
+
+static int yellow_carp_set_performance_level(struct smu_context *smu,
+						enum amd_dpm_forced_level level)
+{
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t sclk_min = 0, sclk_max = 0;
+	uint32_t fclk_min = 0, fclk_max = 0;
+	uint32_t socclk_min = 0, socclk_max = 0;
+	int ret = 0;
+
+	switch (level) {
+	case AMD_DPM_FORCED_LEVEL_HIGH:
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
+		sclk_min = sclk_max;
+		fclk_min = fclk_max;
+		socclk_min = socclk_max;
+		break;
+	case AMD_DPM_FORCED_LEVEL_LOW:
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
+		sclk_max = sclk_min;
+		fclk_max = fclk_min;
+		socclk_max = socclk_min;
+		break;
+	case AMD_DPM_FORCED_LEVEL_AUTO:
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
+		break;
+	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+		/* Temporarily do nothing since the optimal clocks haven't been provided yet */
+		break;
+	case AMD_DPM_FORCED_LEVEL_MANUAL:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+		return 0;
+	default:
+		dev_err(adev->dev, "Invalid performance level %d\n", level);
+		return -EINVAL;
+	}
+
+	if (sclk_min && sclk_max) {
+		ret = yellow_carp_set_soft_freq_limited_range(smu,
+							    SMU_SCLK,
+							    sclk_min,
+							    sclk_max);
+		if (ret)
+			return ret;
+
+		smu->gfx_actual_hard_min_freq = sclk_min;
+		smu->gfx_actual_soft_max_freq = sclk_max;
+	}
+
+	if (fclk_min && fclk_max) {
+		ret = yellow_carp_set_soft_freq_limited_range(smu,
+							    SMU_FCLK,
+							    fclk_min,
+							    fclk_max);
+		if (ret)
+			return ret;
+	}
+
+	if (socclk_min && socclk_max) {
+		ret = yellow_carp_set_soft_freq_limited_range(smu,
+							    SMU_SOCCLK,
+							    socclk_min,
+							    socclk_max);
+		if (ret)
+			return ret;
+	}
+
+	return ret;
+}
+
+static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+
+	smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
+	smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
+	smu->gfx_actual_hard_min_freq = 0;
+	smu->gfx_actual_soft_max_freq = 0;
+
+	return 0;
+}
+
+static const struct pptable_funcs yellow_carp_ppt_funcs = {
+	.check_fw_status = smu_v13_0_1_check_fw_status,
+	.check_fw_version = smu_v13_0_1_check_fw_version,
+	.init_smc_tables = yellow_carp_init_smc_tables,
+	.fini_smc_tables = smu_v13_0_1_fini_smc_tables,
+	.get_vbios_bootup_values = smu_v13_0_1_get_vbios_bootup_values,
+	.system_features_control = yellow_carp_system_features_control,
+	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
+	.send_smc_msg = smu_cmn_send_smc_msg,
+	.dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,
+	.dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,
+	.set_default_dpm_table = smu_v13_0_1_set_default_dpm_tables,
+	.read_sensor = yellow_carp_read_sensor,
+	.is_dpm_running = yellow_carp_is_dpm_running,
+	.set_watermarks_table = yellow_carp_set_watermarks_table,
+	.get_power_profile_mode = yellow_carp_get_power_profile_mode,
+	.set_power_profile_mode = yellow_carp_set_power_profile_mode,
+	.get_gpu_metrics = yellow_carp_get_gpu_metrics,
+	.get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
+	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
+	.set_driver_table_location = smu_v13_0_1_set_driver_table_location,
+	.gfx_off_control = smu_v13_0_1_gfx_off_control,
+	.post_init = yellow_carp_post_smu_init,
+	.mode2_reset = yellow_carp_mode2_reset,
+	.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
+	.od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
+	.print_clk_levels = yellow_carp_print_clk_levels,
+	.force_clk_levels = yellow_carp_force_clk_levels,
+	.set_performance_level = yellow_carp_set_performance_level,
+	.set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters,
+};
+
+void yellow_carp_set_ppt_funcs(struct smu_context *smu)
+{
+	smu->ppt_funcs = &yellow_carp_ppt_funcs;
+	smu->message_map = yellow_carp_message_map;
+	smu->feature_map = yellow_carp_feature_mask_map;
+	smu->table_map = yellow_carp_table_map;
+	smu->workload_map = yellow_carp_workload_map;
+	smu->is_apu = true;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
new file mode 100644
index 000000000000..b3ad8352c68a
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __YELLOW_CARP_PPT_H__
+#define __YELLOW_CARP_PPT_H__
+
+extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index dc7d2e71aa6f..e802f9a95f08 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -104,8 +104,8 @@ int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
 
 	ret = smu_cmn_wait_for_response(smu);
 	if (ret != 0x1) {
-		dev_err(adev->dev, "Msg issuing pre-check failed and "
-		       "SMU may be not in the right state!\n");
+		dev_err(adev->dev, "Msg issuing pre-check failed(0x%x) and "
+		       "SMU may be not in the right state!\n", ret);
 		if (ret != -ETIME)
 			ret = -EIO;
 		return ret;
@@ -126,7 +126,7 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 	struct amdgpu_device *adev = smu->adev;
 	int ret = 0, index = 0;
 
-	if (smu->adev->in_pci_err_recovery)
+	if (smu->adev->no_hw_access)
 		return 0;
 
 	index = smu_cmn_to_asic_specific_index(smu,
@@ -398,6 +398,19 @@ int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
 
 }
 
+uint64_t smu_cmn_get_indep_throttler_status(
+					const unsigned long dep_status,
+					const uint8_t *throttler_map)
+{
+	uint64_t indep_status = 0;
+	uint8_t dep_bit = 0;
+
+	for_each_set_bit(dep_bit, &dep_status, 32)
+		indep_status |= 1ULL << throttler_map[dep_bit];
+
+	return indep_status;
+}
+
 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
 					uint64_t feature_mask,
 					bool enabled)
@@ -575,23 +588,52 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
 	return ret;
 }
 
+/**
+ * smu_cmn_disable_all_features_with_exception - disable all dpm features
+ *                                               except this specified by
+ *                                               @mask
+ *
+ * @smu:               smu_context pointer
+ * @no_hw_disablement: whether real dpm disablement should be performed
+ *                     true: update the cache(about dpm enablement state) only
+ *                     false: real dpm disablement plus cache update
+ * @mask:              the dpm feature which should not be disabled
+ *                     SMU_FEATURE_COUNT: no exception, all dpm features
+ *                     to disable
+ *
+ * Returns:
+ * 0 on success or a negative error code on failure.
+ */
 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
+						bool no_hw_disablement,
 						enum smu_feature_mask mask)
 {
+	struct smu_feature *feature = &smu->smu_feature;
 	uint64_t features_to_disable = U64_MAX;
 	int skipped_feature_id;
 
-	skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
-							    CMN2ASIC_MAPPING_FEATURE,
-							    mask);
-	if (skipped_feature_id < 0)
-		return -EINVAL;
+	if (mask != SMU_FEATURE_COUNT) {
+		skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
+								    CMN2ASIC_MAPPING_FEATURE,
+								    mask);
+		if (skipped_feature_id < 0)
+			return -EINVAL;
 
-	features_to_disable &= ~(1ULL << skipped_feature_id);
+		features_to_disable &= ~(1ULL << skipped_feature_id);
+	}
 
-	return smu_cmn_feature_update_enable_state(smu,
-						   features_to_disable,
-						   0);
+	if (no_hw_disablement) {
+		mutex_lock(&feature->mutex);
+		bitmap_andnot(feature->enabled, feature->enabled,
+				(unsigned long *)(&features_to_disable), SMU_FEATURE_MAX);
+		mutex_unlock(&feature->mutex);
+
+		return 0;
+	} else {
+		return smu_cmn_feature_update_enable_state(smu,
+							   features_to_disable,
+							   0);
+	}
 }
 
 int smu_cmn_get_smc_version(struct smu_context *smu,
@@ -761,12 +803,21 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
 	case METRICS_VERSION(1, 1):
 		structure_size = sizeof(struct gpu_metrics_v1_1);
 		break;
+	case METRICS_VERSION(1, 2):
+		structure_size = sizeof(struct gpu_metrics_v1_2);
+		break;
+	case METRICS_VERSION(1, 3):
+		structure_size = sizeof(struct gpu_metrics_v1_3);
+		break;
 	case METRICS_VERSION(2, 0):
 		structure_size = sizeof(struct gpu_metrics_v2_0);
 		break;
 	case METRICS_VERSION(2, 1):
 		structure_size = sizeof(struct gpu_metrics_v2_1);
 		break;
+	case METRICS_VERSION(2, 2):
+		structure_size = sizeof(struct gpu_metrics_v2_2);
+		break;
 	default:
 		return;
 	}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index da6ff6f024f9..9add5f16ff56 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -60,6 +60,10 @@ int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
 					uint32_t *feature_mask,
 					uint32_t num);
 
+uint64_t smu_cmn_get_indep_throttler_status(
+					const unsigned long dep_status,
+					const uint8_t *throttler_map);
+
 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
 					uint64_t feature_mask,
 					bool enabled);
@@ -75,6 +79,7 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
 				uint64_t new_mask);
 
 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
+						bool no_hw_disablement,
 						enum smu_feature_mask mask);
 
 int smu_cmn_get_smc_version(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index 68d9464ababc..59f9cfff3d61 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -57,7 +57,7 @@
 #define smu_feature_set_allowed_mask(smu)				smu_ppt_funcs(set_allowed_mask, 0, smu)
 #define smu_feature_get_enabled_mask(smu, mask, num)			smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num)
 #define smu_feature_is_enabled(smu, mask)				smu_ppt_funcs(feature_is_enabled, 0, smu, mask)
-#define smu_disable_all_features_with_exception(smu, mask)		smu_ppt_funcs(disable_all_features_with_exception, 0, smu, mask)
+#define smu_disable_all_features_with_exception(smu, no_hw_disablement, mask)		smu_ppt_funcs(disable_all_features_with_exception, 0, smu, no_hw_disablement, mask)
 #define smu_is_dpm_running(smu)						smu_ppt_funcs(is_dpm_running, 0 , smu)
 #define smu_notify_display_change(smu)					smu_ppt_funcs(notify_display_change, 0, smu)
 #define smu_populate_umd_state_clk(smu)					smu_ppt_funcs(populate_umd_state_clk, 0, smu)
@@ -82,7 +82,7 @@
 #define smu_i2c_fini(smu, control)					smu_ppt_funcs(i2c_fini, 0, smu, control)
 #define smu_get_unique_id(smu)						smu_ppt_funcs(get_unique_id, 0, smu)
 #define smu_log_thermal_throttling(smu)					smu_ppt_funcs(log_thermal_throttling_event, 0, smu)
-#define smu_get_asic_power_limits(smu)					smu_ppt_funcs(get_power_limit, 0, smu)
+#define smu_get_asic_power_limits(smu, current, default, max)		smu_ppt_funcs(get_power_limit, 0, smu, current, default, max)
 #define smu_get_pp_feature_mask(smu, buf)				smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)
 #define smu_set_pp_feature_mask(smu, new_mask)				smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
 #define smu_gfx_ulv_control(smu, enablement)				smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)